LIGBT structure and preparation method thereof

Abstract

This invention provides a LIGBT structure and its fabrication method. The LIGBT structure includes a semiconductor structure, first and second trench structures, a base region, second conductivity type pillars, a buffer zone, an emitter region, first and second contact regions, an emitter, a collector, and a gate. The semiconductor structure includes a substrate, a dielectric layer, and an epitaxial layer. The first trench structure and a second trench structure located within the second conductivity type pillars are spaced apart. The base region and the second conductivity type pillars are located on opposite sides of the first trench structure. A buffer zone with a collector region is located within the epitaxial layer. The emitter region and the first contact region are located within the base region, and the second contact region is located within the second conductivity type pillars. The emitter is electrically connected to the emitter region and the first and second contact regions, and the gate is electrically connected to the first and second trench structures. This invention reduces the on-state voltage drop and the off-state power consumption of the device by incorporating second conductivity type pillars, a second trench structure, and a second contact region electrically connected to the emitter.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing and relates to a LIGBT structure and its preparation method. Background Technology

[0002] Power semiconductor devices, as core components in energy control, serve as a bridge for converting high voltage to low voltage and are also a crucial foundation for energy conservation and emission reduction. Therefore, they are widely used in consumer electronics, industrial control circuits, aerospace, and radio frequency drive circuits. Insulated-gate bipolar transistors (IGBTs), as gate-controlled bipolar devices, possess advantages such as low conduction loss, fast switching speed, high input impedance, and strong current capability, making them highly sought after in the energy conversion and control market. They are often referred to as the "central processing unit (CPU)" of power electronic devices. As a bipolar device, IGBTs utilize both electrons and holes as charge carriers during conduction. Simultaneously, the drift region generates a conductivity modulation effect, further reducing the device's on-resistance, on-voltage, and conduction loss, thereby improving the device's forward conduction performance.

[0003] Lateral insulated-gate bipolar transistors (LIGBTs), as a type of lateral IGBT device, possess the advantages of vertical IGBTs, as well as ease of integration, simple processing, and low manufacturing cost, and are widely used in smart power modules, high-power drive circuits, and power integrated circuits. For example... Figure 1 The diagram shows a cross-sectional view of a LIGBT structure, including a semiconductor structure 01, substrate 011, dielectric layer 012, epitaxial layer 013, base region 014, emitter region 0141, contact region 0142, buffer zone 015, collector region 0151, drift region 016, trench structure 02, trench 021, gate conductive layer 022, gate dielectric layer 023, emitter 03, collector 04, and gate 05. During the device's turn-off process, the P+ contact region extracts electrons from the N-type drift region (N-type epitaxial layer), while simultaneously injecting holes into the N-type drift region. This leads to increased turn-off time and turn-off losses. When the collector voltage reaches 80% of the breakdown voltage, a large number of carriers in the device disappear primarily through non-equilibrium carrier recombination, further increasing the turn-off time and turn-off losses, and resulting in a longer tail current. Currently, the turn-off loss E of devices is typically improved by reducing the non-equilibrium carrier injection efficiency or shortening the non-equilibrium carrier lifetime in the drift region. off While reducing turn-off time, this leads to decreased device conduction performance, resulting in a higher on-state voltage drop V. on .

[0004] Therefore, there is an urgent need to find a LIGBT structure that can simultaneously reduce the on-state voltage drop and the off-state loss of the device. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a LIGBT structure and its fabrication method, which solves the problem that it is difficult to reduce the on-state voltage drop of LIGBT devices while reducing the turn-off loss in the prior art.

[0006] To achieve the above and other related objectives, the present invention provides a LIGBT structure, comprising:

[0007] A semiconductor structure comprising a substrate, a dielectric layer, and an epitaxial layer of a first conductivity type, stacked sequentially.

[0008] A first trench structure and a second trench structure are disposed at intervals on the upper surface of the epitaxial layer, and the bottom surface of the second trench structure is higher than the bottom surface of the first trench structure.

[0009] A second conductive type base region and a second conductive type pillar, wherein the base region is adjacent to the sidewall of the first trench structure on the side away from the second trench structure and its bottom surface is higher than the bottom surface of the first trench structure, and the second conductive type pillar is adjacent to the sidewall of the first trench structure on the side away from the base region and its bottom surface is higher than the first trench structure, and the second trench structure is located in the second conductive type pillar;

[0010] A first conductivity type buffer is located on the upper surface of the epitaxial layer on the side of the second conductivity type pillar away from the base region. The buffer is spaced at a preset distance from the second conductivity type pillar. The buffer contains a second conductivity type collector region located on the upper surface of the buffer.

[0011] The system comprises a first conductive type emission region, a second conductive type first contact region, and a second conductive type second contact region. The emission region is located on the upper surface of the base region and is adjacent to the sidewall of the first trench structure away from the second conductive type pillar. The first contact region is adjacent to the sidewall of the emission region away from the first trench structure. The second contact region is located on the upper surface of the second conductive type pillar between the first trench structure and the second trench structure.

[0012] The device includes an emitter, a collector, and a gate. The emitter is electrically connected to the emitter region, the first contact region, and the second contact region. The collector is electrically connected to the collector region. The gate is electrically connected to the first trench structure and the second trench structure.

[0013] Optionally, the first trench structure includes a first trench, a first gate conductive layer, and a first gate dielectric layer, wherein the first gate dielectric layer is located on the inner wall and bottom surface of the first trench and wraps around the side wall and bottom surface of the first gate conductive layer; the second trench structure includes a second trench, a second gate conductive layer, and a second gate dielectric layer, wherein the second gate dielectric layer is located on the inner wall and bottom surface of the second trench and wraps around the side wall and bottom surface of the second gate conductive layer.

[0014] Optionally, the doping concentration of the epitaxial layer is less than the doping concentration of the buffer, and the doping concentration of the epitaxial layer is less than the doping concentration of the emitter region.

[0015] Optionally, the sidewall of the current collector area is spaced apart from the sidewall of the buffer zone by a preset distance.

[0016] Optionally, the doping concentration of the second contact region is greater than the doping concentration of the second conductivity type pillar.

[0017] Optionally, the bottom surface of the second contact area is higher than the bottom surface of the second trench structure.

[0018] Optionally, the sidewall of the second contact area is adjacent to the sidewall of the first trench structure and the sidewall of the second trench structure, respectively.

[0019] Optionally, the gate includes a first gate and a second gate.

[0020] Optionally, the first gate is electrically connected to the first trench structure, and the second gate is electrically connected to the second trench structure.

[0021] This invention also provides a method for preparing a LIGBT structure, comprising the following steps:

[0022] A semiconductor structure is provided, the semiconductor structure comprising a substrate, a dielectric layer and an epitaxial layer of a first conductivity type stacked sequentially;

[0023] A first trench structure and a second trench structure are formed on the upper surface of the epitaxial layer at a predetermined distance, wherein the bottom surface of the second trench structure is higher than the bottom surface of the first trench structure;

[0024] A second conductive type base region and a second conductive type pillar are formed on the upper surface of the epitaxial layer. The base region is adjacent to the sidewall of the first trench structure away from the second trench structure and its bottom surface is higher than the bottom surface of the first trench structure. The second conductive type pillar is adjacent to the sidewall of the first trench structure away from the base region and its bottom surface is higher than the first trench structure. The second trench structure is embedded in the second conductive type pillar.

[0025] A first contact area of ​​a second conductivity type and a first emission area of ​​a first conductivity type are formed on the upper surface of the base region. A second contact area of ​​a second conductivity type is formed on the upper surface of the second conductivity type pillar between the first trench structure and the second trench structure. The sidewall of the emission area away from the first trench structure is adjacent to the first contact area, and the sidewall of the emission area away from the first contact area is adjacent to the sidewall of the first trench structure.

[0026] A first conductivity type buffer and a second conductivity type collector area are formed on the upper surface of the epitaxial layer, and the buffer and the second conductivity type pillar are spaced apart by a preset distance.

[0027] An emitter is formed that is electrically connected to the emitter region, the first contact region, and the second contact region; a collector is formed that is electrically connected to the collector region; and a gate is formed that is electrically connected to the first trench structure and the second trench structure.

[0028] As described above, the LIGBT structure and its fabrication method of the present invention involve providing a second conductive type pillar adjacent to the sidewall of the first trench structure on the side of the first trench structure away from the base region, with the bottom surface of the second conductive type pillar being higher than the bottom surface of the first trench structure. The second conductive type pillar contains a second trench structure spaced a predetermined distance from the first trench structure. A second contact area electrically connected to the emitter is provided on the upper surface of the second conductive type pillar between the first trench structure and the second trench structure. The second trench structure and the first trench structure jointly control the consumption of charge carriers in the second conductive type pillar, thereby controlling the resistance of the second conductive type pillar. When the device is forward-biased, by controlling the voltage of the first gate and the second gate, the charge carriers in the second conductive type pillar are depleted, increasing the resistance of the second conductive type pillar. The resistance of the second conductivity type post prevents holes in the device from entering the emitter through the second conductivity type post and the second contact region between the first trench structure and the second trench structure. This increases the amount of holes entering the emitter through the base region and the first contact region, thereby enhancing the conductivity modulation effect and reducing the on-state voltage drop of the device. During device turn-off, the applied voltage on the first gate and the second gate is disconnected, and the charge carriers in the second conductivity type post cannot be consumed. This creates a low-resistance hole extraction path between the second conductivity type post and the second contact region. The holes stored in the drift region enter the emitter through the second conductivity type post and the first contact region, as well as the base region and the second contact region, respectively. This accelerates the hole extraction speed in the drift region, thereby reducing the device's turn-off loss and has high industrial application value. Attached Figure Description

[0029] Figure 1 The diagram shown is a cross-sectional view of the LIGBT structure.

[0030] Figure 2 The diagram shown is a cross-sectional view of the LIGBT structure of this invention.

[0031] Figure 3 The diagram shown is a simplified equivalent circuit diagram of the LIGBT structure of this invention.

[0032] Figure 4 The diagram shows the hole current distribution when the LIGBT structure of the present invention is turned off.

[0033] Figure 5 Displayed as Figure 1 The IV curves of the LIGBT structure in the present invention and the LIGBT structure of the present invention.

[0034] Figure 6 Displayed as Figure 1 The voltage and current change curves of the LIGBT structure in the present invention when it is turned off are shown.

[0035] Figure 7 Displayed as Figure 1 The diagram shows the relationship between the on-state voltage drop and the off-state loss of the LIGBT structure in the present invention and the LIGBT structure of the present invention.

[0036] Figure 8 The diagram shows the process flow of the method for preparing the LIGBT structure of the present invention.

[0037] Figure 9 The diagram shown is a cross-sectional view of the semiconductor structure used in the fabrication method of the LIGBT structure of the present invention.

[0038] Figure 10 The diagram shows a cross-sectional view of the LIGBT structure fabrication method of the present invention after forming the first trench structure and the second trench structure.

[0039] Figure 11 The diagram shown is a cross-sectional view of the base region and the second conductivity type pillar after the formation of the LIGBT structure of the present invention.

[0040] Figure 12 The diagram shows a cross-sectional structure of the LIGBT structure prepared according to the present invention after forming the first contact region, the second contact region, and the emission region.

[0041] Figure 13 The diagram shows a cross-sectional view of the LIGBT structure fabrication method of the present invention after the formation of the buffer zone and the collector region.

[0042] Explanation of icon numbers

[0043] 01 Semiconductor Structure

[0044] 011 Substrate

[0045] 012 Dielectric Layer

[0046] 013 Epitaxial Layer

[0047] 014 Base Area

[0048] Launch Area 0141

[0049] 0142 Contact Area

[0050] 015 Buffer

[0051] 0151 Collection Area

[0052] 016 Drift Zone

[0053] 02 Trench Structure

[0054] 021 Trench

[0055] 022 Gate conductive layer

[0056] 023 Gate dielectric layer

[0057] 03 Emitter

[0058] 04 Collector

[0059] 05 Gate

[0060] 1. Semiconductor Structure

[0061] 11 Substrate

[0062] 12 dielectric layers

[0063] 13 Epitaxial Layer

[0064] 14 base regions

[0065] Launch Area 141

[0066] 142 First Contact Zone

[0067] 15 Second type of conductive column

[0068] 151 Second Contact Zone

[0069] 16 Buffer

[0070] 161 Collection Area

[0071] 17 Drift Zone

[0072] 2 First trench structure

[0073] 21 First trench

[0074] 22 First gate conductive layer

[0075] 23 First gate dielectric layer

[0076] 3 Second trench structure

[0077] 31 Second trench

[0078] 32 Second gate conductive layer

[0079] 33 Second gate dielectric layer

[0080] 4 Emitter

[0081] 5 collectors

[0082] 6 gates

[0083] 61 First gate

[0084] 62 Second gate Detailed Implementation

[0085] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0086] Please see Figures 2 to 13 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0087] Example 1

[0088] This embodiment provides a LIGBT structure, such as Figure 2 and Figure 3The figures shown are a cross-sectional view of the LIGBT structure and an equivalent circuit diagram of the LIGBT structure, respectively. The LIGBT structure includes a semiconductor structure 1, a first trench structure 2, a second trench structure 3, a second conductivity type base region 14, a second conductivity type pillar 15, a first conductivity type buffer zone 16, a first conductivity type emitter region 141, a second conductivity type first contact region 142, a second conductivity type second contact region 151, an emitter 4, a collector 5, and a gate 6. The semiconductor structure 1 includes a substrate 11, a dielectric layer 12, and a first conductivity type epitaxial layer 13 stacked sequentially. The first trench structure 2 and the second trench structure 3 are spaced apart on the upper surface of the epitaxial layer 13, with the bottom surface of the second trench structure 3 higher than the bottom surface of the first trench structure 2. The base region 14 is adjacent to the sidewall of the first trench structure 2 away from the second trench structure 3, and its bottom surface is higher than the bottom surface of the first trench structure 2. The second conductivity type pillar 15 is adjacent to the sidewall of the first trench structure 2 away from the base region 14, and its bottom surface is higher than the first trench structure 2. Structure 2, wherein the second trench structure 3 is located in the second conductivity type pillar 15; the buffer zone 16 is located on the upper surface of the epitaxial layer 13 on the side of the second conductivity type pillar 15 away from the base region 14, the buffer zone 16 is spaced apart from the second conductivity type pillar 15 by a predetermined distance, and the buffer zone 16 is provided with a second conductivity type collector region 161 located on the upper surface of the buffer zone 16; the emitter region 141 is located on the upper surface of the base region 14 and is adjacent to the sidewall of the first trench structure 2 away from the second conductivity type pillar 3, the first contact region 142 is adjacent to the sidewall of the emitter region 141 away from the first trench structure 2, and the second contact region 151 is located on the upper surface of the second conductivity type pillar 15 between the first trench structure 2 and the second trench structure 3; the emitter 4 is electrically connected to the emitter region 141, the first contact region 142 and the second contact region 151, the collector 5 is electrically connected to the collector region 161, and the gate 6 is electrically connected to the first trench structure 2 and the second trench structure 3.

[0089] Specifically, the first conductivity type includes either N-type or P-type, and the second conductivity type includes either N-type or P-type, with the first conductivity type and the second conductivity type being opposite in nature. In this embodiment, the first conductivity type is N-type, and the second conductivity type is P-type.

[0090] Specifically, the substrate 11 is made of silicon, silicon carbide, silicon germanium, or other suitable materials. In this embodiment, a silicon substrate is used.

[0091] Specifically, the dielectric layer 12 is made of silicon oxide, silicon nitride, or other suitable dielectric materials.

[0092] Specifically, while ensuring device performance, the doping concentration of the epitaxial layer 13 can be set according to the actual situation, and is not limited here.

[0093] As an example, the first trench structure 2 includes a first trench 21, a first gate conductive layer 22 and a first gate dielectric layer 23. The first gate dielectric layer 23 is located on the inner wall and bottom surface of the first trench 21 and wraps around the side wall and bottom surface of the first gate conductive layer 22. The second trench structure 3 includes a second trench 31, a second gate conductive layer 32 and a second gate dielectric layer 33. The second gate dielectric layer 33 is located on the inner wall and bottom surface of the second trench 31 and wraps around the side wall and bottom surface of the second gate conductive layer 32.

[0094] Specifically, while ensuring device performance, the opening size and depth of the first trench 21 can be set according to actual conditions and are not limited here; the thickness of the first gate dielectric layer 23 can be set according to actual conditions and is not limited here. The depth here refers to the distance from the opening of the first trench 21 to the bottom surface of the first trench 21.

[0095] Specifically, the depth of the first trench 21 is greater than the depth of the second trench 31. While ensuring device performance, the opening size of the second trench 31 can be set according to actual conditions and is not limited here. The thickness of the second gate dielectric layer 33 can be set according to actual conditions and is not limited here.

[0096] Specifically, the material of the first gate dielectric layer 23 includes silicon oxide, silicon nitride, or other suitable high-dielectric materials; the material of the second gate dielectric layer 33 includes silicon oxide, silicon nitride, or other suitable high-dielectric materials.

[0097] Specifically, the first gate conductive layer 22 is made of polycrystalline silicon or other suitable conductive materials, and the second gate conductive layer 32 is made of polycrystalline silicon or other suitable conductive materials.

[0098] Specifically, while ensuring device performance, the doping concentration of the base region 14 can be set according to actual conditions, and this is no longer limited; the doping concentration of the second conductivity type pillar 15 can be set according to actual conditions, and this is no longer limited.

[0099] Specifically, while ensuring the performance of the device and that the bottom surface of the base region 14 is higher than the bottom surface of the first trench structure 2, the bottom surface height of the base region 14 can be set according to the actual situation, and is not limited here. The bottom surface height here refers to the distance from the bottom surface of the base region 14 to the bottom surface of the semiconductor structure 1.

[0100] Specifically, provided that the bottom surface of the second conductive type post 15 is located at the horizontal plane between the bottom surface of the first trench structure 2 and the bottom surface of the second trench structure 3, the position of the bottom surface of the second conductive type post 15 can be set according to the actual situation, and is not restricted here.

[0101] Specifically, while ensuring device performance, the size and thickness of the emission area 141 can be set according to actual conditions, and are not limited here; the size and thickness of the first contact area 142 can be selected according to actual conditions, and are not limited here.

[0102] As an example, the doping concentration of the epitaxial layer 13 is less than the doping concentration of the emitter region 141.

[0103] Specifically, the doping concentration of the first contact region 142 is higher than that of the base region 14.

[0104] Specifically, while ensuring device performance and that the first contact region 142 and the emitter region 141 form an ohmic contact with the emitter 4, the doping concentration of the first contact region 142 can be set according to actual conditions and is not limited here; the doping concentration of the emitter region 141 can be set according to actual conditions and is not limited here.

[0105] As an example, the doping concentration of the second contact region 151 is greater than the doping concentration of the second conductivity type pillar 15.

[0106] Specifically, while ensuring device performance and the formation of an ohmic contact between the second contact region 151 and the emitter 4, the doping concentration of the second contact region 151 can be selected according to actual conditions, and is not limited here.

[0107] As an example, the bottom surface of the second contact area 151 is higher than the bottom surface of the second trench structure 3, that is, the bottom surface of the second contact area 151 is higher than the bottom surface of the second trench 31.

[0108] As an example, the sidewall of the second contact area 151 is adjacent to the sidewalls of the first trench structure 2 and the second trench structure 3, respectively.

[0109] Specifically, while ensuring device performance, the sidewall of the second contact area 151 may not contact the sidewall of the second trench structure 3 or the sidewall of the first trench structure 2.

[0110] As an example, the sidewall of the collector area 161 is spaced apart from the sidewall of the buffer zone 16 by a predetermined distance.

[0111] Specifically, while ensuring device performance, the distance between the sidewall of the collector area 161 and the sidewall of the buffer area 16 can be set according to actual conditions, and is not limited here; the size of the buffer area 16 and the size of the collector area 161 can be set according to actual conditions, and is not limited here.

[0112] Specifically, while ensuring device performance and that the collector region 161 can form an ohmic contact with the collector electrode 5, the doping concentration of the collector region 161 can be set according to actual conditions, and is not limited here.

[0113] As an example, the doping concentration of the epitaxial layer 13 is lower than that of the buffer layer 16 to shorten the device size.

[0114] Specifically, the epitaxial layer 13, excluding the buffer zone 16, the base region 14, and the second conductivity type pillar 15, serves as the drift region 17.

[0115] As an example, the gate 6 includes a first gate 61 and a second gate 62.

[0116] As an example, the first gate 61 is electrically connected to the first trench structure 2, and the second gate 62 is electrically connected to the second trench structure 3, that is, the first gate 61 is electrically connected to the first gate conductive layer 22, and the second gate 62 is electrically connected to the second gate conductive layer 32.

[0117] Specifically, since the second contact area 151 is electrically connected to the emitter 4, the second gate conductive layer 32 is electrically connected to the second gate 62, and the first gate conductive layer 61 is electrically connected to the first gate 22, the bottom surface of the second trench structure 3 is higher than the bottom surface of the second conductive type pillar 15. A hole extraction path is formed in the second conductive type pillar 15 through the second contact area 151 to enter the emitter 4. When the device is forward-biased, by controlling the voltage of the first gate 61 and the second gate 62, a hole extraction path is formed in the second conductive type pillar 15. An inversion layer is formed in the 5th layer, which depletes the charge carriers in the second conductivity type pillar 15, increases the resistance of the second conductivity type pillar 15 between the first trench structure 2 and the second trench structure 3, and prevents holes from entering the emitter 4 through the second conductivity type pillar 15 and the second contact region 151 between the first trench structure 2 and the second trench structure 3. This increases the amount of holes entering the emitter 4 through the base region 14, thereby enhancing the conductivity modulation effect of the drift region 17, reducing the on-resistance of the device, and thus reducing the on-voltage drop of the device.

[0118] Specifically, when the device is turned off, the voltage applied to the first gate 61 and the second gate 62 is disconnected, resulting in the carriers in the second conductivity type pillar 15 not being consumed. The second conductivity type pillar 15 is in a low resistance state, which adds a hole extraction path in the device composed of the second conductivity type pillar 15 and the second contact region 151. Subsequently, the holes stored in the drift region 17 enter the emitter through the second conductivity type pillar 15, the second contact region 151, the base region 14, and the first contact region 142, which speeds up the extraction of holes in the drift region 17 and reduces the turn-off loss of the device.

[0119] Specifically, while ensuring device performance, the voltages of the first gate 61 and the second gate 62 can be different. For example, as needed, after the device is forward-biased, the voltage value of the second gate 62 can be controlled to partially or completely deplete the carriers in the second conductivity type pillar 15. In this embodiment, the first gate 61 and the second gate 62 are connected to the same voltage, which facilitates voltage control. By selecting an appropriate doping concentration for the second conductivity type pillar 15, the carriers in the second conductivity type pillar 15 can be consumed before the voltage value reaches the device's cutoff voltage during the simultaneous voltage increase of the first gate 61 and the second gate 62.

[0120] Specifically, such as Figure 4 The figure shows the hole current distribution when the LIGBT structure of the present invention is turned off. As can be seen from the figure, when the device is turned off, the charge carriers stored in the drift region 17 flow into the emitter 4 through the hole extraction paths formed by the second conductivity type pillar 15, the second contact region 151, the base region 14, and the first contact region 142.

[0121] Specifically, such as Figure 5 , Figure 6 and Figure 7 As shown, they are respectively Figure 1 IV variation curves of the LIGBT structure in the present invention and the LIGBT structure of the present invention. Figure 1 The LIGBT structure in the present invention and the IV (current-voltage) change curves when the LIGBT structure is turned off are shown in the figure. Figure 1 The diagram shows the relationship between turn-off loss and on-state voltage drop of the LIGBT structure in the figure and the LIGBT structure of the present invention. Figure 1The LIGBT structure in this invention has the same dimensions and doping concentration for the same structural portion as the LIGBT structure of this invention. The length and depth of the first trench structure of this invention are 1.0 μm and 3.0 μm, respectively, and the length and depth of the second trench structure are 0.5 μm and 1.0 μm, respectively. The length and thickness of the second contact region 151 are 0.3 μm and 0.2 μm, respectively, and the doping concentration is 1 × 10⁻⁶. 19 cm -3 The second conductive type pillar 15 has a length of 20.0 μm and a thickness of 2.5 μm, and a doping concentration of 2 × 10⁻⁶. 15 cm -3 Here, length refers to the lateral length along the direction from the emission region 141 to the buffer zone 16, depth refers to the distance between the bottom surface of each structure and the upper surface of the epitaxial layer 13, and thickness refers to the distance between the bottom surface of each structure and the upper surface of that structure. Figure 5 It can be seen that the forward conduction capability of the LIGBT structure described in this invention is superior to that of the LIGBT structure described in this invention. Figure 1 The LIGBT structure in the middle, and its on-state voltage drop is less than Figure 1 The on-state voltage drop of the LIGBT structure in the image. Figure 6 It can be seen that the turn-off time and tail current of the LIGBT structure described in this invention are both less than [the required values]. Figure 1 The LIGBT structure in [the context]. From [the context] Figure 7 It can be seen that the on-state voltage drop during forward conduction and the turn-off loss during turn-off of the LIGBT structure are both less than [the required value]. Figure 1 The LIGBT structure in the LIGBT structure reduces the on-state voltage drop of the device and also reduces the off-state loss of the device by setting the second conductivity type pillar 15, the second trench structure 3 and the second contact area 151.

[0122] In this embodiment, the LIGBT structure provides a second conductivity type post 15 on the side of the first trench structure 2 away from the base region 14, and the second conductivity type post 15 is adjacent to the sidewall of the first trench structure 2. The second conductivity type post 15 contains a second trench structure 3 and a second contact region 151 located between the first trench structure 2 and the second trench structure 3. The second contact region 151 is electrically connected to the emitter 4, thus adding a hole extraction path in the device composed of the second conductivity type post 15 and the second contact region 151. When the device is forward-biased, by controlling the voltage of the first gate 61 and the second gate 62, the carriers in the second conductivity type post 15 are depleted, thereby increasing the resistance of the second conductivity type post 15 while preventing holes from exiting the second conductivity type post 15. The hole extraction path in the base region 14 and the first contact region 142 enters the emitter 4, increasing the amount of holes entering the emitter 4 through the base region 14 and the first contact region 142, thereby enhancing the conductivity modulation effect, reducing the on-resistance of the device, and reducing the on-voltage drop of the device. When the device is turned off, since the voltage applied to the first gate 61 and the second gate 62 is disconnected, the first gate 61 and the second gate 62 cannot consume the carriers of the second conductivity type pillar 15, thus increasing their resistance. This results in a low-resistance hole extraction path composed of the second conductivity type pillar 15 and the second contact region 151. The holes in the drift region 17 enter the emitter 4 through the second conductivity type pillar 15 and the second contact region 151, along with the base region and the first contact region 142, accelerating the hole extraction speed and reducing the turn-off loss of the device.

[0123] Example 2

[0124] This embodiment provides a method for preparing a LIGBT structure, such as Figure 8 The diagram shown is a process flow chart of the fabrication method of the LIGBT structure, which includes the following steps:

[0125] S1: A semiconductor structure is provided, the semiconductor structure comprising a substrate, a dielectric layer and an epitaxial layer of a first conductivity type stacked sequentially;

[0126] S2: A first trench structure and a second trench structure are formed on the upper surface of the epitaxial layer at a predetermined distance, wherein the bottom surface of the second trench structure is higher than the bottom surface of the first trench structure;

[0127] S3: A second conductive type base region and a second conductive type pillar are formed on the upper surface of the epitaxial layer. The base region is adjacent to the sidewall of the first trench structure away from the second trench structure and its bottom surface is higher than the bottom surface of the first trench structure. The second conductive type pillar is adjacent to the sidewall of the first trench structure away from the base region and its bottom surface is higher than the first trench structure. The second trench structure is embedded in the second conductive type pillar.

[0128] S4: A first contact area of ​​a second conductivity type and a first emission area of ​​a first conductivity type are formed on the upper surface of the base region. A second contact area of ​​a second conductivity type is formed on the upper surface of the second conductivity type pillar between the first trench structure and the second trench structure. The sidewall of the emission area away from the first trench structure is adjacent to the first contact area. The sidewall of the emission area away from the first contact area is adjacent to the sidewall of the first trench structure.

[0129] S5: A first conductivity type buffer zone and a second conductivity type collector zone located on the upper surface of the epitaxial layer are formed on the upper surface of the buffer zone, and the buffer zone and the second conductivity type post are spaced apart by a preset distance;

[0130] S6: Form an emitter electrically connected to the emitter region, the first contact region and the second contact region, form a collector electrically connected to the collector region, and form a gate electrically connected to the first trench structure and the second trench structure.

[0131] Please see Figures 9 to 10 Perform steps S1 and S2: provide a semiconductor structure 1, the semiconductor structure 1 including a substrate 11, a dielectric layer 12 and a first conductivity type epitaxial layer 13 stacked sequentially; form a first trench structure 2 and a second trench structure 3 at a predetermined distance on the upper surface of the epitaxial layer 13, the bottom surface of the second trench structure 3 being higher than the bottom surface of the first trench structure 2.

[0132] Specifically, such as Figure 9 The diagram shown is a cross-sectional view of the semiconductor structure 1. The thickness of the substrate 11 can be set according to actual conditions while ensuring device performance; the thickness of the dielectric layer 12 can be set according to actual conditions; and the thickness of the epitaxial layer 13 can be set according to actual conditions; these are not limited here.

[0133] Specifically, such as Figure 10The diagram shows a cross-sectional view of the first trench structure 2 and the second trench structure 3 after their formation. The first trench structure 2 includes a first trench 21, a first gate conductive layer 22, and a first gate dielectric layer 23. The first gate dielectric layer 23 is located on the inner wall and bottom surface of the first trench 21 and wraps around the side wall and bottom surface of the first gate conductive layer 22. The second trench structure 3 includes a second trench 31, a second gate conductive layer 32, and a second gate dielectric layer 33. The second gate dielectric layer 33 is located on the inner wall and bottom surface of the second trench 31 and wraps around the side wall and bottom surface of the second gate conductive layer 32.

[0134] Specifically, the method for forming the first trench 21 includes dry etching, wet etching, or other suitable methods; the method for forming the second trench 31 includes dry etching, wet etching, or other suitable methods.

[0135] Specifically, the method for forming the first gate dielectric layer 23 includes chemical vapor deposition, physical vapor deposition, thermal oxidation, or other suitable methods; the method for forming the second gate dielectric layer 33 includes chemical vapor deposition, physical vapor deposition, thermal oxidation, or other suitable methods.

[0136] Specifically, the first gate dielectric layer 23 and the second gate dielectric layer 33 can be formed simultaneously, or they can be formed separately according to the actual needs of the device to obtain dielectric layers of different thicknesses. In this embodiment, the first gate dielectric layer 23 and the second gate dielectric layer 33 are formed simultaneously, that is, the first gate dielectric layer 23 and the second gate dielectric layer 33 have the same thickness.

[0137] Specifically, the method for forming the first gate conductive layer 22 includes chemical vapor deposition, physical vapor deposition, or other suitable methods; the method for forming the second gate conductive layer 32 includes chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0138] Please see again Figures 11 to 12The steps S3 and S4 are performed as follows: a second conductive type base region 14 and a second conductive type pillar 15 are formed on the upper surface of the epitaxial layer 13. The base region 14 is adjacent to the sidewall of the first trench structure 2 away from the second trench structure 3 and its bottom surface is higher than the bottom surface of the first trench structure 2. The second conductive type pillar 15 is adjacent to the sidewall of the first trench structure 2 away from the base region 14 and its bottom surface is higher than the first trench structure 2. The second trench structure 3 is located in the second conductive type pillar 15. A second conductive type first contact region 142 and a first conductive type emitter region 141 are formed on the upper surface of the base region 14. A second conductive type second contact region 151 is formed on the upper surface of the second conductive type pillar 15 between the first trench structure 2 and the second trench structure 3. The sidewall of the emitter region 141 away from the first trench structure 2 is adjacent to the first contact region 142. The sidewall of the emitter region 141 away from the first contact region 142 is adjacent to the sidewall of the first trench structure 2.

[0139] Specifically, such as Figure 11 The diagram shown is a cross-sectional view of the base region 14 and the second conductivity type pillar 15 after their formation. The method for forming the base region 14 includes ion implantation or other suitable methods; the method for forming the second conductivity type pillar 15 includes ion implantation or other suitable methods.

[0140] Specifically, while ensuring device performance, the base region 14 and the second conductivity type pillar 15 can be formed simultaneously, or the base region 14 and the second conductivity type pillar 15 can be formed separately according to actual needs. In this embodiment, in order to simplify the process and reduce manufacturing costs, the base region 14 and the second conductivity type pillar 15 are formed simultaneously using ion implantation.

[0141] Specifically, such as Figure 12 The diagram shown is a cross-sectional view of the structure after the formation of the emission region 141, the first contact region 142, and the second contact region 151. The method for forming the emission region 141 includes ion implantation or other suitable methods; the method for forming the first contact region 142 includes ion implantation or other suitable methods; and the method for forming the second contact region 151 includes ion implantation or other suitable methods.

[0142] Specifically, while ensuring device performance, the first contact region 142 and the second contact region 151 can be formed simultaneously, or the first contact region 142 and the second contact region 151 can be formed separately according to actual needs. In this embodiment, the first contact region 142 and the second contact region 151 are formed separately using ion implantation.

[0143] Please see Figure 13 and Figure 2 Then, perform steps S5 and S6: form a first conductivity type buffer zone 16 and a second conductivity type collector region 161 on the upper surface of the epitaxial layer 13, wherein the buffer zone 16 and the second conductivity type pillar 15 are spaced apart by a preset distance; form an emitter 4 electrically connected to the emitter region 141, the first contact region 142 and the second contact region 151; form a collector 5 electrically connected to the collector region 161; and form a gate 6 electrically connected to the first trench structure 2 and the second trench structure 3.

[0144] Specifically, such as Figure 13 The diagram shown is a cross-sectional view of the buffer zone 16 and the collector region 161 after their formation. The method for forming the buffer zone 16 includes ion implantation or other suitable methods; the method for forming the collector region 161 includes ion implantation or other suitable methods.

[0145] Specifically, the sidewall of the current collector region 161 is spaced apart from the sidewall of the buffer zone 16 by a predetermined distance, and the epitaxial layer 13 other than the buffer zone 16, the base region 14 and the second conductivity type pillar 15 serves as the drift region 17.

[0146] Specifically, such as Figure 2 The diagram shown is a cross-sectional view of the structure after the formation of the emitter 4, the collector 5, and the gate 6. The method for forming the emitter 4 includes sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.

[0147] Specifically, the material of the emitter 4 includes one of titanium, titanium nitride, silver, gold, copper, aluminum and tungsten, or other suitable conductive materials.

[0148] Specifically, the method for forming the current collector 5 includes sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.

[0149] Specifically, the material of the current collector 5 includes one of titanium, titanium nitride, silver, gold, copper, aluminum and tungsten, or other suitable conductive materials.

[0150] Specifically, the gate 6 further includes a first gate 61 and a second gate 62, the first gate 61 being electrically connected to the first gate conductive layer 22, and the second gate 62 being electrically connected to the second gate conductive layer 32.

[0151] Specifically, the methods for forming the first gate 61 include sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods; the methods for forming the second gate 62 include sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods. In this embodiment, the first gate 61 and the second gate 62 are formed simultaneously.

[0152] Specifically, the material of the first gate 61 includes one of titanium, titanium nitride, silver, gold, copper, aluminum and tungsten, or other suitable conductive materials; the material of the second gate 62 includes one of titanium, titanium nitride, silver, gold, copper, aluminum and tungsten, or other suitable conductive materials.

[0153] Specifically, by forming the second conductivity type pillar 15, the second trench structure 3, and the second contact area 151 in the LIGBT structure, a hole extraction channel composed of the second conductivity type pillar 15 and the second contact area 151 is formed in the device. The second trench structure 3 and the first trench structure 2 jointly control the consumption of charge carriers in the second conductivity type pillar 15, thereby controlling the resistance of the second conductivity type pillar 15. When the device is forward-biased, by controlling the increase of the voltage value on the first gate conductive layer 22 and the second gate conductive layer 32, the charge carriers in the second conductivity type pillar 15 are depleted, thereby increasing the resistance of the second conductivity type pillar 15. Holes enter the emitter 4 through the second conductivity type post 15 and the second contact region 151, increasing the amount of holes entering the emitter 4 through the base region 14 and the first contact region 142. This enhances the conductivity modulation effect, reduces the on-resistance of the device, and consequently reduces the on-state voltage drop. When the device is turned off, the voltage applied to the first gate conductive layer 22 and the second gate conductive layer 32 is disconnected. Holes stored in the drift region 17 enter the emitter 4 through two paths: the second conductivity type post 15 and the second contact region 151, and the base region 14 and the first contact region 142. This accelerates the hole extraction speed in the drift region 17 and reduces the device's turn-off loss.

[0154] The LIGBT structure fabrication method of this embodiment forms a second conductivity type post 15, a second trench structure 3, and a second contact region 151 electrically connected to the emitter 4 in the LIGBT structure, forming a hole extraction path composed of the second conductivity type post 15 and the second contact region 151 in the device. A voltage is applied to the first gate conductive layer 22 and the second gate conductive layer 32, increasing the amount of holes entering the emitter 4 through the second conductivity type post 15 and the first contact region 151, enhancing the conductivity modulation effect of the device's forward conduction, and reducing the forward conduction voltage drop of the device. By disconnecting the voltage applied to the first gate conductive layer 22 and the second gate conductive layer 32, holes enter the emitter 4 through two paths: the second conductivity type post 15 and the second contact region 151, and the base region 14 and the first contact region 142, respectively, accelerating the hole extraction speed in the drift region 17 and reducing the device's turn-off loss.

[0155] In summary, the LIGBT structure and its fabrication method of the present invention involve setting a second conductive type pillar adjacent to the sidewall of the first trench structure on the side away from the base region of the first trench structure, and setting a second trench structure electrically connected to the second gate within the second conductive type pillar at a predetermined distance from the first trench structure. Furthermore, a second contact region electrically connected to the emitter is set on the upper surface of the second conductive type pillar between the second trench structure and the first trench structure. This allows the second conductive type pillar and the second contact region to form a hole extraction path controlled by the first and second gates. During forward conduction of the device, by controlling the voltage applied to the first and second gates, the carriers in the second conductive type pillar are depleted, thereby increasing the resistance of the second conductive type pillar and preventing holes from passing through the second gate. The entry of the conductive type pillar and the second contact region into the emitter increases the number of holes entering the emitter through the base region and the first contact region, enhancing the conductivity modulation effect in the device and thus reducing the forward conduction resistance and forward voltage drop. When the device is turned off, the voltage applied to the first and second gates is disconnected, preventing the carriers in the second conductive type pillar from being consumed. The second conductive type pillar and the second contact region form a low-resistance hole extraction path. The carriers stored in the drift region enter the emitter through the base region, the first contact region, and the second conductive type pillar and the second contact region, accelerating the extraction speed of the holes stored in the device. This, in turn, reduces the device's turn-off power consumption, achieving both a reduction in forward voltage drop and a reduction in turn-off loss. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0156] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An LIGBT structure, characterized by, include: A semiconductor structure comprising a substrate, a dielectric layer, and an epitaxial layer of a first conductivity type, stacked sequentially. A first trench structure and a second trench structure are disposed at intervals on the upper surface of the epitaxial layer, and the bottom surface of the second trench structure is higher than the bottom surface of the first trench structure. A second conductive type base region and a second conductive type pillar, wherein the base region is adjacent to the sidewall of the first trench structure on the side away from the second trench structure and its bottom surface is higher than the bottom surface of the first trench structure, and the second conductive type pillar is adjacent to the sidewall of the first trench structure on the side away from the base region and its bottom surface is higher than the first trench structure, and the second trench structure is located in the second conductive type pillar; A first conductivity type buffer is located on the upper surface of the epitaxial layer on the side of the second conductivity type pillar away from the base region. The buffer is spaced at a preset distance from the second conductivity type pillar. The buffer contains a second conductivity type collector region located on the upper surface of the buffer. The system comprises a first conductive type emission region, a second conductive type first contact region, and a second conductive type second contact region. The emission region is located on the upper surface of the base region and is adjacent to the sidewall of the first trench structure away from the second conductive type pillar. The first contact region is adjacent to the sidewall of the emission region away from the first trench structure. The second contact region is located on the upper surface of the second conductive type pillar between the first trench structure and the second trench structure. The device includes an emitter, a collector, and a gate. The emitter is electrically connected to the emitter region, the first contact region, and the second contact region. The collector is electrically connected to the collector region. The gate is electrically connected to the first trench structure and the second trench structure.

2. The LIGBT structure of claim 1, wherein: The first trench structure includes a first trench, a first gate conductive layer, and a first gate dielectric layer. The first gate dielectric layer is located on the inner wall and bottom surface of the first trench and wraps around the side wall and bottom surface of the first gate conductive layer. The second trench structure includes a second trench, a second gate conductive layer, and a second gate dielectric layer. The second gate dielectric layer is located on the inner wall and bottom surface of the second trench and wraps around the side wall and bottom surface of the second gate conductive layer.

3. The LIGBT structure of claim 1, wherein: The doping concentration of the epitaxial layer is less than the doping concentration of the buffer, and the doping concentration of the epitaxial layer is less than the doping concentration of the emitter region.

4. The LIGBT structure of claim 1, wherein: The sidewall of the current collector area is spaced apart from the sidewall of the buffer zone by a predetermined distance.

5. The LIGBT structure of claim 1, wherein: The doping concentration of the second contact region is greater than the doping concentration of the second conductivity type pillar.

6. The LIGBT structure of claim 1, wherein: The bottom surface of the second contact area is higher than the bottom surface of the second trench structure.

7. The LIGBT structure of claim 1, wherein: The sidewalls of the second contact area are adjacent to the sidewalls of the first trench structure and the second trench structure, respectively.

8. The LIGBT structure of claim 1, wherein: The gate includes a first gate and a second gate.

9. The LIGBT structure of claim 8, wherein: The first gate is electrically connected to the first trench structure, and the second gate is electrically connected to the second trench structure.

10. A method of fabricating an LIGBT structure, characterized by, Includes the following steps: A semiconductor structure is provided, the semiconductor structure comprising a substrate, a dielectric layer and an epitaxial layer of a first conductivity type stacked sequentially; A first trench structure and a second trench structure are formed on the upper surface of the epitaxial layer at a predetermined distance, wherein the bottom surface of the second trench structure is higher than the bottom surface of the first trench structure; A second conductive type base region and a second conductive type pillar are formed on the upper surface of the epitaxial layer. The base region is adjacent to the sidewall of the first trench structure away from the second trench structure and its bottom surface is higher than the bottom surface of the first trench structure. The second conductive type pillar is adjacent to the sidewall of the first trench structure away from the base region and its bottom surface is higher than the first trench structure. The second trench structure is located in the second conductive type pillar. A first contact area of ​​a second conductivity type and a first emission area of ​​a first conductivity type are formed on the upper surface of the base region. A second contact area of ​​a second conductivity type is formed on the upper surface of the second conductivity type pillar between the first trench structure and the second trench structure. The sidewall of the emission area away from the first trench structure is adjacent to the first contact area, and the sidewall of the emission area away from the first contact area is adjacent to the sidewall of the first trench structure. A first conductivity type buffer and a second conductivity type collector area are formed on the upper surface of the epitaxial layer, and the buffer and the second conductivity type pillar are spaced apart by a preset distance. An emitter is formed that is electrically connected to the emitter region, the first contact region, and the second contact region; a collector is formed that is electrically connected to the collector region; and a gate is formed that is electrically connected to the first trench structure and the second trench structure.

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