An insulated gate bipolar transistor device and method of fabrication thereof

Abstract

The application relates to an insulated gate bipolar transistor device and a manufacturing method thereof, and belongs to the technical field of semiconductors, and solves the problem that the short-circuit endurance of an IGBT under a short-circuit mode cannot meet the protection system requirement. The device comprises: a trench gate MOS structure located on the front surface of a substrate, comprising a plurality of long-channel trench gate MOSs and short-channel trench gate MOSs, and the paired long-channel trench gate MOSs and the paired short-channel trench gate MOSs are arranged in an alternating mode; an emitter region is located below the bottom surface of a contact trench on the front surface of the substrate, and comprises a first emitter region located between the paired long-channel trench gate MOSs and a second emitter region located between the paired short-channel trench gate MOSs; an emitter ohmic contact region comprises a first ohmic contact part located in the contact trench and a second ohmic contact part located above the front surface of the substrate; an N-type buffer region is located above the back surface of the substrate; a collector region is located above the N-type buffer region; and a collector ohmic contact region is located above the collector region. The short-circuit endurance of the IGBT is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to an insulated gate bipolar transistor device and a method for fabricating the same. Background Technology

[0002] The Insulated Gate Bipolar Transistor (IGBT) is the latest technology that combines the advantages of both the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) and the Bipolar Junction Transistor (BJT). It controls the switching of the BJT through a MOSFET, resulting in a high input impedance. During turn-off, the thyristor structure exhibits a high breakdown voltage. During turn-on, the internal PIN structure introduces a conductivity modulation effect, reducing the forward voltage drop and overall power consumption. This allows the device to operate at high frequencies, high voltages, and high currents. It is widely used in high-voltage control fields such as marine propulsion, rail transportation, smart grids, AC frequency conversion, aerospace, wind power generation, new energy, motor drives, and automobiles.

[0003] The design requirements for IGBTs include several aspects: low power consumption, high robustness, and high reliability. Low power consumption includes low switching losses and low on-state voltage drop; high robustness includes high short-circuit withstand capability, latch-up resistance, and a wide safe operating area; high reliability refers to the device's ability to withstand switching cycles, parameter drift, and power cycling. Short-circuit withstand capability is a very important aspect of IGBT robustness, and its specifications are usually clearly defined in the datasheets of actual products. Different applications and different drive circuits have different requirements for short-circuit withstand capability. Safety protection systems with fast response have lower requirements for short-circuit withstand capability, generally greater than or equal to 5μs, while protection systems with slow response generally require higher short-circuit withstand capability, generally greater than 10μs, and some even require 15μs. In addition, for some specific applications, IGBTs need to operate in short-circuit mode, which also places higher requirements on short-circuit withstand capability. Summary of the Invention

[0004] Based on the above analysis, the embodiments of this application aim to provide an insulated gate bipolar transistor device and a method for manufacturing the same, in order to solve the problem that the short-circuit withstand capability of existing IGBTs in short-circuit mode cannot meet the requirements of protection systems.

[0005] On one hand, embodiments of this application provide an insulated-gate bipolar transistor device, comprising: a trench gate MOS structure located on the front side of a substrate, including a plurality of long-channel trench gate MOS and a plurality of short-channel trench gate MOS, wherein paired long-channel trench gate MOS and paired short-channel trench gate MOS are configured alternately, and the depth of the long-channel trench gate MOS is greater than the depth of the short-channel trench gate MOS; an emitter region located on the front side of the substrate and below the bottom surface of a contact trench, including a first emitter region located between paired long-channel trench gate MOS and a second emitter region located between paired short-channel trench gate MOS, wherein the depth of the first emitter region is the same as the depth of the second emitter region; an emitter ohmic contact region including a first ohmic contact portion located in the contact trench and a second ohmic contact portion located above the front side of the substrate; an N-type buffer located above the back side of the substrate; a collector region located above the N-type buffer; and a collector ohmic contact region located above the collector region.

[0006] The beneficial effects of the above technical solution are as follows: By increasing the length of the MOS channel, the channel resistance is increased, reducing the saturation current of the MOS, thereby reducing the current of the IGBT when it operates in saturation. When short-circuited, the voltage drop across the IGBT device is the bus voltage, and the current is the saturation current. Reducing the saturation current effectively improves the short-circuit withstand capability of the device. Simultaneously, due to the increased channel length, electrons are injected deeper into the drift region compared to traditional IGBTs without increased channel length. The higher concentration of electrons and holes on the device surface reduces the resistance of the drift region, thereby reducing the on-state voltage drop.

[0007] Based on a further improvement of the above device, the long-channel trench gate MOS includes: a first gate trench with a first depth, a first gate oxide layer conformally located in the first gate trench, and a first polysilicon gate located above the gate oxide layer, wherein the first depth is 4-8 μm; and the short-channel trench gate MOS includes a second gate trench with a second depth, a second gate oxide layer conformally located in the second gate trench, and a second polysilicon gate located above the second gate oxide layer, wherein the second depth is 2-4 μm, and the thickness of the first gate oxide layer and the second gate oxide layer is 80-150 nm.

[0008] Based on further improvements to the above-described device, the insulated gate bipolar transistor (IGBT) further includes a first P-well region, a second P-well region, a third P-well region, a first N-well region, and a second N-well region. The contact trench includes a first contact trench and a second contact trench, with the depth of the first contact trench being greater than the depth of the second contact trench. The first P-well region is located between paired long-channel trench gate MOS transistors, and its depth is 3-7 μm. The second P-well region is located between paired short-channel trench gate MOS transistors. The third P-well region is located between the long-channel trench gate MOS transistor and the short-channel trench gate MOS transistor, and the depth of the third P-well region is 1-3 μm, similar to the depth of the second P-well region. The first N-well region is located above the first P-well region and on the opposite side of the first contact trench. The second N-well region is located above the second P-well region and on the opposite side of the second contact trench. The doping level of the first P-well region, the second P-well region, and the third P-well region is 1 × 10⁻⁶. 16 cm -3 -1×10 18 cm -3 The doping levels of the first N-well region and the second N-well region are 1×10⁻⁶. 19 cm -3 -1×10 20 cm -3 .

[0009] Based on a further improvement of the above device, the first emitter region is located in the first P-well region and is in contact with the first ohmic contact portion in the first contact trench; the second emitter region is located in the second P-well region and is in contact with the first ohmic contact portion in the second contact trench, the depth of the first contact trench is the same as the depth of the second contact trench, and the depth of the first emitter region is the same as the depth of the second emitter region, wherein the first emitter region and the second emitter region are P+ doped and the P+ doping level is 1×10⁻⁶. 18 cm -3 -1×10 20 cm -3 .

[0010] Based on further improvements to the above-described device, the N-type doping level of the substrate is 1×10⁻⁶. 13 cm -3 -1×10 15 cm -3 The substrate has a thickness of 60-600 μm; the N-type buffer has a doping level of 1 × 10⁻⁶. 16 cm -3 -1×10 18 cm -3The thickness of the N-type buffer is 3-10 μm; and the collector region is P+ doped with a P+ doping level of 1 × 10⁻⁶. 18 cm -3 -1×10 20 cm -3 The thickness of the collector region is 0.5-2 μm.

[0011] On the other hand, embodiments of this application provide a method for fabricating an insulated-gate bipolar transistor (IGBT) device, comprising forming a trench gate MOS structure on the front side of a substrate, wherein the trench gate MOS structure includes a long-channel trench gate MOS and a short-channel trench gate MOS, and the paired long-channel trench gate MOS and the paired short-channel trench gate MOS are configured alternately, the depth of the long-channel trench gate MOS being greater than the depth of the short-channel trench gate MOS; forming a SiO2 dielectric layer on the front side of the substrate and patterning the SiO2 dielectric layer into a contact trench mask; and forming a trench gate structure on the front side of the substrate based on the patterned contact trench mask, located at the paired trench gate structure. A first contact trench is formed between long-channel trench gate MOS transistors, and a second contact trench is formed between paired short-channel trench gate MOS transistors, wherein the first contact trench and the second contact trench have the same depth; ion implantation is performed on the first contact trench and the second contact trench to form a first emitter region and a second emitter region, respectively; metal is deposited on the front side of the substrate to form an emitter ohmic contact region, the emitter ohmic contact region including a first ohmic contact portion located in the contact trench and a second ohmic contact portion located above the front side of the substrate; and an N-type buffer, a collector region and a collector ohmic contact region are sequentially formed above the back side of the substrate.

[0012] Further improvements to the above method include forming a trench gate MOS structure on the front side of a substrate by: forming a plurality of first trenches on the front side of the substrate using a first etching process; forming a plurality of second trenches on the front side of the substrate using a second etching process, wherein the depth of the first trenches is greater than the depth of the second trenches, and paired first trenches and paired second trenches are arranged alternately; forming a conformal first gate oxide layer and a conformal second gate oxide layer in the plurality of first trenches and the plurality of second trenches respectively using an oxidation process; and depositing polysilicon over the first gate oxide layer to form paired long-channel trench gate MOS and depositing polysilicon over the second gate oxide layer to form paired short-channel trench gate MOS using a deposition process.

[0013] A further improvement to the above method includes, before forming a SiO2 dielectric layer on the front side of the substrate and patterning the SiO2 dielectric layer into a contact trench mask: forming a first oxide layer on the front side of the substrate; etching the first oxide layer using a first oxide etching process to remove a first portion of the first oxide layer between paired short-channel trench gate MOS transistors and a second portion of the first oxide layer between long-channel trench gate MOS transistors and short-channel trench gate MOS transistors; fabricating a second P-well region and a third P-well region with a depth of 1-3 μm on the front side of the substrate using multiple P-type ion implantation processes; forming a second oxide layer above the second P-well region and the third P-well region, wherein the second oxide layer and the remaining first oxide layer serve as a mask oxide layer; and etching the mask oxide layer using a second oxide etching process to remove the mask. The oxide layer comprises a portion between paired long-channel trench gate MOS transistors; a first P-well region with a depth of 3-7 μm is prepared on the front side of the substrate by multiple P-type ion implantation processes; a third oxide layer is formed above the first P-well region, wherein the third oxide layer and the remaining oxide layer are used as a new mask oxide layer; the new mask oxide layer is etched using a third oxide etching process to remove a portion of the oxide adjacent to the long-channel trench gate MOS transistors and short-channel trench gate MOS transistors in the new mask oxide layer of the first P-well region and the second P-well region; and an N-well region is prepared on the first P-well region and the second P-well region by an N-type ion implantation process, the N-well region comprising a first N-well region above the first P-well region and a second N-well region above the second P-well region, wherein the depth of the first N-well region is the same as the depth of the second N-well region.

[0014] Further improvements to the above method include ion implantation of the first contact trench and the second contact trench to form a first emitter region and a second emitter region, respectively: performing a P+ ion implantation process on the front side of the substrate using a patterned contact trench mask to form a first P+ well region below the bottom surface of the first contact trench as the first emitter region and a second P+ well region below the bottom surface of the second contact trench as the second emitter region, wherein the depth of the first emitter region is the same as the depth of the second emitter region; and depositing metal on the front side of the substrate to form an emitter ohmic contact region includes: depositing metal in the first contact trench and the second contact trench on the front side of the substrate using a patterned contact trench mask through a metal deposition process to form a first ohmic contact portion, wherein the first ohmic contact portion includes a first emitter contact element contacted and connected to the first emitter region and a second emitter contact element contacted and connected to the second emitter region; and continuing to deposit metal above the front side of the substrate to form a second ohmic contact portion.

[0015] A further improvement to the above method involves sequentially forming an N-type buffer zone, a collector region, and a collector ohmic contact region on the back side of the substrate, comprising: fabricating an N-type buffer zone on the back side of the substrate through multiple ion implantation processes, wherein the doping level of the N-type buffer zone is 1×10⁻⁶. 16 cm -3 -1×10 18 cm -3 The thickness of the N-type buffer is 3-10 μm; a P+ collector region is prepared on the back side of the substrate by P+ ion implantation, wherein the P+ doping level of the collector region is 1×10⁻⁶. 18 cm -3 -1×10 20 cm -3 The thickness of the collector region is 0.5-2 μm; and an ohmic contact region for the collector is formed on the back side of the substrate by a metal deposition process.

[0016] Compared with the prior art, this application can achieve at least one of the following beneficial effects: 1. Increasing the length of the MOS channel increases the channel resistance and reduces the MOS saturation current, thereby reducing the IGBT's saturation current. During a short circuit, the voltage drop across the IGBT is equal to the bus voltage, and the current is the saturation current. Reducing the saturation current effectively improves the device's short-circuit withstand capability. Simultaneously, due to the increased channel length, electrons are injected deeper into the drift region compared to traditional IGBTs without increased channel length. The higher concentration of electrons and holes on the device surface reduces the drift region resistance, thus lowering the on-state voltage drop.

[0017] 2. Longer channels allow electrons to be injected deeper into the drift region, resulting in a higher electron concentration at the device surface. Due to the electrical neutrality condition, the hole concentration at the device surface is also higher, thus reducing the on-state voltage drop. Since MOS current exhibits self-saturation, and the channel resistance increases with increasing channel length, the saturation current decreases.

[0018] 3. During a short circuit, the voltage drop across the IGBT device is equal to the bus voltage, and the current is the saturation current. Excessive current will generate more heat, causing the device to burn out faster. Therefore, a low saturation current can reduce heat generation, allowing the device to withstand a short circuit for a longer period of time.

[0019] 4. Due to a load short circuit, the IGBT may experience a hard switching short circuit. Before the protection circuit takes effect, the IGBT can withstand the short circuit for a certain period of time without burning out.

[0020] In this application, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this application will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing this application. The objectives and other advantages of this application can be realized and obtained from the specific points highlighted in the description and accompanying drawings. Attached Figure Description

[0021] The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Throughout the drawings, the same reference numerals denote the same parts.

[0022] Figure 1 A cross-sectional view of an insulated gate bipolar transistor (IGBT) device according to an embodiment of this application; Figures 2A-2M These are cross-sectional views of various fabrication processes of an insulated gate bipolar transistor (IGBT) device according to embodiments of this application; Figure 3A , Figure 3B and Figure 3C The graphs show the transfer characteristics, transport characteristics, and short-circuit withstand capability of the insulated gate bipolar transistor (IGBT) device according to the embodiments of this application. Figure 4 This is a flowchart illustrating the specific steps of an insulated gate bipolar transistor (IGBT) device according to an embodiment of this application. Detailed Implementation

[0023] The preferred embodiments of this application are described in detail below with reference to the accompanying drawings, which constitute a part of this application and are used together with the embodiments of this application to illustrate the principles of this application, but are not intended to limit the scope of this application.

[0024] refer to Figure 1 One specific embodiment of this application discloses an insulated-gate bipolar transistor device comprising: a trench-gate MOS structure located on the front side of a substrate 100, including multiple long-channel trench-gate MOS and multiple short-channel trench-gate MOS, wherein paired long-channel trench-gate MOS and paired short-channel trench-gate MOS are arranged alternately, and the depth of the long-channel trench-gate MOS is greater than the depth of the short-channel trench-gate MOS; and an emitter region located on the front side of the substrate and below the bottom surface of the contact trench, including the emitter region located on the paired long-channel trench-gate MOS. The first emitter region 112 is located between the mating short-channel trench gate MOS and the second emitter region 110 is located between the mating short-channel trench gate MOS, wherein the depth of the first emitter region 112 is the same as the depth of the second emitter region 110; the emitter ohmic contact region includes a first ohmic contact portion located in the contact trench and a second ohmic contact portion located above the front side of the substrate; the N-type buffer 117 is located above the back side 100 of the substrate; the collector region 118 is located above the N-type buffer 117; and the collector ohmic contact region 119 is located above the collector region 118.

[0025] Compared to existing technologies, the insulated-gate bipolar transistor (IGBT) device provided in this embodiment increases the channel resistance by increasing the length of the MOS channel, thereby reducing the MOS saturation current and consequently lowering the IGBT's current during saturation. During a short circuit, the voltage drop across the IGBT is equal to the bus voltage, and the current is the saturation current. Reducing the saturation current effectively improves the device's short-circuit withstand capability. Furthermore, due to the increased channel length, electrons are injected deeper into the drift region compared to traditional IGBTs without increased channel length. The higher concentration of electrons and holes on the device surface reduces the resistance of the drift region, thus lowering the on-state voltage drop.

[0026] The following text will refer to Figure 1 The various parts of the insulated gate bipolar transistor (IGBT) device according to embodiments of this application will be described in detail. The IGBT device includes: a trench gate MOS structure, an emitter region, an emitter ohmic contact region, an N-type buffer 117, a collector region 118 and a collector ohmic contact region 119, a first P-well region 109, a second P-well region 107, a third P-well region 108, a first N-well region 113 and a second N-well region 111.

[0027] The insulated-gate bipolar transistor (IGBT) device includes a trench-gate MOS structure located on the front side of substrate 100, comprising multiple long-channel trench-gate MOS and multiple short-channel trench-gate MOS, wherein paired long-channel trench-gate MOS and paired short-channel trench-gate MOS are arranged alternately, and the depth of the long-channel trench-gate MOS is greater than the depth of the short-channel trench-gate MOS. The N-type doping level of the substrate is 1×10⁻⁶. 13 cm -3-1×10 15 cm -3 The substrate thickness is 60-600 μm. Specifically, the long-channel trench gate MOS includes: a first gate trench 102 with a first depth, a first gate oxide layer 105 conformally located in the first gate trench 102, and a first polysilicon gate 106 located above the gate oxide layer 105, wherein the first depth is 4-8 μm. The short-channel trench gate MOS includes a second gate trench 101 with a second depth, a second gate oxide layer 104 conformally located in the second gate trench 101, and a second polysilicon gate 103 located above the second gate oxide layer 104, wherein the second depth is 2-4 μm, and the thickness of the first gate oxide layer 105 and the second gate oxide layer 104 is 80-150 nm.

[0028] A first P-well region 109 is located between paired long-channel trench gate MOS transistors, wherein the depth of the first P-well region is 3-7 μm; a second P-well region 107 is located between paired short-channel trench gate MOS transistors; a third P-well region 108 is located between the long-channel trench gate MOS transistors and the short-channel trench gate MOS transistors, wherein the depth of the third P-well region is 1-3 μm compared to the depth of the second P-well region; a first N-well region 113 is located above the first P-well region 109 and on the opposite side of the first contact trench; a second N-well region 111 is located above the second P-well region 107 and on the opposite side of the second contact trench, wherein the doping level of the first P-well region, the second P-well region, and the third P-well region is 1 × 10⁻⁶. 16 cm -3 -1×10 18 cm -3 The doping level of the first and second N-well regions is 1×10⁻⁶. 19 cm -3 -1×10 20 cm -3 .

[0029] The emitter regions are located below the bottom surface of the contact trench on the front side of the substrate, including a first emitter region 112 located between paired long-channel trench gate MOS transistors and a second emitter region 110 located between paired short-channel trench gate MOS transistors, wherein the depth of the first emitter region 112 is the same as the depth of the second emitter region 110. The contact trenches include a first contact trench and a second contact trench, and the depth of the first contact trench is the same as the depth of the second contact trench. The first emitter region 112 is located in the first P-well region 109 and is in contact with a first ohmic contact portion in the first contact trench; the second emitter region 110 is located in the second P-well region 107 and is in contact with a first ohmic contact portion in the second contact trench. The depth of the first contact trench is the same as the depth of the second contact trench, and the depth of the first emitter region 112 is the same as the depth of the second emitter region 110, wherein the first emitter region 112 and the second emitter region 110 are P+ doped with a P+ doping level of 1×10⁻⁶. 18 cm -3 -1×10 20 cm -3 .

[0030] The emitter ohmic contact region includes a first ohmic contact portion located in the contact trench and a second ohmic contact portion located above the front side of the substrate. (Reference) Figure 2H The first ohmic contact portion includes a first contact connector 114 that is in contact with the first emitter region 112 and a second contact connector 115 that is in contact with the second emitter region 110.

[0031] The N-type buffer 117 is located above the back side of the substrate 100. The doping level of the N-type buffer is 1 × 10⁻⁶. 16 cm -3 -1×10 18 cm -3 The thickness of the N-type buffer is 3-10 μm.

[0032] Collector region 118 is located above N-type buffer 117. The collector region is P+ doped with a P+ doping level of 1 × 10⁻⁶. 18 cm -3 -1×10 20 cm -3 The thickness of the collector region is 0.5-2 μm.

[0033] The collector ohmic contact region 119 is located above the collector region 118.

[0034] refer to Figure 5Another specific embodiment of this application discloses a method for fabricating an insulated-gate bipolar transistor device, including step S501, forming a trench gate MOS structure on the front side of a substrate, wherein the trench gate MOS structure includes a long-channel trench gate MOS and a short-channel trench gate MOS, and the paired long-channel trench gate MOS and the paired short-channel trench gate MOS are configured alternately, the depth of the long-channel trench gate MOS being greater than the depth of the short-channel trench gate MOS; in step S502, referring to Figure 2G A SiO2 dielectric layer 120 is formed on the front side of the substrate, and the SiO2 dielectric layer 120 is patterned into a contact trench mask; in step S503, a reference... Figure 2H Based on a patterned contact trench mask, a first contact connector 114 trench is formed on the front side of the substrate, located between paired long-channel trench gate MOS, and a second contact connector 115 trench is formed between paired short-channel trench gate MOS, wherein the first contact connector 114 trench and the second contact connector 115 trench have the same depth; in step S504, a reference is made... Figure 2I Ion implantation is performed on the trenches of the first contact connector 114 and the second contact connector 115 to form the first emitter region 112 and the second emitter region 110, respectively; in step S505, reference Figure 2J Metal is deposited on the front side of the substrate to form an emitter ohmic contact region, the emitter ohmic contact region including a first ohmic contact portion located in a contact trench and a second ohmic contact portion located above the front side of the substrate; and in step S506, reference... Figure 2K , Figure 2L and Figure 2M An N-type buffer zone 117, a collector region 118, and a collector ohmic contact region 119 are sequentially formed above the back side of the substrate.

[0035] Forming a trench gate MOS structure on the front side of the substrate includes: Reference Figure 2A A plurality of first gate trenches 101 are formed on the front side of the substrate 100 using a first etching process; Reference Figure 2B A plurality of second gate trenches 102 are formed on the front side of the substrate 100 using a second etching process. The depth of the second gate trenches 102 is greater than the depth of the first gate trenches 101, and paired first gate trenches 101 and paired second gate trenches 102 are arranged alternately. (Reference) Figure 2CA conformal first gate oxide layer 104 and a conformal second gate oxide layer 105 are formed in a plurality of first gate trenches 101 and a plurality of second gate trenches 102 using an oxidation process; and polysilicon 106 is deposited over the second gate oxide layer 105 using a deposition process to form paired long-channel trench gate MOS and polysilicon 103 is deposited over the first gate oxide layer 104 to form paired short-channel trench gate MOS.

[0036] Before forming a SiO2 dielectric layer on the front side of the substrate and patterning the SiO2 dielectric layer into a contact trench mask, the method further includes: forming a first oxide layer on the front side of the substrate 100; Reference Figure 2D The first oxide layer is etched using a first oxide etching process to remove the first portion of the first oxide layer between the paired short-channel trench gate MOS and the second portion of the first oxide layer between the long-channel trench gate MOS and the short-channel trench gate MOS. A second P-well region 107 and a third P-well region 108 with a depth of 1-3 μm are fabricated on the front side of the substrate using multiple P-type ion implantation processes. A second oxide layer is formed above the second P-well region 107 and the third P-well region 108, wherein the second oxide layer and the remaining first oxide layer serve as a mask oxide layer. (Reference) Figure 2E The mask oxide layer is etched using a second oxide etching process to remove the portion of the mask oxide layer between the paired long-channel trench gate MOS transistors. A first P-well region 109 with a depth of 3-7 μm is fabricated on the front side of the substrate using multiple P-type ion implantation processes. A third oxide layer is formed above the first P-well region 109, wherein the third oxide layer and the remaining oxide layer serve as a newer mask oxide layer. The newer mask oxide layer is etched using a third oxide etching process to remove a portion of the oxide adjacent to the long-channel trench gate MOS transistors and short-channel trench gate MOS transistors in the newer mask oxide layer of the first P-well region 109 and the second P-well region 107. (Reference) Figure 2F An N-well region is prepared on the first P-well region and the second P-well region by an N-type ion implantation process. The N-well region includes a first N-well region 113 located above the first P-well region 109 and a second N-well region 111 located above the second P-well region 107, wherein the depth of the first N-well region 113 is the same as the depth of the second N-well region 111.

[0037] Ion implantation of the first contact trench and the second contact trench to form the first emitter region and the second emitter region, respectively, includes: Reference Figure 2IA P+ ion implantation process is performed on the front side of the substrate using a patterned contact trench mask to form a first P+ well region as a first emitter region 112 below the bottom surface of a first contact trench and a second P+ well region as a second emitter region 110 below the bottom surface of a second contact trench. The depths of the first emitter region 112 and the second emitter region 110 are the same. (Reference) Figure 2J The method of depositing metal on the front side of a substrate to form an emitter ohmic contact region includes: depositing metal in a first contact trench and a second contact trench on the front side of the substrate using a patterned contact trench mask through a metal deposition process to form a first ohmic contact portion, wherein the first ohmic contact portion includes a first emitter contact element that is contacted and connected to a first emitter region and a second emitter contact element that is contacted and connected to a second emitter region; and continuing to deposit metal above the front side of the substrate to form a second ohmic contact portion.

[0038] An N-type buffer zone, a collector region, and a collector ohmic contact region are sequentially formed above the back side of the substrate, including: Reference Figure 2K An N-type buffer 117 was fabricated on the back side of a substrate using a multiple ion implantation process, wherein the doping level of the N-type buffer was 1 × 10⁻⁶. 16 cm -3 -1×10 18 cm -3 The thickness of the N-type buffer is 3-10 μm; Reference Figure 2L A P+ collector region 118 was fabricated on the back side of the substrate using a P+ ion implantation process, wherein the P+ doping level of the collector region 118 was 1 × 10⁻⁶. 18 cm -3 -1×10 20 cm -3 The thickness of the collector region 118 is 0.5-2 μm; and the reference... Figure 2M An ohmic contact region 119 is formed on the back side of the substrate using a metal deposition process.

[0039] In the following text, refer to Figures 2A to 2M , Figures 3A to 3C as well as Figure 4 The insulated gate bipolar transistor device according to the embodiments of this application will be described in detail by way of specific examples.

[0040] This application proposes a trench gate IGBT structure that improves short-circuit withstand capability and reduces on-state voltage drop. The operating principle of this trench gate IGBT is the same as that of a basic IGBT: when turned on, electrons are injected into the drift region through the electron channel of the MOS transistor, and holes are injected into the drift region through the P+ / N-buffer junction on the back side. This conductivity modulation effect increases the IGBT's current conduction capability. The structure proposed in this application, by designing the MOS conductive channel and increasing its length, increases the channel resistance and reduces the MOS saturation current, thereby reducing the IGBT's current at saturation. During a short circuit, the voltage drop across the IGBT is equal to the bus voltage, and the current is the saturation current. Reducing the saturation current effectively improves the device's short-circuit withstand capability. Simultaneously, due to the increased channel length, electrons are injected deeper into the drift region compared to traditional IGBTs without increased channel length. The higher concentration of electrons and holes on the device surface reduces the resistance of the drift region, thus lowering the on-state voltage drop. The structure and fabrication method of the IGBT are as follows: The device structure includes a trench gate MOS structure with long and short channels on the front side, an N-drift region, an N-buffer layer, and a P+ collector region. The long and short channel structure is located on the front side of the trench gate MOS structure. The front-side process includes: forming the trench gate and P-well through two etching processes and two P-type implantations. The first etching is a shallower trench gate. The P-well is formed by P-type ion implantation. The second etching is a deeper trench gate. The P-well is formed by P-type ion implantation. By adjusting the energy, dose, and number of ion implantations, P-wells with consistent doping levels are fabricated. Then, an N+ source region is formed by N-type ion implantation, followed by the deposition of a SiO2 dielectric layer. Emitter contact holes are etched. Using the SiO2 dielectric layer as a mask, a P+ ohmic contact is formed by P-type ion implantation. Finally, emitter metal is deposited. The back-side process includes: forming an N-buffer layer through multiple N-type ion implantations. A P+ collector region is formed by P-type ion implantation. Collector metal is deposited.

[0041] The IGBT cell structure proposed in this application is compatible with traditional IGBT processes when completing the front and back structures, without involving additional process operations. It can significantly reduce the on-state voltage drop, increase the short-circuit withstand capability, and enhance the device's robustness. Traditional trench gates (using the same channel) typically adjust the on-state voltage drop and saturation current (related to short-circuit capability; lower values ​​result in better short-circuit withstand capability) by adjusting the concentration of P+ on the back side to regulate the hole concentration injected into the drift region: increasing the P+ concentration increases the hole concentration injected into the drift region, reducing the drift region resistance and lowering the on-state voltage drop. However, excessively high hole concentration leads to high saturation current, generating more heat during short-circuit operation and potentially causing device burnout. Traditional structures cannot simultaneously optimize these two aspects, while this structure can reduce the on-state voltage drop while simultaneously reducing the saturation current and increasing the short-circuit withstand capability, thus achieving better optimized device design.

[0042] The general process of IGBT device fabrication is as follows: Figures 2A to 2M As shown, the fabrication process includes the following steps for the front structure and the back structure.

[0043] The front-side structure process includes: forming a 3μm deep trench on an N- substrate through a first etching; forming a 6μm deep trench on an N- substrate through a second etching; forming a trench gate by oxidation and deposition of polysilicon; preparing a 2μm deep PWell region on the surface through multiple P-type ion implantations; preparing a 5μm deep PWell region on the surface through multiple P-type ion implantations; activating PWell impurity ions by high-temperature annealing after ion implantation; preparing an N+ region on the PWell by N-type ion implantation; activating N+ impurity ions by high-temperature annealing after ion implantation; depositing a 1-3μm thick SiO2 dielectric layer on the surface; etching to form an emitter metal connection hole on the surface; using the SiO2 dielectric layer as a mask, preparing the P+ region by P-type ion implantation; activating P+ impurity ions by high-temperature annealing after ion implantation; depositing the emitter metal and forming an emitter ohmic contact by high-temperature annealing.

[0044] For the back-side structure process: a 5μm deep N-buffer layer is prepared on the back side by multiple N-type ion implantations; after ion implantation, high-temperature annealing is performed to activate N+ impurity ions; a 0.5μm deep P+ collector region is prepared on the back side by P-type ion implantation; after ion implantation, high-temperature annealing is performed to activate P+ impurity ions; collector metal is deposited and high-temperature annealing is performed to form an emitter ohmic contact.

[0045] The beneficial effects of this application are: by using a long and short channel structure, the saturation current of the device is reduced while the on-state voltage drop is also reduced. This improves the short-circuit withstand capability of the device and enhances its robustness.

[0046] Simulation software was used. Figure 1 The transfer characteristics, transmission characteristics, and short-circuit withstand curves of traditional trench gate IGBT structures with both short channels are presented.

[0047] In the simulation, the material parameters were set based on the research group's experience in fabrication, taking into account the actual device fabrication situation. Except for the long-channel and short-channel MOS structures, all other parameters were the same. The trench depth for the long channel was 6 μm, and the trench depth for the short channel was 3 μm. The PWell depth for the long channel was 5 μm, and the PWell depth for the short channel was 2 μm. Figure 3A The transfer characteristic curves of the two devices under the same collector voltage bias condition (Vc=8V) are given. As can be seen from Figure 3A, the threshold voltages of the two structures are almost the same, indicating that the new structure has little effect on the threshold voltage of the device. Figure 3B The output characteristic curves of the two devices under the same gate voltage bias condition (Vg=15V) are given. Figure 3B As can be seen, the on-state voltage drop of the long-channel and short-channel structures is reduced under the same current conditions, and the saturation current is also significantly reduced compared to the traditional structure. The longer channel allows electrons to be injected deeper into the drift region, resulting in a higher electron concentration at the device surface. Due to the charge-neutral condition, the hole concentration at the device surface is also higher, thus reducing the on-state voltage drop. Since MOS current exhibits self-saturation, and the channel resistance increases with increasing channel length, the saturation current decreases. Figure 3C The short-circuit characteristic curves of the two devices under the same collector voltage bias condition (Vc=400V) are presented. Figure 3C As can be seen, under 400V operating conditions, the gate voltage turns on, and the device enters a short-circuit operating state. Due to its low saturation current, the long-short channel structure has a significantly greater short-circuit withstand capability than the traditional structure. It can be observed that the proposed structure has better on-state voltage drop and short-circuit withstand performance. During a short circuit, the voltage drop across the IGBT device is equal to the bus voltage, and the current is the saturation current. Excessive current generates more heat, leading to faster device burnout. Therefore, a low saturation current reduces heat generation, allowing the device to withstand short circuits for a longer period.

[0048] Figure 4 This document presents a flowchart illustrating the fabrication process of the N-type trench gate IGBT with long and short channels, as described in this application. In practical IGBT applications, load short circuits can cause hard switching short circuits in the IGBT. Before the protection circuit activates, the IGBT can withstand a short circuit for a certain period without burning out. Specific applications include motor drive systems, DC-AC inverters, and high-voltage, high-power charging systems. This method can be used to fabricate... Figure 1 The IGBT shown includes the following steps: Step 1 involves forming trenches with a depth of 2-4 μm on an N- substrate through a first etching process; Step 2 involves forming trenches with a depth of 4-8 μm on the N- substrate through a second etching process; Step 3 involves forming a trench gate by oxidation and deposition of polysilicon; Step 4 involves preparing PWell regions with a depth of 1-3 μm on the surface through multiple ion implantations; Step 5 involves preparing PWell regions with a depth of 3-7 μm on the surface through multiple ion implantations; Step 6: Prepare N+ regions on the PWell via ion implantation; Step 7: Deposit a SiO2 layer with a thickness of 1-3 μm on the surface; Step 8: Etch the surface to form an emitter metal connection hole; Step 9: Use SiO2 as a mask to prepare the P+ region by ion implantation; Step 10: Deposit metal to form an emitter ohmic contact; Step 11 involves preparing an N-buffer layer on the back side via multiple ion implantations; Step 12: Prepare a P+ current collector region on the back side by ion implantation; Step 13: Deposit metal on the back side to form a collector ohmic contact; The trench gate IGBT device structure and fabrication method proposed in this application, which improves short-circuit withstand capability and reduces on-state voltage drop, have the following beneficial effects: They reduce the device's saturation current while simultaneously lowering the on-state voltage drop. This improves the device's short-circuit withstand capability and enhances its robustness.

[0049] Those skilled in the art will understand that all or part of the processes of the methods described in the above embodiments can be implemented by a computer program instructing related hardware, and the program can be stored in a computer-readable storage medium. The computer-readable storage medium may be a disk, optical disk, read-only memory, or random access memory, etc.

[0050] The above description is merely a preferred embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. An insulated-gate bipolar transistor device, characterized in that, include: A trench gate MOS structure, located on the front side of a substrate, includes multiple long-channel trench gate MOS and multiple short-channel trench gate MOS, wherein paired long-channel trench gate MOS and paired short-channel trench gate MOS are configured in an alternating manner, and the depth of the long-channel trench gate MOS is greater than the depth of the short-channel trench gate MOS. The emitter region, located on the front side of the substrate and below the bottom surface of the contact trench, includes a first emitter region located between paired long-channel trench gate MOS and a second emitter region located between paired short-channel trench gate MOS, wherein the depth of the first emitter region is the same as the depth of the second emitter region. The emitter ohmic contact region includes a first ohmic contact portion located in the contact trench and a second ohmic contact portion located above the front side of the substrate; An N-type buffer is located above the back side of the substrate; The collector region is located above the N-type buffer; and The collector ohmic contact region is located above the collector region.

2. The insulated-gate bipolar transistor device according to claim 1, characterized in that, The long-channel trench gate MOS includes: a first gate trench having a first depth, a first gate oxide layer conformally located in the first gate trench, and a first polysilicon gate located above the first gate oxide layer, wherein the first depth is 4-8 μm; and The short-channel trench gate MOS includes a second gate trench with a second depth, a second gate oxide layer conformally located in the second gate trench, and a second polysilicon gate located above the second gate oxide layer, wherein the second depth is 2-4 μm, and the thickness of the first gate oxide layer and the second gate oxide layer is 80-150 nm.

3. The insulated-gate bipolar transistor device according to claim 2, characterized in that, It also includes a first P-well region, a second P-well region, a third P-well region, a first N-well region, and a second N-well region. The contact trench includes a first contact trench and a second contact trench, and the depth of the first contact trench is the same as the depth of the second contact trench. The first P-well region is located between paired long-channel trench gate MOS transistors, wherein the depth of the first P-well region is 3-7 μm; The second P-well region is located between paired short-channel trench gate MOS transistors; The third P-well region is located between the long-channel trench gate MOS and the short-channel trench gate MOS, wherein the depth of the third P-well region and the depth of the second P-well region are 1-3 μm; The first N-well region is located above the first P-well region and on the opposite side of the first contact trench; The second N-well region is located above the second P-well region and on the opposite side of the second contact trench, wherein the doping level of the first P-well region, the second P-well region, and the third P-well region is 1 × 10⁻⁶. 16 cm -3 -1×10 18 cm -3 The doping levels of the first N-well region and the second N-well region are 1×10⁻⁶. 19 cm -3 -1×10 20 cm -3 .

4. The insulated-gate bipolar transistor device according to claim 3, characterized in that, The first emitter region is located in the first P-well region and is in contact with the first ohmic contact portion in the first contact trench. The second emitter region is located in the second P-well region and is in contact with the first ohmic contact portion in the second contact trench. The depth of the first contact trench is the same as the depth of the second contact trench, and the depth of the first emitter region is the same as the depth of the second emitter region. Both the first and second emitter regions are P+ doped with a P+ doping level of 1 × 10⁻⁶. 18 cm -3 -1×10 20 cm -3 .

5. The insulated-gate bipolar transistor device according to claim 2, characterized in that, The N-type doping level of the substrate is 1×10⁻⁶. 13 cm -3 -1×10 15 cm -3 The thickness of the substrate is 60-600 μm; The doping level of the N-type buffer is 1×10⁻⁶. 16 cm -3 -1×10 18 cm -3 The thickness of the N-type buffer is 3-10 μm; and The collector region is P+ doped with a P+ doping level of 1×10⁻⁶. 18 cm -3 -1×10 20 cm -3 The thickness of the collector region is 0.5-2 μm.

6. A method for fabricating an insulated-gate bipolar transistor device, characterized in that, include: A trench gate MOS structure is formed on the front side of a substrate, wherein the trench gate MOS structure includes a long-channel trench gate MOS and a short-channel trench gate MOS, and the paired long-channel trench gate MOS and the paired short-channel trench gate MOS are configured alternately, and the depth of the long-channel trench gate MOS is greater than the depth of the short-channel trench gate MOS. A SiO2 dielectric layer is formed on the front side of the substrate, and the SiO2 dielectric layer is patterned into a contact trench mask; Based on a patterned contact trench mask, a first contact trench is formed between paired long-channel trench gate MOS and a second contact trench is formed between paired short-channel trench gate MOS on the front side of the substrate, wherein the first contact trench and the second contact trench have the same depth. Ion implantation is performed on the first contact trench and the second contact trench to form a first emitter region and a second emitter region, respectively; Metal is deposited on the front side of the substrate to form an emitter ohmic contact region, the emitter ohmic contact region including a first ohmic contact portion located in the contact trench and a second ohmic contact portion located above the front side of the substrate; and An N-type buffer zone, a collector region, and a collector ohmic contact region are sequentially formed above the back side of the substrate.

7. The method for fabricating an insulated-gate bipolar transistor device according to claim 6, characterized in that, Forming a trench gate MOS structure on the front side of the substrate includes: A plurality of first gate trenches are formed on the front side of the substrate using a first etching process; A plurality of second gate trenches are formed on the front side of the substrate using a second etching process, wherein the depth of the first gate trench is less than the depth of the second gate trench, and paired first gate trenches and paired second gate trenches are arranged in an alternating manner. A conformal first gate oxide layer and a conformal second gate oxide layer are formed respectively in the plurality of first gate trenches and the plurality of second gate trenches using an oxidation process; and Polysilicon is deposited over the first gate oxide layer using a deposition process to form paired short-channel trench gate MOS, and polysilicon is deposited over the second gate oxide layer to form paired long-channel trench gate MOS.

8. The method for fabricating an insulated-gate bipolar transistor device according to claim 7, characterized in that, Before forming a SiO2 dielectric layer on the front side of the substrate and patterning the SiO2 dielectric layer into a contact trench mask, the following steps are also included: A first oxide layer is formed on the front side of the substrate; The first oxide layer is etched using a first oxide etching process to remove the first portion of the first oxide layer between the paired short-channel trench gate MOS and to remove the second portion of the first oxide layer between the long-channel trench gate MOS and the short-channel trench gate MOS. A second P-well region and a third P-well region with a depth of 1-3 μm are prepared on the front side of the substrate by multiple P-type ion implantation processes; A second oxide layer is formed above the second P-well region and the third P-well region, wherein the second oxide layer and the remaining first oxide layer are used as mask oxide layers. The mask oxide layer is etched using a second oxide etching process to remove the portion of the mask oxide layer between the paired long-channel trench gate MOS; A first P-well region with a depth of 3-7 μm is prepared on the front side of the substrate by multiple P-type ion implantation processes; A third oxide layer is formed above the first P-well region, wherein the third oxide layer and the remaining oxide layer are used as a newer mask oxide layer. The updated mask oxide layer is etched using a third oxide etching process to remove a portion of the oxide adjacent to the long-channel trench gate MOS and the short-channel trench gate MOS in the updated mask oxide layer in the first P-well region and the second P-well region; and An N-well region is prepared on the first P-well region and the second P-well region by an N-type ion implantation process. The N-well region includes a first N-well region located above the first P-well region and a second N-well region located above the second P-well region, wherein the depth of the first N-well region is the same as the depth of the second N-well region.

9. The method for fabricating an insulated-gate bipolar transistor device according to claim 7, characterized in that, Ion implantation of the first contact trench and the second contact trench to form a first emitter region and a second emitter region, respectively, includes: performing a P+ ion implantation process on the front side of the substrate using a patterned contact trench mask to form a first P+ well region below the bottom surface of the first contact trench as the first emitter region and a second P+ well region below the bottom surface of the second contact trench as the second emitter region, wherein the depth of the first emitter region is the same as the depth of the second emitter region; and Depositing metal on the front side of the substrate to form an emitter ohmic contact region includes: depositing metal in a first contact trench and a second contact trench on the front side of the substrate using a patterned contact trench mask through a metal deposition process to form a first ohmic contact portion, wherein the first ohmic contact portion includes a first emitter contact element that is in contact with the first emitter region and a second emitter contact element that is in contact with the second emitter region; and continuing to deposit metal above the front side of the substrate to form a second ohmic contact portion.

10. The method for fabricating an insulated-gate bipolar transistor device according to claim 9, characterized in that, The N-type buffer zone, collector region, and collector ohmic contact region are sequentially formed above the back side of the substrate, including: An N-type buffer was fabricated on the back side of a substrate using a multiple ion implantation process, wherein the doping level of the N-type buffer was 1 × 10⁻⁶. 16 cm -3 -1×10 18 cm -3 The thickness of the N-type buffer is 3-10 μm; A P+ collector region is fabricated on the back side of the substrate using a P+ ion implantation process, wherein the P+ doping level of the collector region is 1 × 10⁻⁶. 18 cm -3 -1×10 20 cm -3 The thickness of the current collector region is 0.5-2 μm; and An ohmic collector contact region is formed on the back side of the substrate using a metal deposition process.

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