Vcsel chip, method of manufacturing the same, and vcsel wafer

Abstract

VCSEL chip, its preparation method and VCSEL wafer, wherein the VCSEL chip comprises a plurality of VCSEL light emitting units integrally connected, wherein each VCSEL light emitting unit has a light emitting hole, wherein at least part of the light emitting holes are arranged in such a way that the arrangement direction of one light emitting hole and another light emitting hole most adjacent to it deviates from the lattice extension direction of the VCSEL chip, thereby blocking the diffusion path of epitaxial defects between adjacent light emitting units, so as to reduce the proportion of dark spots.

Description

Technical Field

[0001] This application relates to the field of semiconductor lasers, and more specifically to VCSEL chips, their fabrication methods, and VCSEL wafers. Background Technology

[0002] In recent years, VCSEL (Vertical-Cavity Surface-Emitting Laser) has been widely used in optical communication, optical storage, and optical interconnects, due to its characteristics such as easy fiber coupling, low power consumption, and good dynamic single-mode performance.

[0003] VCSELs typically consist of multiple light-emitting points forming a VCSEL array. The performance of each light-emitting point affects the overall performance of the VCSEL array. In practical applications, if more than 1% of the light-emitting points in a VCSEL array are substandard dark spots, it will significantly impact the overall performance of the VCSEL array.

[0004] Specifically, in the VCSEL molding process, if the final luminescent dots have epitaxial defects (e.g., poor alignment, voids, impurities), their performance is affected, failing to meet the preset standards and becoming dark defects. Furthermore, during subsequent burn-in testing (i.e., accelerated aging testing), these epitaxial defects are prone to propagation, causing more luminescent dots to become dark defects, thus increasing the proportion of dark defects.

[0005] More specifically, during the VCSEL molding process, the epitaxial structure of the light-emitting points is affected by various factors. Correspondingly, the causes of epitaxial defects are complex and diverse. For example, in a VCSEL light-emitting unit with an oxide-confined layer, the oxide-confined layer is formed by selectively oxidizing the P-DBR layer. The unoxidized portion of the reflective layer forms the confinement aperture of the oxide-confined layer, while the peripheral portion of the reflective layer is oxidized, forming the oxidized portion of the oxide-confined layer located around the confinement aperture. The confinement aperture of the oxide-confined layer corresponds to the light-emitting aperture formed by the ohmic contact layer. The current density at the edge of the confinement aperture is relatively high, and the lattice size of the confinement aperture and the oxidized portion of the oxide-confined layer are inconsistent, resulting in stress between the confinement aperture and the oxidized portion of the oxide-confined layer, thus causing epitaxial defects at the oxide-confined layer. Furthermore, these epitaxial defects may diffuse to other structural layers and then to other light-emitting points. During subsequent burn-in testing, under the influence of thermal stress, these epitaxial defects will further diffuse, forming more dark spots.

[0006] Figure 1The illustration shows a lattice extension method for a 100P VCSEL wafer in the prior art. Figure 2 The diagram shows... Figure 1 The diagram illustrates the arrangement of 60 P VCSEL light-emitting units and the distribution of dark spots in a 100P VCSEL wafer of the prior art. Figure 2 Multiple dots represent multiple VCSEL light-emitting units. The light-emitting points in the dashed circle have lower whiteness and are dark dead pixels (70P).

[0007] The lattice marker 101P indicates the lattice extension direction. When the lattice extension direction of the substrate of the VCSEL light-emitting unit 60P is a first direction and a second direction that are perpendicular to each other, that is... Figure 1 When the VCSEL light-emitting units 60P are arranged in the horizontal and vertical directions, and each VCSEL light-emitting unit 60P is arranged along a first and second direction that are perpendicular to each other, that is, the arrangement of each VCSEL light-emitting unit 60P is the same as the lattice extension direction of the substrate of the VCSEL light-emitting unit 60P, after a VCSEL light-emitting unit 60P becomes a dark spot 70P due to an epitaxial defect, the epitaxial defect of the VCSEL light-emitting unit 60P is likely to extend along the first or second direction, causing multiple VCSEL light-emitting units 60P in the first or second direction to generate epitaxial defects, forming dark spots 70P arranged along the first or second direction. For example, in Figure 2 In the middle, dark spot 70P extends along the direction perpendicular to the second direction.

[0008] Figure 3 The illustration shows another lattice extension method for a 100P VCSEL wafer in the prior art. Figure 4 The diagram shows... Figure 3 The diagram shows the arrangement of 60 P VCSEL light-emitting units and the distribution of dark spots in a 100P VCSEL wafer. Figure 4 Multiple white dots represent multiple VCSEL light-emitting units 60P. The light-emitting dots in the dashed circle have lower whiteness, or even appear black, and are dark dead dots 70P.

[0009] When the lattice extension direction of the substrate of the VCSEL light-emitting unit 60P, namely the first direction of 45° and the second direction of 135° extending obliquely in the figure, is the same as the arrangement of the VCSEL light-emitting units 60P, after one VCSEL light-emitting unit 60P becomes a dark spot 70P due to epitaxial defects, the epitaxial defects of the VCSEL light-emitting unit 60P are prone to extend along the lattice extension direction, causing multiple VCSEL light-emitting units 60P in the lattice extension direction to generate epitaxial defects, forming dark spots 70P arranged along the lattice extension direction. For example Figure 4 As shown, the dark spot 70P extends along the same inclined direction as the first direction. Figure 2 and Figure 4 The example illustrates that changing the direction of lattice extension also changes the direction of dark spot 70P, indicating that dark spot 70P extends along the lattice direction.

[0010] Currently, to address the aforementioned problems, high-temperature annealing is mainly used to reduce the stress between the oxidized portion of the oxide confinement layer and the confinement holes, thereby reducing epitaxial defects between the oxideized portion of the oxide confinement layer and the confinement holes. However, this method has little effect on reducing epitaxial defects and thus the number of dark spots. Alternatively, ion implantation can be used to change the location of areas with high current density. Specifically, ion implantation forms a high-resistivity region at the edge of the confinement holes, altering the current density distribution and shifting the location of the highest current density from the edge of the confinement holes to other areas. However, this method not only increases costs, but the ions implanted into the luminescent points may also create another type of defect, which is difficult to control in actual production. Summary of the Invention

[0011] One advantage of this application is that it provides a VCSEL chip, a method for fabricating the same, and a VCSEL wafer, wherein the VCSEL chip provides a solution for reducing the proportion of dark defects, thereby improving its overall performance.

[0012] Another advantage of this application is that it provides a VCSEL chip, a method for fabricating the same, and a VCSEL wafer, wherein the VCSEL chip can block the diffusion path of epitaxial defects between individual light-emitting points, thereby reducing the proportion of dark spots.

[0013] Another advantage of this application is that it provides a VCSEL chip, a method for fabricating the same, and a VCSEL wafer, wherein the VCSEL chip can block the diffusion path of epitaxial defects between multiple light-emitting points by changing the arrangement of multiple light-emitting points.

[0014] Another advantage of this application is that it provides a VCSEL chip, its fabrication method, and a VCSEL wafer. The solution for reducing dark spots provided by the VCSEL chip described in this application is not only applicable to scenarios where epitaxial defects caused by stress between different parts of the oxide confinement layer lead to dark spots, but also applicable to scenarios where epitaxial defects caused by other reasons lead to dark spots. In other words, the solution for reducing dark spots provided by the VCSEL chip described in this application provides a solution to the problem of dark spots caused by epitaxial defects caused by various reasons.

[0015] Another advantage of this application is that it provides a VCSEL chip, a method for fabricating the same, and a VCSEL wafer, which minimizes or avoids the number of light-emitting holes along the lattice direction to reduce the number or proportion of dark spots, and can further change the location of heat accumulation to increase heat dissipation uniformity.

[0016] Another advantage of this application is that it provides a VCSEL chip, its fabrication method, and a VCSEL wafer. The VCSEL chip can still use the existing VCSEL chip fabrication process during the fabrication process. Only the positional relationship between the semiconductor epitaxial structure used to form the VCSEL chip and the mask needs to be changed during production, or a specific mask needs to be used to change the arrangement of multiple light-emitting points. In this way, the original VCSEL wafer production line and equipment can be retained as much as possible for the fabrication of the VCSEL wafer of this application, effectively reducing the cost of modifying the VCSEL wafer production line, and thus reducing the fabrication cost of the VCSEL wafer.

[0017] To achieve at least one of the above advantages or other advantages and objectives, according to one aspect of this application, a VCSEL chip is provided, comprising:

[0018] Multiple VCSEL light-emitting units are integrally connected, wherein each VCSEL light-emitting unit has a light-emitting hole, and at least some of the light-emitting holes are arranged such that the arrangement direction of one light-emitting hole and its adjacent other light-emitting hole is deviated from the lattice extension direction of the VCSEL chip.

[0019] According to some embodiments, each VCSEL light-emitting unit includes a substrate layer, a first reflective layer, an active region, a confinement layer with light-emitting holes, and a second reflective layer, wherein the lattice extension direction is consistent with the lattice extension direction of the substrate layer, and the arrangement direction of one of the light-emitting holes and its adjacent other light-emitting hole forms an angle with the lattice extension direction.

[0020] According to some embodiments, the plurality of light-emitting holes of the plurality of VCSEL light-emitting units are arranged in a regular array, and the arrangement direction of two adjacent light-emitting holes deviates from the lattice extension direction.

[0021] According to some embodiments, the plurality of light-emitting holes of the plurality of VCSEL light-emitting units are arranged in an irregular discrete pattern, wherein at least some of the light-emitting holes have an angle between the arrangement direction of one light-emitting hole and its adjacent other light-emitting hole and the lattice extension direction, thereby deviating from the lattice extension direction.

[0022] According to some embodiments, the lattice extension direction includes a first direction and a second direction that are perpendicular to each other, wherein the arrangement direction of one of the light-emitting holes and the other light-emitting hole adjacent to it is the extension direction of the line connecting their centers and extends along a third direction that has an angle with both the first direction and the second direction.

[0023] According to some embodiments, in some of the light-emitting holes, at least three adjacent light-emitting holes are arranged to extend along an arc direction.

[0024] According to some embodiments, in some of the light-emitting holes, a plurality of light-emitting holes are arranged along a circumferential direction to form an annular light-emitting hole group, wherein two adjacent light-emitting holes in the annular light-emitting hole group are closest in position and their arrangement directions are not in the lattice extension direction.

[0025] According to some embodiments, in some of the light-emitting holes, the polygonal shape formed by the center line connecting four or more adjacent light-emitting holes is different from the shape of the lattice of the VCSEL chip.

[0026] According to some embodiments, the lattice of the VCSEL chip is a cube, wherein in some of the light-emitting holes, the center line connecting four adjacent light-emitting holes forms an irregular quadrilateral, which is different from the shape of the lattice of the VCSEL chip and makes the arrangement direction of at least two adjacent light-emitting holes deviate from the extension direction of the lattice of the VCSEL chip.

[0027] According to some embodiments, the shape of the lattice of the substrate layer is selected from one of the following shapes: cube, octahedron, and dodecahedron.

[0028] The present invention also provides a VCSEL chip, wherein the VCSEL chip has a plurality of light-emitting holes, wherein at least a portion of the plurality of light-emitting holes includes the following:

[0029] First light-emitting hole;

[0030] A second light-emitting hole adjacent to the first light-emitting hole, wherein a first spacing exists between the first light-emitting hole and the second light-emitting hole; and

[0031] A third light-emitting hole that is closest to the first light-emitting hole along the extension direction of the VCSEL chip lattice, wherein there is a second spacing between the first light-emitting hole and the third light-emitting hole, wherein the second spacing is greater than the first spacing.

[0032] According to some embodiments, the second spacing is greater than the first spacing between any two adjacent light-emitting holes in the plurality of light-emitting holes.

[0033] The present invention also provides a VCSEL wafer, comprising:

[0034] A plurality of VCSEL light-emitting units are integrally connected, wherein each VCSEL light-emitting unit has a light-emitting aperture, and at least some of the light-emitting apertures are arranged such that the arrangement direction of one light-emitting aperture and its adjacent light-emitting aperture is offset from the lattice extension direction of the VCSEL chip; and

[0035] Lattice identifier used to indicate the direction of lattice extension.

[0036] According to some embodiments, the lattice is identified as a notched structure, and the outer edge of the notched structure is aligned with the lattice extension direction.

[0037] This invention also provides a method for fabricating a VCSEL chip, comprising the following steps:

[0038] (a) Forming a semiconductor epitaxial structure including a substrate layer, a first reflective layer, an active region, a confinement layer, and a second reflective layer; and

[0039] (b) The confinement layer is oxidized to form a plurality of light-emitting holes, and at least some of the light-emitting holes are arranged such that the arrangement direction of one light-emitting hole and its adjacent other light-emitting hole is deviated from the lattice extension direction of the substrate layer.

[0040] According to some embodiments, the fabrication method includes the steps of: generating a relative rotation angle between the semiconductor epitaxial structure and the mask used for photolithography or ion etching to control the arrangement of the finally formed multiple VCSEL units, and after step (b), causing the arrangement direction of two adjacent light-emitting holes in the finally formed regular light-emitting hole array to be misaligned and deviated from the lattice extension direction.

[0041] According to some embodiments, the fabrication method includes the steps of: performing photolithography or ion etching on the semiconductor epitaxial structure through a mask with a preset pattern, wherein the preset pattern is configured to control the arrangement of the multiple VCSEL units ultimately formed, and after step (b), the multiple light-emitting holes formed are arranged irregularly and discretely, and at least a portion of the light-emitting holes and their adjacent light-emitting holes are arranged in a direction that deviates from the lattice extension direction of the substrate layer.

[0042] The further objectives and advantages of this application will become fully apparent from the following description and accompanying drawings. Attached Figure Description

[0043] These and / or other aspects and advantages of this application will become clearer and more readily understood from the following detailed description of embodiments of this application taken in conjunction with the accompanying drawings, wherein:

[0044] Figure 1 The illustration shows a schematic diagram of a lattice extension method for a VCSEL wafer in the prior art.

[0045] Figure 2 The diagram shows Figure 1 The diagram illustrates the arrangement of light-emitting points and the distribution of dark spots on a conventional VCSEL wafer.

[0046] Figure 3 The illustration shows another lattice extension method for existing VCSEL wafers.

[0047] Figure 4 The diagram shows Figure 3 The diagram illustrates the arrangement of light-emitting points and the distribution of dark spots on a conventional VCSEL wafer.

[0048] Figure 5 The illustration shows a schematic diagram of a VCSEL wafer according to an embodiment of this application.

[0049] Figure 6 The figure shows a three-dimensional schematic diagram of a lattice of the substrate layer of a VCSEL chip according to an embodiment of the present application.

[0050] Figure 7 The illustration shows a three-dimensional schematic diagram of another lattice of the substrate layer of a VCSEL chip according to an embodiment of this application.

[0051] Figure 8 The illustration shows a three-dimensional schematic diagram of another lattice of the substrate layer of a VCSEL chip according to an embodiment of this application.

[0052] Figure 9 The diagram illustrates the relationship between the lattice extension method and the arrangement of light-emitting points in a conventional VCSEL wafer.

[0053] Figure 10A The illustration shows a schematic diagram of the relationship between the lattice extension mode and the arrangement mode of the light-emitting points of the VCSEL wafer according to an embodiment of this application.

[0054] Figure 10B yes Figure 10A A magnified view of a portion of point A in the middle.

[0055] Figure 11A The illustration shows a schematic diagram of the arrangement of light-emitting points on a VCSEL wafer according to another specific example of an embodiment of this application.

[0056] Figure 11B yes Figure 11A A magnified view of a portion of point B in the middle.

[0057] Figure 12A The illustration shows a schematic diagram of the arrangement of light-emitting points on a VCSEL wafer in another specific example according to an embodiment of this application.

[0058] Figure 12B yes Figure 12A A magnified view of a portion of point C in the middle.

[0059] Figure 13A The illustration shows a schematic diagram of the arrangement of light-emitting points on a VCSEL wafer in another specific example according to an embodiment of this application.

[0060] Figure 13B yes Figure 13A A magnified view of a portion of point D in the middle.

[0061] Figure 14A The illustration shows a schematic diagram of the arrangement of light-emitting points on a VCSEL wafer in another specific example according to an embodiment of this application.

[0062] Figure 14B yes Figure 14A A magnified view of a portion of point E in the middle.

[0063] Figure 15 The figure shows a partial cross-sectional schematic diagram of a VCSEL chip according to an embodiment of this application. Detailed Implementation

[0064] The terms and words used in the following specification and claims are not limited to their literal meaning, but are used solely by the inventors to enable a clear and consistent understanding of this application. Therefore, it will be apparent to those skilled in the art that the following description of various embodiments of this application is provided for illustrative purposes only and not for the purpose of limiting this application as defined in the appended claims and their equivalents.

[0065] It is understood that the term "a" should be understood as "at least one" or "one or more", that is, in one embodiment, the number of an element can be one, while in another embodiment, the number of the element can be multiple, and the term "a" should not be understood as a limitation on the number.

[0066] While ordinal numbers such as "first," "second," etc., will be used to describe various components, there is no limitation on which components are used herein. The term is used only to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the teachings of this application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0067] The terminology used herein is for the purpose of describing various embodiments only and is not intended to be limiting. As used herein, the singular form also includes the plural form, unless the context clearly indicates otherwise. It will also be understood that the terms “comprising” and / or “having” as used in this specification specify the presence of the described features, numbers, steps, operations, components, elements or combinations thereof, without excluding the presence or addition of one or more other features, numbers, steps, operations, components, elements or groups thereof.

[0068] Application Overview

[0069] As mentioned above, in the VCSEL molding process, if the final luminescent dots have epitaxial defects (e.g., poor alignment, voids, impurities), their performance is affected, and they cannot meet the preset standards, becoming dark defects. Furthermore, during subsequent burn-in testing (i.e., accelerated aging testing), these epitaxial defects are prone to propagation, causing more luminescent dots to become dark defects, thus increasing the proportion of dark defects.

[0070] Currently, to address the aforementioned problems, high-temperature annealing is mainly used to reduce the stress between the oxidized portion of the oxide confinement layer and the confinement holes, thereby reducing epitaxial defects between the oxideized portion of the oxide confinement layer and the confinement holes. However, this method has little effect on reducing epitaxial defects and thus the number of dark spots. Alternatively, ion implantation can be used to change the location of areas with high current density. Specifically, ion implantation forms a high-resistivity region at the edge of the confinement holes, altering the current density distribution and shifting the location of the highest current density from the edge of the confinement holes to other areas. However, this method not only increases costs, but the ions implanted into the luminescent points may also create another type of defect, which is difficult to control in actual production.

[0071] The inventors of this application propose that the problem of dark spots caused by epitaxial defects can be solved in two ways or a combination of the following two ways: the first way is to solve the problem at its source, that is, to reduce epitaxial defects; the second way is to block or prolong the diffusion path of epitaxial defects.

[0072] Currently, existing technologies primarily address the problem of dark spots caused by epitaxial defects through the first method. However, due to the complex and diverse causes of epitaxial defects, and the fact that the morphology of epitaxial structures is influenced by multiple factors and is difficult to control, solving the problem of dark spots caused by epitaxial defects through the first method is quite challenging.

[0073] The second method for solving dark spot problems caused by epitaxial defects does not require excessive attention to the cause of the epitaxial defects, is easier to implement, and is applicable to dark spot problems caused by epitaxial defects caused by various different reasons, thus having a wide range of applications.

[0074] Based on this, this application proposes to prevent the diffusion of epitaxial defects between light-emitting points by blocking the diffusion path of epitaxial defects between them, thereby reducing the number or proportion of dark spots. Specifically, the inventors of this application have observed that the formation of dark spots in existing VCSEL chips follows a certain pattern, typically appearing continuously along a specific direction. Furthermore, the inventors of this application have found that this pattern is mainly related to the lattice extension direction of each light-emitting point. More specifically, since the light-emitting points are interconnected, epitaxial defects diffuse along the lattice extension direction of the interconnected portions of the light-emitting points, and the extension direction of dark spots is consistent with the lattice extension direction of the interconnected portions of the light-emitting points.

[0075] Accordingly, according to one aspect of this application, a VCSEL chip is proposed, comprising: a plurality of VCSEL light-emitting units integrally connected, wherein each of the VCSEL light-emitting units has a light-emitting hole, wherein at least some of the light-emitting holes are arranged such that the arrangement direction of one light-emitting hole and its adjacent other light-emitting hole is deviated from the lattice extension direction of the VCSEL chip.

[0076] After introducing the basic principles of this application, various non-limiting embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0077] Schematic VCSEL wafer and VCSEL chip

[0078] like Figures 5 to 15 As shown, a VCSEL wafer 100 and a VCSEL chip 30 according to an embodiment of this application are illustrated, wherein the VCSEL wafer 100 includes at least one chip formation region 10. The VCSEL wafer 100 has at least one dicing channel 20 formed around the chip formation region 10, such as... Figure 5 As shown. During the fabrication of the VCSEL chip 30, the VCSEL wafer 100 is diced along the dicing path 20, and each diced chip forming region 10 forms a VCSEL chip 30. That is, the VCSEL chip 30 is formed from the diced chip forming regions 10 cut from the VCSEL wafer 100. Accordingly, the structure of each chip forming region 10 of the VCSEL wafer 100 is the same as the structure of the VCSEL chip 30.

[0079] Specifically, each of the chip forming regions 10 (or each VCSEL chip 30) includes a plurality of VCSEL light-emitting units 60, wherein a portion of the structure of at least one VCSEL light-emitting unit 60 is integrally connected to a portion of the structure of at least one other VCSEL light-emitting unit 60. In this way, these VCSEL light-emitting units 60 are integrally connected, and the integral connection of two adjacent VCSEL light-emitting units 60 forms an integral connection portion of the VCSEL light-emitting unit 60.

[0080] More specifically, in the embodiments of this application, such as Figure 15 As shown, each VCSEL light-emitting unit 60 includes a light-emitting body and an electrical connection structure electrically connected to the light-emitting body. The light-emitting body, from bottom to top, includes: a substrate layer 611, a first reflective layer 612, an active region 613, a confinement layer 614 with a confinement hole 601, and a second reflective layer 615. Each VCSEL light-emitting unit correspondingly has a light-emitting hole 610, which corresponds to the position of the confinement hole 601. That is, the confinement hole 601 formed by the oxidation of the confinement layer 614 forms the light-emitting hole 610 of the corresponding VCSEL light-emitting unit. The light-emitting hole 610 refers to the unoxidized, light-emitting portion in the middle of the confinement layer 614. The first reflective layer 612 and the second reflective layer 615 are implemented as distributed Bragg mirrors. The first reflective layer 612 is implemented as an N-DBR layer, and the second reflective layer 615 is implemented as a P-DBR layer, or the first reflective layer 612 is implemented as a P-DBR layer, and the second reflective layer 615 is implemented as an N-DBR layer.

[0081] The N-DBR layer is composed of N-type doped Al with high aluminum content. x Ga 1-x As (x = 1 to 0) and N-type doped low-aluminum Al x Ga 1-x Alternating layers of As (x = 1 to 0) are formed. The P-DBR layer is composed of p-type doped Al with high aluminum content. x Ga 1-x As (x = 1 to 0) and P-type doped low-aluminum Al x Ga 1-x Alternating layers of As (x = 1 to 0) are formed. In some examples of this application, the materials used to make the N-DBR layer and the P-DBR layer may even contain no aluminum, that is, no aluminum is included.

[0082] The active region 613 is sandwiched between the first reflective layer 612 and the second reflective layer 615 to form a resonant cavity, in which photons are repeatedly amplified by reflection within the resonant cavity after being excited to form laser oscillation, thereby forming a laser.

[0083] The first reflective layer 612 and the second reflective layer 615 are configured such that after the VCSEL light-emitting unit 60 is turned on, the laser generated by the active region 613 is reflected multiple times in the resonant cavity formed between the first reflective layer 612 and the second reflective layer 615 and then emitted from the first reflective layer 612 or the second reflective layer 615.

[0084] The confinement layer 614 has a confinement hole 601 and a confinement region 602 surrounding the confinement hole 601. The confinement region 602 has a high resistivity so that when the VCSEL light-emitting unit 60 is turned on, the current flow is confined by the confinement layer 614, and charge carriers flow into the confinement hole 601 of the VCSEL light-emitting unit 60, thereby causing the portion of the active region 613 opposite to the confinement layer 614 to generate laser light. Furthermore, the confinement region 602 has a low refractive index to laterally confine photons. This carrier and optical lateral confinement increases the density of charge carriers and photons within the active region 613, improving the efficiency of light generation within the active region 613.

[0085] In some embodiments of this application, the confinement layer 614 is implemented as an oxide confinement layer, which is formed above or below the active region 613 by an oxidation process. In other embodiments of this application, the confinement layer 614 may be implemented as other types, for example, as an ion confinement layer, which is formed above or below the active region 613 by an ion planting process, and this is not limited to this application.

[0086] In this embodiment, the electrical connection structure of each VCSEL light-emitting unit 60 includes a first electrically conductive layer 61 electrically connected to the light-emitting body and a first electrode 63 electrically connected to the first electrically conductive layer 61, as well as a second electrically conductive layer 62 electrically connected to the light-emitting body and a second electrode 64 electrically connected to the second electrically conductive layer 62. The first electrically conductive layer 61 is a P-type ohmic contact layer structure, the second electrically conductive layer 62 is an N-type ohmic contact layer structure, the first electrode 63 is a positive electrode, and the second electrode 64 is a negative electrode; alternatively, the first electrically conductive layer 61 is an N-type ohmic contact layer structure, the second electrically conductive layer 62 is a P-type ohmic contact layer structure, the first electrode 63 is a negative electrode, and the second electrode 64 is a positive electrode.

[0087] The first electrically conductive layer 61 and / or the second electrically conductive layer 62 may be sandwiched within the light-emitting body or formed on the surface of the light-emitting body; this is not limited to this application. In one specific example of this application, the first electrically conductive layer 61 is sandwiched between the substrate layer 611 and the first reflective layer 613. In another specific example of this application, the first electrically conductive layer 61 is located below the substrate layer 611.

[0088] It is worth mentioning that in the VCSEL molding process, if the final VCSEL light-emitting unit 60 has epitaxial defects, its performance will be affected, failing to meet the preset standards and becoming a dark defect. Furthermore, during subsequent burn-in testing, these epitaxial defects are prone to propagation, causing more VCSEL light-emitting units 60 to become dark defects, i.e., increasing the proportion of dark defects.

[0089] The inventors of this application propose that the problem of dark spots caused by epitaxial defects can be solved in two ways or a combination of the following two ways: the first way is to solve the problem at its source, that is, to reduce epitaxial defects; the second way is to block or prolong the diffusion path of epitaxial defects.

[0090] Currently, existing technologies primarily address dark spot problems caused by epitaxial defects through the first method. However, due to the complex and diverse causes of epitaxial defects, and the fact that the morphology of epitaxial structures is influenced by multiple factors and is difficult to control, solving the problem through the first method is quite challenging. The second method, on the other hand, does not require excessive focus on the causes of epitaxial defects, is easier to implement, and is applicable to dark spot problems caused by epitaxial defects from various reasons, thus having a wider range of applications.

[0091] Based on this, this application proposes to prevent the diffusion of epitaxial defects between VCSEL light-emitting units 60 by blocking the diffusion path of epitaxial defects between each VCSEL light-emitting unit 60, thereby reducing the number or proportion of dark spots. Specifically, the inventors of this application have observed that the formation of dark spots in existing VCSEL chips follows a certain pattern, typically appearing continuously along a specific direction. Furthermore, the inventors of this application have found that the above-mentioned pattern is mainly related to the lattice extension direction of each VCSEL light-emitting unit 60. More specifically, when the VCSEL light-emitting units 60 are interconnected, epitaxial defects diffuse along the lattice extension direction of the interconnection portion (i.e., the integral connection portion), and the extension direction of dark spots is consistent with the lattice extension direction of the integral connection portion.

[0092] For example, in some embodiments of this application, the confinement layer 614 is implemented as an oxide confinement layer, and the confinement region 602 of the oxide confinement layer is formed by oxidizing the first reflective layer 612 or the second reflective layer 615 and is located around the confinement hole 601. The current density at the edge of the confinement hole 601 of the oxide confinement layer is large, and the lattice size of the confinement hole 601 and the confinement region 602 are inconsistent, resulting in stress between the confinement hole 601 and the confinement region 602, which may lead to epitaxial defects at the oxide confinement layer. Furthermore, the epitaxial defects of the oxide confinement layer of one VCSEL light-emitting unit 60 may diffuse to other layer structures (e.g., the first reflective layer 612, the second reflective layer 615, the substrate layer 611) and diffuse along the lattice extension direction of the integral connection between it and another VCSEL light-emitting unit 60 to another VCSEL light-emitting unit 60, and diffuse continuously in sequence.

[0093] Furthermore, the inventors of this application have discovered that in existing VCSEL chips, such as Figures 1 to 4 As shown, each of the VCSEL light-emitting units 60P is arranged along the lattice extension direction. Since epitaxial defects diffuse along the lattice extension direction of each VCSEL light-emitting unit 60P, the arrangement of the VCSEL light-emitting units 60P places them along the diffusion path of the epitaxial defects. Consequently, if one VCSEL light-emitting unit 60P becomes a dark spot due to its epitaxial defects, these defects can easily diffuse to other VCSEL light-emitting units 60P arranged along its diffusion path.

[0094] In this application, by changing the arrangement of the VCSEL light-emitting units 60, at least a portion of the light-emitting holes 610 are arranged such that the arrangement direction of the light-emitting hole 610 of one VCSEL light-emitting unit 60 and the light-emitting hole 610 of its adjacent other VCSEL light-emitting unit 60 deviates from the lattice extension direction of the VCSEL chip, that is, the lattice extension direction of the integral connection portion of each VCSEL light-emitting unit 60. Then, the arrangement direction of these two adjacent VCSEL light-emitting units 60 deviates from the diffusion path of epitaxial defects, and the diffusion path of epitaxial defects between these two adjacent VCSEL light-emitting units 60 is blocked, thereby reducing the number or proportion of dark spots.

[0095] In this application, the arrangement direction of the light-emitting aperture 610 of one VCSEL light-emitting unit 60 and the light-emitting aperture 610 of its adjacent other VCSEL light-emitting unit 60 refers to the extension direction of the line connecting the centers of the two light-emitting apertures 610. It is understood that, in a preferred embodiment, all the light-emitting apertures 610 are arranged in the manner described above to block the diffusion path of epitaxial defects.

[0096] Figure 9 The diagram illustrates the relationship between the lattice extension of a 100P VCSEL wafer and the arrangement of the 610P light-emitting holes in a 60P VCSEL light-emitting unit. Figure 10A and Figure 10B The illustration shows a schematic diagram of the relationship between the lattice extension mode of a VCSEL wafer 100 and the arrangement mode of the light-emitting points 60 in an embodiment of this application. Figure 9 In this context, the lattice extension of the VCSEL wafer 100P and the arrangement of the light-emitting holes 610P of the multiple VCSEL light-emitting units 60P are consistent. Figure 10A and Figure 10B In this context, the lattice extension of the VCSEL wafer 100 and the arrangement of the multiple VCSEL light-emitting units 60 are inconsistent, but rather relative to... Figure 9 These VCSEL light-emitting units 60 are offset by 45 degrees as a whole.

[0097] More specifically, in Figure 10A and Figure 10B In the illustrated embodiment of this application, the lattice extension of the VCSEL wafer 100 and the VCSEL chip 30 is inconsistent with the arrangement of the light-emitting holes 610 of the plurality of VCSEL light-emitting units 60. These light-emitting holes 610 are arranged in an array, and there is an angle between the arrangement direction of two adjacent light-emitting holes 610 of the VCSEL light-emitting units 60 integrally connected to each other and the lattice extension direction of their integral connection portion; that is, the angle between the arrangement direction of the light-emitting holes 610 of the VCSEL light-emitting units 60 and the lattice extension direction of their integral connection portion is not equal to 0 degrees or 180 degrees. The specific value of this angle is not limited to this application; for example, 10 degrees, 30 degrees, 45 degrees, 60 degrees, 105 degrees, 120 degrees, 135 degrees, 150 degrees, etc. In this embodiment, each chip forming region 10 optionally forms an isolation trench between every two adjacent VCSEL light-emitting units 60, the isolation trench extending recessedly from the upper surface of the VCSEL light-emitting unit 60 to the underside of the active region 613. Accordingly, at least a portion of the underside of the active region 613 of every two adjacent VCSEL light-emitting units 60 is integrally connected.

[0098] In some embodiments of this application, the isolation trench extends to the first reflective layer 612, and the integral connection portion of the VCSEL light-emitting unit 60 includes a substrate layer 611 and the first reflective layer 612. The arrangement direction of two adjacent light-emitting holes 610 of the VCSEL light-emitting unit 60 forms an angle with the lattice extension direction of its first reflective layer 612 and / or the substrate layer 611. Thus, the arrangement direction of two adjacent VCSEL light-emitting units 60 deviates from the diffusion path of epitaxial defects, and after an epitaxial defect in the confinement layer 614 of one VCSEL light-emitting unit 60 extends to the first reflective layer 612 and / or the substrate layer 611, it is less likely to extend to another adjacent VCSEL light-emitting unit 60 that is not on the diffusion path of the epitaxial defect. In other embodiments of this application, the isolation layer may extend to the substrate layer 611, the integral connection portion includes the substrate layer 611, and the arrangement direction of the light-emitting holes 610 of the VCSEL light-emitting unit 60 forms an angle with the lattice extension direction of its substrate layer 611.

[0099] In this embodiment of the application, the substrate layer 611 and the first reflective layer 612 of the VCSEL light-emitting unit 60 are formed by an epitaxial growth process. The crystal axes of the substrate layer 611 and the first reflective layer 612 are aligned with each other, and the lattice extension direction of the first reflective layer 612 is aligned with the lattice extension direction of the substrate layer 611.

[0100] In this embodiment, the lattice shape of the substrate layer 611 is selected from one of the following shapes: cube, octahedron, and dodecahedron, such as... Figures 6 to 8 As shown. The lattice extension direction of the VCSEL chip 30 and each of the VCSEL light-emitting units 60 is determined by the shape of the lattice, such as a cube, octahedron, or dodecahedron. In a specific example of this application, the lattice shape of the substrate layer 611 is a cube, and the lattice of the substrate layer 611 extends along a first direction and / or along a second direction perpendicular to the first direction. Two adjacent VCSEL light-emitting units 60 extend along a straight line and along a third direction that forms an angle with both the first and second directions. The first direction is implemented as a horizontal direction, the second direction as a vertical direction, and the angle between the third direction and the first direction is implemented as 45 degrees.

[0101] That is, Figure 10A and Figure 10BIn the specific example shown, the lattice orientation of the VCSEL chip 30 is a first direction D1, schematically horizontal, and a second direction D2, schematically vertical. The extension direction of two adjacent light-emitting holes 610 of two adjacent VCSEL light-emitting units 60 is D3, which forms angles α and β with the first direction D1 and the second direction D2, respectively, and the angles α and β are each implemented as 45 degrees. The arrangement direction of two adjacent light-emitting holes 610 in these regularly arranged arrays deviates from the first direction D1 and the second direction D2 by forming an angle.

[0102] It is understandable that when the lattice shape is octahedral or dodecahedral, the arrangement direction of the light-emitting holes of two adjacent VCSEL light-emitting units 60 can be deviated from the lattice extension direction of the corresponding VCSEL chip 30, thereby blocking the epitaxial defect diffusion path.

[0103] It is worth mentioning that, in this specific example, Figure 9 When two adjacent VCSEL light-emitting units 60P are arranged in the same direction as the extension direction of the crystal lattice, the spacing between the light-emitting apertures 610P of the two adjacent VCSEL light-emitting units 60P is S0, that is... Figure 9 In existing technologies, the propagation path of epitaxial defects is S0. Figure 10A and Figure 10B In the VCSEL light-emitting unit 60, the spacing between the light-emitting apertures 610 along the lattice extension direction is S2, that is... Figure 10A and Figure 10B In the embodiments of this application, the diffusion path of the epitaxial defect is S2. It can be seen that S2 is significantly greater than S0, that is, Figure 10A and Figure 10B The arrangement of the VCSEL light-emitting units 60 in this way increases the diffusion path of the epitaxial defects of each VCSEL light-emitting unit 60, and reduces the number or proportion of dark spots.

[0104] In addition, it is understandable that Figure 10A and Figure 10B In the example, the VCSEL light-emitting unit 60 forms at least one first light-emitting hole 610a among the light-emitting holes 610 formed therein, wherein the distance between the first light-emitting hole 610a and its adjacent second light-emitting hole 610b is S1, and the distance between the first light-emitting hole 610a and its nearest third light-emitting hole 610c along the extension direction of the crystal lattice is S2, wherein S2 is greater than S1, i.e. Figure 10AThe arrangement of at least some of the light-emitting holes 610 increases the diffusion path of the epitaxial defects of the corresponding VCSEL light-emitting unit 60, thereby reducing the number or proportion of dark spots, and can further change the position of heat accumulation to increase heat dissipation uniformity.

[0105] like Figures 11A to 14B As shown, in other specific examples of embodiments of this application, these VCSEL light-emitting units 60 are not similar Figure 10A Instead of forming a regular array, the light-emitting holes 610 of these VCSEL light-emitting units 60 can be arranged irregularly, that is, the light-emitting holes 610 of these VCSEL light-emitting units 60 can be randomly and discretely distributed, and their arrangement avoids being arranged along their lattice extension direction. Similarly, at least some of the light-emitting holes 610 of these VCSEL light-emitting units 60 are arranged such that the arrangement direction of the light-emitting hole 610 of one VCSEL light-emitting unit 60 and the light-emitting hole 610 of its adjacent other VCSEL light-emitting unit 60 deviates from the lattice extension direction, thereby blocking the diffusion path of epitaxial defects.

[0106] refer to Figure 11B , 12B As shown in Figures 13B and 14B, the lattice orientation of the VCSEL chip 30 is a first direction D1, schematically horizontal, and a second direction D2, schematically vertical. The extension direction of the two adjacent light-emitting holes 610 of two adjacent VCSEL light-emitting units 60 is D3, and the angles between D3 and the first direction D1 and the second direction D2 are α and β, respectively, and the angles α and β can each be acute or obtuse. At least some of these irregularly and discretely arranged light-emitting holes 610 have an angle with the arrangement direction D3 of their nearest neighbor light-emitting holes 610, thus deviating from the first direction D1 and the second direction D2.

[0107] In addition, some of the VCSEL light-emitting units 60 are arranged in such a way that the light-emitting holes 610 of three adjacent VCSEL light-emitting units 60 are arranged along an arc direction. In this way, the diffusion path of epitaxial defects between the three adjacent VCSEL light-emitting units 60 is blocked, thereby reducing the number or proportion of dark spots.

[0108] exist Figures 11A to 14B In the example shown, a plurality of light-emitting holes 610 of some of the VCSEL light-emitting units 60 are arranged along a circular circumferential direction to form an annular light-emitting hole group 6100A. The two adjacent light-emitting holes 610 in the annular light-emitting hole group 6100A are closest to each other and their arrangement directions are not in the lattice extension direction. It can be understood that the annular arrangement of the annular light-emitting hole group 6100A can be either circular or elliptical.

[0109] Understandably, in Figures 11A to 14B In the example shown, the lattice cross-section is square, and the plurality of light-emitting holes 610 of some of the VCSEL light-emitting units 60 are arranged as follows: the line connecting the centers of four adjacent light-emitting holes 610 forms an irregular quadrilateral 6100B, that is, the lengths of the sides of the quadrilateral are not equal and are not parallel, thus differing from the square shape of the lattice cross-section. After translation, the irregular quadrilateral 6100B cannot coincide with the square of the lattice cross-section. This makes at least two adjacent light-emitting holes 610 in the irregular quadrilateral 6100B the closest to each other and their arrangement direction is not in the lattice extension direction.

[0110] It is understood that the circles, ellipses and irregular quadrilaterals formed by connecting the multiple light-emitting holes 610 are only examples. In reality, they can be various other shapes, as long as they are different from the crystal lattice shape and do not overlap, so that the positions of two adjacent light-emitting holes 610 in some of the light-emitting holes 610 are closest and their arrangement direction is not in the crystal lattice extension direction.

[0111] exist Figures 11A to 14B In the example, the light-emitting holes 610 formed by the VCSEL light-emitting unit 60 also include at least a first light-emitting hole 610a. The distance between the first light-emitting hole 610a and its adjacent second light-emitting hole 610b is a first distance S1, and the distance between the first light-emitting hole 610a and its nearest third light-emitting hole 610c along the extension direction of the crystal lattice is a second distance S2, where S2 is greater than S1. That is, at least part of the arrangement of the light-emitting holes 610 increases the diffusion path of the epitaxial defects of the corresponding VCSEL light-emitting unit 60. In other words, given the same number of light-emitting holes 610, compared with the conventional regular arrangement of light-emitting holes along the crystal lattice direction, the arrangement of the present application can minimize or reduce the number of light-emitting holes 610 encountered along the crystal lattice direction, thereby reducing the number or proportion of dark spots, and can further change the position of heat accumulation to increase heat dissipation uniformity. It is understood that the second light-emitting hole 610b can be any light-emitting hole adjacent to the first light-emitting hole 610a, and not just the light-emitting hole closest to the first light-emitting hole 610a.

[0112] In this embodiment, the VCSEL wafer 100 includes a lattice marker 101 for indicating the lattice extension direction of the VCSEL wafer 100. The specific implementation of the lattice marker 101 is not limited to this application. For example, in one specific example, the lattice marker 101 is implemented as a notch structure, the outer edge of which coincides with the lattice extension direction of the VCSEL wafer 100. Specifically, the notch structure is formed at the edge of the VCSEL wafer 100, recessed inward from the outer edge. For example, when the lattice is cubic, it forms a right-angled notch. The right-angled notch has a first outer edge aligned with the first direction and a second outer edge aligned with the second direction, the first and second directions being perpendicular to each other. The notch structure can also serve a positioning function during the fabrication or testing of the VCSEL wafer 100. As another example, in another specific example, the lattice marker 101 is implemented as a marking line.

[0113] In summary, the VCSEL wafer 100 and the VCSEL chip 30 based on the embodiments of this application are explained, and the VCSEL wafer 100 provides a solution to reduce the proportion of dark defects, thereby improving its overall performance.

[0114] Schematic fabrication method of VCSEL chip

[0115] According to another aspect of this application, a method for fabricating a VCSEL chip 30 is also provided, which is used to fabricate the VCSEL chip 30 as described above. The method for fabricating the VCSEL chip 30 according to embodiments of this application is illustrated with reference to the accompanying drawings. It is worth mentioning that, in the embodiments of this application, the existing VCSEL chip 30 fabrication process can still be used in the fabrication process of the VCSEL chip 30. Only the positional relationship between the semiconductor epitaxial structure used to form the VCSEL chip 30 and the mask needs to be changed during production, or a specific mask needs to be used to change the arrangement of the multiple VCSEL light-emitting units 60. In this way, the original VCSEL chip 30 production line and equipment can be retained as much as possible for fabricating the VCSEL chip 30 of this application, effectively reducing the cost of modifying the VCSEL chip 30 production line, and thus reducing the fabrication cost of the VCSEL chip 30.

[0116] In this embodiment, the method for fabricating the VCSEL chip 30 includes: forming a substrate structure, a first conductive layer structure, a first reflective layer structure, an active region structure, a confinement layer structure, and a second reflective layer structure; S120, removing at least a portion of the semiconductor epitaxial structure to form a plurality of sub-unit structures, each sub-unit structure including a substrate layer 611, a first conductive layer 61, a first reflective layer 612, an active region 613, a confinement layer 614, and a second reflective layer 615; S130, forming a plurality of second conductive layers 62 on the plurality of sub-unit structures; S140, oxidizing the confinement layer 614 of the plurality of sub-unit structures to form an oxide confinement layer with light-emitting holes 610, wherein at least a portion of the light-emitting holes 610 are arranged such that the arrangement direction of one light-emitting hole 610 and its adjacent other light-emitting hole 610 deviates from the lattice extension direction of the substrate layer 611.

[0117] In step S110, a semiconductor epitaxial structure is formed. Specifically, a substrate structure, a first electrically conductive layer structure, a first reflective layer structure, an active region structure, and a second reflective layer structure are formed by an epitaxial growth process. The first electrically conductive layer structure is a P-type electrical contact layer structure, the first reflective layer structure is a P-DBR layer structure, and the second reflective layer structure is an N-DBR layer structure. It is understood that the semiconductor epitaxial structure may also optionally include other layer structures, such as a buffer layer disposed between the substrate layer and the first reflective layer.

[0118] In step S120, at least a portion of the semiconductor epitaxial structure is removed to form a plurality of sub-unit structures. Specifically, the semiconductor epitaxial structure is subjected to photolithography or ion etching to expose the etchable layer through a mask with a preset pattern, thereby removing a portion of the etchable layer based on the preset pattern. The portion of the etchable layer corresponding to the preset pattern is removed, and the retained portion of the etchable layer forms a template with a preset shape and size.

[0119] In this embodiment, by removing at least a portion of the semiconductor epitaxial structure, an isolation trench can be formed extending downwards from the upper surface of the semiconductor epitaxial structure to below the active region 613, such that at least a portion below the active region 613 of at least two of the resulting plurality of sub-unit structures is integrally connected. Specifically, the semiconductor epitaxial structure can be etched using exposure and etching processes to form a trench of a predetermined depth. A non-metallic isolation layer can be further deposited in subsequent processes into the aforementioned trench.

[0120] In this embodiment, at least two of the sub-unit structures, the substrate layer 611 and / or the first reflective layer 612, are integrally connected. A portion of the light-emitting holes 610 and their adjacent light-emitting holes 610 are arranged at an angle to the lattice extension direction of the substrate layer 611, and / or at an angle to the lattice extension direction of the first reflective layer 612. Thus, the arrangement direction of the final VCSEL light-emitting units 60 will be at an angle to the lattice extension direction of the substrate layer 611 and / or the first reflective layer 612. Correspondingly, two adjacent VCSEL light-emitting units 60 can deviate from the diffusion direction of epitaxial defects, reducing the number or proportion of dark spots and improving the overall performance of the final VCSEL chip 30.

[0121] The arrangement direction of two adjacent light-emitting holes 610 can be at an angle to the lattice extension direction of the substrate layer 611, and / or the arrangement direction of two adjacent light-emitting holes 610 can be at an angle to the lattice extension direction of the first reflective layer 612. For example, compared to the fabrication process of existing VCSEL chips, the positional relationship between the semiconductor epitaxial structure and the mask can be adjusted, or the pattern of the mask can be changed.

[0122] Accordingly, in a specific example of this application, compared to the fabrication process of existing VCSEL chips, the overall placement of the semiconductor epitaxial structure is adjusted. Specifically, compared to the placement of the semiconductor epitaxial structure in the fabrication process of existing VCSEL chips, it is only necessary to rotate the semiconductor epitaxial structure by a preset angle to adjust the positional relationship between the semiconductor epitaxial structure and the mask to complete the photolithography or ion etching process. This ensures that the arrangement direction of the two adjacent light-emitting holes 610 formed by the final oxidation confinement layer 614 process has an angle with the lattice extension direction of the substrate layer 611, and / or an angle with the lattice extension direction of the first reflective layer 612, and ultimately, a... Figure 10A The VCSEL chip 30 shown is shown.

[0123] In another specific example of this application, compared to the existing VCSEL chip fabrication process, the placement of the first mask with a first preset pattern is adjusted. Specifically, compared to the semiconductor placement in the existing VCSEL chip fabrication process, only the first mask needs to be rotated by a preset angle to adjust the positional relationship between the semiconductor epitaxial structure and the mask, and ultimately, a [missing information - likely a specific pattern or design] can be fabricated. Figure 10A The VCSEL chip 30 shown is shown.

[0124] By adjusting the positional relationship between the semiconductor epitaxial structure and the mask, the fabrication process of VCSEL chips can be achieved without changing the mask, compared to the existing technology. Alternatively, the mask can be replaced while adjusting the positional relationship between the semiconductor epitaxial structure and the mask, replacing the first mask with a first preset pattern with a second mask with a second preset pattern to obtain the desired result. Figures 11A to 14B The VCSEL chip 30 shown is shown.

[0125] In another specific example of this application, the pattern of the mask is changed compared to the fabrication process of the existing VCSEL chip. Specifically, the arrangement of the multiple VCSEL light-emitting units 60 formed in the etching process is controlled by a second mask with a second preset pattern. After the corresponding light-emitting holes 610 are formed in the confinement layer 614, the arrangement direction of a portion of the light-emitting holes 610 and its adjacent light-emitting hole 610 forms an angle with the lattice extension direction of the substrate layer 611, and / or with the lattice extension direction of the first reflective layer 612. The first preset pattern of the first mask is different from the second preset pattern of the second mask.

[0126] In step S130, multiple second conductive layers 62 are formed on the multiple sub-unit structures respectively. Specifically, when the first conductive layer structure is a P-type ohmic contact layer structure (correspondingly, the first conductive layer 61 is a P-type ohmic contact layer), the second conductive layer 62 is an N-type ohmic contact layer; when the first conductive layer structure is an N-type ohmic contact layer structure (correspondingly, the first conductive layer 61 is an N-type ohmic contact layer), the second conductive layer 62 is a P-type ohmic contact layer.

[0127] In step S140, the plurality of sub-unit structures are oxidized to form an oxidized confinement layer having a confinement hole 601, i.e., the light-emitting hole 610. Specifically, the plurality of sub-unit structures can be oxidized by an oxidation process, such that a portion of the first reflective layer 612 or a portion of the second reflective layer 615 is oxidized to form an oxidized confinement layer above or below the active region 613.

[0128] The confinement layer 614 can also be formed by other processes. For example, an ion confinement layer can be formed above or below the active region 613 by an ion planting process. This is not limited to the present application.

[0129] In some embodiments of this application, the method for fabricating the VCSEL chip 30 further includes: S150, forming a first electrode 63 electrically connected to the first conductive layer 61 and a second electrode 64 electrically connected to the second conductive layer 62. Specifically, at least a portion of the first conductive layer 61 is exposed, and the first electrode 63 electrically connected to the first conductive layer 61 is formed by an electroplating process, the first electrode 63 extending outward from the exposed portion of the first conductive layer 61. The second electrode 64 electrically connected to the second conductive layer 62 is formed on the upper surface of the second conductive layer 62 by an electroplating process.

[0130] In some embodiments of this application, a VCSEL wafer 100 including at least one chip formation region 10 can be obtained through steps S110 to S150. The VCSEL wafer 100 has at least one dicing channel 20 located around the chip formation region 10. Each chip formation region 10 includes a plurality of integrally connected VCSEL light-emitting units 60, each VCSEL light-emitting unit 60 having a light-emitting aperture 610, wherein at least some of the light-emitting apertures 610 are arranged such that the arrangement direction of one light-emitting aperture 610 and its adjacent other light-emitting aperture 610 is offset from the lattice extension direction of the VCSEL chip 30. Each VCSEL light-emitting unit 60 includes, from bottom to top: a substrate layer 611, a first reflective layer 612, an active region 613, an oxide confinement layer 614 with a confinement aperture 601, and a second reflective layer 615. The VCSEL wafer 100 can be diced along the dicing path 20 to separate at least one chip forming region 10 from the VCSEL wafer 100, thereby forming at least one VCSEL chip 30. Accordingly, in some embodiments of this application, the fabrication process of the VCSEL chip 30 further includes: S160, dicing the VCSEL wafer 100 along the dicing path 20 to separate at least one chip forming region 10 from the VCSEL wafer 100, thereby forming at least one VCSEL chip 30.

[0131] In summary, the fabrication method of VCSEL chip 30 based on the embodiments of this application has been clarified, and the VCSEL chip 30 provides a solution to reduce the proportion of dark spots, thereby improving its overall performance.

[0132] It should be noted that in the apparatus and method of this application, the components or steps in different embodiments can be disassembled and / or recombined without departing from the principle of the present invention. These disassemblies and / or recombinations should be considered as included within the inventive concept of this application.

[0133] The basic principles of this application have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this application are merely examples and not limitations, and should not be considered as essential features of each embodiment of this application. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the application to the necessity of employing the aforementioned specific details for implementation.

Claims

1. A VCSEL chip, characterized in that, include: Multiple VCSEL light-emitting units are integrally connected, wherein each VCSEL light-emitting unit has a light-emitting hole, and at least some of the light-emitting holes are arranged in such a way that the arrangement direction of one light-emitting hole and its adjacent other light-emitting hole is deviated from the lattice extension direction of the VCSEL chip; The VCSEL chip has a square lattice cross-section; in some of the light-emitting holes, the center line connecting four adjacent light-emitting holes forms an irregular quadrilateral, which is different from the shape of the VCSEL chip lattice and makes the arrangement direction of at least two adjacent light-emitting holes deviate from the extension direction of the VCSEL chip lattice. The plurality of light-emitting holes include a first light-emitting hole, wherein the distance between the first light-emitting hole and its nearest second light-emitting hole is a first distance, and the distance between the first light-emitting hole and its nearest third light-emitting hole along the extension direction of the lattice is a second distance, wherein the second distance is greater than the first distance.

2. The VCSEL chip according to claim 1, wherein each VCSEL light-emitting unit includes a substrate layer, a first reflective layer, an active region, a confinement layer with light-emitting holes, and a second reflective layer, wherein the lattice extension direction is consistent with the lattice extension direction of the substrate layer, and the arrangement direction of one of the light-emitting holes and its adjacent other light-emitting hole forms an angle with the lattice extension direction.

3. The VCSEL chip according to claim 1, wherein the lattice extension direction includes a first direction and a second direction that are perpendicular to each other, and the arrangement direction of one of the light-emitting holes and the other light-emitting hole adjacent to it is the extension direction of the line connecting their centers and extends along a third direction that has an angle with both the first direction and the second direction.

4. The VCSEL chip according to claim 1, wherein in a portion of the light-emitting holes, at least three adjacent light-emitting holes are arranged extending along an arc direction.

5. The VCSEL chip according to claim 1, wherein in some of the light-emitting holes, a plurality of light-emitting holes are arranged along a circumferential direction to form an annular light-emitting hole group, wherein two adjacent light-emitting holes in the annular light-emitting hole group are closest in position and their arrangement directions are not in the lattice extension direction.

6. A VCSEL wafer, characterized in that, Includes at least one chip forming region, each of the at least one chip forming region including: A plurality of VCSEL light-emitting units are integrally connected, wherein each VCSEL light-emitting unit has a light-emitting aperture, wherein at least some of the light-emitting apertures are arranged such that the arrangement direction of one light-emitting aperture and its adjacent light-emitting aperture deviates from the lattice extension direction of the chip formation region; the lattice cross-section of the chip formation region is square; wherein in some of the light-emitting apertures, the center line connecting four adjacent light-emitting apertures forms an irregular quadrilateral; the plurality of light-emitting apertures include a first light-emitting aperture, wherein the distance between the first light-emitting aperture and its adjacent second light-emitting aperture is a first distance, and the distance between the first light-emitting aperture and its adjacent third light-emitting aperture along the lattice extension direction is a second distance, wherein the second distance is greater than the first distance; and Lattice identifier used to indicate the direction of lattice extension.

7. The VCSEL wafer according to claim 6, wherein, The lattice is identified as a notched structure, and the outer edge of the notched structure is consistent with the extension direction of the lattice.

8. A method for fabricating a VCSEL chip, characterized in that, Including the following steps: (a) Forming a semiconductor epitaxial structure including a substrate layer, a first reflective layer, an active region, a confinement layer, and a second reflective layer; and (b) The confinement layer forms a plurality of light-emitting holes and at least some of the light-emitting holes are arranged such that the arrangement direction of one light-emitting hole and its adjacent other light-emitting hole is deviated from the lattice extension direction of the substrate layer; The substrate layer has a cubic lattice shape; in some of the light-emitting holes, the center line connecting four adjacent light-emitting holes forms an irregular quadrilateral. The plurality of light-emitting holes include a first light-emitting hole, wherein the distance between the first light-emitting hole and its nearest second light-emitting hole is a first distance, and the distance between the first light-emitting hole and its nearest third light-emitting hole along the extension direction of the lattice is a second distance, wherein the second distance is greater than the first distance.

9. The method for fabricating a VCSEL chip according to claim 8, comprising the steps of: generating a relative rotation angle between the semiconductor epitaxial structure and the mask used for photolithography or ion etching to control the arrangement of the finally formed plurality of VCSEL units, and after step (b), causing the arrangement direction of two adjacent light-emitting holes in the finally formed regular light-emitting hole array to be misaligned and deviated from the lattice extension direction.

10. The method for fabricating a VCSEL chip according to claim 8, comprising the steps of: performing photolithography or ion etching on the semiconductor epitaxial structure through a mask having a preset pattern, wherein the preset pattern is configured to control the arrangement of the plurality of VCSEL units finally formed, and after step (b), the plurality of light-emitting holes formed are arranged irregularly and discretely, and at least a portion of the light-emitting holes and their adjacent light-emitting holes are arranged in a direction that deviates from the lattice extension direction of the substrate layer.

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