Hybrid modular multilevel converter capacitor voltage balancing control method

Abstract

The present application relates to the technical field of multi-level converter, and discloses a kind of hybrid modular multi-level converter capacitor voltage equalization control method, first determine the total energy of sub-module is adjusted by controlling the pulse width and conduction time of direction switch, according to the key voltage and current waveform under the control of direction switch conduction angle, obtain the conduction signal of direction switch, and calculate the conduction angle for maintaining HMC capacitor voltage balance;Finally, considering AC symmetric / asymmetric fault, determine the closed-loop control strategy based on the conduction angle of direction switch, including: grid-connected control link, capacitor total energy balance control link and single sub-module capacitor voltage balance control link.The present application controls the energy balance of sub-module capacitor based on the conduction angle of direction switch, not only has full regulation system and full four-quadrant operation ability, and the switch of converter also has uniform loss and heat consumption, even under low regulation system or low power factor condition, can greatly reduce the fluctuation of sub-module capacitor voltage.

Description

Technical Field

[0001] This invention relates to the field of multilevel converter technology, specifically to a method for capacitor voltage equalization control of a hybrid modular multilevel converter. Background Technology

[0002] With the rapid development and widespread application of renewable energy, long-distance DC transmission systems for new energy sources have received increasing attention. Flexible converters, as a key component for voltage transformation, have their size and cost being crucial performance indicators.

[0003] The half-bridge modular multilevel converter (HB-MMC), widely used in traditional flexible DC transmission systems, boasts advantages such as simple structure and high modularity. However, the HB-MMC relies on two sets of bridge arms outputting different voltages to create a potential difference between the midpoint and neutral point of the bridge arms for energy transfer. Consequently, the utilization rate of the sub-modules is only half. Furthermore, since the bridge arm current carries 1 / 3 DC current and 1 / 2 AC current, the sub-module capacitor value needs to be relatively large to suppress significant energy fluctuations. Therefore, the HB-MMC performs poorly in terms of size and cost, making it difficult to meet the increasingly robust demands of new energy power conversion station construction.

[0004] To address the aforementioned issues, some researchers have proposed a hybrid multilevel converter (HMC) topology. This topology combines a two-level directional switch composed of series-connected IGBTs with cascaded full-bridge submodules, resulting in higher submodule utilization, lower capacitor energy fluctuations, and the ability to self-clear DC faults. Therefore, it offers significant advantages in construction cost and size compared to the traditional HB-MMC.

[0005] However, unlike traditional HB-MMC where the upper and lower bridge arms are connected in parallel with the DC side, HMC's full-bridge submodules are alternately connected in series with the DC side via directional switches. This results in a completely different energy balance mode compared to traditional HB-MMC, rendering the traditional HB-MMC submodule capacitor voltage equalization control method unsuitable for HMC. Therefore, HMC currently still faces the technical challenge of difficult capacitor voltage equalization control.

[0006] There is limited research on capacitor voltage balance control methods for HMCs both domestically and internationally. The main reason is that HMCs cannot establish an energy balance channel with the DC side, making capacitor voltage balance control difficult to achieve. Currently, the typical capacitor voltage balance control method for HMCs is based on the directional switch conduction pulse width. However, this method currently has the following drawbacks:

[0007] (1) Traditional methods can only support a narrow range of regulation operation and cannot be adapted to the large-scale temporary sag operation of AC power grid.

[0008] (2) In this control mode, when the system outputs pure inductive / capacitive reactive power, the steady-state operating point of the control quantity is not unique, which will cause the control method to fail to maintain capacitor voltage balance (i.e., the HMC under this control method cannot operate in four quadrants).

[0009] (3) This method will result in uneven switching times in the up and down directions and unequal maximum positive and negative voltages of the cascaded H-bridge modules, leading to different loss distribution, heat distribution and lifespan of the switches, which will reduce the reliability of the system.

[0010] (4) As the modulation or power factor decreases, the capacitor voltage fluctuation under the traditional method will increase sharply, which will affect the system stability under the condition of a large voltage drop in the grid. Summary of the Invention

[0011] To address the aforementioned problems, the present invention aims to provide a hybrid modular multilevel converter capacitor voltage balancing control method. Based on the directional switch conduction angle control of the submodule capacitor's energy balance, this method not only possesses full regulation and full four-quadrant operation capabilities, but also ensures uniform losses and heat dissipation during converter switching. Even under low regulation or low power factor conditions, it can significantly reduce the voltage fluctuation of the submodule capacitors. The technical solution is as follows:

[0012] A hybrid modular multilevel converter capacitor voltage equalization control method includes the following steps:

[0013] Step 1: Determine the single-phase equivalent circuit of the HMC based on its topology. The HMC topology includes cascaded FBSMs consisting of N series-connected FBSM submodules, and N... DS S is an upward direction switch composed of series-connected IGBTs. uj and down direction switch S dj The subscript j = a, b, c represents the phase number; based on the instantaneous voltage values ​​of the submodule branch voltage and the submodule equivalent capacitor obtained from the single-phase equivalent circuit of the fixed HMC, the adjustment of the total energy of the submodule is determined by controlling the pulse width and conduction time of the directional switch.

[0014] Step 2: Based on the key voltage and current waveforms controlled by the directional switch conduction angle, obtain the conduction signal of the directional switch. Set the energy of the cascaded FBSMs to 0 in one fundamental cycle, and calculate the conduction angle to maintain the voltage balance of the HMC capacitor.

[0015] Step 3: Considering AC symmetrical / asymmetrical faults, determine the closed-loop control strategy based on the directional switch conduction angle, including:

[0016] 1) Grid connection control

[0017] During normal operation, the HMC uses the PQ power outer loop and the grid-connected current inner loop control in the dq coordinate system. When there is a symmetrical / asymmetrical fault on the AC side, the power outer loop switches to low voltage ride-through control and will reduce the active current reference and increase the reactive current reference according to the voltage sag depth. Under asymmetrical fault conditions, the negative sequence current inner loop is used to suppress the negative sequence component of the grid-connected current.

[0018] 2) Capacitor total energy balance control circuit

[0019] The sliding average value of the sum of the capacitor voltages of each phase submodule is selected as the feedback quantity to control the direction switch, thereby realizing the extraction of the change trend of the capacitor voltage of the submodule and the determination of the closed-loop control expression of the conduction angle.

[0020] 3) Individual submodule capacitor voltage balancing control circuit

[0021] When the number of submodules exceeds the set number, the nearest level modulation combined with capacitor voltage sorting control is used to switch the submodules to maintain the voltage of each submodule tending to be consistent; when the number of submodules is less than the set number, carrier phase shift modulation combined with modulation wave compensation control is used to correct the modulation wave of each submodule, thereby adjusting the energy change of each submodule to achieve the voltage of each submodule tending to be consistent.

[0022] Furthermore, step 1 specifically includes:

[0023] Step 1.1: Obtain the loop voltage equation according to Kirchhoff's laws:

[0024]

[0025] Among them, v Sj andi Sj L represents the mains current and voltage, respectively. f For the filter reactance on the AC side, v Oj V is the output voltage of the converter. SMj V is the branch voltage of the submodule. j The voltage at ports ABC;

[0026] Step 1.2: Define the mains voltage and current:

[0027]

[0028] In the formula, V m and I m These represent the amplitudes of voltage and current, respectively, and ω is the angular frequency of the power grid. θ is the power factor angle. j Let be the initial phase of the j-phase grid voltage;

[0029] Step 1.3: The submodule branch voltages of the cascaded FBSMs can be approximated as follows:

[0030]

[0031] In the formula, v DC S represents DC voltage. uj Indicates the upward direction switch;

[0032] Step 1.4: Calculate the instantaneous voltage value of the equivalent capacitance of the submodule.

[0033] According to the instantaneous power conservation on the AC and DC sides of cascaded FBSMs, we can obtain:

[0034]

[0035] In the formula, C eq For the equivalent capacitance of multiple submodules, v Cj This is the instantaneous voltage value of the equivalent capacitance of the submodule;

[0036] Integrating both sides of the above equation, we obtain the instantaneous voltage value of the equivalent capacitance of the submodule:

[0037]

[0038] In the formula: v Cj0 The initial voltage of the equivalent capacitance is given.

[0039] Furthermore, step 2 specifically includes:

[0040] Step 2.1: Represent the directional switch's on signal as:

[0041] S uj =~S dj =sgn(sin(ωt+θ) j -α j (6)

[0042] In the formula, S dj For downward direction switching; α j ∈[-π / 2,π / 2] represents the upward direction switch S. uj The conduction time lags behind the grid voltage of phase j by an angle, where j = a, b, c, representing the phase number; ω is the grid angular frequency, and θ is the phase angular frequency. j Let be the initial phase of the j-phase grid voltage;

[0043] If the pulse width of the directional switch remains constant at 50%, then the energy W of the cascaded FBSMs in phase a within one fundamental cycle is... SMa for:

[0044]

[0045] In the formula, The power factor angle is V. m and I m These are the amplitudes of voltage and current, respectively;

[0046] Step 2.2: Let W SMj =0, thus obtaining the conduction angle α that maintains the voltage balance of the HMC capacitor. j The value can be:

[0047]

[0048] In the formula, M j To adjust the system.

[0049] Furthermore, in step 3, the sliding average value of the sum of the capacitor voltages of each phase submodule in the capacitor total energy balance control loop is:

[0050]

[0051] Among them, v Cij Let represent the capacitor voltage of the i-th FBSM in the j-th phase, i = 1, 2, 3, ..., N; mean represents the moving average function.

[0052] When the proposed directional switch conduction angle control is used, the conduction angle α j The closed-loop control expression is:

[0053]

[0054] Where: K P1 and K I1 These are the proportional and integral parameters of the PI controller. This is used to reflect the effect of different current directions on the increase / decrease of the submodule capacitor voltage. Used to determine the sign of the conduction angle, V CN Let N be the moving average function, and N be the number of FBSMs in the cascaded FBSMs.

[0055] Furthermore, the specific implementation method of the individual submodule capacitor voltage balancing control link in step 3 includes:

[0056] 1) Nearest level approximation with capacitor voltage sorting

[0057] The reference modulation wave is multiplied by the number of sub-modules and then rounded to obtain the current number of modules n that should be deployed. j The control system collects the capacitor voltage V of each submodule. Cij and the branch voltage i of the cascaded submodule Sj When n j ≥0,iSj ≥0, positive input n j The FBSMs with the lowest capacitor voltage; when n j ≥0,i Sj <0, positive input n j The FBSMs with the highest capacitor voltage; when n j <0,i Sj ≥0, negative input -n j The FBSMs with the highest capacitor voltage; when n j <0,i Sj <0, negative input -n j The FBSMs with the lowest capacitor voltage;

[0058] 2) Carrier phase-shift modulation plus modulated wave compensation

[0059] The control system collects the capacitor voltage V of each submodule. Cij The process involves low-pass filtering, followed by calculating the average voltage of the submodule capacitors as a reference value. The difference between this reference value and the filtered value is then passed through a PI controller to obtain the control input. This control input is multiplied by sgn1(v * mj *i Sj ) and v * mj The modulation wave deviation Δv of the corresponding submodule is then obtained. mij After being added to the original modulated wave, the modulation signal reference v corresponding to each submodule is obtained. * mij Finally, the signal is sent to the phase-shift carrier modulator to generate the corresponding switching pulse signal.

[0060] The beneficial effects of this invention are as follows: The HMC capacitor voltage equalization control method proposed in this invention is based on the directional switch conduction angle. It has the capability of full regulation and full four-quadrant operation. The conduction time of the upper and lower bridge arms and the maximum positive and negative voltage output of the cascaded FBSMs are equal. Therefore, the converter switching has uniform loss and heat dissipation. Even under low regulation or low power factor conditions, the voltage fluctuation of the submodule capacitor is much smaller than that of traditional methods, thus having significant advantages. Attached Figure Description

[0061] Figure 1 This is a topology diagram of the HMC.

[0062] Figure 2 This is the equivalent circuit diagram of the single-phase fundamental frequency of the HMC.

[0063] Figure 3 This is a key waveform diagram of the system under the direction switch conduction angle control.

[0064] Figure 4 For different M j and condition α j The value of .

[0065] Figure 5(a) shows the HMC closed-loop capacitor voltage control strategy based on the directional switch conduction angle—grid-connected control loop.

[0066] Figure 5(b) shows the HMC closed-loop capacitor voltage control strategy based on the directional switch conduction angle—the capacitor total energy balance control loop.

[0067] Figure 5(c1) shows the HMC closed-loop capacitor voltage control strategy based on the directional switch conduction angle—single submodule capacitor voltage equalization control loop—NLM modulation combined with capacitor voltage sorting control.

[0068] Figure 5(c2) shows the HMC closed-loop capacitor voltage control strategy based on the directional switch conduction angle—single submodule capacitor voltage equalization control loop—CPS-PWM modulation combined with modulation wave compensation control. Detailed Implementation

[0069] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0070] This invention proposes a method for equalizing HMC capacitor voltage based on the conduction angle of a directional switch. Specifically, this invention includes the following:

[0071] 1. HMC Topology Description

[0072] HMC topology as follows Figure 1 As shown, each phase of the converter consists of two parts: N FBSMs (Full Bridge Sub-Modules) connected in series and N... DS S is a vertical direction switch composed of series-connected IGBTs. uj and S dj (j = a, b, c). Figure 1 In the middle, L f and L DC These are the filter reactances for the AC and DC sides, respectively. C SM and C f These are the submodule capacitor and the DC-side filter capacitor, respectively. DC and i DC These represent DC voltage and DC current, respectively; i uj andi dj These represent the current of the directional switches in the upper and lower bridge arms, respectively; v Sj andi Sj These represent the mains current and voltage, respectively. Oj V is the output voltage of the converter. j For the voltage at ports ABC, v SMj V is the branch voltage of the submodule.Cij (i = 1, 2, 3, ..., N) represents the capacitor voltage of the i-th FBSM in the j-th phase.

[0073] Figure 2 The single-phase equivalent circuit diagram of the HMC is shown. Figure 2 C eq =NC SM For the equivalent capacitance of multiple submodules, v Cj C eq The voltage of the loop. According to Kirchhoff's laws, the loop voltage equation is:

[0074]

[0075] The grid voltage and current are defined as follows:

[0076]

[0077] In the formula, V m and I m These represent the amplitudes of voltage and current, respectively, and ω is the angular frequency of the power grid. θ is the power factor angle. j Let be the initial phase of the j-phase grid voltage.

[0078] Due to the AC side filter reactance L f The voltage drop across is small, v Oj Approximately equal to v Sj In addition, the upward direction switch S uj and the down direction switch S dj Strict complementary conduction, when the upper direction switch S uj When the circuit is on, the voltage v at ports ABC is... j Equal to 0.5V DC When the up direction switch S uj When turned off, the voltage v at ports ABC j equal to -0.5V DC Therefore, the sub-module branch voltage v of cascaded FBSMs SMj It can be approximated as:

[0079]

[0080] According to the instantaneous power conservation on the AC and DC sides of cascaded FBSMs, we can obtain:

[0081]

[0082] Integrating both sides of the above equation, we can obtain the instantaneous voltage value of the equivalent capacitance of the submodule:

[0083]

[0084] In the formula: v Cj0 The initial voltage of the equivalent capacitance is given.

[0085] To maintain capacitor voltage / energy balance, the integral term in equation (5) (i.e., the total energy W of the submodule) needs to be guaranteed. SMj The integral value within one fundamental cycle is 0. Combining equation (3), it can be seen that the pulse width and conduction time of the control direction switch (i.e., the control of v) SMj It can adjust the total energy of the submodule.

[0086] 2. The novel energy balance principle of HMC

[0087] This invention proposes a submodule capacitor energy balance control method based on the directional switch conduction angle. The key voltage and current waveforms under directional switch conduction angle control are shown below. Figure 3 As shown, the on signal of the direction switch can be represented as:

[0088] S uj =~S dj =sgn(sin(ωt+θ) j -α j (6)

[0089] In the formula, α j ∈[-π / 2,π / 2] represents the direction switch S. uj The conduction time lags behind the voltage of phase j of the grid by an angle. The pulse width of the directional switch remains constant at 50%. Similarly, the energy W of the cascaded FBSMs of phase a within one fundamental cycle can be obtained. SMa for:

[0090]

[0091] Let W SMj =0, so the conduction angle α that maintains the voltage balance of the HMC capacitor can be obtained. j The theoretical value under open-loop conditions is:

[0092]

[0093] Figure 4 Different M were shown j and condition α j The value of α can be observed. j polarity and They have the same polarity, α j The value of will vary depending on | The value decreases as | increases. HMC using directional switch conduction angle control can operate stably within a wide modulation range of [0, 4 / π]. For example, when a voltage dip in phase j of the grid causes a modulation index M... j When M1 changes to M2, α can be...j From α j1 Change to α j2 To maintain capacitor voltage balance.

[0094] 3. Closed-loop capacitor voltage equalization control strategy of HMC

[0095] To maintain capacitor voltage balance under conditions such as load changes, faults, parameter fluctuations, and controller errors, a closed-loop controller is needed to dynamically generate the conduction angle α. j This invention considers AC symmetrical / asymmetrical faults and proposes a closed-loop control strategy based on the conduction angle of the direction switch, as shown in Figures 5(a), 5(b), and 5(c1) and (c2), which includes the following three components.

[0096] A. Grid connection control stage

[0097] As shown in Figure 5(a), during normal operation, the HMC employs a PQ power outer loop and an inner loop control of the grid-connected current in the dq coordinate system. During AC-side symmetrical / asymmetrical faults, the power outer loop switches to low-voltage ride-through control. At this time, the active current reference is reduced and the reactive current reference is increased based on the voltage sag depth. Under asymmetrical fault conditions, a negative-sequence current inner loop is also used to suppress the negative-sequence component of the grid-connected current.

[0098] B. Capacitor Total Energy Balance Control Circuit

[0099] As shown in Figure 5(b), the overall energy balance of the capacitors is the foundation for achieving voltage balance among the capacitors of each submodule. Due to the alternating switching of the direction switches, the capacitor voltages of the submodules will exhibit irregular fluctuations of 100Hz. To extract the trend of the submodule capacitor voltage changes, the sliding average value of the sum of the capacitor voltages of each phase submodule can be selected as the feedback quantity to control the direction switches, i.e.:

[0100]

[0101] When the proposed directional switch conduction angle control is used, the conduction angle α j The closed-loop control expression is:

[0102]

[0103] Where: K P1 and K I1 These are the proportional and integral parameters of the PI controller. This is used to reflect the effect of different current directions on the increase / decrease of the submodule capacitor voltage. Used according to Figure 4 Determine the sign of the conduction angle.

[0104] Wherein, equation (8) is the conduction angle α jThe theoretical values ​​under open-loop conditions need to be dynamically obtained using equation (10) under closed-loop conditions. When the entire system is in steady state, the results of the two equations are close.

[0105] C. Individual Submodule Capacitor Voltage Balancing Control Circuit

[0106] Because of the adoption of total capacitor energy balance control, the total energy of the cascaded FBSMs will be maintained at 0 (i.e., reactive power is generated), which is a prerequisite for achieving capacitor voltage balance in a single submodule. Furthermore, when there are many submodules, nearest-level modulation combined with capacitor voltage sorting control can be used to flexibly switch submodules to maintain voltage consistency across all submodules. When there are few submodules, carrier phase-shift modulation combined with modulation wave compensation control can be used to correct the modulation wave of each submodule, thereby adjusting the energy change of each submodule to achieve voltage consistency across all submodules. Ultimately, capacitor voltage balance across all submodules will be achieved. The specific implementation method is as follows:

[0107] (1) Nearest level approximation with capacitor voltage sorting

[0108] As shown in Figure 5(c1), the reference modulation wave is multiplied by the number of sub-modules and then rounded to obtain the current number of modules n that should be deployed. j The control system collects the capacitor voltage V of each submodule. Cij and the branch voltage i of the cascaded submodule Sj When n j ≥0,i Sj ≥0, positive input n j The FBSMs with the lowest capacitor voltage; when n j ≥0,i Sj <0, positive input n j The FBSMs with the highest capacitor voltage; when n j <0,i Sj ≥0, negative input -n j The FBSMs with the highest capacitor voltage; when n j <0,i Sj <0, negative input -n j The FBSMs with the lowest capacitor voltage.

[0109] (2) Carrier phase-shift modulation plus modulating wave compensation

[0110] As shown in Figure 5(c2), the control system collects the capacitor voltage v of each submodule. Cij A low-pass filter is then applied, followed by the calculation of the average voltage across the submodule capacitors as a reference value. The difference between this reference value and the filtered value is then passed through a PI controller to obtain the control input. This control input is multiplied by sgn1(v * mj *iSj ) and v * mj The modulation wave deviation Δv of the corresponding submodule is then obtained. mij After being added to the original modulated wave, the modulation signal reference v corresponding to each submodule is obtained. * mij Finally, the signal is sent to the phase-shift carrier modulator to generate the corresponding switching pulse signal.

Claims

1. A method for equalizing capacitor voltage control in a hybrid modular multilevel converter, characterized in that, Includes the following steps: Step 1: Determine the single-phase equivalent circuit of the HMC based on its topology. The HMC topology includes cascaded FBSMs consisting of N series-connected FBSM submodules, and N... DS S is an upward direction switch composed of series-connected IGBTs. uj and down direction switch S dj The subscript j = a, b, c represents the phase number; based on the instantaneous voltage values ​​of the submodule branch voltage and the submodule equivalent capacitor obtained from the single-phase equivalent circuit of the fixed HMC, the adjustment of the total energy of the submodule is determined by controlling the pulse width and conduction time of the directional switch. Step 2: Based on the key voltage and current waveforms controlled by the directional switch conduction angle, obtain the conduction signal of the directional switch. Set the energy of the cascaded FBSMs to 0 in one fundamental cycle, and calculate the conduction angle to maintain the voltage balance of the HMC capacitor. Step 3: Considering AC symmetrical / asymmetrical faults, determine the closed-loop control strategy based on the directional switch conduction angle, including: 1) Grid connection control During normal operation, the HMC uses the PQ power outer loop and the grid current inner loop control in the dq coordinate system. When there is a symmetrical / asymmetrical fault on the AC side, the power outer loop switches to low voltage ride-through control and will reduce the active current reference and increase the reactive current reference according to the voltage sag depth. Under asymmetrical fault conditions, the negative sequence current inner loop is used to suppress the negative sequence component of the grid current. 2) Capacitor total energy balance control stage The sliding average value of the sum of the capacitor voltages of each phase submodule is selected as the feedback quantity to control the direction switch, thereby realizing the extraction of the change trend of the capacitor voltage of the submodule and the determination of the closed-loop control expression of the conduction angle. 3) Individual submodule capacitor voltage balancing control circuit When the number of submodules exceeds the set number, the nearest level modulation combined with capacitor voltage sorting control is used to switch the submodules to maintain the voltage of each submodule tending to be consistent; when the number of submodules is less than the set number, carrier phase shift modulation combined with modulation wave compensation control is used to correct the modulation wave of each submodule, thereby adjusting the energy change of each submodule to achieve the voltage of each submodule tending to be consistent.

2. The hybrid modular multilevel converter capacitor voltage equalization control method according to claim 1, characterized in that, Step 1 specifically involves: Step 1.1: Obtain the loop voltage equation according to Kirchhoff's laws: Among them, v Sj andi Sj L represents the mains current and voltage, respectively. f For the filter reactance on the AC side, v Oj This is the output voltage of the converter. v SMj V is the branch voltage of the submodule. j The voltage at ports ABC; Step 1.2: Define the mains voltage and current: In the formula, V m and I m These represent the amplitudes of voltage and current, respectively, and ω is the angular frequency of the power grid. θ is the power factor angle. j Let be the initial phase of the j-phase grid voltage; Step 1.3: The submodule branch voltages of the cascaded FBSMs can be approximated as follows: In the formula, v DC S represents DC voltage. uj Indicates the upward direction switch; Step 1.4: Calculate the instantaneous voltage value of the equivalent capacitance of the submodule. According to the instantaneous power conservation on the AC and DC sides of cascaded FBSMs, we can obtain: In the formula, C eq For the equivalent capacitance of multiple submodules, v Cj This is the instantaneous voltage value of the equivalent capacitance of the submodule; Integrating both sides of the above equation, we obtain the instantaneous voltage value of the equivalent capacitance of the submodule: In the formula: v Cj0 The initial voltage of the equivalent capacitance is given.

3. The hybrid modular multilevel converter capacitor voltage equalization control method according to claim 1, characterized in that, Step 2 specifically involves: Step 2.1: Represent the directional switch's on signal as: S uj =~S dj =sgn(sin(ωt+θ) j -a j )) (6) In the formula, S dj For downward direction switching; α j ∈[-π / 2,π / 2] represents the upward direction switch S. uj The conduction time lags behind the grid voltage of phase j by an angle, where j = a, b, c, representing the phase number; ω is the grid angular frequency, and θ is the phase angular frequency. j Let be the initial phase of the j-phase grid voltage; If the pulse width of the directional switch remains constant at 50%, then the energy W of the cascaded FBSMs in phase a within one fundamental cycle is... SMa for: In the formula, The power factor angle is V. m and I m These are the amplitudes of voltage and current, respectively; Step 2.2: Let W SMj =0, thus obtaining the conduction angle α that maintains the voltage balance of the HMC capacitor. j The theoretical value under open-loop conditions is: In the formula, M j To adjust the system.

4. The hybrid modular multilevel converter capacitor voltage equalization control method according to claim 1, characterized in that, In step 3, the total capacitor energy balance control loop, the sliding average value of the sum of the capacitor voltages of each phase submodule is: Among them, v Cij Let represent the capacitor voltage of the i-th FBSM in the j-th phase, i = 1, 2, 3, ..., N; mean represents the moving average function. When the proposed directional switch conduction angle control is used, the conduction angle α j The closed-loop control expression is: Where: K P1 K I1 These are the proportional and integral parameters of the PI controller. This is used to reflect the effect of different current directions on the increase / decrease of the submodule capacitor voltage. Used to determine the sign of the conduction angle, V CN Let N be the moving average function, and N be the number of FBSMs in the cascaded FBSMs.

5. The hybrid modular multilevel converter capacitor voltage equalization control method according to claim 1, characterized in that, The specific implementation methods of the individual submodule capacitor voltage equalization control link in step 3 include: 1) Nearest level approximation with capacitor voltage sorting The reference modulation wave is multiplied by the number of sub-modules and then rounded to obtain the current number of modules n that should be deployed. j The control system collects the capacitor voltage V of each submodule. Cij and the branch voltage i of the cascaded submodule Sj When n j ≥0,i Sj ≥0, positive input n j The FBSMs with the lowest capacitor voltage; when n j ≥0,i Sj <0, positive input n j The FBSMs with the highest capacitor voltage; when n j <0,i Sj ≥0, negative input -n j The FBSMs with the highest capacitor voltage; when n j <0,i Sj <0, negative input -n j The FBSMs with the lowest capacitor voltage; 2) Carrier phase-shift modulation plus modulated wave compensation The control system collects the capacitor voltage V of each submodule. Cij The process involves low-pass filtering, followed by calculating the average voltage of the submodule capacitors as a reference value. The difference between this reference value and the filtered value is then passed through a PI controller to obtain the control input. This control input is multiplied by sgn1(v * mj *i Sj ) and v * mj The modulation wave deviation Δv of the corresponding submodule is then obtained. mij After being added to the original modulated wave, the modulation signal reference v corresponding to each submodule is obtained. * mij Finally, the signal is sent to the phase-shift carrier modulator to generate the corresponding switching pulse signal.

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