Zero crossing comparison circuit and switching power supply

Abstract

This invention relates to a zero-crossing comparator circuit and a switching power supply. The zero-crossing comparator circuit includes a voltage sampling circuit, a first comparator circuit, and a second comparator circuit. The voltage sampling circuit samples the output voltage of the switching power supply and generates an offset current positively correlated with the output voltage. This offset current causes an offset voltage positively correlated with the output voltage to be generated at either the first or second comparator output of the first comparator circuit. The first comparator circuit generates a differential signal based on the comparison result between the voltage at the switching node and ground. The second comparator circuit then outputs a comparator signal based on the differential signal and the offset voltage. Therefore, when outputting the comparator signal, the zero-crossing comparator circuit compensates for the delay in the zero-crossing comparator circuit through the offset voltage. Compared to a fixed offset voltage compensation, this offset voltage is positively correlated with the output voltage and automatically follows different output voltages, adapting to a wider output voltage range. This allows for more precise control of the lower transistor's shutdown and reduces energy loss.

Description

Technical Field

[0001] This invention relates to the field of zero-crossing comparison, and in particular to a zero-crossing comparison circuit and a switching power supply. Background Technology

[0002] In the operation of a BUCK switching power supply, the inductor current of the lower transistor can flow from the inductor to ground, causing energy loss. Therefore, a zero-crossing detection circuit is needed to compare the voltage of the switching node with ground to determine the direction of the inductor current. When the inductor current is zero, the lower transistor is controlled to turn off by the drive circuit to prevent energy loss.

[0003] The zero-crossing comparator circuit uses two stages of operational amplifiers to compare the voltage at the switching node with ground. The two stages output a comparison signal. When the inductor current is zero, the comparison signal is high. However, due to parasitic capacitance at the output of the two stages of operational amplifiers, a delay occurs, causing the comparison signal to output a high-level signal after a certain period. To eliminate this delay, a fixed offset voltage can be added to the input of the zero-crossing comparator circuit to compensate for the delay. However, when the output voltage range of the switching power supply is relatively wide, the fixed offset voltage still cannot completely eliminate the delay, resulting in a lagging output comparison result. Consequently, it is impossible to accurately control the lower transistor to turn off, causing energy loss. Summary of the Invention

[0004] The present invention aims to provide a zero-crossing comparator circuit and a switching power supply that can adapt to a wider output voltage range, so that the offset voltage changes with the output voltage, thereby eliminating comparator delay, and thus accurately controlling the lower transistor to turn off and reducing energy loss.

[0005] To address the aforementioned technical problems, the embodiments of the present invention provide the following technical solutions:

[0006] In a first aspect, embodiments of the present invention provide a zero-crossing comparator circuit applied to a switching power supply, the switching power supply including a master transistor, a slave transistor, and an inductor, the common connection point of the master transistor, the slave transistor, and the inductor being a switching node, the zero-crossing comparator circuit including: a voltage sampling circuit, a first comparator circuit, and a second comparator circuit;

[0007] The voltage sampling circuit includes a first sampling terminal for receiving the output voltage of the switching power supply and a second sampling terminal connected to the load terminal of the first comparator circuit. The voltage sampling circuit is used to sample the output voltage and generate an offset current positively correlated with the output voltage at the second sampling terminal.

[0008] The first comparison circuit includes a first comparison input terminal for connecting the voltage of the switching node and a second comparison input terminal grounded, and also includes a first comparison output terminal and a second comparison output terminal connected to the first input terminal and the second input terminal of the second comparison circuit, respectively; the offset current causes the first or second comparison output terminal to generate an offset voltage positively correlated with the output voltage; the first comparison circuit is used to generate a differential signal based on the comparison result between the voltage of the switching node and ground and output it from the first and second comparison output terminals;

[0009] The second comparator circuit is used to generate a comparison signal based on the differential signal and the offset voltage, so as to output the comparison signal at the output terminal of the second comparator circuit.

[0010] In some embodiments, the voltage sampling circuit includes a current generation module and a mirror module;

[0011] The current generation module includes a first sampling terminal and a control output terminal connected to the input terminal of the mirror module. The current generation module is used to generate a feedback current that is positively correlated with the output voltage.

[0012] The mirroring module further includes a control terminal for receiving the control signal of the switching power supply and a second sampling terminal. The mirroring module is used to mirror the feedback current to generate the offset current and output the offset current under the control of the control signal.

[0013] In some embodiments, the current generation module includes a first comparator, a first MOSFET, and a first resistor;

[0014] The first MOSFET and the first resistor are connected in series between a voltage source and ground, and the common connection point of the first MOSFET and the first resistor is the clamping terminal;

[0015] The inverting input of the first comparator is the first sampling terminal, the non-inverting input is connected to the clamping terminal, and the output is the control output and connected to the gate of the first MOS transistor. The first comparator is used to clamp the voltage at the clamping terminal to the output voltage.

[0016] In some embodiments, the mirror module includes a second MOS transistor and a third MOS transistor connected in series between the voltage source and the second sampling terminal; the gate of the second MOS transistor is the control terminal of the mirror module, and the gate of the third MOS transistor is the input terminal of the mirror module.

[0017] The third MOSFET is used to mirror the feedback current to generate the offset current, and the second MOSFET is used to control whether the offset current is output.

[0018] In some embodiments, the mirror module includes a second MOS transistor and a third MOS transistor connected in series between the second sampling terminal and ground; the gate of the second MOS transistor is the control terminal of the mirror module, and the gate of the third MOS transistor is the input terminal of the mirror module.

[0019] The third MOSFET is used to mirror the feedback current to generate the offset current, and the second MOSFET is used to control whether the offset current is output.

[0020] In some embodiments, the first comparison circuit includes a first switching module, a comparison module, and a load module;

[0021] The first switching module includes a first comparison input terminal, a second terminal connected to the first input terminal of the comparison module, and a control terminal for receiving control signals from the switching power supply. The first switching module is used to switch the voltage connection between the first input terminal of the comparison module and the switching node or to ground.

[0022] The comparison module includes a second comparison input terminal, a first comparison output terminal, and a second comparison output terminal. The comparison module is used to generate the differential signal based on the comparison result between the voltage of the switching node and ground, and output it from the first comparison output terminal and the second comparison output terminal.

[0023] The load module includes an offset resistor, and the load terminal is connected to the offset resistor. The load module is used to generate the offset voltage based on the offset resistor according to the offset current, so as to apply the offset voltage to the first comparison output terminal or the second comparison output terminal of the comparison module.

[0024] In some embodiments, the first comparison circuit further includes a second switching module;

[0025] The second switching module includes a first terminal connected to the first comparison output terminal, a second terminal connected to the second comparison output terminal, and a control terminal for receiving control signals from the switching power supply. The second switching module is used to control the connection status of the first comparison output terminal and the second comparison output terminal of the comparison module.

[0026] In some embodiments, the first switching module includes a fourth MOSFET and a fifth MOSFET;

[0027] The source of the fourth MOS transistor is the first comparison input terminal, the common connection point of the gate of the fourth MOS transistor and the gate of the fifth MOS transistor is the control terminal of the first switching module, and the common connection point of the drain of the fourth MOS transistor and the drain of the fifth MOS transistor is the second terminal of the first switching module.

[0028] In some embodiments, the comparison module includes a first transistor, a second transistor, and a first current source;

[0029] One end of the first current source is used to connect to the DC power supply, and the other end of the first current source is connected to the emitter of the first transistor and the emitter of the second transistor respectively. The base of the first transistor serves as the first input terminal of the comparison module, and the collector of the first transistor serves as the first comparison output terminal.

[0030] The base of the second transistor is the second comparator input terminal, and the collector of the second transistor is the second comparator output terminal.

[0031] In some embodiments, the second switching module includes a sixth MOSFET;

[0032] The gate of the sixth MOS transistor is the control terminal of the second switching module, the source of the sixth MOS transistor is the first terminal of the second switching module, and the drain of the sixth MOS transistor is the second terminal of the second switching module.

[0033] In some embodiments, the offset current flows from the second sampling terminal to the load terminal, the load terminal is grounded through the offset resistor, and the load terminal is also connected to the second comparison output terminal; the load module further includes a balancing resistor connected between the first comparison output terminal and ground.

[0034] In some embodiments, the offset current flows from the load terminal to the second sampling terminal, the load terminal is connected to the first comparison output terminal through the offset resistor, and the load terminal is also grounded; the load module further includes a balancing resistor connected between the second comparison output terminal and ground.

[0035] In some embodiments, the second comparison circuit includes a second comparator and a seventh MOS transistor;

[0036] The non-inverting input of the second comparator is the first input, the inverting input of the second comparator is the second input, the output of the second comparator is connected to the drain of the seventh MOS transistor, and the output of the second comparator is used to output the comparison signal.

[0037] The gate of the seventh MOS transistor is used to receive the control signal of the switching power supply, and the source of the seventh MOS transistor is grounded.

[0038] In a second aspect, embodiments of the present invention provide a switching power supply, the switching power supply including an inductor, a higher-level transistor, a lower-level transistor, and a zero-crossing comparator circuit as described above.

[0039] In various embodiments of the present invention, the zero-crossing comparator circuit includes a voltage sampling circuit, a first comparator circuit, and a second comparator circuit. The voltage sampling circuit samples the output voltage of the switching power supply and generates an offset current positively correlated with the output voltage at its second sampling terminal. This offset current causes an offset voltage positively correlated with the output voltage to be generated at either the first or second comparator output terminal of the first comparator circuit. The first comparator circuit is further configured to generate a differential signal based on the comparison result between the voltage of the switching node and ground and output it from the first and second comparator output terminals. The second comparator circuit then generates a comparison signal based on the differential signal and the offset voltage and outputs the comparison signal at its output terminal. Therefore, when outputting the comparison signal, the zero-crossing comparator circuit compensates for the delay in the zero-crossing comparator circuit through the offset voltage. Simultaneously, relative to a fixed offset voltage compensation, this offset voltage is positively correlated with the output voltage and automatically follows different output voltages, adapting to a wider output voltage range. This allows for more precise control of the lower transistor's shutdown and reduces energy loss. Attached Figure Description

[0040] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0041] Figure 1 This is a schematic diagram of the structure of one of the switching power supplies provided in the embodiments of the present invention;

[0042] Figure 2 This is a timing diagram of the voltage and comparison signal of node LX in one embodiment of the present invention;

[0043] Figure 3 This is a schematic diagram of one type of zero-crossing comparator circuit provided in an embodiment of the present invention;

[0044] Figure 4 This is a schematic diagram of one type of zero-crossing comparator circuit provided in an embodiment of the present invention;

[0045] Figure 5 This is a schematic diagram of one type of zero-crossing comparator circuit provided in an embodiment of the present invention;

[0046] Figure 6 This is a schematic diagram of the circuit structure of one type of zero-crossing comparator circuit provided in an embodiment of the present invention;

[0047] Figure 7 This is a timing diagram of the voltage and comparison signal of one of the switching nodes provided in an embodiment of the present invention;

[0048] Figure 8This is a schematic diagram of the circuit structure of one of the zero-crossing comparison circuits provided in an embodiment of the present invention. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0050] Please see Figure 1 , Figure 1 This is a schematic diagram of a switching power supply provided in an embodiment of the present invention. This switching power supply belongs to the synchronous buck converter category of DC-DC converters. It includes an inductor L, a power transistor MH, and a synchronous transistor ML. MH is a power transistor, and ML is a synchronous transistor. The switching power supply also includes a signal control unit, which outputs a PWM signal. The two output terminals of the signal control unit are respectively connected to the control terminals of the power transistor MH and the ML. The signal control unit controls the conduction or cutoff of the power transistor MH and the ML through the control signal.

[0051] The input terminal of the upper transistor MH is connected to the input voltage VIN. The common connection point of the upper transistor MH and the lower transistor ML is the switching node LX. The corresponding load circuit includes inductor L and capacitor Cout. The common connection point of inductor L and capacitor Cout is used to output the output voltage VOUT. The negative terminal of capacitor Cout is grounded with the lower terminal of the lower transistor ML.

[0052] This switching power supply has two operating modes: Connected On Mode (CCM) and Discontinuous On Mode (DCM). In Discontinuous On Mode, a zero-crossing comparator circuit is used to detect whether the current of inductor L has crossed zero. When the current of inductor L is detected to be zero, the lower transistor ML is turned off, thereby reducing power consumption and improving efficiency.

[0053] The direction of the inductor current in L is typically determined by comparing the voltage at the switching node LX with ground PGND using a zero-crossing comparator circuit. The non-inverting input of the zero-crossing comparator circuit is connected to the switching node LX, the inverting input is grounded, and the output is connected to the input of the signal control unit. Specifically, during the down-transistor's operating cycle in the switching power supply, if the voltage at the switching node LX is higher than PGND, it indicates that the direction of the inductor current in L has reversed, and the current flows from the switching node LX to PGND, resulting in energy loss.

[0054] Therefore, when the zero-crossing comparator circuit detects that the voltage of the switching node LX has crossed zero, it indicates that the current direction of the inductor L has reversed. The signal control unit then controls the lower transistor ML to turn off based on the comparison result output by the zero-crossing comparator circuit to prevent energy loss.

[0055] The zero-crossing detection circuit consists of a first-stage high-speed operational amplifier ZCD_comparator1 and a second-stage high-gain operational amplifier ZCD_comparator2. When the voltage at the switching node LX is higher than PGND, the comparison signal ZCD_OUT output by the second-stage high-gain operational amplifier ZCD_comparator2 is a high-level signal. However, due to the parasitic capacitance at the outputs of the two operational amplifiers, the comparison signal ZCD_OUT will be delayed by Tdelay before outputting a high-level signal. The specific timing diagram is as follows. Figure 2 As shown, the solid line L1 represents the voltage of the switching node LX. At this time, the output voltage is VOUT. When the voltage of the switching node LX crosses zero, the comparison signal ZCD_OUT outputs a high-level signal after a delay of Tdelay.

[0056] To eliminate delay, existing technologies typically add a fixed offset voltage to the input of the zero-crossing comparator circuit to compensate for the delay (e.g., ...). Figure 1 As shown in the diagram, a fixed offset voltage Vos' is applied to the positive input of the first-stage high-speed operational amplifier ZCD_comparator1. When the voltage at the switching node LX is greater than Vos', the comparison signal ZCD_OUT can output a high-level signal after passing through a Tdelay. However, when the output voltage range of the switching power supply is relatively wide, for example... Figure 2 As shown by the dashed line L2, if the output voltage of the switching power supply is 2*VOUT, and the offset voltage Vos' is a fixed voltage, then the slope of the current change in inductor L is relatively large, causing the voltage slope at the switching node LX to double (e.g., Figure 2 As shown by the dashed line L2, the rapid rise is higher than PGND, and existing solutions still cannot eliminate comparator delay, resulting in a delayed output of the ZCD_OUT signal. Figure 2 As shown, the dashed line L2 represents the voltage waveform of the switching node LX corresponding to twice VOUT. When the voltage of the switching node LX is greater than Vos', after a Tdelay, the voltage of the switching node LX will still be higher than PGND. It will take a certain delay before the comparison signal ZCD_OUT outputs a high-level signal.

[0057] Therefore, embodiments of the present invention provide a zero-crossing comparator circuit that can adapt to a wider output voltage range, so that the offset voltage changes with the change of the output voltage, thereby eliminating comparator delay and accurately controlling the lower transistor to turn off, reducing energy loss.

[0058] Specifically, such as Figure 3 As shown in the diagram, this embodiment of the invention provides a schematic diagram of a zero-crossing comparator circuit. Figure 3As shown, the zero-crossing comparator circuit 100 includes a voltage sampling circuit 10, a first comparator circuit 20, and a second comparator circuit 30. The voltage sampling circuit 10 includes a first sampling terminal for connecting to the output voltage VOUT of the switching power supply and a second sampling terminal connected to the load terminal of the first comparator circuit 20. The first comparator circuit 20 includes a voltage VOUT for connecting to the switching node. LX The circuit includes a first comparison input terminal and a second comparison input terminal grounded PGND, as well as a first comparison output terminal and a second comparison output terminal connected to the first input terminal and the second input terminal of the second comparison circuit 30, respectively.

[0059] The voltage sampling circuit 10 samples the output voltage VOUT and generates an offset current positively correlated with the output voltage VOUT at the second sampling terminal. This offset current acts on the load terminal of the first comparator circuit 20, causing the first or second comparator output terminal of the first comparator circuit 20 to generate an offset voltage positively correlated with the output voltage VOUT. This offset voltage is applied to the first or second input terminal of the second comparator circuit 30. For example, if the offset current causes the first comparator output terminal to generate an offset voltage positively correlated with the output voltage VOUT, then the offset voltage acts on the first input terminal of the second comparator circuit 30; if the offset current causes the second comparator output terminal to generate an offset voltage positively correlated with the output voltage VOUT, then the offset voltage acts on the second input terminal of the second comparator circuit 30.

[0060] The first comparator circuit 20 also compares the voltage V of the switching node. LX The signal is compared with ground (PGND), and a differential signal is generated based on the comparison result and output from the first and second comparison output terminals. The differential signal characterizes the voltage V of the switching node. LX The size of the ground PGND.

[0061] The second comparator circuit 30 then generates a comparison signal ZCD_OUT based on the differential signal and the offset voltage, and outputs the comparison signal ZCD_OUT at the output terminal of the second comparator circuit 30. When the voltage V of the switching node... LX When the voltage exceeds the offset voltage, the first or second input of the second comparator circuit 30 is high, and the other input is low. After a delay, the output comparator signal ZCD_OUT is high. At this time, the voltage V at the switching node... LX It is exactly zero.

[0062] The signal control unit controls the lower-level transistor ML to turn off based on the comparison signal ZCD_OUT. When the comparison signal ZCD_OUT is high, the signal control unit controls the lower-level transistor ML to turn off. Simultaneously, the offset voltage has been used to compensate for the delay in the first comparison circuit 20 and the second comparison circuit 30. Compared to a fixed offset voltage compensation, this offset voltage is positively correlated with the output voltage VOUT, changing with the output voltage VOUT to adapt to a wider range of output voltage VOUT. This allows the comparison result to accurately output a high-level signal when the inductor L current is zero, completely eliminating the delay. This, in turn, enables the signal control unit to accurately control the lower-level transistor ML to turn off, reducing energy loss.

[0063] In this embodiment, the offset voltage is applied to the first or second input terminal of the second comparator circuit 30. It can be understood that the offset voltage can also be applied to the first or second comparison input terminal of the first comparator circuit 20, simply by performing a relevant relationship conversion on the offset voltage. For example, if the offset voltage applied to the first or second input terminal of the second comparator circuit 30 is the first offset voltage Vos, and the corresponding offset voltage applied to the non-inverting input terminal of the first comparator circuit 20 is the second offset voltage Vos', then the relationship between the first offset voltage Vos and the second offset voltage Vos' is: Vos' = Vos / (gm_Q*R), where gm_Q is the transconductance of the operational amplifier input transistor in the first or second comparison input terminal of the first comparator circuit 20, and R is the resistance between the first or second comparison output terminal of the first comparator circuit 20 and ground.

[0064] In summary, when the zero-crossing comparator outputs a comparator signal, it compensates for the delay in the zero-crossing comparator circuit with an offset voltage. At the same time, compared with a fixed offset voltage compensation, this offset voltage is positively correlated with the output voltage and automatically follows different output voltages to adapt to a wider output voltage range. This allows for more precise control of the lower transistor's shutdown and reduces energy loss.

[0065] Please see Figure 4 , Figure 4 This is a schematic diagram of a zero-crossing comparator circuit provided in an embodiment of the present invention, as shown below. Figure 4 As shown, the voltage sampling circuit 10 includes a current generation module 11 and a mirror module 12. The current generation module 11 includes a first sampling terminal and a control output terminal connected to the input terminal of the mirror module 12. The mirror module 12 further includes a control terminal for receiving control signals from the switching power supply and a second sampling terminal.

[0066] The current generation module 11 samples the output voltage VOUT and generates a feedback current that is positively correlated with the output voltage VOUT. Then, the mirror module 12 mirrors the feedback current to generate an offset current and outputs the offset current under the control of the control signal.

[0067] The feedback current is proportional to the offset current, which is determined by the mirror ratio of the mirror module 12. For example, if the mirror ratio is 1:1, the ratio of the feedback current to the offset current is also 1:1. If the mirror ratio is 1:2, the ratio of the feedback current to the offset current is also 1:2.

[0068] The control signal is a PWM wave output by the signal control unit to control the working state of the lower transistor ML. The duty cycle of the PWM wave represents the conduction time of the lower transistor ML. At the same time, when the PWM wave is a high-level signal, the mirror module 12 outputs an offset current, which is applied to the load.

[0069] The above method can generate a feedback current that is positively correlated with the output voltage VOUT. By using a mirror circuit, the proportional change of the feedback current can be realized as needed to generate an offset current.

[0070] In some embodiments, such as Figure 4 As shown, the first comparison circuit 20 includes a first switch module 21, a comparison module 22, and a load module 23. The first switch module 21 includes a first comparison input terminal, a second terminal connected to the first input terminal of the comparison module 22, and a control terminal for receiving the control signal of the switching power supply. The comparison module 22 includes a second comparison input terminal, a first comparison output terminal, and a second comparison output terminal.

[0071] The first comparison input is used to connect the voltage V of the switching node. LX The first switching module 21 also includes a ground terminal. When the control signal controls the first switching module 21 to be in the first state, the voltage V between the first input terminal of the comparison module 22 and the switching node is... LX When the control signal controls the first switch module 21 to be in the second state, the first input terminal of the comparison module 22 is connected to ground PGND.

[0072] When the first input terminal of the comparison module 22 is compared with the voltage V of the switching node LX During connection, the comparison module 22 compares the voltage V of the switching node. LX It is compared with the ground PGND of its second input terminal to generate a differential signal based on the comparison result. The differential signal is output from the first comparison output terminal and the second comparison output terminal and applied to the first and second input terminals of the second comparison circuit 30.

[0073] Specifically, when the voltage V at the first input terminal of the comparison module 22 is compared with that at the switching node... LX During connection, if the voltage V of the switching node... LX If the voltage is less than zero (ground voltage), then the first comparison output terminal of the comparison module 22 outputs a high-level signal, and the second comparison output terminal also outputs a high-level signal. If the voltage V of the switching node is... LX If the signal is greater than zero, the first comparison output terminal of the comparison module 22 outputs a low-level signal, and the second comparison output terminal outputs a high-level signal. The signals output by the first comparison output terminal and the signals output by the second comparison output terminal form a differential signal, which is applied to the first and second input terminals of the second comparison circuit 30, respectively.

[0074] The load module 23 includes an offset resistor. The load terminal is connected to the offset resistor. The offset current acts on the offset resistor through the load terminal, generating an offset voltage at the load terminal. The value of the offset voltage is obtained by multiplying the offset resistor and the offset current. The offset voltage is also applied to the first comparison output terminal or the second comparison output terminal of the comparison module 22. The offset voltage and the differential signal act together on the first and second input terminals of the second comparison circuit 30.

[0075] Understandably, the number of offset resistors can be set as needed. If there are multiple offset resistors, the product of the sum of the multiple offset resistors and the offset current will give the offset voltage value.

[0076] The offset voltage can be applied to either the first or second comparator output. Specifically, in some embodiments, such as... Figure 4 As shown, the offset current I VOUT The voltage flows from the second sampling terminal to the load terminal, and the load terminal is grounded to PGND through the offset resistor. An offset voltage is generated at the load terminal, which is also connected to the second comparator output terminal. This offset voltage is applied to the second comparator output terminal. The load module 23 also includes a balancing resistor connected between the first comparator output terminal and ground. This balancing resistor is used to balance the offset resistor. The resistance value of the balancing resistor is equal to that of the offset resistor, and the number of balancing resistors can be set as needed.

[0077] In some embodiments, such as Figure 5 As shown, the offset current I VOUT The voltage flows from the load terminal to the second sampling terminal. The load terminal is connected to the first comparator output terminal through an offset resistor, and the load terminal is grounded (PGND). The offset voltage is applied to the first comparator output terminal and is negative. The load module 23 also includes a balancing resistor connected between the second comparator output terminal and ground. Similarly, the balancing resistor is used to balance the offset resistor. The resistance values ​​of the balancing resistor and the offset resistor are equal, and their number can be set as needed.

[0078] In some embodiments, such as Figure 4As shown, the first comparison circuit 20 further includes a second switching module 24, which includes a first terminal connected to the first comparison output terminal, a second terminal connected to the second comparison output terminal, and a control terminal for receiving the control signal of the switching power supply.

[0079] The control signal of the switching power supply controls the operating state of the second switching module 24. When the second switching module 24 is in the ON state, the first comparison output terminal and the second comparison output terminal are connected and are at the same level, which is the voltage V of the switching node. LX The comparison with ground (PGND) is performed for initialization preparation. When the second switch module 24 is in the off state, the first comparison circuit 20 can directly perform the comparison without going through the initialization process, thus improving working efficiency.

[0080] Please see Figure 6 , Figure 6 This is a schematic diagram of the circuit structure of a zero-crossing comparator circuit provided in an embodiment of the present invention, as shown below. Figure 6 As shown, the current generation module 11 includes a first comparator OP1, a first MOSFET M1, and a first resistor R1. The first MOSFET M1 and the first resistor R1 are connected in series between a voltage source VDD and ground. The common connection point of the first MOSFET M1 and the first resistor R1 is the clamping terminal. The inverting input terminal of the first comparator OP1 is the first sampling terminal, the non-inverting input terminal is connected to the clamping terminal, and the output terminal is the control output terminal and is connected to the gate of the first MOSFET M1.

[0081] The inverting input of the first comparator OP1 is connected to the output voltage VOUT. The voltage at its inverting input is the clamping voltage VFB. It amplifies the difference between the output voltage VOUT and the clamping voltage VFB. The voltage at the output is connected to the gate of the first MOSFET M1. By adjusting the impedance of the first MOSFET M1, the voltage at the clamping end is finally clamped to the output voltage VOUT. That is, the first comparator OP1 clamps the voltage at the clamping end to the output voltage VOUT.

[0082] At this time, the current flowing through the first MOSFET M1 is VFB / R1 = VOUT / R1, that is, the feedback current is VOUT / R1.

[0083] The mirror module 12 includes a second MOS transistor M2 and a third MOS transistor M3 connected in series between the voltage source VDD and the second sampling terminal; the gate of the second MOS transistor M2 is the control terminal of the mirror module 12, and the gate of the third MOS transistor M3 is the input terminal of the mirror module 12.

[0084] The gate of the second MOSFET M2 is used to connect to the control signal of the switching power supply, which is a PWM signal. This PWM signal controls the conduction and cutoff of the second MOSFET M2. When PWM is 1, the second MOSFET M2 is in the cutoff state, and when PWM is 0, the second MOSFET M2 is in the conduction state.

[0085] When the second MOSFET M2 is turned on, the gate voltage of the third MOSFET M3 is equal to that of the gate voltage of the first MOSFET M1. The feedback current is mirrored to generate the offset current. The third MOSFET M3 outputs the offset current through the second sampling terminal, and the offset current Ivout flows into the load terminal through the second sampling terminal.

[0086] In this embodiment of the invention, the offset current is equal to the feedback current; in other embodiments, the offset current may also be proportional to the feedback current.

[0087] Please continue reading. Figure 6 The first switching module 21 includes a fourth MOS transistor M4 and a fifth MOS transistor M5. The source of the fourth MOS transistor M4 is the first comparison input terminal. The common connection point between the gate of the fourth MOS transistor M4 and the gate of the fifth MOS transistor M5 is the control terminal of the first switching module 21. The common connection point between the drain of the fourth MOS transistor M4 and the drain of the fifth MOS transistor M5 is the second terminal of the first switching module 21.

[0088] The gates of the fourth MOSFET M4 and the fifth MOSFET M5 are both connected to the control signal of the switching power supply, which is a PWM signal. When PWM is 1, the fourth MOSFET M4 is off and the fifth MOSFET M5 is on, and the first input terminal of the comparator module 22 is grounded. When PWM is 0, the fourth MOSFET M4 is on and the fifth MOSFET M5 is off, and the first input terminal of the comparator module 22 is connected to the voltage V of the switching node. LX .

[0089] The comparison module 22 includes a first transistor Q1, a second transistor Q2, and a first current source Ib1. One end of the first current source Ib1 is connected to the DC power supply VDD, and the other end of the first current source Ib1 is connected to the emitter of the first transistor Q1 and the emitter of the second transistor Q2. The base of the first transistor Q1 serves as the first input terminal of the comparison module 22, and the collector of the first transistor Q1 serves as the first comparison output terminal. The base of the second transistor Q2 serves as the second comparison input terminal, and the collector of the second transistor Q2 serves as the second comparison output terminal.

[0090] If the base of the first transistor Q1 is connected to the voltage V of the switching node... LXIf the first transistor Q1 is connected to ground PGND, then the first transistor Q1 is turned off, the base of the second transistor Q2 is grounded to PGND, the second transistor Q2 is turned on, the second comparator outputs a high-level signal, and the first comparator outputs a low-level signal. If the base of the first transistor Q1 is connected to ground PGND, then the first transistor Q1 is turned on, the base of the second transistor Q2 is grounded to PGND, the second transistor Q2 is turned on, the first comparator outputs a high-level signal, and the second comparator outputs a high-level signal.

[0091] The second switching module 24 includes a sixth MOSFET M6. The gate of the sixth MOSFET M6 is the control terminal of the second switching module 24, the source of the sixth MOSFET M6 is the first terminal of the second switching module 24, and the drain of the sixth MOSFET M6 is the second terminal of the second switching module 24.

[0092] The gate of the sixth MOSFET M6 is connected to the control signal of the switching power supply, which is a PWM signal. When PWM is 1, the sixth MOSFET M6 is turned on, and the first comparison output terminal is connected to the second comparison output terminal. The two terminals have the same level. When PWM is 0, the sixth MOSFET M6 is turned off, and the first comparison output terminal and the second comparison output terminal output differential signals normally.

[0093] The second comparator circuit 30 includes a second comparator COMP1 and a seventh MOSFET M7. The non-inverting input of the second comparator COMP1 is the first input, the inverting input of the second comparator COMP1 is the second input, the output of the second comparator COMP1 is connected to the drain of the seventh MOSFET M7, the output of the second comparator COMP1 is used to output the comparison signal ZCD_OUT, the gate of the seventh MOSFET M7 is used to connect to the control signal of the switching power supply, and the source of the seventh MOSFET M7 is grounded.

[0094] When the control signal of the switching power supply is 1, the seventh MOSFET M7 is turned on, the output of the second comparator COMP1 is reliably grounded, the first and second inputs of the second comparator COMP1 are at the same level, and the second comparator COMP1 is initialized. When the control signal of the switching power supply is 0, the seventh MOSFET M7 is turned off, the second comparator COMP1 compares the differential signal and the offset voltage, and outputs the comparison signal ZCD_OUT normally.

[0095] In this embodiment of the invention, the load module 23 includes a second resistor R2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5. The second resistor R2 and the third resistor R3 are connected in series and serve as balancing resistors. The fourth resistor R4 and the fifth resistor R5 are connected in series and serve as offset resistors. The common connection point of the fourth resistor R4 and the fifth resistor R5 is the load terminal.

[0096] Combination Figure 6 The working principle of the zero-crossing comparator circuit 100 can be described as follows:

[0097] Phase 1: When the PWM signal is 1, which is the stage where the lower transistor ML of the switching power supply is not working, the inverting input of the first comparator OP1 samples the output voltage VOUT, and the non-inverting input clamps the voltage at the clamping terminal to the output voltage VOUT. The current flowing through the first MOSFET M1 is the feedback current, which is VOUT / R1. At this time, the second MOSFET M2 is cut off, so the current flowing through the third MOSFET M3 is 0.

[0098] The fourth MOSFET M4 is off, the fifth MOSFET M5 is on, the base of the first transistor Q1 is grounded, the sixth MOSFET M6 is on, the collector of the first transistor Q1 is connected to the collector of the second transistor Q2, that is, the first comparator output terminal is connected to the second comparator output terminal, and the voltages of the collectors of the first transistor Q1 and the second transistor Q2 are clamped to Vclamp = Ib1*(R1+R3) / 2.

[0099] The voltages at the first and second input terminals of the second comparator COMP1 are equal, the output voltage VOUT is 0, and the seventh MOSFET M7 is turned on, ensuring that the output voltage VOUT of the second comparator COMP1 is reliably 0. This state ensures that both the first transistor Q1 and the second transistor Q2 are in the on state, and the default state is also 0. As long as PWM = 0, it can start working immediately without going through the turn-off to turn-on process, thus achieving initialization.

[0100] Second stage: When the PWM signal is 0, the feedback current flowing through the first MOSFET M1 is still VOUT / R1. The second MOSFET M2 is turned on, and the second sampling terminal of the third MOSFET M3 outputs an offset current Ivout = VOUT / R1. This offset current flows from the second sampling terminal to the load terminal, generating an offset voltage Vos = R5 * VOUT / R1 on the fifth resistor R5. This offset voltage is applied to the second comparator output terminal, that is, it acts on the non-inverting input terminal of the second comparator COMP1.

[0101] The offset voltage is applied to the second comparator output terminal of the first comparator circuit 20, which is equivalent to generating an offset voltage Vos' = (R5*VOUT / R1) / (gm_Q2*(R4+R5)) at the first comparator input terminal of the first comparator circuit 20, where gm_Q2 is the transconductance of the second transistor Q2. This offset voltage is proportional to the output voltage VOUT. If the output voltage VOUT is relatively large, it can provide a dynamic offset voltage when the inductor L current slope is relatively large, ensuring that the comparison error caused by the delay between the first comparator circuit 20 and the second comparator circuit 30 can be offset.

[0102] If the total delay time Tdelay of the first comparator OP1 and the second comparator COMP1 is known, the value of the external inductor L is L, and the on-resistance Rfet of the lower transistor ML of the switching power supply, the value of (R5 / R1) / (gm_Q2*(R4+R5)) in Vos' can be calculated.

[0103] Specifically, since the hysteresis voltage generated by Tdelay is (VOUT / L)*Tdelay*Rfet, therefore Vos' = (VOUT / L)*Tdelay*Rfet. Since Vos' = (R5*VOUT / R1) / (gm_Q2*(R4+R5)), we have (R5 / R1) / (gm_Q2*(R4+R5)) = Tdelay*Rfet / L. When the voltage at switching node LX is greater than -Vos', the comparison signal ZCD_OUT output after Tdelay is high. At this time, the voltage V at the switching node... LX It is exactly 0, which means that no negative current is generated.

[0104] Voltage V of the switching node LX The waveform of the comparison signal ZCD_OUT is as follows: Figure 7 As shown, the solid line L3 represents the voltage V at the switching node when the output voltage VOUT is VOUT. LX The waveform, whose corresponding offset voltage is Vos1, when the voltage V at the switching node... LX After the voltage is greater than -Vos1, the output comparison signal ZCD_OUT after Tdelay is high, at which point the voltage V of the switching node... LX It is exactly 0. The dashed line L4 represents the voltage V at the switching node when the output voltage VOUT is 2*VOUT. LX Its corresponding offset voltage is Vos2, when the voltage V of the switching node... LX After the voltage is greater than -Vos2, the output comparison signal ZCD_OUT after Tdelay is high, at which point the voltage V of the switching node... LX It is exactly 0.

[0105] Therefore, regardless of how the output voltage VOUT changes, the offset voltage changes with the output voltage VOUT, compensating for the comparator circuit and completely eliminating the delay. This allows for precise control of the lower transistor ML, avoiding energy loss.

[0106] Please see Figure 8 , Figure 8 This is a schematic diagram of the circuit structure of another zero-crossing comparator circuit provided in an embodiment of the present invention. Figure 8 Implementation examples and Figure 6 The only difference in the embodiment is the connection method of the first MOSFET M1, the second MOSFET M2, and the third MOSFET M3, as well as the current direction of the offset current and the offset voltage loading terminal.

[0107] Specifically, the feedback current flowing through the first MOSFET M1 remains VOUT / R1. The second MOSFET M2 and the third MOSFET M3 are connected in series between the second sampling terminal and ground. The source of the third MOSFET M3 is grounded, and the source of the second MOSFET M2 is the second sampling terminal. When the second MOSFET M2 is turned on, the third MOSFET M3 mirrors the feedback current and generates an offset current Ivout, which is the same as the feedback current, also VOUT / R1.

[0108] The offset current flows from the load terminal to the second sampling terminal, which is the common connection point of the second resistor R2 and the third resistor R3. It is grounded through the offset resistor. The third resistor R3 is the offset resistor. The load terminal is also connected to the first comparator output terminal. The fourth resistor R4 and the fifth resistor R5 are balancing resistors.

[0109] The offset current flows from the load terminal to the second sampling terminal, which is equivalent to drawing Ivout from the second resistor R2. At this time, the offset voltage Vos generated at the load terminal is -(R2*VOUT / R1). This offset voltage Vos is applied to the first comparator output terminal, which is equivalent to generating an offset voltage Vos' = -(R2*VOUT / R1) / (gm_Q2*(R2+R3)) at the second comparator input terminal (negative input terminal). Similarly, an offset voltage Vos' proportional to the output voltage VOUT can be generated to eliminate the delay.

[0110] In summary, when the zero-crossing comparator outputs a comparator signal, it compensates for the delay in the zero-crossing comparator circuit with an offset voltage. At the same time, compared with a fixed offset voltage compensation, this offset voltage is positively correlated with the output voltage and automatically follows different output voltages to adapt to a wider output voltage range. This allows for more precise control of the lower transistor's shutdown and reduces energy loss.

[0111] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; under the concept of the present invention, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the present invention as described above, which are not provided in detail for the sake of brevity; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A zero-crossing comparator circuit, applied to a switching power supply, characterized in that, The switching power supply includes a master transistor, a slave transistor, and an inductor. The common connection point of the master transistor, the slave transistor, and the inductor is a switching node. The zero-crossing comparison circuit includes a voltage sampling circuit, a first comparison circuit, and a second comparison circuit. The voltage sampling circuit includes a first sampling terminal for receiving the output voltage of the switching power supply and a second sampling terminal connected to the load terminal of the first comparator circuit. The voltage sampling circuit is used to sample the output voltage and generate an offset current positively correlated with the output voltage at the second sampling terminal. The first comparison circuit includes a first comparison input terminal for connecting the voltage of the switching node and a second comparison input terminal grounded, and also includes a first comparison output terminal and a second comparison output terminal connected to the first input terminal and the second input terminal of the second comparison circuit, respectively; the offset current causes the first or second comparison output terminal to generate an offset voltage positively correlated with the output voltage; the first comparison circuit is used to generate a differential signal based on the comparison result between the voltage of the switching node and ground and output it from the first and second comparison output terminals; The second comparator circuit is used to generate a comparison signal based on the differential signal and the offset voltage, so as to output the comparison signal at the output terminal of the second comparator circuit; The voltage sampling circuit includes a current generation module and a mirror module; The current generation module includes a first sampling terminal and a control output terminal connected to the input terminal of the mirror module. The current generation module is used to generate a feedback current that is positively correlated with the output voltage. The mirroring module further includes a control terminal for receiving the control signal of the switching power supply and a second sampling terminal. The mirroring module is used to mirror the feedback current to generate the offset current and output the offset current under the control of the control signal.

2. The zero-crossing comparator circuit according to claim 1, characterized in that, The current generation module includes a first comparator, a first MOSFET, and a first resistor; The first MOSFET and the first resistor are connected in series between a voltage source and ground, and the common connection point of the first MOSFET and the first resistor is the clamping terminal; The inverting input of the first comparator is the first sampling terminal, the non-inverting input is connected to the clamping terminal, and the output is the control output and connected to the gate of the first MOS transistor. The first comparator is used to clamp the voltage at the clamping terminal to the output voltage.

3. The zero-crossing comparator circuit according to claim 1, characterized in that, The mirror module includes a second MOS transistor and a third MOS transistor connected in series between the voltage source and the second sampling terminal; the gate of the second MOS transistor is the control terminal of the mirror module, and the gate of the third MOS transistor is the input terminal of the mirror module. The third MOSFET is used to mirror the feedback current to generate the offset current, and the second MOSFET is used to control whether the offset current is output.

4. The zero-crossing comparator circuit according to claim 1, characterized in that, The mirror module includes a second MOS transistor and a third MOS transistor connected in series between the second sampling terminal and ground; the gate of the second MOS transistor is the control terminal of the mirror module, and the gate of the third MOS transistor is the input terminal of the mirror module. The third MOSFET is used to mirror the feedback current to generate the offset current, and the second MOSFET is used to control whether the offset current is output.

5. The zero-crossing comparator circuit according to claim 1, characterized in that, The first comparison circuit includes a first switching module, a comparison module, and a load module; The first switching module includes a first comparison input terminal, a second terminal connected to the first input terminal of the comparison module, and a control terminal for receiving control signals from the switching power supply. The first switching module is used to switch the voltage connection between the first input terminal of the comparison module and the switching node or to ground. The comparison module includes a second comparison input terminal, a first comparison output terminal, and a second comparison output terminal. The comparison module is used to generate the differential signal based on the comparison result between the voltage of the switching node and ground, and output it from the first comparison output terminal and the second comparison output terminal. The load module includes an offset resistor, the load terminal is connected to the offset resistor, and the load module is used to generate the offset voltage based on the offset resistor according to the offset current, so as to apply the offset voltage to the first comparison output terminal or the second comparison output terminal of the comparison module. The first comparison circuit also includes a second switching module; The second switching module includes a first terminal connected to the first comparison output terminal, a second terminal connected to the second comparison output terminal, and a control terminal for receiving control signals from the switching power supply. The second switching module is used to control the connection status of the first comparison output terminal and the second comparison output terminal of the comparison module.

6. The zero-crossing comparator circuit according to claim 5, characterized in that, The first switching module includes a fourth MOSFET and a fifth MOSFET; The source of the fourth MOS transistor is the first comparison input terminal, the common connection point of the gate of the fourth MOS transistor and the gate of the fifth MOS transistor is the control terminal of the first switching module, and the common connection point of the drain of the fourth MOS transistor and the drain of the fifth MOS transistor is the second terminal of the first switching module.

7. The zero-crossing comparator circuit according to claim 5, characterized in that, The comparison module includes a first transistor, a second transistor, and a first current source; One end of the first current source is used to connect to a DC power supply, and the other end of the first current source is connected to the emitter of the first transistor and the emitter of the second transistor respectively. The base of the first transistor serves as the first input terminal of the comparison module, and the collector of the first transistor serves as the first comparison output terminal. The base of the second transistor is the second comparator input terminal, and the collector of the second transistor is the second comparator output terminal.

8. The zero-crossing comparator circuit according to claim 5, characterized in that, The second switching module includes a sixth MOSFET; The gate of the sixth MOS transistor is the control terminal of the second switching module, the source of the sixth MOS transistor is the first terminal of the second switching module, and the drain of the sixth MOS transistor is the second terminal of the second switching module.

9. The zero-crossing comparator circuit according to claim 5, characterized in that, The offset current flows from the second sampling terminal to the load terminal, the load terminal is grounded through the offset resistor, and the load terminal is also connected to the second comparison output terminal; the load module also includes a balancing resistor connected between the first comparison output terminal and ground.

10. The zero-crossing comparator circuit according to claim 5, characterized in that, The offset current flows from the load terminal to the second sampling terminal. The load terminal is connected to the first comparison output terminal through the offset resistor, and the load terminal is also grounded. The load module also includes a balancing resistor connected between the second comparison output terminal and ground.

11. The zero-crossing comparator circuit according to any one of claims 1-10, characterized in that, The second comparator circuit includes a second comparator and a seventh MOSFET; The non-inverting input of the second comparator is the first input, the inverting input of the second comparator is the second input, the output of the second comparator is connected to the drain of the seventh MOS transistor, and the output of the second comparator is used to output the comparison signal. The gate of the seventh MOS transistor is used to receive the control signal of the switching power supply, and the source of the seventh MOS transistor is grounded.

12. A switching power supply, characterized in that, The switching power supply includes an inductor, a master transistor, a slave transistor, and a zero-crossing comparator circuit as described in any one of claims 1-11.

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