A multi-inverter parallel system circulating current suppression method

Abstract

The application belongs to the technical field of power electronics, and discloses a kind of multi-inverter parallel system circulating current suppression method, it is characterized by comprising the following steps: (1) the step of feeder impedance estimation;(2) the step of maximum impedance selection;(3) the step of virtual impedance value calculation.The application takes suppressing circulating current as the goal, and proposes a kind of adaptive virtual complex impedance multi-loop control strategy.Firstly, the mathematical model of parallel inverters is established, and by deducing its power characteristics and circulating current characteristics, the root cause of circulating current is explored;Secondly, virtual power is introduced in the power loop to decouple power;Thirdly, a voltage and current double loop based on model prediction and two degrees of freedom is introduced to improve dynamic response speed, eliminate the influence of load disturbance, and introduce adaptive virtual complex impedance in the control loop to eliminate feeder impedance differences.The application solves the circulating current problem between parallel inverters and maintains system stability and reliability.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and more specifically to a method for suppressing circulating current in a multi-inverter parallel system. Background Technology

[0002] In power systems, inverters are key power electronic devices used to convert direct current (DC) to alternating current (AC). With the rapid development of renewable energy, especially solar photovoltaic and wind power, the application of inverters has become increasingly widespread. In many applications, multiple inverters are often used in parallel to meet higher power demands or improve system reliability. However, a critical problem exists in parallel inverter systems: circulating current.

[0003] Circulating currents are primarily caused by two factors: inconsistencies in electrical parameters between inverters, such as differences in inductance and capacitance, and asynchrony in control strategies. These differences lead to slight deviations in voltage or current between inverters, resulting in circulating currents. The presence of circulating currents has multiple impacts on parallel inverter systems: increased internal inverter losses, overheating of power semiconductor devices, increased electromagnetic interference, and decreased overall system stability.

[0004] To address the circulating current problem, various suppression methods have been proposed by industry and academia, mainly falling into two categories: hardware and software. Hardware methods include adding damping devices and using circulating current suppression transformers, directly limiting or eliminating circulating current through physical means. While these methods are effective to some extent, they increase system complexity and cost. Furthermore, the feasibility and efficiency of hardware methods in high-power applications still need to be verified.

[0005] Software methods focus on suppressing circulating currents through control strategies. For example, the output voltage and frequency of a synchronous inverter are dynamically adjusted using algorithms such as model predictive control and adaptive control. The advantage of software methods is that they do not require additional hardware and can be implemented by upgrading the inverter's control system. However, software methods place high demands on the accuracy and response speed of the control system and may suffer from stability and reliability issues in dynamically changing power grid environments.

[0006] CN116131355A discloses a circulating current resonance suppression method for multi-inverter systems. It utilizes modal analysis to calculate participation factors, determine the dominant inverter group, and locate the dominant inverter. Based on the circulating current expression of the dominant inverter, it determines the circulating current constraint conditions. By combining the suppression of the circulating current resonance peak with the original parameter design scheme and continuously adjusting the amplitude of the resonance peak, the constraint conditions for circulating current resonance suppression intersect with the original parameter design scheme, satisfying both the stability requirements of the original parameter design scheme and effectively suppressing circulating current resonance. During parallel operation of inverters, it can effectively suppress circulating current resonance between different inverters without affecting the stability of the grid-connected current. This solves the problem of excessive circulating current in large-scale new energy systems causing malfunctions of system protection devices, significantly improving the stability of multi-inverter systems.

[0007] Documents on the prior art: R.de Azevedo, MHCintuglu, T.Ma and O.A.Mohammed.Multiagent-Based Optimal Microgrid Control Using FullyDistributed Diffusion Strategy[J].IEEE Transactions on Smart Grid, 2017,8(04):1997-2008.1.2S.Patel,S.Chakraborty,B.Lundstrom, SMSalapaka andM.V.Salapaka, "Isochronous Architecture-Based Voltage-Active Power Droop for Multi-Inverter Systems," in IEEE Transactions on Smart Grid, vol.12, no.2, pp.1088-1103, March 2021.

[0008] However, existing technologies have some drawbacks in suppressing circulating currents. First, hardware solutions typically require additional equipment and space, increasing cost and system complexity. Second, these methods may not completely eliminate circulating currents, especially when inverter parameters are extremely mismatched. While software methods offer a flexible and cost-effective solution, they place higher demands on the design and implementation of control strategies. Furthermore, software methods may face performance bottlenecks when dealing with large-scale parallel inverter systems, especially under constantly changing grid conditions. Summary of the Invention

[0009] To improve the overall efficiency of multi-inverter parallel systems, extend the service life of inverters and related equipment, enhance the stability and reliability of the entire power system, reduce maintenance and operating costs, and improve power quality, this invention proposes a circulating current suppression method for multi-inverter parallel systems. This method achieves circulating current suppression by using adaptive virtual complex impedance to match the line impedances.

[0010] To achieve the above-mentioned objectives, the present invention adopts the following technical solution:

[0011] On one hand, the present invention provides an improved voltage and current dual-loop and power outer loop, comprising:

[0012] The power outer loop is improved by introducing a virtual power control method to decouple the power and achieve separate control of active and reactive power. A voltage-current dual loop based on model prediction and two degrees of freedom is introduced to solve the shortcomings of poor dynamic performance and poor load tracking capability of traditional voltage-current dual loops.

[0013] On the other hand, an adaptive virtual complex impedance is proposed to eliminate line impedance mismatch, including:

[0014] An adaptive virtual complex impedance based on known feeder impedance is proposed, and virtual impedance is assigned to parallel inverter systems with equal and unequal capacity according to different strategies.

[0015] When inverters of equal capacity are connected in parallel, the maximum value of each feeder impedance is first obtained as a reference value. Then, the reference value is subtracted from the impedance value of each feeder to obtain the virtual complex impedance corresponding to each inverter.

[0016] When inverters of unequal capacity are connected in parallel, the maximum value of each feeder impedance is first obtained as the reference value. Assuming that the obtained maximum feeder impedance is the impedance of the j-th line, then the virtual impedance Z of the j-th line is... vj =0, the virtual impedance of the remaining lines is matched according to the following formula:

[0017]

[0018] The above method enables line impedance matching between inverters of equal and unequal capacity, thereby achieving circulating current suppression.

[0019] Compared with the closest existing technology, the technical solution provided by the present invention has the following beneficial effects:

[0020] The circulating current suppression method for multi-inverter parallel systems provided by this invention is divided into power decoupling, voltage and current dual-loop improvement, and adaptive virtual complex impedance to control the circulating current between parallel inverters. When the load changes suddenly, the inverter system has good dynamic response, stability and dynamic adjustment capability.

[0021] The circulating current suppression method of the present invention can effectively suppress the circulating current between inverters when dual inverters of equal capacity are connected in parallel or dual inverters of unequal capacity are connected in parallel, regardless of whether the load suddenly increases or decreases.

[0022] The circulating current suppression method of this invention exhibits excellent power distribution and circulating current suppression effects during load surges and decreases when three inverters of equal or unequal capacity are connected in parallel. It effectively addresses sudden load fluctuations and other emergencies, further improving the overall operating efficiency and reliability of microgrid systems. It can be extended to multi-inverter parallel systems, broadening its application scope. Attached Figure Description

[0023] Figure 1 This is a diagram of the decoupling process in Embodiment 1 of the present invention.

[0024] Figure 2 This is the voltage and current double-loop diagram in Embodiment 1 of the present invention.

[0025] Figure 3 This is a control strategy design diagram of the entire control layer in Embodiment 1 of the present invention.

[0026] Figure 4 This is a schematic diagram of the adaptive virtual impedance working principle in Embodiment 2 of the present invention.

[0027] Figure 5 The diagram shows the active power output of the inverter in an equal-capacity dual inverter, illustrating the application effect of the circulating current suppression method for multi-inverter parallel systems proposed in Embodiment 3 of this invention.

[0028] Figure 6 The diagram shows the reactive power output of the inverter in an equal-capacity dual inverter, illustrating the effect of the circulating current suppression method for multi-inverter parallel systems proposed in Embodiment 3 of this invention.

[0029] Figure 7 This is an inter-inverter circulating current diagram showing the application effect of the circulating current suppression method for multi-inverter parallel systems proposed in Embodiment 3 of the present invention in a dual inverter of equal capacity.

[0030] Figure 8 The diagram shows the active power output of the inverter in the application effect of the circulating current suppression method for multi-inverter parallel systems proposed in Embodiment 4 of this invention in dual inverters with unequal capacity.

[0031] Figure 9 The diagram shows the reactive power output of the inverter in a dual inverter with unequal capacity, illustrating the application effect of the circulating current suppression method for multi-inverter parallel systems proposed in Embodiment 4 of this invention.

[0032] Figure 10 This is the application effect of the circulating current suppression method for multi-inverter parallel systems proposed in Embodiment 4 of the present invention in dual inverters of unequal capacity.H1 Inter-inverter circulating current diagram.

[0033] Figure 11 This is the application effect of the circulating current suppression method for multi-inverter parallel systems proposed in Embodiment 4 of the present invention in dual inverters of unequal capacity. H2 Inter-inverter circulating current diagram.

[0034] Figure 12 The diagram shows the active power output of the inverter in an equal-capacity three-inverter system, illustrating the application effect of the circulating current suppression method for multi-inverter parallel systems proposed in Embodiment 5 of this invention.

[0035] Figure 13 The diagram shows the reactive power output of the inverter in a three-inverter system with equal capacity, based on the circulating current suppression method for multi-inverter parallel systems proposed in Embodiment 5 of this invention.

[0036] Figure 14 This is the application effect of the circulating current suppression method for multi-inverter parallel systems proposed in Embodiment 5 of the present invention in three inverters of equal capacity. H1 Inter-inverter circulating current diagram.

[0037] Figure 15 This is the application effect of the circulating current suppression method for multi-inverter parallel systems proposed in Embodiment 5 of the present invention in three inverters of equal capacity. H2 Diagram of active power output of inverter.

[0038] Figure 16 This is the application effect of the circulating current suppression method for multi-inverter parallel systems proposed in Embodiment 5 of the present invention in three inverters of equal capacity. H3 Diagram of active power output of inverter.

[0039] Figure 17 The inverter output active power diagram shows the application effect of the circulating current suppression method of the multi-inverter parallel system proposed in Example 5 in a three-inverter of equal capacity.

[0040] Figure 18 The inverter output reactive power diagram shows the application effect of the circulating current suppression method for multi-inverter parallel systems proposed in Example 5 in three inverters of equal capacity.

[0041] Figure 19 The effect of the circulating current suppression method for multi-inverter parallel systems proposed in Example 5 on the application of three inverters of equal capacity is shown in Figure I. H1 Inter-inverter circulating current diagram.

[0042] Figure 20 The effect of the circulating current suppression method for multi-inverter parallel systems proposed in Example 5 on the application of three inverters of equal capacity is shown in Figure I. H2 Inter-inverter circulating current diagram.

[0043] Figure 21 The effect of the circulating current suppression method for multi-inverter parallel systems proposed in Example 5 on the application of three inverters of equal capacity is shown in Figure I. H3 Inter-inverter circulating current diagram.

[0044] Figure 22 This is a block diagram of the control layer structure. Detailed Implementation

[0045] The present invention will now be described in further detail with reference to the accompanying drawings.

[0046] Example 1

[0047] Please see Figure 21 Embodiment 1 of the present invention provides a circulating current suppression method for a multi-inverter parallel system, specifically including power decoupling and voltage-current dual-loop improvement;

[0048] Decoupling is achieved by converting actual power into virtual active power P′ and virtual reactive power Q′ using virtual power.

[0049]

[0050] In the formula, α is the line impedance angle, Z i =R i +jX i Let be the line impedance of line i;

[0051]

[0052] In the formula P i Q i Let be the active power and reactive power output by inverter i. Substituting equation (1) into equation (2), we obtain the virtual power expression after coordinate transformation:

[0053]

[0054] In the formula E i Let δ be the output voltage of the i-th inverter. i The output voltage phase of inverter i, V is the voltage at the point of common coupling, Z i Let be the line impedance of the i-th line. The decoupling process is as follows: Figure 1 .

[0055] To ensure excellent reference voltage tracking performance, the following is adopted: Figure 2The dual-loop regulation structure shown includes an inner current loop and an outer voltage loop. The inner current loop employs a current predictive model control (CPMC) algorithm, omitting the PWM stage and the inner current loop PI controller, thereby improving the robustness of the control system and achieving real-time equivalence between the inverter output current and the reference current, i.e., normalizing the inner loop transfer function. The outer voltage loop uses two-degree-of-freedom control, combining feedback and feedforward control to improve the system's anti-interference capability and robustness, and reduce the bandwidth limitation of feedback control. Specifically, the feedforward controller is designed as the inverse model of the filter capacitor, working in conjunction with the PI feedback controller to eliminate the inner loop residual error, thus normalizing the outer voltage loop transfer function. This hybrid control strategy aims to eliminate load disturbances and improve the stability of multi-inverter parallel systems.

[0056] The current prediction model is a finite set model, and the algorithm design idea is as follows:

[0057] 1. Construct a prediction model f{x,S} based on the mathematical relationship between the switching function S and the controlled variable x of the converter.

[0058] 2. Collect the measured value x(k) and the switch state Si at time tk, and use the prediction model to calculate the predicted value xi(k+1)=f{x(k),Si} at time tk+1.

[0059] 3. Considering the constraints of the converter system, construct the constructor g{x*,xi(k+1),Si,...} to achieve the performance target of the system optimization.

[0060] 4. By iterating through the optimization objective function, determine the switching state Sj that satisfies the minimum objective function g, and apply it to the converter. The value function is:

[0061] f min =min(f i_1 ,f i_2 ,L,f i_8 (4)

[0062]

[0063] In the value function and This represents the αβ axis component of the reference current.

[0064] Figure 3 The control strategy design diagram of the entire control layer shown contains two nested control loops, consisting of an inner current loop using FCS-MPC and an outer voltage loop using two degrees of freedom control.

[0065] The control objective of the voltage outer loop is the voltage of the filter capacitor. The object in the control system is the filter capacitor. To eliminate the static error of the system, a PI control loop is usually introduced as a feedback controller. The steady-state error generated by the current inner loop can be further eliminated by the PI controller in the voltage outer loop. Feedforward control is represented by the function G(s). According to the idea of ​​two-degree-of-freedom control, to achieve complete tracking of input and output, the feedforward controller should be designed as the dynamic inverse model of the controlled object P(s). P(s) describes the analytical relationship between the capacitor voltage uc and the current ig. Therefore, the expression of the feedforward controller is as follows:

[0066]

[0067] To achieve normalization of the transfer function of the outer voltage loop, i.e. The expressions for the feedforward output and feedback output in the outer voltage loop should be:

[0068]

[0069] Figure 2 Chinese K u_P and k u_I These are the proportional and integral coefficients of the two-degree-of-freedom control voltage outer loop PI controller, respectively; i 1d_FF i 1q_FF The dq-axis components of the feedforward signal in the two-degree-of-freedom control of the outer voltage loop; i 1d_FB i 1q_FB This represents the dq-axis component of the feedback signal in the voltage outer loop two-degree-of-freedom control; u Cd u Cq and This represents the filter capacitor voltage u. C and the dq-axis components of the reference value; R C This represents the parasitic resistance of the filter capacitor.

[0070] Employing a dual-loop control structure can provide higher control performance. The inner loop is typically used for fast response and disturbance suppression to reduce inner loop error. The outer loop is used for more accurate tracking of the reference value and elimination of the system's static error. By decomposing the control task into inner and outer loops, the dynamic response and steady-state accuracy of the system can be better balanced.

[0071] The decoupling process diagram provided in Embodiment 1 of the present invention is as follows: Figure 1 As shown, the voltage and current double loop is as follows: Figure 2 , Figure 3 The diagram shows the control strategy design for the entire control layer.

[0072] Example 2

[0073] Embodiment 2 of the present invention provides an adaptive virtual impedance strategy, the specific process of which is as follows:

[0074] Based on the obtained impedance value of each feeder, the maximum feeder impedance is first obtained using the following formula:

[0075] Z max =R max +jX max =max(Z1,Z2,L,Z) j (8)

[0076] Then determine whether the inverter capacity is the same. If the inverter capacity is the same, directly subtract the maximum feeder impedance obtained from equation (8) from the impedance of each line to obtain the virtual impedance of the corresponding line, which is summarized as follows:

[0077]

[0078] If the inverter capacities are different, the capacity ratio is n1:n2:…:n j Assuming the maximum feeder impedance obtained from equation (8) is the impedance of the j-th line, then the virtual impedance Z of the j-th line is... vj =0, the virtual impedance of the remaining lines is matched according to the following formula:

[0079]

[0080] After obtaining the virtual impedance, MGCC sends the corresponding virtual impedance command to each inverter.

[0081] Overall flowchart as follows Figure 4 As shown. The process is as follows: Based on the known feeder impedance, first compare and obtain the feeder impedance value Z with the largest among all feeder impedances. max Then, based on whether the capacities are the same, the corresponding virtual impedance is calculated. If the capacities are the same, the maximum feeder impedance is directly subtracted from the impedances of each feeder to obtain the virtual impedance value (Z) corresponding to each inverter. v1 Z v2 ,…,Z vj (This is the obtained virtual impedance value); if the capacitances are different, the capacitance ratio is n1:n2:…:n j Assuming the maximum feeder impedance obtained from equation (8) is the impedance of the j-th line, then the virtual impedance Z of the j-th line is... vj =0, the virtual impedance of the remaining lines is solved according to equation (10) to obtain the virtual impedance value (Z) corresponding to each inverter. vj Z v1 ,…,Z vj-1 (These are the virtual impedance values ​​of the j-th, 1st, 2nd, ..., j-1th inverters, respectively). After obtaining the feeder impedance, the feeder impedance value is sent to the corresponding inverter.

[0082] The entire operation process can be summarized as follows: The feeder impedance is stored in the central controller. First, the maximum line impedance is selected. Based on this result, a corresponding virtual impedance is generated according to whether the inverter capacities are the same. The generated virtual impedance is then sent to each inverter. Once all inverters confirm receipt of the Zv command, the MGCC and LBC stop operating and only restart when the system configuration changes. Although the proposed method relies on the MGCC and LBC, system reliability is not compromised: the system only operates intermittently for very short periods, and the requirements for the LBC are low.

[0083] By adding virtual impedances to match the impedances of each line, the uneven power distribution caused by line impedance mismatch is eliminated, thereby suppressing the circulating current problem caused by uneven power distribution.

[0084] In general, this application discloses a circulating current suppression method for a multi-inverter parallel system, which includes the following steps: (1) a feeder impedance estimation step; (2) a maximum impedance selection step; and (3) a virtual impedance value calculation step.

[0085] Among them, (1) the steps for estimating the feeder impedance are: assuming that the impedance values ​​of each feeder are known;

[0086] (2) The steps for selecting the maximum impedance are as follows: There are a total of n feeder impedances. First, assume that the first feeder impedance is the largest feeder impedance. Then compare it with the second feeder impedance. If it is smaller than the second feeder impedance, then Zmax = Z2. Then compare the second feeder impedance with the third feeder impedance. If it is larger than the second feeder impedance, then continue to compare the first feeder impedance with the third feeder impedance, and so on, until all comparisons are completed and the maximum value among all feeder impedances is obtained.

[0087] (3) The steps for calculating the virtual impedance value are as follows: After obtaining the maximum feeder impedance from step (2), the virtual impedance is calculated according to whether the capacity is the same. If the capacity is the same, the maximum feeder impedance is directly subtracted from the impedance of each feeder to obtain the virtual impedance value corresponding to each inverter, where Zv1, Zv2, ..., Zvj are the obtained virtual impedance values; if the capacity is different, the capacity ratio is n1:n2:...:nj. Assuming that the maximum feeder impedance obtained from equation (4) is the impedance of the j-th line, the virtual impedance Zvj of the j-th line is 0. The virtual impedance of the remaining lines is solved according to equation (6) to obtain the virtual impedance value corresponding to each inverter, where Zvj, Zv1, ..., Zvj-1 are the virtual impedance values ​​of the j-th, 1st, 2nd, ..., j-1 inverters, respectively.

[0088] Example 3

[0089] See Figures 5 to 7In this model, DG1 and DG2 are inverter 1 and inverter 2, respectively. A parallel model of two inverters with equal capacity is established, and the line impedance is set to be mismatched. No virtual impedance is added during the first 0-1s. At 1s, both inverters are simultaneously added with a fixed virtual impedance. At 2s, the aforementioned adaptive virtual impedance is added. At 3s, the load is suddenly increased by 1000W and 1000var, while the initial load is 3000W and 3000var.

[0090] Even under sudden load changes, active and reactive power can still be evenly distributed. The circulating current between inverters fluctuates only briefly before quickly stabilizing and remaining close to zero.

[0091] Example 4

[0092] See Figures 8 to 11 A parallel inverter model with a capacity ratio of 2:1 and line impedance mismatch was constructed. The simulation conditions were set as follows: no virtual impedance was added from 0 to 1s; at 1s, both inverters were simultaneously added with fixed virtual impedance; at 2s, the adaptive virtual impedance proposed in this paper was added; and at 3s, a sudden increase in load of 1000W and 1000var was added, with the initial load being 3000W and 3000var.

[0093] By adjusting the virtual impedance, this strategy enables the inverter load power to be distributed proportionally to its capacity, effectively suppressing the generation of circulating current, thereby significantly improving the stability and performance of the system.

[0094] Example 5

[0095] See Figures 12 to 16 A parallel system of three inverters of equal capacity was constructed, but the line impedance settings were mismatched. DG1, DG2, and DG3 are inverters 1, 2, and 3, respectively. The load suddenly increases by 3kW and 3kvar in 1.5 seconds, and then suddenly decreases by 3kW and 3kvar in 3 seconds.

[0096] See Figures 17 to 21 A parallel system of three inverters with a capacity ratio of 2:1.5:1 was constructed. Due to line impedance mismatch, the load suddenly increased by 3kW and 3kvar in 1.5 seconds, and then suddenly decreased by 3kW and 3kvar in 3 seconds.

[0097] In this application, I H1 I H2 I H3 These are the circulating currents output from the 1st, 2nd, and 3rd inverters, respectively.

[0098] Figure 22 The control layer structure diagram shows that the system is mainly composed of power decoupling, voltage and current dual loops, and adaptive virtual impedance.

[0099] By adjusting the adaptive virtual impedance, effective matching of line impedances between inverters is achieved. This ensures uniform power distribution and significantly reduces the circulating current amplitude to near zero. Under sudden load increases, the circulating current fluctuates only briefly before quickly stabilizing and maintaining a near-zero amplitude. Similarly, under sudden load decreases, the circulating current also exhibits only brief fluctuations before rapidly stabilizing and continuing to remain near zero. Compared to traditional control strategies, the proposed control strategy demonstrates significant advantages in handling line impedance differences between inverters and its response to dynamic load changes, exhibiting minimal fluctuations and significant circulating current suppression during transient processes such as load switching.

[0100] For ease of description, the various parts of the device described above are divided into modules or units according to their functions. Of course, in implementing this application, the functions of each module or unit can be implemented in one or more software or hardware components.

[0101] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media containing computer-usable program code, including but not limited to disk storage, CD-ROM, optical storage, etc.

[0102] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus, or systems, and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0103] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0104] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0105] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Those skilled in the art can still make modifications or equivalent substitutions to the specific implementation of the present invention by referring to the above embodiments. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention are within the protection scope of the claims of the present invention pending approval.

Claims

1. A circulating current suppression method applicable to multi-inverter parallel systems, characterized in that, include: Virtual power is introduced into the power loop for power decoupling, and model prediction and two degrees of freedom are introduced into the voltage and current dual loops to improve dynamic response speed and disturbance rejection capability. An adaptive virtual complex impedance is introduced to eliminate the circulating current problem caused by mismatched line impedance; The inverter parallel system employs two nested control loops: an inner current loop using FCS-MPC and an outer voltage loop using two degrees of freedom control. The control objective of the outer voltage loop is the voltage of the filter capacitor, and the object in the control system is the filter capacitor. A PI control element is introduced as a feedback controller. The residual error generated by the inner current loop is further eliminated by the PI controller in the outer voltage loop. The feedforward control is represented by the function G(s), and the feedforward controller is designed as a dynamic inverse model of the controlled object P(s). P(s) describes the analytical relationship between the capacitor voltage uc and the current ig. The expression of the feedforward controller is as follows: ; To achieve normalization of the transfer function of the outer voltage loop, Then the expressions for the feedforward output and feedback output in the voltage outer loop are: ； The specific process for obtaining the adaptive virtual impedance is as follows: Based on the obtained impedance value of each feeder, the maximum feeder impedance is first obtained using the following formula, which is called the maximum feeder impedance formula: Then determine if the inverter capacities are the same. If the inverter capacities are the same, directly subtract the maximum feeder impedance obtained from the above formula from the impedance of each line to obtain the virtual impedance of the corresponding line, as shown in the following formula: If the inverter capacities are different, the capacity ratio is n1:n2:…:n j Assuming the maximum feeder impedance obtained from the maximum feeder impedance formula is the impedance of the j-th line, then the virtual impedance Z of the j-th line is... vj =0, the virtual impedance of the remaining lines is matched according to the following formula: After obtaining the virtual impedance, MGCC sends the corresponding virtual impedance command to each inverter. In inverter parallel systems, including power decoupling and voltage-current dual-loop improvements, decoupling is achieved by converting actual power into virtual active power P′ and virtual reactive power Q′ using virtual power. This is called decoupling. In the formula, α is the line impedance angle, Z i =R i +jX i Let be the line impedance of line i; In the formula P i Q i Let the active and reactive power output of inverter i be denoted by equation (i = 1 / 2). Substituting the decoupling equation into the above equation, we obtain the virtual power expression after coordinate transformation: In the formula E i Let δ be the output voltage of the i-th inverter. i The output voltage phase of inverter i, V is the voltage at the point of common coupling, Z i Let be the line impedance of the i-th line.

2. The circulating current suppression method for a multi-inverter parallel system according to claim 1, characterized in that, By introducing virtual power to decouple the power, active power and reactive power can be controlled separately.

3. The circulating current suppression method for a multi-inverter parallel system according to claim 1, characterized in that, The traditional voltage and current dual-loop circuit is improved to enhance dynamic response speed and noise immunity.

4. The circulating current suppression method for a multi-inverter parallel system according to claim 1, characterized in that, Depending on whether the capacities are the same, corresponding adaptive virtual complex impedances are introduced to match the line impedances, thereby achieving reasonable power distribution and ultimately suppressing circulating current.

5. The circulating current suppression method for a multi-inverter parallel system according to claim 1, characterized in that, When two inverters of equal capacity and three inverters are connected in parallel, they can still maintain the circulating current suppression effect and dynamic effect even under sudden load increases or decreases.

6. The circulating current suppression method for a multi-inverter parallel system according to claim 1, characterized in that, When dual inverters and three inverters of unequal capacity are connected in parallel, they can still maintain the circulating current suppression effect and dynamic effect even under sudden load increases or decreases.

7. A circulating current suppression method for a multi-inverter parallel system according to claim 1, characterized in that: The process includes the following steps: (1) the feeder impedance estimation step; (2) the maximum impedance selection step; and (3) the virtual impedance value calculation step; wherein: (1) The steps for estimating feeder impedance are as follows: assume that the impedance values ​​of each feeder are known; (2) The steps for selecting the maximum impedance are as follows: There are a total of n feeder impedances. First, assume that the first feeder impedance is the largest feeder impedance. Then compare it with the second feeder impedance. If it is smaller than the second feeder impedance, then Zmax = Z2. Then compare the second feeder impedance with the third feeder impedance. If it is larger than the second feeder impedance, then continue to compare the first feeder impedance with the third feeder impedance, and so on until all comparisons are completed and the maximum value among all feeder impedances is obtained. (3) The steps for calculating the virtual impedance value are as follows: After obtaining the maximum feeder impedance from step (2), the virtual impedance is calculated according to whether the capacity is the same. If the capacity is the same, the maximum feeder impedance is directly subtracted from the impedance of each feeder to obtain the virtual impedance value corresponding to each inverter, where Zv1, Zv2, ..., Zvj are the obtained virtual impedance values; if the capacity is different, the capacity ratio is n1:n2:...:nj. Assuming that the maximum feeder impedance obtained from the value function is the impedance of the j-th line, the virtual impedance Zvj of the j-th line is 0. The virtual impedance of the remaining lines is solved according to the expression of the feedforward controller to obtain the virtual impedance value corresponding to each inverter, where Zvj, Zv1, ..., Zvj-1 are the virtual impedance values ​​of the j-th, 1st, 2nd, ..., j-1 inverters, respectively.

8. The method for calculating adaptive virtual impedance in a parallel inverter system according to claim 1, characterized in that: In the inner current loop, the current prediction model is a finite set model, and the algorithm is as follows: Step 1: Construct a prediction model f{x, S} based on the mathematical relationship between the switching function S and the controlled variable x of the converter; Step 2: Collect the measured value x(k) and the switch state Si at time tk, and use the prediction model to calculate the predicted value xi(k+1) = f{x(k), Si} at time tk+1; Step 3: Consider the converter system constraints and construct the constructor g{x*, xi(k+1), Si, ...} to achieve the performance target of the system optimization. Step 4: By iterating through the optimization objective function, determine the switching state Sj that satisfies the minimum objective function g, and apply it to the converter. The value function is: ， ， In the value function and This represents the αβ axis component of the reference current.

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