Low-cost, low-temperature drift, high power supply rejection ratio oscillation circuit

Abstract

This invention provides a low-cost, low-temperature-drift, high-power-resistance-ratio oscillation circuit, comprising: a temperature-compensated current generation circuit, a common-source cascode mirror circuit, a charge / discharge control circuit, a discharge discrimination circuit, a reset-position RS flip-flop, and a first current source. Through the temperature-compensated current generation circuit and the common-source cascode mirror circuit, it generates a compensation current with the same temperature coefficient as the voltage difference between the capacitor's charge and discharge states, reducing temperature drift. Its process and structure are simple, and it can achieve a high temperature coefficient and power-resistance ratio while reducing circuit area and cost, thus having broader application prospects.

Description

Technical Field

[0001] This invention belongs to the field of electronic circuit technology, specifically relating to a low-cost, low-temperature drift, high power supply rejection ratio oscillation circuit. Background Technology

[0002] With the advent of the big data era, various portable devices and smart home appliances are emerging in large numbers. Information processing and control are needed between devices, between chips, and within chips themselves. As an indispensable component in digital and analog signal processing and control, the performance of the oscillator directly impacts the overall chip performance. Furthermore, with the increasing demands for integration and device miniaturization, traditional quartz crystal oscillators cannot meet the needs of some low-cost, highly integrated applications. Therefore, the need for on-chip integrated high-performance oscillators is becoming increasingly apparent.

[0003] Currently, most on-chip oscillators use traditional RC oscillators, which generate a clock signal by charging and discharging a capacitor. Their oscillation frequency is often affected by process errors, temperature variations, and operating voltage changes, resulting in significant deviations from the desired frequency. Therefore, most oscillator circuits mitigate the effects of temperature and process by improving the temperature characteristics of the charging current and switching voltage, and by using metal capacitors with higher process stability. However, this approach is complex, leading to high resource consumption and high manufacturing costs. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a low-cost, low-temperature drift, high power supply rejection ratio oscillation circuit. This invention is achieved through the following technical solution:

[0005] This invention provides a low-cost, low-temperature drift, high power supply rejection ratio oscillation circuit, comprising:

[0006] Temperature-compensated current generation circuit, common-source common-gate mirror circuit, charge-discharge control circuit, discharge discrimination circuit, and reset-position RS flip-flop, first current source;

[0007] The output terminal of the temperature-compensated current generating circuit is connected to the input terminal of the common-source cascode mirror circuit;

[0008] The output terminals of the common-source cascode mirror circuit are connected to the first and second input terminals of the charge / discharge control circuit, respectively.

[0009] The first output terminal of the charge / discharge control circuit is connected to the first input terminal of the discharge discrimination circuit, and the second output terminal is connected to the second input terminal of the discharge discrimination circuit.

[0010] The first input terminal of the RS flip-flop is connected to the first output terminal of the discharge discrimination circuit, the second input terminal is connected to the second output terminal of the discharge discrimination circuit, the first output terminal is connected to the fourth and fifth input terminals of the charge and discharge control circuit, and the second output terminal is connected to the third and sixth input terminals of the charge and discharge control circuit respectively.

[0011] The first current source is connected to the seventh and eighth input terminals of the charge and discharge control circuit, respectively.

[0012] Temperature compensation current generating circuit, used to generate the first temperature compensation current;

[0013] A common-source cascode mirror circuit is used to mirror the first temperature compensation current to obtain the second temperature compensation current.

[0014] The charge and discharge control circuit is used to charge and discharge internal devices according to the second temperature compensation current, the output signal of the RS flip-flop and the output current of the first current source, so as to output a first voltage signal and a second voltage signal.

[0015] The discharge discrimination circuit is used to output a corresponding first-level signal and a corresponding second-level signal based on the first voltage signal and the second voltage signal;

[0016] An RS flip-flop is used to output a first clock signal and a second clock signal based on a first level signal and a second level signal. The first clock signal and the second clock signal have the same frequency but opposite phase.

[0017] The beneficial effects of this invention are:

[0018] The low-cost, low-temperature drift, high power supply rejection ratio oscillation circuit provided by this invention generates a compensation current with the same temperature coefficient as the voltage difference between the capacitor's charging and discharging through a temperature compensation current generation circuit and a common-source, common-gate mirror circuit, thereby reducing temperature drift. Its process and structure are simple, and it can reduce circuit area and cost while achieving a high temperature coefficient and power supply rejection ratio, thus having a broader application prospect.

[0019] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0020] Figure 1 This invention provides a schematic diagram of a low-cost, low-temperature drift, high power supply rejection ratio oscillation circuit.

[0021] Figure 2 A schematic diagram of a charging and discharging control circuit provided by the present invention;

[0022] Figure 3 A schematic diagram of the structure of a charge / discharge control unit provided by the present invention;

[0023] Figure 4 A schematic diagram of a discharge discrimination circuit provided by the present invention;

[0024] Figure 5 This is a schematic diagram of a temperature compensation current generating circuit provided by the present invention;

[0025] Figure 6 A schematic diagram of another low-cost, low-temperature drift, high power supply rejection ratio oscillation circuit provided by the present invention;

[0026] Figure 7 A schematic diagram of another low-cost, low-temperature drift, high power supply rejection ratio oscillation circuit provided by the present invention;

[0027] Figure 8 A schematic diagram of the structure of an adjustable zero-temperature resistance unit provided by the present invention;

[0028] Figure 9 A schematic diagram of another adjustable zero-temperature resistance unit provided by the present invention;

[0029] Figure 10 A capacitance-voltage (C-V) curve of an NMOS capacitor provided by the present invention;

[0030] Figure 11 The voltage waveform diagram of a low-cost, low-temperature drift, high power supply rejection ratio oscillation circuit provided by the present invention. Detailed Implementation

[0031] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0032] Figure 1 This is a schematic diagram of a low-cost, low-temperature drift, high power supply rejection ratio oscillation circuit provided by the present invention, as shown below. Figure 1 As shown, the circuit includes:

[0033] Temperature-compensated current generation circuit, common-source common-gate mirror circuit, charge / discharge control circuit, discharge discrimination circuit, and reset-position RS flip-flop, first current source.

[0034] The output of the temperature-compensated current generating circuit is connected to the input of the common-source cascode mirror circuit.

[0035] The output of the common source cascode mirror circuit is connected to the first and second inputs of the charge / discharge control circuit, respectively.

[0036] The first output terminal of the charge / discharge control circuit is connected to the first input terminal of the discharge discrimination circuit, and the second output terminal is connected to the second input terminal of the discharge discrimination circuit.

[0037] The first input terminal of the RS flip-flop is connected to the first output terminal of the discharge discrimination circuit, the second input terminal is connected to the second output terminal of the discharge discrimination circuit, the first output terminal is connected to the fourth and fifth input terminals of the charge and discharge control circuit, and the second output terminal is connected to the third and sixth input terminals of the charge and discharge control circuit, respectively.

[0038] The first current source is connected to the seventh and eighth input terminals of the charge / discharge control circuit, respectively.

[0039] Temperature compensation current generating circuit, used to generate the first temperature compensation current.

[0040] A common-source, common-gate mirror circuit is used to mirror the first temperature compensation current to obtain the second temperature compensation current.

[0041] The charge / discharge control circuit is used to charge and discharge internal devices based on the second temperature compensation current, the output signal of the RS flip-flop, and the output current of the first current source, so as to output a first voltage signal and a second voltage signal.

[0042] The discharge discrimination circuit is used to output a corresponding first level signal and a corresponding second level signal based on the first voltage signal and the second voltage signal.

[0043] An RS flip-flop is used to output a first clock signal and a second clock signal based on a first level signal and a second level signal. The first clock signal and the second clock signal have the same frequency but opposite phase.

[0044] Figure 2 A schematic diagram of a charge / discharge control circuit provided by the present invention is shown below. Figure 2 As shown, optionally, the charge / discharge control circuit includes a first charge / discharge control unit and a second charge / discharge control unit.

[0045] The first input terminal of the first charge / discharge control unit and the first input terminal of the second charge / discharge control unit are both connected to the output terminal of the common source cascode mirror circuit.

[0046] The output terminal of the first charge / discharge control unit is connected to the first input terminal of the discharge discrimination circuit and the second input terminal of the discharge discrimination circuit.

[0047] The second input terminal of the second charge / discharge control unit and the fourth input terminal of the first charge / discharge control unit are both connected to the first output terminal of the RS flip-flop.

[0048] The second input terminal of the first charge / discharge control unit and the fourth input terminal of the second charge / discharge control unit are both connected to the second output terminal of the RS flip-flop.

[0049] The third input terminal of both the first charge / discharge control unit and the second charge / discharge control unit is connected to the first current source.

[0050] The first charge / discharge control unit is used to charge and discharge internal devices according to the second temperature compensation current, the output signal of the RS trigger and the output current of the first current source, so as to output a first voltage signal.

[0051] The second charge / discharge control unit is used to charge and discharge internal devices according to the second temperature compensation current, the output signal of the RS trigger and the output current of the first current source, so as to output a second voltage signal.

[0052] Figure 3 A schematic diagram of a charge / discharge control unit provided by the present invention is shown below. Figure 3 As shown, the optional charge / discharge control unit includes a charge / discharge control subunit and a MOSFET capacitor.

[0053] The input terminal of the charge / discharge control subunit is connected to the output terminal of the common source cascode mirror circuit, the output terminal of the RS flip-flop, and the first current source, respectively.

[0054] The output terminal of the charge / discharge control subunit is connected to the MOS transistor capacitor.

[0055] The charge / discharge control subunit is used to charge and discharge the MOS transistor capacitor according to the second temperature compensation current, the output signal of the RS flip-flop and the output current of the first current source, so as to adjust the first voltage signal output by the MOS transistor capacitor.

[0056] In one possible implementation, the charge / discharge control unit includes a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor, as well as a MOS transistor capacitor.

[0057] The source of the tenth transistor is connected to the output of the common-source cascode mirror circuit, and its drain is connected to the drain of the eighth transistor and the gate of the MOS capacitor. The gate of the MOS capacitor is the output of the charge / discharge control unit.

[0058] The gate of the tenth transistor is connected to the gate of the eighth transistor and the output of the RS flip-flop.

[0059] The source of the eighth transistor is connected to the drain and gate of the seventh transistor, and the drain of the ninth transistor.

[0060] The source of the seventh transistor is connected to the source and gate of the MOS transistor capacitor.

[0061] The gate of the ninth transistor is connected to the output of the RS flip-flop, and its source is connected to the first current source.

[0062] Figure 6 A schematic diagram of another low-cost, low-temperature drift, high power supply rejection ratio oscillation circuit provided by the present invention is provided, exemplarily shown below. Figure 6 The charge / discharge control unit 631 includes a seventh transistor M6, an eighth transistor M7, a ninth transistor M8, and a tenth transistor M9, as well as a MOS transistor capacitor C0.

[0063] Among them, M6 and M7 are NMOS transistors, and M8 and M9 are PMOS transistors.

[0064] The source of M9 is connected to the output of the common source and common gate mirror circuit 62, and the drain is connected to the drain of M7 and the gate of C0 respectively. The gate of C0 is the output of the charge and discharge control unit 631.

[0065] The gate of M9 is connected to the gate of M7 and the output of RS flip-flop 65, respectively.

[0066] The source of M7 is connected to the drain and gate of M6, and the drain of M8, respectively.

[0067] The source of M6 is connected to the source and gate of C0.

[0068] The gate of M8 is connected to the output of RS flip-flop 65, and its source is connected to the first current source I1. The other end of the first current source I1 is connected to the power supply.

[0069] The charge / discharge control unit 632 and the charge / discharge control unit 631 have similar structures, and will not be described in detail here.

[0070] Figure 7 This is a schematic diagram of another low-cost, low-temperature drift, high power supply rejection ratio oscillation circuit provided by the present invention. For example, see [link to schematic diagram]. Figure 7 The charge / discharge control unit 732 includes a seventh transistor M6', an eighth transistor M7', a ninth transistor M8', and a tenth transistor M9', as well as a PMOS transistor capacitor C0'.

[0071] Among them, M6' and M7' are PMOS transistors, and M8' and M9' are NMOS transistors.

[0072] The source of M9' is connected to the output of the common-source common-gate mirror circuit 72, and the drain is connected to the drain of M7' and the gate of C0' respectively. The gate of C0' is the output of the charge and discharge control unit 731.

[0073] The gate of M9' is connected to the gate of M7' and the output of RS flip-flop 75, respectively.

[0074] The source of M7' is connected to the drain and gate of M6', and the drain of M8', respectively.

[0075] The source of M6' is connected to the source and gate of C0'.

[0076] The gate of M8' is connected to the output of RS flip-flop 75, and its source is connected to the first current source I1'. The other end of the first current source I1' is grounded.

[0077] The charge / discharge control unit 732 and the charge / discharge control unit 731 have similar structures, and will not be described in detail here.

[0078] Figure 4 This is a schematic diagram of a discharge discrimination circuit provided by the present invention, as shown below. Figure 4 As shown, the optional discharge discrimination circuit includes a first discharge discrimination unit and a second discharge discrimination unit.

[0079] The input terminal of the first discharge discrimination unit is connected to the output terminal of the first charge and discharge control unit.

[0080] The input terminal of the second discharge discrimination unit is connected to the output terminal of the second charge and discharge control unit.

[0081] The first input terminal of the RS flip-flop is connected to the output terminal of the first discharge discrimination unit, and the output terminal of the second discharge discrimination unit is connected to the second input terminal of the RS flip-flop.

[0082] The first discharge discrimination unit is used to output a corresponding first level signal based on the first voltage signal.

[0083] The second discharge discrimination unit is used to output a corresponding second flat signal based on the second voltage signal.

[0084] In one possible implementation, the discharge discrimination unit includes an eleventh transistor, a twelfth transistor, and a third current source.

[0085] The drain and gate of the eleventh transistor are both connected to the source of the twelfth transistor.

[0086] The drain of the twelfth transistor is connected to the third current source, and the gate is the input terminal of the discharge discrimination unit.

[0087] For example, see Figure 6 The discharge discrimination unit 641 includes an eleventh transistor M14, a twelfth transistor M15, and a third current source I2.

[0088] Among them, M14 and M15 are NMOS transistors.

[0089] The drain and gate of M14 are both connected to the source of M15.

[0090] The drain of M15 is connected to the third current source I2, the gate is the input terminal of the discharge discrimination unit 641, and the other end of I2 is connected to the power supply.

[0091] The discharge discrimination unit 641 and the discharge discrimination unit 642 have similar structures, and will not be described in detail here.

[0092] For example, see Figure 7 The discharge discrimination unit 741 includes an eleventh transistor M14', a twelfth transistor M15', and a third current source I2'.

[0093] Among them, M14' and M15' are PMOS transistors.

[0094] The drain and gate of M14' are both connected to the source of M15'.

[0095] The drain of M15' is connected to the third current source I2', the gate is the input terminal of the discharge discrimination unit 741, and the other end of I2' is grounded.

[0096] The discharge discrimination unit 741 and the discharge discrimination unit 742 have similar structures, and will not be described in detail here.

[0097] Figure 5 This is a schematic diagram of a temperature compensation current generating circuit provided by the present invention, as shown below. Figure 5 As shown, the optional temperature-compensated current generating circuit includes:

[0098] Temperature-compensated current generation unit and adjustable zero-temperature resistor unit.

[0099] The first output terminal of the temperature-compensated current generating unit is connected to the input terminal of the common-source cascode mirror circuit, and the second output terminal is connected to the first input terminal of the adjustable zero-temperature resistor unit.

[0100] The second input terminal of the adjustable zero-temperature resistance unit is connected to an external adjustment control signal, and the output terminal is connected to the input terminal of the temperature compensation current generation unit.

[0101] The adjustable zero-temperature resistor unit is used to change its own resistance value according to an external adjustment control signal, and then adjust the voltage signal fed back to the temperature compensation current generation unit according to the voltage signal input to the temperature compensation current generation unit, so as to adjust the first temperature compensation current output by the temperature compensation current generation unit, thereby adjusting the signal period of the first clock signal and the second clock signal.

[0102] The temperature-compensated current generating unit is used to apply a temperature-compensated voltage to the adjustable zero-temperature resistor unit, thereby generating a temperature-compensated current.

[0103] An external adjustment control signal is used to adjust the resistance value of the adjustable zero-temperature resistor unit to change the temperature-compensated current and adjust the effects of process errors.

[0104] In one possible implementation, the temperature compensation current generating unit in the temperature compensation current generating circuit includes a second current source, a first transistor and a second transistor, and an operational amplifier.

[0105] The second current source is connected to the drain of the first transistor and the positive input terminal of the operational amplifier, respectively.

[0106] The inverting input of the operational amplifier is connected to the output of the adjustable zero-temperature resistor unit, and the output is connected to the gate of the second transistor.

[0107] The source of the second transistor is connected to the first input terminal of the adjustable zero-temperature resistor unit, and the drain is connected to the input terminal of the common-source cascode mirror circuit.

[0108] The first transistor and the second transistor can be either NMOS transistors or PMOS transistors.

[0109] For example, see Figure 6 The temperature-compensated current generating unit 611 includes a second current source I0, a first transistor M0, a second transistor M1, and an operational amplifier U1.

[0110] M0 and M1 are both NMOS transistors.

[0111] The first terminal of the second current source I0 is connected to the power supply, and the second terminal is connected to the drain and gate of M0, as well as the positive input terminal of U1.

[0112] The source of M0 is grounded.

[0113] The drain of M1 is connected to the input terminal of the cascode mirror circuit 62, and the gate is connected to the output terminal of U1.

[0114] The source of M1 is connected to the first input terminal of the adjustable zero-temperature resistor unit 612.

[0115] The output terminal of the adjustable zero-temperature resistor unit 612 is connected to the inverting input terminal of U1, the second input terminal is connected to an external adjustment control signal, and the third input terminal is grounded.

[0116] For example, see Figure 7 The temperature-compensated current generating unit 711 includes a second current source I0', a first transistor M0', a second transistor M1', and an operational amplifier U1'.

[0117] M0' and M1' are both PMOS transistors.

[0118] The first terminal of the second current source I0' is connected to the drain and gate of M0' and the positive input terminal of U1', respectively, and the second terminal of the second current source I0' is grounded.

[0119] The source of M0' is connected to the power supply.

[0120] The drain of M1' is connected to the input terminal of the cascode mirror circuit 72, and the gate is connected to the output terminal of U1'.

[0121] The source of M1' is connected to the first input terminal of the adjustable zero-temperature resistor unit 712.

[0122] The output terminal of the adjustable zero-temperature resistor unit 712 is connected to the inverting input terminal of U1', the second input terminal is connected to the external adjustment control signal, and the third input terminal is connected to the power supply.

[0123] Due to capacitor manufacturing process errors, the transistor capacitance value has an error of ±15% depending on the process. In addition, factors such as the operational amplifier offset voltage and the matching transistor offset also affect the signal period of the output square wave. To obtain a more accurate signal period, this invention employs a feedback adjustment method, adjusting the signal period variation caused by global process errors by changing the resistor value.

[0124] In one possible implementation, the adjustable zero-temperature resistance unit includes n-2 n Decoder, 2 n One inverter, 2 n One resistor, and 2 n There are n transmission gate switches, where n is a positive integer.

[0125] n-2 n The decoder's encoding signal input is connected to an external adjustment control signal, 2 n The output terminals are connected to the corresponding inverter input terminals and the positive control terminals of the corresponding transmission gate switches, respectively.

[0126] The output of each inverter is connected to the inverting control terminal of the corresponding transmission gate switch.

[0127] 2 n The second input and output terminals of each transmission gate switch are connected to the input terminal of the temperature compensation current generation unit.

[0128] The first terminal of each resistor is connected to the first input / output terminal of the corresponding transmission gate switch.

[0129] 2 n The resistors are connected in series, and the highest potential of the series path is the first end of the corresponding resistor, which is connected to the second output terminal of the temperature compensation current generating unit. The lowest potential of the series path is the second end of the corresponding resistor, which is grounded.

[0130] 2 n The decoder refers to the one that can output 2 n The decoder can be selected according to actual needs, such as a 2-to-4 decoder, a 3-to-8 decoder, a 4-to-16 decoder, etc.

[0131] The decoder in the adjustable zero-temperature resistor unit decodes the input external adjustment control signal to obtain 2. n The unique hot code is generated by the corresponding inverter. n The one's complement of the path, then use 2 n Road unique hot code and 2 n The corresponding inverted code signal controls the corresponding transmission gate to output the voltage on the corresponding resistor to the feedback terminal. This method can effectively avoid the transmission gate conducting voltage drop caused by the continuous flow of current, thus improving the accuracy of the follower.

[0132] based on Figure 6 The present invention provides a schematic diagram of the structure of an adjustable zero-temperature resistance unit, as exemplified by [example shown]. Figure 8 , Figure 8 The adjustable zero-temperature resistor unit shown includes a 4-16 decoder U2, inverters F0-F15, resistors R0-R15, and transmission gate openers K0-K15.

[0133] The input terminals of decoder U2 are connected to external input signals A0-A3, and the output terminals transmit 16 output signals B0-B15 to inverters F0-F15 and the positive control terminals of transmission gate switches K0-K15 respectively.

[0134] Inverters F0-F15 output corresponding control signals NB0-NB15 to the inverting control terminals of transmission gate switches K0-K15.

[0135] The output signal of decoder U2 controls the conduction state of the transmission gate switch.

[0136] The second input / output terminals of the transmission gate switches K0-K15 are connected in parallel to Figure 6 The inverting input terminal of operational amplifier U1 in the circuit shown.

[0137] The first input and output terminals of the transmission gate switches K0-K15 are respectively connected to the first terminals of resistors R0-R15.

[0138] Resistors R0-R15 are connected in series. The first end of the resistor connected to only one transmission gate switch, i.e., the first end of R15, is also connected to the second output terminal of the temperature compensation current generating unit; the second end of the resistor not connected to any transmission gate switch, i.e., the second end of R0, is grounded.

[0139] based on Figure 7The present invention provides a schematic diagram of the structure of an adjustable zero-temperature resistance unit, as exemplified by [example shown]. Figure 9 , Figure 9 The adjustable zero-temperature resistor unit shown includes a 4-16 decoder U2', inverters F0'-F15', resistors R0-R15', and transmission gate openers K0'-K15'.

[0140] The input terminal of decoder U2' is connected to external input signals A0-A3, and the output terminal transmits 16 output signals B0-B15 to the positive control terminals of inverters F0'-F15' and transmission gate switches K0'-K15' respectively.

[0141] The inverters F0'-F15' output corresponding control signals NB0-NB15 to the inverting control terminals of the transmission gate switches K0'-K15'.

[0142] The output signal of decoder U2' controls the conduction state of the transmission gate switch.

[0143] The second input / output terminals of the transmission gate switches K0'-K15' are connected in parallel to Figure 7 The inverting input terminal of the operational amplifier U1' in the circuit shown.

[0144] The first input and output terminals of the transmission gate switches K0'-K15' are respectively connected to the first terminals of resistors R0'-R15'.

[0145] Resistors R0'-R15' are connected in series. The first end of the resistor connected to only one transmission gate switch, i.e., the first end of R15', is also connected to the second output terminal of the temperature compensation current generating unit; the second end of the resistor not connected to any transmission gate switch, i.e., the second end of R0', is connected to the power supply.

[0146] In one possible implementation, the common-source cascode mirror circuit includes a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor.

[0147] The drain of the third transistor is connected to the source of the fourth transistor.

[0148] The drain of the fourth transistor is the input terminal of the cascode mirror circuit, and is connected to the gate of the third transistor and the gate of the fifth transistor, respectively.

[0149] The drain of the fifth transistor is connected to the source of the sixth transistor.

[0150] The drain of the sixth transistor is the output terminal of the cascode mirror circuit.

[0151] The gate of the fourth transistor is connected to the gate of the sixth transistor.

[0152] The third, fourth, fifth, and sixth transistors can be either NMOS or PMOS transistors.

[0153] The common-source cascode mirror circuit is a structure in which transistors form a common-source cascode current mirror. The current of the third transistor in the mirror is transmitted to the fifth transistor, providing a temperature-compensated charging current for the charge and discharge control circuit.

[0154] For example, see Figure 6 The common-source common-gate mirror circuit 62 includes a third transistor M2, a fourth transistor M3, a fifth transistor M4, and a sixth transistor M5. M2-M5 are all PMOS transistors.

[0155] The drain of M2 is connected to the source of M3.

[0156] The drain of M3 is the input terminal of the cascode mirror circuit, and is connected to the gate of M2 and the gate of M4 respectively.

[0157] The drain of M4 is connected to the source of M5.

[0158] The drain of M5 is the output terminal of the cascode mirror circuit.

[0159] The gate of M3 is connected to the gate of M5.

[0160] The source terminals of M2 and M4 are connected to the power supply.

[0161] For example, see Figure 7 The common-source common-gate mirror circuit 72 includes a third transistor M2', a fourth transistor M3', a fifth transistor M4', and a sixth transistor M5'. M2'-M5' are all NMOS transistors.

[0162] The drain of M2' is connected to the source of M3'.

[0163] The drain of M3' is the input terminal of the cascode mirror circuit, and is connected to the gate of M2' and the gate of M4' respectively.

[0164] The drain of M4' is connected to the source of M5'.

[0165] The drain of M5' is the output terminal of the cascode mirror circuit.

[0166] The gate of M3' is connected to the gate of M5'.

[0167] The source of M2' and the source of M4' are grounded.

[0168] In one possible implementation, such as Figure 6 As shown, the RS flip-flop includes NAND gates NAND0 and NAND1, and buffers BUFFER0 and BUFFER1.

[0169] The first input terminal of NAND0 is connected to the first discharge discrimination circuit 641, and the second input terminal is connected to the output terminal of NAND1 and the input terminal of BUFFER1.

[0170] The first input terminal of NAND1 is connected to the output terminal of NAND0 and the input terminal of BUFFER0, and the second input terminal is connected to the second discharge discrimination circuit 642.

[0171] The output terminal of BUFFER0 outputs the signal CK.

[0172] The output terminal of BUFFER1 outputs the signal CKB.

[0173] In one possible implementation, such as Figure 7 As shown, the RS flip-flop includes NOR0 and NOR1 gates, and BUFFER0' and BUFFER1' buffers.

[0174] The first input terminal of NOR0 is connected to the first discharge discrimination circuit 641, and the second input terminal is connected to the output terminal of NOR1 and the input terminal of BUFFER1'.

[0175] The first input terminal of NOR1 is connected to the output terminal of NOR0 and the input terminal of BUFFER0', and the second input terminal is connected to the second discharge discrimination circuit 642.

[0176] The output terminal of BUFFER0' outputs the signal CKB.

[0177] The output terminal of BUFFER1' outputs the signal CK.

[0178] To better understand the intended effects of this invention, the following is combined with... Figure 6 A further detailed description of the corresponding circuit principles is provided. Figure 7 and Figure 6 Since they are commutative structures, their circuit principles can be referenced interchangeably, and will not be elaborated upon here.

[0179] When an NMOS transistor is used as a capacitor, its capacitance changes significantly when the gate-source voltage is lower than the threshold voltage. As the gate-source voltage gradually changes from negative to positive, holes in the P-type substrate beneath the oxide layer are repelled, forming a negatively charged depletion layer at the junction. This depletion layer capacitance is connected in parallel with the gate oxide capacitance, causing the total equivalent capacitance to decrease. At this point, the capacitance C between the gate and the substrate... GB This is manifested as oxide layer capacitance C ox and depletion layer capacitance C dep Therefore, the total capacitance corresponding to the NMOS transistors is expressed as:

[0180]

[0181] As the voltage increases, the width of the space charge region increases, and the total capacitance continues to decrease. When the gate-source voltage V... GS As the number of carriers continues to increase, minority carriers are attracted to the surface to form an inversion layer, which in turn forms an N-type channel. The source and drain ends are connected together by the channel, and the capacitance at this point is the gate oxide capacitance.

[0182] Figure 10 The image shows the CV curve of an NMOS capacitor. Figure 10 It is known that to ensure a relatively stable NMOS capacitance value, the difference between its gate potential and source-drain potential must always be greater than its threshold voltage. As provided in this invention... Figure 6 In the circuit shown, the difference between the gate potential and the source-drain potential of the NMOS capacitors C0 and C1 is kept within (V). THN +V DS,sat )~2(V THN +V DS,sat )between.

[0183] Similarly, to ensure a relatively stable PMOS capacitance value, the difference between its source-drain potential and gate potential must always be greater than its corresponding threshold voltage. As provided in this invention... Figure 7 In the circuit shown, the difference between the source-drain potential and the gate potential of PMOS capacitors C0 and C1 is made to be within (|V THP |+V SD,sat )~2(|V THP |+V SD,sat )between

[0184] like Figure 6 As shown, after the low-cost, low-temperature drift, high power rejection ratio oscillation circuit is powered on, since there is no charge accumulation on NMOS capacitors C0 and C1, the input voltages of both the first discharge discrimination circuit 641 and the second discharge discrimination circuit 642 are zero. This results in both the output voltages of the first discharge discrimination circuit 641 and the second discharge discrimination circuit 642 being high. Therefore, the output of the RS flip-flop 65 will remain in a state where one is 1 and the other is 0. Assuming the output signal CK of the RS flip-flop 65 is 1 and CKB is 0, then the PMOS transistor M9 controlled by CK is turned off, the NMOS transistor M7 is turned on, the PMOS transistor M12 is turned off, the PMOS transistor M8 controlled by CKB is turned on, the NMOS transistor M11 is turned off, and the PMOS transistor M13 is turned on. This causes the current I of the current source I1 to... refThe voltage flows through the PMOS transistor M8 to the diode-connected NMOS transistor M6, thereby stabilizing the first charge / discharge control circuit 631. At this point, the voltage of the NMOS capacitor C0 is consistent with the gate-source voltage of the NMOS transistor M6. The voltage of the NMOS capacitor C0 at this time is:

[0185]

[0186] Among them, V C10 This represents the minimum voltage across the NMOS capacitor C0, in μ. n C represents the drift velocity of electrons in the N-channel. oc The NMOS transistor's gate oxide capacitance per unit area is represented by W, which represents the NMOS transistor's channel width, and L represents the NMOS transistor's channel length. ref V represents the current of current source I1. THN This represents the threshold voltage of an NMOS transistor.

[0187] Meanwhile, the temperature compensation current I generated by the mirror image from PMOS transistors M4 and M5 com The NMOS capacitor C1, whose voltage is currently 0, is charged via PMOS transistor M13. Upon initial power-up, the difference between the gate potential and the source-drain potential of NMOS capacitors C0 and C1 increases from 0, not from the lowest voltage in the steady state. Therefore, the first charging time is longer, resulting in a longer first cycle time. In the clock steady state, charging of NMOS capacitor C1 begins from the gate voltage of M10. The voltage across NMOS capacitor C1 increases linearly over time, satisfying the following equation:

[0188] I com ×t=C×ΔV (3)

[0189] Where C represents the capacitance of NMOS capacitor C1, and t represents the mirror current I. com For the charging time of NMOS capacitor C1, ΔV represents the change in voltage across the capacitor. As the voltage of NMOS capacitor C1 rises to the point where the pull-down capability of the pull-down circuit composed of NMOS transistors M16 and M17 exceeds the current of current source I2, the output of the second discharge discrimination circuit 642 changes to 0. That is, the input terminal of NAND1 in RS flip-flop 65 is 0, the output terminal CK changes to 0, and CKB changes to 1. Ignoring the second-order effect, the switching voltage of NMOS capacitor C1 is:

[0190]

[0191] Therefore, the voltage change of NMOS capacitor C1 is:

[0192]

[0193] Because the output of RS flip-flop 65 changes, PMOS transistor M9, controlled by CK, turns on, NMOS transistor M7 turns off, PMOS transistor M12 turns on, PMOS transistor M8, controlled by CKB, turns off, NMOS transistor M11 turns on, and PMOS transistor M13 turns off. This causes the current I from current source I1 to change. ref The current flows through the PMOS transistor M12 to the diode-connected NMOS transistor M10. At this time, the voltage across the MOS capacitor C1 is higher than that of the current flowing solely through I. ref The gate-source voltage of the diode-connected NMOS transistor M10 causes the MOS capacitor C1 to discharge through the NMOS transistor M11 in a manner similar to the RC discharge of a resistor and capacitor, until the voltage of the NMOS capacitor C1 matches the gate-source voltage of the NMOS transistor M10 through which only the current source I1 flows. At the start of discharge, the gate-source voltage of M10 is the upper limit V of the voltage of the NMOS capacitor C1. C11 Its current discharge capability is extremely high, but as the gate-source voltage of M10 decreases, its current capability gradually decreases, similar to an RC discharge method, and its discharge speed slows down until the voltage stabilizes at V. C10 Simultaneously, the temperature-compensated current I generated by the mirror image from PMOS transistors M4 and M5... com The NMOS capacitor C0 is charged by the PMOS transistor M9, and its voltage change over time and the magnitude of the switching voltage also satisfy formulas (2) and (3). This ultimately causes the output of the first discharge discrimination circuit 641 to change to 0, which in turn causes the RS flip-flop 65 to output inverted. This process repeats continuously, generating complementary square wave signals CK and CKB. Figure 11 The voltage waveforms of four key nodes in the oscillator circuit are given. When C0 is charging, the CK signal is high. It can be seen that due to the constant charging current, the voltage changes uniformly with time. Meanwhile, C1, due to the conduction of M11, discharges directly through the transistor M10, exhibiting a voltage curve similar to RC discharge. Similarly, when C1 is charging, the CK signal is low, and the voltage changes uniformly with time. Meanwhile, C1, due to the conduction of M7, discharges directly through the transistor M6, exhibiting a voltage curve similar to RC discharge.

[0194] The period of the output square wave signal is:

[0195]

[0196] Wherein, the threshold voltage V THN It decreases non-linearly with increasing temperature. medium μ n It increases non-linearly with increasing temperature, but because V THN The value is much greater than Therefore, it can be seen from formula (6) that, when the effect of capacitance change with temperature is not considered, the main temperature coefficient of the voltage change of NMOS capacitor C1 is mainly determined by V, which has a negative temperature coefficient. THN When I com When used as a constant current source, the period of the output square wave signal exhibits a negative temperature coefficient characteristic as the temperature changes. Furthermore, V THN The value of the charging time t in formula (3) varies by more than 50% due to temperature and process variations, making it difficult to ensure that the charging time t remains near the desired value. Based on these problems, this invention proposes a temperature-compensated current generation circuit and a cascode mirror circuit, which can use V... THN The voltage generates a temperature compensation current that is proportional to the temperature, enabling the low-temperature drift coefficient oscillator circuit to output a square wave signal that is independent of temperature.

[0197] like Figure 6 As shown, the reference current I0 uses the same current I. ref The current flows through the diode-connected NMOS transistor M0, generating the corresponding gate-source voltage of NMOS transistor M0:

[0198]

[0199] It employs a low-temperature-coefficient resistor and a negative feedback circuit network to generate a current at the output that is proportional to the gate-source voltage of the NMOS transistor M0, the magnitude of which is:

[0200]

[0201] Therefore, the period of the output square wave signal becomes:

[0202] T = 2C × R

[0203] Therefore, by using a temperature-compensated current generation circuit and a cascode mirror circuit, a compensation current with the same temperature coefficient as the capacitor charging and discharging voltage difference is generated, reducing temperature drift. However, manufacturing process errors still affect the oscillator frequency. Therefore, an adjustable zero-temperature resistor unit is used to adjust the oscillator period to the required clock period, further addressing the mismatch problem caused by high capacitor manufacturing errors and circuit matching. Furthermore, by using a MOS capacitor as the charging and discharging capacitor and controlling the upper and lower limits of its charging and discharging voltage, its capacitance stability is improved, achieving circuit functionality while further reducing mask costs. This invention significantly reduces circuit area and cost, and has a high temperature coefficient and power supply rejection ratio.

[0204] The present invention also provides an oscillator chip, which includes any of the low-cost, low-temperature drift, high power supply rejection ratio oscillator circuits provided in the above embodiments.

[0205] The present invention also provides a device configured with the oscillator chip provided by the present invention, or a low-cost, low-temperature drift, high power supply rejection ratio oscillator circuit.

[0206] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A low-cost, low-temperature drift, high power supply rejection ratio oscillation circuit, characterized in that, include: Temperature-compensated current generation circuit, common-source common-gate mirror circuit, charge-discharge control circuit, discharge discrimination circuit, and reset-position RS flip-flop, first current source; The output terminal of the temperature-compensated current generating circuit is connected to the input terminal of the common-source cascode mirror circuit; The output terminal of the common source cascode mirror circuit is connected to the first input terminal and the second input terminal of the charge / discharge control circuit, respectively. The first output terminal of the charge / discharge control circuit is connected to the first input terminal of the discharge discrimination circuit, and the second output terminal is connected to the second input terminal of the discharge discrimination circuit. The first input terminal of the RS flip-flop is connected to the first output terminal of the discharge discrimination circuit, the second input terminal is connected to the second output terminal of the discharge discrimination circuit, the first output terminal is connected to the fourth and fifth input terminals of the charge and discharge control circuit, and the second output terminal is connected to the third and sixth input terminals of the charge and discharge control circuit respectively. The first current source is connected to the seventh and eighth input terminals of the charge and discharge control circuit, respectively. The temperature compensation current generating circuit is used to generate a first temperature compensation current; The common-source cascode mirror circuit is used to mirror the first temperature compensation current to obtain the second temperature compensation current. The charge-discharge control circuit is used to charge and discharge internal devices according to the second temperature compensation current, the output signal of the RS flip-flop and the output current of the first current source, so as to output a first voltage signal and a second voltage signal. The discharge discrimination circuit is used to output a corresponding first level signal and a corresponding second level signal according to the first voltage signal and the second voltage signal; The RS flip-flop is used to output a first clock signal and a second clock signal according to the first level signal and the second level signal, wherein the first clock signal and the second clock signal have the same frequency but opposite phase.

2. The circuit according to claim 1, characterized in that, The temperature compensation current generating circuit includes: Temperature-compensated current generation unit and adjustable zero-temperature resistor unit; The first output terminal of the temperature-compensated current generating unit is connected to the input terminal of the common-source cascode mirror circuit, and the second output terminal is connected to the first input terminal of the adjustable zero-temperature resistor unit. The second input terminal of the adjustable zero-temperature resistance unit is connected to an external adjustment control signal, and the output terminal is connected to the input terminal of the temperature compensation current generating unit. The adjustable zero-temperature resistor unit is used to change its own resistance value according to an external control signal, and then adjust the voltage signal fed back to the temperature compensation current generating unit according to the voltage signal input to the temperature compensation current generating unit, so as to adjust the first temperature compensation current output by the temperature compensation current generating unit, thereby adjusting the signal period of the first clock signal and the second clock signal.

3. The circuit according to claim 2, characterized in that, The charge-discharge control circuit includes a first charge-discharge control unit and a second charge-discharge control unit. The first input terminal of the first charge-discharge control unit and the first input terminal of the second charge-discharge control unit are both connected to the output terminal of the common source cascode mirror circuit; The output terminal of the first charge / discharge control unit is connected to the first input terminal of the discharge discrimination circuit and the second input terminal of the discharge discrimination circuit; The second input terminal of the second charge-discharge control unit and the fourth input terminal of the first charge-discharge control unit are both connected to the first output terminal of the RS trigger; The second input terminal of the first charge-discharge control unit and the fourth input terminal of the second charge-discharge control unit are both connected to the second output terminal of the RS trigger; The third input terminal of the first charging and discharging control unit and the third input terminal of the second charging and discharging control unit are both connected to the first current source; The first charge-discharge control unit is used to charge and discharge internal devices according to the second temperature compensation current, the output signal of the RS trigger and the output current of the first current source, so as to output a first voltage signal; The second charge / discharge control unit is used to charge and discharge internal devices according to the second temperature compensation current, the output signal of the RS trigger and the output current of the first current source, so as to output a second voltage signal.

4. The circuit according to claim 3, characterized in that, The discharge discrimination circuit includes a first discharge discrimination unit and a second discharge discrimination unit; The input terminal of the first discharge discrimination unit is connected to the output terminal of the first charge and discharge control unit; The input terminal of the second discharge discrimination unit is connected to the output terminal of the second charge and discharge control unit; The output terminal of the first discharge discrimination unit is connected to the first input terminal of the RS flip-flop, and the output terminal of the second discharge discrimination unit is connected to the second input terminal of the RS flip-flop; The first discharge discrimination unit is used to output a corresponding first level signal according to the first voltage signal; The second discharge discrimination unit is used to output a corresponding second flat signal according to the second voltage signal.

5. The circuit according to any one of claims 2-4, characterized in that, The charge / discharge control unit includes a charge / discharge control subunit and a MOSFET capacitor; The input terminal of the charge / discharge control subunit is connected to the output terminal of the common source cascode mirror circuit, the output terminal of the RS flip-flop, and the first current source, respectively. The output terminal of the charge / discharge control subunit is connected to the MOS transistor capacitor; The charge / discharge control subunit is used to charge and discharge the MOS transistor capacitor according to the second temperature compensation current, the output signal of the RS flip-flop and the output current of the first current source, so as to adjust the first voltage signal output by the MOS transistor capacitor.

6. The circuit according to claim 5, characterized in that, The adjustable zero-temperature resistance unit includes n-2 n Decoder, 2 n One inverter, 2 n One resistor, and 2 n There are n transmission gate switches, where n is a positive integer; The n-2 n The decoder's encoded signal input is connected to the external tuning control signal, 2 n The output terminals are connected to the corresponding inverter input terminals and the positive control terminals of the corresponding transmission gate switches, respectively. The output terminal of each inverter is connected to the inverting control terminal of the corresponding transmission gate switch; The 2 n The second input and output terminals of each transmission gate switch are connected to the input terminal of the temperature compensation current generating unit; The first terminal of each resistor is connected to the first input / output terminal of the corresponding transmission gate switch; The 2 n The first end of a resistor connected in series, and connected only to one of the transmission gate switches, is connected to the second output terminal of the temperature compensation current generating unit.

7. The circuit according to claim 6, characterized in that, The temperature-compensated current generating unit includes a second current source, a first transistor and a second transistor, and an operational amplifier; The second current source is connected to the drain of the first transistor and the positive input terminal of the operational amplifier, respectively. The inverting input terminal of the operational amplifier is connected to the output terminal of the adjustable zero-temperature resistor unit, and the output terminal is connected to the gate of the second transistor. The source of the second transistor is connected to the first input terminal of the adjustable zero-temperature resistor unit, and the drain is connected to the input terminal of the common-source common-gate mirror circuit.

8. The circuit according to claim 6 or 7, characterized in that, The common-source cascode mirror circuit includes a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; The drain of the third transistor is connected to the source of the fourth transistor; The drain of the fourth transistor is the input terminal of the cascode mirror circuit, and is connected to the gate of the third transistor and the gate of the fifth transistor, respectively. The drain of the fifth transistor is connected to the source of the sixth transistor; The drain of the sixth transistor is the output terminal of the cascode mirror circuit; The gate of the fourth transistor is connected to the gate of the sixth transistor.

9. The circuit according to claim 8, characterized in that, The charging and discharging control unit includes a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor, as well as a MOS transistor capacitor; The source of the tenth transistor is connected to the output terminal of the common-source common-gate mirror circuit, and the drain is connected to the drain of the eighth transistor and the gate of the MOS transistor capacitor. The gate of the MOS transistor capacitor is the output terminal of the charge-discharge control unit. The gate of the tenth transistor is connected to the gate of the eighth transistor and the output of the RS flip-flop. The source of the eighth transistor is connected to the drain and gate of the seventh transistor, and the drain of the ninth transistor, respectively. The source of the seventh transistor is connected to the source and gate of the MOS transistor capacitor; The gate of the ninth transistor is connected to the output of the RS flip-flop, and its source is connected to the first current source.

10. The circuit according to claim 9, characterized in that, The discharge discrimination unit includes an eleventh transistor, a twelfth transistor, and a third current source; The drain and gate of the eleventh transistor are both connected to the source of the twelfth transistor. The drain of the twelfth transistor is connected to the third current source, and the gate is the input terminal of the discharge discrimination unit.

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