Inverters and Fault Detection Methods

Abstract

An inverter and a fault detection method are disclosed, relating to the field of inverters. The inverter includes a DC bus, an inverter circuit, and a controller, or includes a DC bus, an inverter circuit, an output filter circuit, and a controller. Compared to fault detection using the inverter's output signal, fault detection using this voltage difference is beneficial because the voltage difference between the output potential point of at least one inverter bridge arm of the inverter circuit or the voltage across the capacitor in the output filter circuit and the reference potential point of the DC bus is not affected by the output filter circuit. This voltage difference helps avoid fault detection delays and improves fault detection efficiency and timeliness. Furthermore, by connecting a voltage-regulating resistor in parallel to each of the at least two switching transistors on at least one inverter bridge arm, voltage stabilization can be achieved, ensuring that the actual value of the aforementioned voltage difference does not deviate significantly from the true value due to aging of the switching transistors, thereby improving the accuracy of fault detection.

Description

Technical Field

[0001] This application belongs to the field of inverters, specifically relating to an inverter and a fault detection method. Background Technology

[0002] If a fault in the inverter circuit is not detected in time, the continued operation of the inverter may cause other circuits in the inverter to malfunction, resulting in a fault propagation phenomenon. Therefore, timely detection of inverter circuit faults enables timely protective actions to be taken to prevent the fault from spreading.

[0003] Currently, the inverter's output signal is typically used to detect whether the inverter circuit is faulty. However, because the inverter contains an output filter circuit, there is a certain delay in using the inverter's output signal to detect inverter circuit faults. This prevents timely detection of inverter circuit faults and affects the efficiency and timeliness of fault detection. Summary of the Invention

[0004] To improve the efficiency and timeliness of fault detection in inverter circuits, as well as the accuracy of fault detection in inverter circuits, this application provides the following aspects.

[0005] In a first aspect, an inverter according to this application includes a DC bus, an inverter circuit, and a controller.

[0006] The DC bus can be the energy transmission channel of the inverter. It has two ports, positive and negative, and is responsible for transmitting DC power to the inverter circuit for conversion.

[0007] In one possible implementation, the DC bus has a reference potential point, which may include any one of the positive input potential point of the DC bus, the negative input potential point of the DC bus, or the midpoint clamping input potential point of the DC bus.

[0008] Inverter circuits can include various topologies, such as single-phase, multi-phase, two-level, multi-level, neutral point clamped (NPC), and T-type structures. They use transistors, insulated-gate bipolar transistors (IGBTs), and field-effect transistors (MOSFETs) to switch current and convert DC to AC.

[0009] In one possible implementation, the inverter circuit may include one or more inverter bridge arms, with one input terminal of each inverter bridge arm connected to the positive terminal of the DC bus, the other input terminal of each inverter bridge arm connected to the negative terminal of the DC bus, and at least one inverter bridge arm having all or part of the switching transistors connected in parallel with a voltage-regulating resistor.

[0010] It should be noted that since parallel voltage regulator resistors across the switching transistors may reduce the operating performance of the inverter circuit, in actual fault detection, this application can connect voltage regulator resistors in parallel to all switching transistors, or selectively connect them to some switching transistors, depending on the specific topology and component parameters of the inverter circuit. Furthermore, this application can dynamically adjust the switching transistors connected to the parallel voltage regulator resistors and the resistance values ​​of the voltage regulator resistors to achieve an effective balance between the operating performance of the inverter circuit and the accuracy of fault detection.

[0011] Furthermore, while a higher number of switching transistors with parallel voltage-regulating resistors may reduce the performance of the inverter circuit, it also increases the accuracy of fault detection. Therefore, to achieve an effective balance between inverter circuit performance and fault detection accuracy, this application limits the number of switching transistors with parallel voltage-regulating resistors to at least two. In other words, at least two switching transistors on at least one inverter bridge arm are connected in parallel with voltage-regulating resistors.

[0012] In one possible implementation, the at least two switches can be any switches on the inverter bridge arm, can be switches with a positive half-cycle, can be switches with a negative half-cycle, or can be switches with one end connected to the output potential point of at least one inverter bridge arm. The specific type can be determined according to the topology of the inverter bridge arm.

[0013] In this way, this application allows for flexible configuration of which switching transistors on the inverter bridge arm require parallel voltage-regulating resistors based on the inverter bridge arm topology, achieving an effective balance between inverter circuit performance and fault detection accuracy. Furthermore, the method of connecting a voltage-regulating resistor in parallel to a switching transistor with one end connected to the output potential point of the inverter bridge arm ensures both a small number of switching transistors requiring parallel voltage-regulating resistors and consistent inverter circuit performance. In other words, this method achieves a better balance between inverter circuit performance and fault detection accuracy.

[0014] In one possible implementation, the voltage regulator resistor connected in parallel with the switching transistor can be a single resistor, or multiple resistors connected in parallel and / or in series. This allows for flexible configuration of the voltage regulator resistor, improving the flexibility of fault detection.

[0015] In one possible implementation, each inverter bridge arm of the inverter circuit has an NPC-I type three-level topology or an NPC-T type three-level topology, which consists of four switching transistors, four voltage-regulating resistors, and two diodes. The connection point between the upper and lower bridge arms of this NPC-I type three-level topology or NPC-T type three-level topology is the output potential point of the inverter bridge arm, and each switching transistor in this NPC-I type three-level topology or NPC-T type three-level topology is connected in parallel with a voltage-regulating resistor.

[0016] Thus, this application can improve the NPC-I type three-level topology or the NPC-T type three-level topology by connecting a voltage-regulating resistor in parallel with each switching transistor, so as to realize fault detection of inverter circuits with improved NPC-I type three-level topology or NPC-T type three-level topology.

[0017] In one possible implementation, each inverter bridge arm of the inverter circuit has an NPC-I type three-level topology or an NPC-T type three-level topology, which consists of four switching transistors, two voltage-regulating resistors, and two diodes. The connection point between the upper and lower bridge arms of this NPC-I type three-level topology or NPC-T type three-level topology is the output potential point of the inverter bridge arm, and each of the two switching transistors connected to the output potential point of the inverter bridge arm in the NPC-I type three-level topology or NPC-T type three-level topology has a voltage-regulating resistor connected in parallel.

[0018] Thus, this application can improve the NPC-I type three-level topology or the NPC-T type three-level topology by connecting some of the switching transistors in parallel with voltage-regulating resistors, so as to realize fault detection of inverter circuits with improved NPC-I type three-level topology or NPC-T type three-level topology.

[0019] In one possible implementation, each of the multiple inverter arms includes at least two switches on the upper arm and at least two switches on the lower arm;

[0020] The connection point between the upper and lower arms of each inverter bridge arm is the output potential point of the inverter bridge arm.

[0021] Each switching transistor on both the upper and lower arms of each inverter bridge arm is connected in parallel with a voltage-regulating resistor; or,

[0022] Each inverter bridge arm has two switching transistors connected in parallel to the output potential point of the inverter bridge arm on both the upper and lower bridge arms.

[0023] Thus, this application can improve the NPC-I type three-level topology by connecting a voltage-regulating resistor in parallel with each or some of the switching transistors, so as to enable fault detection of inverter circuits with the improved NPC-I type three-level topology.

[0024] In one possible implementation, each of the multiple inverter arms includes a first switch, a second switch, a third switch, a fourth switch, a first diode, and a second diode;

[0025] The collector of the first switching transistor is connected to the positive input terminal of the DC bus, and the emitter of the first switching transistor is connected to the negative terminal of the first diode and the collector of the second switching transistor, respectively.

[0026] The collector of the third switch is connected to the emitter of the second switch and the output potential point of the inverter bridge arm, respectively. The emitter of the third switch is connected to the positive terminal of the second diode and the collector of the fourth switch, respectively.

[0027] The negative terminal of the second diode is connected to the midpoint clamping input terminal of the DC bus and the positive terminal of the first diode, respectively.

[0028] The emitter of the fourth switching transistor is connected to the negative input terminal of the DC bus;

[0029] In this configuration, the first, second, third, and fourth switching transistors are all connected in parallel with voltage-regulating resistors; or, the second and third switching transistors are each connected in parallel with voltage-regulating resistors.

[0030] Thus, this application can improve the NPC-I type three-level topology by connecting a voltage-regulating resistor in parallel with each or some of the switching transistors, so as to enable fault detection of inverter circuits with the improved NPC-I type three-level topology.

[0031] In one possible implementation, each inverter arm of the inverter circuit has an ANPC three-level topology, which consists of four high-frequency switches, two power-frequency switches, and six voltage-regulating resistors. The connection point between the two power-frequency switches is the output potential point of the inverter arm, and each switch in the ANPC three-level topology is connected in parallel with a voltage-regulating resistor.

[0032] Thus, this application can improve the ANPC three-level topology by connecting a voltage regulator resistor in parallel with each switch, so as to enable fault detection of inverter circuits with the improved ANPC three-level topology.

[0033] In one possible implementation, each of the multiple inverter arms includes a fifth and a sixth switch on the upper arm, and a seventh, a eighth, a ninth, and a tenth switch on the lower arm.

[0034] The collector of the fifth switch is connected to the positive input terminal of the DC bus, and the emitter of the fifth switch is connected to the collectors of the sixth switch and the ninth switch, respectively.

[0035] The collector of the seventh switch is connected to the emitter of the sixth switch and the output potential point of the inverter bridge arm, respectively. The emitter of the seventh switch is connected to the collector of the eighth switch and the emitter of the tenth switch, respectively.

[0036] The emitter of the eighth switching transistor is connected to the negative input terminal of the DC bus;

[0037] The emitter of the ninth switch is connected to the midpoint clamping input terminal of the DC bus and the collector of the tenth switch, respectively.

[0038] Among them, the fifth, sixth, seventh, eighth, ninth, and tenth switching transistors are all connected in parallel with voltage-regulating resistors; or, the sixth and seventh switching transistors are each connected in parallel with voltage-regulating resistors.

[0039] Thus, this application can improve the NPC-I type three-level topology by connecting a voltage-regulating resistor in parallel with each or some of the switching transistors, so as to enable fault detection of inverter circuits with the improved NPC-I type three-level topology.

[0040] In one possible implementation, each inverter bridge arm of the inverter circuit has a T-type three-level topology, which consists of four switching transistors and four voltage-regulating resistors. The connection point between the vertical and horizontal arms of this T-type three-level topology is the output potential point of the inverter bridge arm, and each switching transistor in this T-type three-level topology is connected in parallel with a voltage-regulating resistor.

[0041] Thus, this application can improve the T-type three-level topology by connecting a voltage regulator resistor in parallel with each switch, so as to enable fault detection of inverter circuits with the improved T-type three-level topology.

[0042] In one possible implementation, each inverter bridge arm of the inverter circuit has a T-type three-level topology, which consists of four switching transistors and two voltage-regulating resistors. The connection point between the vertical and horizontal bridge arms of this T-type three-level topology is the output potential point of the inverter bridge arm, and each switching transistor on the vertical bridge arm is connected in parallel with a voltage-regulating resistor.

[0043] Thus, this application can improve the T-type three-level topology by connecting some of the switching transistors in parallel with voltage-regulating resistors, so as to realize fault detection of inverter circuits with improved T-type three-level topology.

[0044] In one possible implementation, each of the multiple inverter arms includes at least two switching transistors on the vertical arm and at least two switching transistors on the horizontal arm;

[0045] The connection point between the vertical and horizontal arms of each inverter bridge arm is the output potential point of the inverter bridge arm.

[0046] Each switch on the vertical arm of each inverter bridge arm and each switch on the horizontal arm is connected in parallel with a voltage-regulating resistor; or,

[0047] Each inverter bridge arm has two switching transistors connected in parallel to the output potential point of the inverter bridge arm on its vertical bridge arm.

[0048] Thus, this application can improve the T-type three-level topology by connecting some of the switching transistors in parallel with voltage-regulating resistors, so as to realize fault detection of inverter circuits with improved T-type three-level topology.

[0049] In one possible implementation, each of the multiple inverter arms includes an eleventh and fourteenth switch on the vertical arm and a twelfth and thirteenth switch on the horizontal arm.

[0050] The collector of the eleventh switch is connected to the positive input terminal of the DC bus, and the emitter of the eleventh switch is connected to the collector of the thirteenth switch, the collector of the fourteenth switch, and the output potential point of the inverter bridge arm, respectively.

[0051] The collector of the thirteenth switch is connected to the midpoint clamping input terminal of the DC bus, and the emitter of the thirteenth switch is connected to the emitter of the fourteenth switch.

[0052] The emitter of the fourteenth switch is connected to the negative input terminal of the DC bus;

[0053] Among them, the eleventh, twelfth, thirteenth and fourteenth switching transistors are all connected in parallel with voltage-regulating resistors; or, the eleventh and fourteenth switching transistors are each connected in parallel with voltage-regulating resistors.

[0054] Thus, this application can improve the T-type three-level topology by connecting a voltage-regulating resistor in parallel with each or some of the switching transistors, so as to enable fault detection of inverter circuits with the improved T-type three-level topology.

[0055] The controller serves as the intelligent control center of the inverter, responsible for monitoring and controlling its operating status. It typically consists of a microcontroller or digital signal processor (DSP), which acquires and processes various signals to control the inverter circuit's operation and output parameters. Furthermore, the controller can detect inverter circuit faults based on the circuit's output signals.

[0056] The controller can be used to output a signal indicating that the inverter is in a fault state based on the voltage difference between the output potential point of at least one inverter bridge arm and the reference potential point of the DC bus.

[0057] The inverter being in a fault state can indicate a fault in the inverter circuit, or a fault in a circuit within the inverter (such as the inverter circuit itself or the drive circuit). Faults can include switching transistor faults in the inverter circuit, drive circuit faults, drive signal trace faults, inverter circuit over-temperature, and inverter over-temperature. Switching transistor faults in the inverter circuit include overcurrent in the switching transistor, short circuit in the switching transistor, decreased equivalent insulation resistance of the switching transistor, and inability of the switching transistor to conduct.

[0058] It is evident that, compared to fault detection via the inverter's output signal, fault detection via this voltage difference is beneficial in avoiding fault detection delays and improving fault detection efficiency and timeliness, since the voltage difference between the output potential point of at least one inverter bridge arm and the reference potential point of the DC bus is not affected by the output filter circuit.

[0059] Meanwhile, since the voltage at the output potential point of at least one inverter bridge arm may be affected by factors such as aging of the switching transistors, reduced lifespan, or increased operating time, the actual value of the voltage difference may deviate significantly from the true value, resulting in inaccurate fault detection. Therefore, by connecting a voltage regulator resistor in parallel to each of the at least two switching transistors on at least one inverter bridge arm, a voltage stabilizing effect can be achieved, ensuring that the actual value of the voltage difference does not deviate significantly from the true value due to factors such as aging of the switching transistors, thereby improving the accuracy of fault detection.

[0060] When a certain voltage is applied to a non-operating inverter arm via the DC bus, if all the switches on that inverter arm are functioning correctly (e.g., not short-circuited or with reduced equivalent insulation resistance), the absolute value of the voltage difference between the output potential of that inverter arm and the reference potential of the DC bus will be approximately equal to a preset value (e.g., 0V). However, if one or more switches on that inverter arm fail, the absolute value of the voltage difference between the output potential of that inverter arm and the reference potential of the DC bus may exceed the preset value.

[0061] Based on this, the controller can detect whether the absolute value of the voltage difference between the output potential point and the reference potential point of at least one inverter bridge arm exceeds a preset value. If the absolute value of the voltage difference exceeds the preset value, the controller outputs a signal indicating that the inverter is in a fault state, thereby realizing fault detection through the output signal of the inverter circuit.

[0062] In one possible implementation, the preset value can be obtained through repeated experimental measurements. In each measurement, it is ensured that the inverter circuit has a fixed circuit topology and fixed component parameters, that the inverter circuit is in a non-operating state, and that the inverter circuit has not malfunctioned. Furthermore, the preset value obtained from the experimental measurements will differ depending on the different circuit topologies and component parameters of the inverter circuit.

[0063] In one possible implementation, the reference potential point of the DC bus may include any of the following: the positive input potential point of the DC bus, the negative input potential point of the DC bus, or the midpoint clamping input potential point of the DC bus.

[0064] When a certain voltage is applied to a working inverter bridge arm through the DC bus, under normal drive conditions, the voltage difference between the output potential point of that inverter bridge arm and the reference potential point of the DC bus is compared with multiple reference voltages to obtain multiple comparison results. These multiple comparison results are then matched with the comparison results under normal drive conditions. At this point, if the inverter circuit malfunctions, these multiple comparison values ​​will not perfectly match the comparison results under normal drive conditions; if the inverter circuit is not malfunctioning, these multiple comparison values ​​will perfectly match the comparison results under normal drive conditions.

[0065] In other words, the controller can compare the voltage difference between the output potential point of at least one inverter bridge arm and the reference potential point with multiple reference voltages to obtain multiple comparison results. These multiple comparison results are then matched with the comparison results under normal drive conditions. If at least one of the multiple comparison results is inconsistent with the comparison results under normal drive conditions, the controller outputs a signal indicating that the inverter is in a fault state, thereby enabling fault detection through the output signal of the inverter circuit.

[0066] In one possible implementation, the comparison result under normal driving can be understood as all or part of the driving signals output by the driving circuit under normal operation.

[0067] In one possible implementation, the multiple reference voltages can be multiple preset voltages measured experimentally and stored in the controller; multiple reference voltages can be obtained by connecting multiple bus capacitors in series with the DC bus voltage; or multiple reference voltages can be obtained by dividing the DC bus voltage with multiple bus resistors, etc., without specific limitations.

[0068] In one possible implementation, there may be multiple reference voltages, including two reference voltages, one of which (referred to as the "first reference voltage") is less than half of the DC bus voltage and is the negative terminal voltage of the DC bus, while the other (referred to as the "second reference voltage") is greater than half of the DC bus voltage and less than the positive terminal voltage of the DC bus.

[0069] In this way, the controller can compare the voltage difference between the output potential point and the reference potential point of at least one inverter bridge arm with a first reference voltage and a second reference voltage, respectively, to obtain two comparison results (referred to as "first comparison result" and "second comparison result"). Then, the first and second comparison results are matched with the comparison results under normal drive conditions. Specifically, the first comparison result includes cases where the voltage difference between the output potential point and the reference potential point of at least one inverter bridge arm is greater than the first reference voltage, and cases where the voltage difference between the output potential point and the reference potential point of at least one inverter bridge arm is less than the first reference voltage; the second comparison result includes cases where the voltage difference between the output potential point and the reference potential point of at least one inverter bridge arm is greater than the second reference voltage, and cases where the voltage difference between the output potential point and the reference potential point of at least one inverter bridge arm is less than the second reference voltage.

[0070] If either the first comparison result or the second comparison result is inconsistent with the given comparison result, the controller outputs a signal indicating that the inverter is in a fault state. Therefore, by using two reference voltages, fault detection can be easily achieved through the output signal of the inverter circuit, improving fault detection efficiency.

[0071] In one possible implementation, the first reference voltage is one-quarter of the DC bus voltage; the second reference voltage is three-quarters of the DC bus voltage. This allows for easy comparison of the voltage difference with both one-quarter and three-quarters of the DC bus voltage, providing two possible comparison results.

[0072] Optionally, the multiple reference voltages may include three reference voltages, wherein the first reference voltage is less than one-third of the DC bus voltage and greater than the negative terminal voltage of the DC bus, the second reference voltage is greater than one-third of the DC bus voltage and less than two-thirds of the DC bus voltage, and the third reference voltage is greater than two-thirds of the DC bus voltage and less than the positive terminal voltage of the DC bus.

[0073] In this way, the controller can compare the voltage difference between the output potential point and the reference potential point of at least one inverter bridge arm with three reference voltages, obtaining three comparison results. These three comparison results are then matched with the comparison results under normal drive conditions. If at least one of the three comparison results is inconsistent with the comparison results under normal drive conditions, the controller outputs a signal indicating that the inverter is in a fault state. Therefore, using two reference voltages facilitates fault detection through the output signal of the inverter circuit.

[0074] Of course, multiple reference voltages can also include one reference voltage, or three or more reference voltages.

[0075] In one possible implementation, the reference potential point of the DC bus may include the negative input potential point of the DC bus.

[0076] Secondly, this application provides an inverter, which includes a DC bus, an inverter circuit, an output filter circuit, and a controller.

[0077] In one possible implementation, the DC bus and inverter circuit in the second aspect are consistent with the DC bus and inverter circuit in the first aspect described above.

[0078] The output filter circuit in an inverter plays a role in smoothing the output voltage, reducing harmonic interference, and filtering out high-frequency noise and harmonics. For example, by filtering out high-frequency components in the output voltage of the inverter circuit, the output voltage becomes closer to a pure sine wave.

[0079] In one possible implementation, the output filter circuit can have various topologies, such as a single-L filter circuit, an RC filter circuit, an LC filter circuit, an LCL filter circuit, etc.

[0080] When the inverter circuit is not in operation, the output signal across the capacitor in the output filter circuit can be approximately equal to the output signal of the inverter circuit. At this time, the inverter circuit fault can be detected by the output signal across the capacitor in the filter circuit, which can also avoid fault detection delay and improve fault detection efficiency and timeliness.

[0081] When the inverter circuit is in a non-operating state, since the voltage across the capacitor in the output filter circuit can be equal to the voltage at the output potential point of at least one inverter bridge arm, combined with the above-mentioned "Method 1", when a certain voltage is applied to a non-operating inverter bridge arm through the DC bus, if all the switches on that inverter bridge arm are not faulty (e.g., short-circuited or with reduced equivalent insulation impedance), the absolute value of the voltage difference between the voltage across the capacitor in the output filter circuit and the voltage at the reference potential point of the DC bus can be approximately equal to a preset value (e.g., 0V). However, if one or more switches on that inverter bridge arm are faulty, the absolute value of the voltage difference between the voltage across the capacitor in the output filter circuit and the voltage at the reference potential point of the DC bus may exceed this preset value.

[0082] Based on this, the controller can detect whether the absolute value of the voltage difference between the voltage across the capacitor in the output filter circuit and the voltage at the reference potential point of the DC bus exceeds a preset value. If the absolute value of the voltage difference exceeds the preset value, the controller outputs a signal indicating that the inverter is in a fault state.

[0083] It is evident that, compared to fault detection through the inverter's output signal, when the inverter circuit is in a non-operating state, the voltage across the capacitor in the output filter circuit can be equal to the voltage of the output potential point of at least one inverter bridge arm of the inverter circuit. Furthermore, the voltage difference between the voltage across the capacitor in the output filter circuit and the voltage of the reference potential point of the DC bus is not affected by other components in the output filter circuit. Therefore, fault detection through this voltage difference is beneficial to avoid fault detection delays and improve fault detection efficiency and timeliness.

[0084] Meanwhile, since the voltage at the output potential point of at least one inverter bridge arm may be affected by factors such as aging of the switching transistors, reduced lifespan, or increased operating time, the voltage across the capacitor in the output filter circuit will also be affected. This will cause a large error between the actual value and the true value of the voltage difference, resulting in inaccurate fault detection. Therefore, by connecting a voltage regulator resistor in parallel to each of the at least two switching transistors on at least one inverter bridge arm, a voltage stabilizing effect can be achieved, ensuring that the actual value of the voltage difference does not deviate significantly from the true value due to factors such as aging of the switching transistors, thereby improving the accuracy of fault detection.

[0085] In one possible implementation, the preset value can be obtained through repeated experimental measurements. In each measurement, it is ensured that the inverter circuit and output filter circuit have fixed circuit topologies and component parameters, that the inverter circuit is in a non-operating state, and that neither the inverter circuit nor the output filter circuit malfunctions. Furthermore, the "preset value" obtained from the experimental measurements will differ depending on the different circuit topologies and component parameters of the inverter circuit and / or the output filter circuit.

[0086] In one possible implementation, the reference potential point of the DC bus may include any of the following: the positive input potential point of the DC bus, the negative input potential point of the DC bus, or the midpoint clamping input potential point of the DC bus.

[0087] Thirdly, a fault detection method according to this application is applied to an inverter, the inverter including a DC bus and an inverter circuit, the inverter circuit including multiple inverter bridge arms, one input terminal of the multiple inverter bridge arms being connected to the positive terminal of the DC bus, and the other input terminal of the multiple inverter bridge arms being connected to the negative terminal of the DC bus; each of at least two switching transistors on at least one of the multiple inverter bridge arms is connected in parallel with a voltage-regulating resistor; the method includes:

[0088] The inverter is determined to be in a fault state based on the voltage difference between the output potential point of at least one inverter bridge arm and the reference potential point of the DC bus; the reference potential point includes any one of the following: the positive input potential point of the DC bus, the negative input potential point of the DC bus, and the midpoint clamping input potential point of the DC bus.

[0089] It is evident that, compared to fault detection via the inverter's output signal, fault detection via this voltage difference is beneficial in avoiding fault detection delays and improving fault detection efficiency and timeliness, since the voltage difference between the output potential point of at least one inverter bridge arm and the reference potential point of the DC bus is not affected by the output filter circuit.

[0090] Meanwhile, since the voltage at the output potential point of at least one inverter bridge arm may be affected by factors such as aging of the switching transistors, reduced lifespan, or increased operating time, the actual value of the voltage difference may deviate significantly from the true value, resulting in inaccurate fault detection. Therefore, by connecting a voltage regulator resistor in parallel to each of the at least two switching transistors on at least one inverter bridge arm, a voltage stabilizing effect can be achieved, ensuring that the actual value of the voltage difference does not deviate significantly from the true value due to factors such as aging of the switching transistors, thereby improving the accuracy of fault detection.

[0091] In one possible implementation, one end of each of at least two switching transistors is connected to the output potential point of at least one inverter bridge arm.

[0092] Thus, by connecting a switching transistor with a parallel voltage-regulating resistor at one end to the output potential point of the inverter bridge arm, this method ensures that the number of switching transistors connected to the parallel voltage-regulating resistor is small while maintaining the operating performance of the inverter circuit. In other words, this method achieves a better balance between the operating performance of the inverter circuit and the accuracy of fault detection.

[0093] In one possible implementation, determining that the inverter is in a fault state based on the voltage difference between the output potential point of at least one inverter bridge arm and the reference potential point of the DC bus includes:

[0094] If the absolute value of the voltage difference between the output potential point and the reference potential point of at least one inverter bridge arm exceeds a preset value, the inverter is determined to be in a fault state.

[0095] In this way, by checking whether the absolute value of the voltage difference between the output potential point of at least one inverter bridge arm and the reference potential point exceeds a preset value, it is easy to detect whether the inverter circuit is faulty, thus improving the fault detection efficiency.

[0096] In one possible implementation, the reference potential point includes the negative input potential point of the DC bus;

[0097] Determining that the inverter is in a fault state based on the voltage difference between the output potential point of at least one inverter bridge arm and the reference potential point of the DC bus includes:

[0098] If either the first comparison result or the second comparison result is inconsistent with the comparison result under normal drive, the inverter is determined to be in a fault state.

[0099] The first comparison result is the difference between the voltage difference between the output potential point and the reference potential point of at least one inverter bridge arm and the first reference voltage.

[0100] The second comparison result is the difference between the voltage difference between the output potential of at least one inverter bridge arm and the reference potential point and the second reference voltage.

[0101] The first reference voltage is less than half of the DC bus voltage, and the second reference voltage is greater than half of the DC bus voltage.

[0102] It is evident that by comparing the voltage difference with two reference voltages, the comparison results can be compared with the comparison results under normal driving conditions. This makes it easy to detect whether the inverter circuit is faulty and improves the fault detection efficiency.

[0103] In one possible implementation, the first reference voltage is one-quarter of the DC bus voltage; the second reference voltage is three-quarters of the DC bus voltage. This allows for easy comparison of the voltage difference with both one-quarter and three-quarters of the DC bus voltage, providing two possible comparison results.

[0104] Fourthly, this application provides a fault detection method applied to an inverter. The inverter includes a DC bus, an inverter circuit, and an output filter circuit. The inverter circuit includes multiple inverter bridge arms. One input terminal of each inverter bridge arm is connected to the positive terminal of the DC bus, and the other input terminal of each inverter bridge arm is connected to the negative terminal of the DC bus. At least two switching transistors on at least one of the inverter bridge arms are connected in parallel with a voltage-regulating resistor. The method includes:

[0105] If the absolute value of the target voltage difference exceeds the preset value, the inverter is determined to be in a fault state.

[0106] The target voltage difference is the difference between the voltage across the capacitor in the output filter circuit and the voltage at the reference potential point of the DC bus. The reference potential point includes any one of the following: the positive input potential point of the DC bus, the negative input potential point of the DC bus, or the midpoint clamping input potential point of the DC bus.

[0107] It is evident that, compared to fault detection through the inverter's output signal, when the inverter circuit is in a non-operating state, the voltage across the capacitor in the output filter circuit can be equal to the voltage of the output potential point of at least one inverter bridge arm of the inverter circuit. Furthermore, the voltage difference between the voltage across the capacitor in the output filter circuit and the voltage of the reference potential point of the DC bus is not affected by other components in the output filter circuit. Therefore, fault detection through this voltage difference is beneficial to avoid fault detection delays and improve fault detection efficiency and timeliness.

[0108] Meanwhile, since the voltage at the output potential point of at least one inverter bridge arm may be affected by factors such as aging of the switching transistors, reduced lifespan, or increased operating time, the voltage across the capacitor in the output filter circuit will also be affected. This will cause a large error between the actual value and the true value of the voltage difference, resulting in inaccurate fault detection. Therefore, by connecting a voltage regulator resistor in parallel to each of the at least two switching transistors on at least one inverter bridge arm, a voltage stabilizing effect can be achieved, ensuring that the actual value of the voltage difference does not deviate significantly from the true value due to factors such as aging of the switching transistors, thereby improving the accuracy of fault detection.

[0109] In one possible implementation, the at least two switches can be any switches on the inverter bridge arm, can be switches with a positive half-cycle, can be switches with a negative half-cycle, or can be switches with one end connected to the output potential point of the inverter bridge arm. The specific type can be determined according to the topology of the inverter bridge arm.

[0110] In this way, this application allows for flexible configuration of which switching transistors on the inverter bridge arm require parallel voltage-regulating resistors based on the inverter bridge arm topology, achieving an effective balance between inverter circuit performance and fault detection accuracy. Furthermore, the method of connecting a voltage-regulating resistor in parallel to a switching transistor with one end connected to the output potential point of the inverter bridge arm ensures both a small number of switching transistors requiring parallel voltage-regulating resistors and consistent inverter circuit performance. In other words, this method achieves a better balance between inverter circuit performance and fault detection accuracy. Attached Figure Description

[0111] Figure 1 This is a schematic diagram of the architecture of a photovoltaic energy storage system according to an embodiment of this application;

[0112] Figure 2 This is a schematic diagram of the structure of a switching transistor according to an embodiment of this application;

[0113] Figure 3 This is a schematic diagram of the structure of an inverter according to an embodiment of this application;

[0114] Figure 4 This is a schematic diagram of an inverter circuit with an NPC-I type three-level topology according to an embodiment of this application;

[0115] Figure 5 This is a schematic diagram of another inverter circuit with an NPC-I type three-level topology according to an embodiment of this application;

[0116] Figure 6 This is a schematic diagram of an inverter circuit with an NPC-T type three-level topology according to an embodiment of this application;

[0117] Figure 7 This is a schematic diagram of another inverter circuit with an NPC-T type three-level topology according to an embodiment of this application;

[0118] Figure 8 This is a schematic diagram of an inverter circuit with a T-type three-level topology according to an embodiment of this application;

[0119] Figure 9 This is a schematic diagram of another inverter circuit with a T-type three-level topology according to an embodiment of this application;

[0120] Figure 10 This is a schematic diagram of an inverter circuit with an ANPC three-level topology according to an embodiment of this application;

[0121] Figure 11 This is a schematic diagram of another inverter circuit with an ANPC three-level topology according to an embodiment of this application;

[0122] Figure 12 This is a schematic diagram of the structure of a driving circuit driving an inverter circuit in a working state according to an embodiment of this application;

[0123] Figure 13 This is a schematic diagram of the structure of another inverter according to an embodiment of this application;

[0124] Figure 14 This is a schematic diagram of another driving circuit driving an inverter circuit to a working state according to an embodiment of this application;

[0125] Figure 15 This is a schematic diagram of the structure of another inverter according to an embodiment of this application;

[0126] Figure 16 This is a flowchart illustrating a fault detection method according to an embodiment of this application;

[0127] Figure 17 This is a schematic diagram of the structure of another inverter according to an embodiment of this application;

[0128] Figure 18 This is a schematic diagram of an inverter circuit connected to an output filter circuit according to an embodiment of this application;

[0129] Figure 19 This is a flowchart illustrating another fault detection method according to an embodiment of this application. Detailed Implementation

[0130] To enable those skilled in the art to better understand the technical solutions of this application, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the description of the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0131] It should be understood that the terms "first," "second," etc., used in this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, software, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but also includes steps or units not listed, or other steps or units inherent to such processes, methods, products, or apparatus.

[0132] The term "embodiment" in this application means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. Furthermore, the embodiments described herein may be combined with other embodiments.

[0133] In the embodiments of this application, "and / or" can describe the relationship between associated objects, and there can be three types of relationships. For example, A and / or B can represent the following three cases: "A", "B", and "A and B". Among them, A and B can be singular or plural.

[0134] In this application's embodiments, the symbol " / " can indicate that the preceding and following objects are in an "or" relationship. Additionally, the symbol " / " can also represent a division sign, i.e., performing a division operation. For example, A / B can mean A divided by B.

[0135] In the embodiments of this application, "at least one item" or its similar expression refers to any combination of these items, including any combination of a single item or a plurality of items, meaning one or more; "multiple items" means two or more. For example, at least one item of a, b, or c can represent the following seven cases: "a", "b", "c", "a and b", "a and c", "b and c", and "a, b, and c". Each of a, b, and c can be an element or a set containing one or more elements.

[0136] In the embodiments of this application, "coupling" and "connection" can be used to refer to electrical connections, which may include direct connections via wires or connection terminals or indirect connections via other devices (such as inductors, capacitors, or resistors). Therefore, "coupling" and "connection" can be considered as a broad type of electronic communication connection. Furthermore, the mutual coupling / direct coupling / connection shown or discussed may be indirect coupling or connection through interfaces, devices, units, or components, and may be communication, electrical, or other forms.

[0137] The circuits or other components in the embodiments of this application may be described as "used for" performing one or more tasks. In this context, "used for" can imply a structure (e.g., a circuit system) that indicates the circuit / component includes a structure that performs one or more tasks during operation. Therefore, even when the specified circuit / component is currently inoperable, it can still be referred to as "used for performing the task." Circuits / components used with the term "used for" include hardware, such as circuits that perform operations.

[0138] To better understand the embodiments of this application, the technical solutions, beneficial effects, and related concepts involved in the embodiments of this application will be specifically described below.

[0139] In an inverter circuit, a fault is generally considered to have occurred when at least one switching transistor exhibits overcurrent, short circuit, reduced equivalent insulation resistance, or inability to conduct. If a fault in the inverter circuit is not detected in time, it may trigger faults in other circuits within the inverter as the inverter continues to operate, resulting in a fault propagation phenomenon. Therefore, to prevent fault propagation, it is necessary to detect inverter circuit faults as promptly as possible. However, when using the inverter's output signal to detect inverter circuit faults, the presence of an output filtering circuit within the inverter introduces a certain delay in fault detection.

[0140] Taking photovoltaic energy storage systems as an example, such as Figure 1 As shown, the photovoltaic energy storage system 10 includes a photovoltaic panel 110, an inverter 120, and a transformer 130. The inverter 120 includes an inverter circuit 1201, an output filter circuit 1202, and a detection circuit 1203. The photovoltaic energy storage system 10 primarily converts solar energy into electrical energy through the photovoltaic panel 110, then converts the direct current (DC) to alternating current (AC) through the inverter 120, and finally, the voltage and current are regulated by the transformer 130 to supply power to the load or the power grid. The inverter circuit 1201 converts DC to AC by controlling switching transistors (such as transistors or switching devices). The output filter circuit 1202 (such as an LCL filter circuit) typically uses inductors, capacitors, and other components to filter harmonics and interference signals. The detection circuit 1203 is used to monitor the operating status of the inverter 120 and parameters such as output voltage and current.

[0141] Of course, the inverter 120 may also include other circuits, such as drive circuits, control circuits, protection circuits, etc., without specific limitations.

[0142] As can be seen, when using the output signal of inverter 120 to detect faults in inverter circuit 1201, the inverter circuit 1201 converts DC to AC, and the AC current flows to the output filter circuit 1202. Since the output filter circuit 1202 contains capacitors or inductors, the charging and discharging process of the AC points on the capacitors or inductors requires a certain amount of time. This results in a certain delay in the output signal of inverter 120 (i.e., the signal flowing to transformer 130). Therefore, when using the output signal of inverter 120 to detect faults in inverter circuit 1201, the delay in the output signal also leads to a delay in fault detection, making it impossible to detect faults in inverter circuit 1201 in a timely manner, thus affecting the efficiency and timeliness of fault detection in inverter circuit 1201.

[0143] Based on this, this application can detect inverter circuit faults by using the output signal of the inverter circuit (i.e., "Scheme 1" below), or by using the output signal across the capacitor in the output filter circuit (i.e., "Scheme 2" below).

[0144] Therefore, compared to fault detection using the inverter's output signal, since the inverter circuit's output signal is not affected by the output filter circuit, fault detection using the inverter circuit's output signal helps avoid fault detection delays and improves fault detection efficiency and timeliness. Alternatively, when the inverter circuit is not operating, the output signal across the capacitor in the output filter circuit is to some extent equivalent to the inverter circuit's output signal. In this case, detecting inverter circuit faults using the output signal across the capacitor in the filter circuit can also avoid fault detection delays and improve fault detection efficiency and timeliness.

[0145] Meanwhile, voltage-regulating resistors are connected in parallel across some or all of the switching transistors in the inverter circuit. This is because the actual output signal of the inverter circuit may be affected by factors such as aging of the switching transistors, reduced lifespan, or increased operating time, leading to a significant error between the actual output signal and the true output signal. This results in inaccurate fault detection. Therefore, connecting voltage-regulating resistors in parallel helps to stabilize the voltage, ensuring that the actual output signal of the inverter circuit does not deviate significantly from the true output signal due to aging of the switching transistors, thus improving the accuracy of fault detection.

[0146] For example, taking an Insulated Gate Bipolar Transistor (IGBT) as the switching transistor... Figure 2 As shown. In Figure 2 In (a), no voltage-regulating resistor is connected in parallel across the switching transistor 200, and the switching transistor 200 has an equivalent insulation resistance 201. This equivalent insulation resistance 201 gradually decreases as the switching transistor 200 ages, its lifespan decreases, or its operating time increases, while the leakage current of the switching transistor 200 gradually increases with its aging. Therefore, for an inverter circuit containing the switching transistor 200, the aging of the switching transistor 200 can cause a significant deviation between the actual output signal and the true output signal of the inverter circuit. Furthermore, the inaccuracy of the inverter circuit's output signal ultimately leads to inaccurate fault detection.

[0147] exist Figure 2In (b), a voltage regulator resistor 202 is connected in parallel across the switching transistor 200. Since the equivalent insulation impedance 201 is much larger than the resistance of the voltage regulator resistor 202, the current flows through the voltage regulator resistor 202, making the voltage across the switching transistor 200 approximately equal to the voltage across the voltage regulator resistor 202. Thus, even with aging of the switching transistor 200, the resistance of the voltage regulator resistor 202 remains constant for a long time, ensuring a stable voltage across it. Therefore, the aging of the switching transistor 200 has a smaller impact on the output signal of the inverter circuit, resulting in a smaller deviation between the actual output signal and the true output signal, thereby improving the accuracy of fault detection.

[0148] It should be noted that the voltage-regulating resistor connected in parallel across the switching transistor can be a single resistor, or multiple resistors connected in parallel and / or in series, etc., without any specific restrictions.

[0149] Furthermore, since parallel voltage regulator resistors across the switching transistors may reduce the performance of the inverter circuit, in actual fault detection, this application can connect voltage regulator resistors in parallel to all switching transistors, or selectively connect them to only some, depending on the specific topology and component parameters of the inverter circuit. Simultaneously, this application can also dynamically adjust the switching transistors connected in parallel with the voltage regulator resistors and the resistance values ​​of the regulator resistors to achieve an effective balance between the inverter circuit's performance and the accuracy of fault detection.

[0150] The following application will provide a detailed explanation of the above content from several different perspectives. These different perspectives can be independent of each other, or they can be related or combined; no specific restrictions are imposed on this.

[0151] In “Option 1”, the inverter may include a DC bus, an inverter circuit and a controller.

[0152] For example, such as Figure 3 As shown, the inverter 300 includes a DC bus 310, an inverter circuit 320, and a controller 330. The inverter circuit 320 includes one or more inverter arms 321; one input terminal of each inverter arm 321 is connected to the positive terminal of the DC bus 310, and the other input terminal of each inverter arm 321 is connected to the negative terminal of the DC bus 310; the input terminal of the controller 330 is connected to the output terminal of each inverter arm 321.

[0153] The functions of the DC bus, inverter circuit, and controller are explained in detail below.

[0154] The DC bus can be the energy transmission channel of the inverter. It has two ports, positive and negative, and is responsible for transmitting DC power to the inverter circuit for conversion.

[0155] The positive terminal can be a positive potential port on the DC bus, usually connected to the positive terminal of an external DC power supply. The external DC power supply generates DC current, which is input to the DC bus through the positive terminal, and then transmitted by the DC bus to the inverter circuit for conversion and processing.

[0156] The negative terminal can be a negative potential port on the DC bus, usually connected to the negative terminal of an external DC power supply. Electrons generated by the internal chemical reaction of the external DC power supply flow through the negative terminal into the DC bus, forming a closed circuit.

[0157] Optionally, the DC bus has a reference potential point. This reference potential point includes any one of the following: the positive input potential point of the DC bus, the negative input potential point of the DC bus, or the midpoint clamping input potential point of the DC bus.

[0158] It should be noted that the midpoint clamp input potential of the DC bus refers to the potential point connected to the midpoint of the DC bus in a DC power supply system. In some specific DC power supply systems, such as bipolar DC power supplies or high-voltage DC transmission systems, a midpoint clamp exists. This midpoint clamp is located in the middle of the DC bus and usually has a fixed potential value. The midpoint clamp is crucial for the operation of a balanced system, as it provides a reliable reference potential and ensures potential balance among the various parts of the circuit.

[0159] Inverter circuits can include various topologies, such as single-phase, multi-phase, two-level, multi-level, NPC, and T-type structures. They use transistors, IGBTs, MOSFETs, and other switching devices to switch current and convert DC to AC.

[0160] Optionally, the inverter circuit may include one or more inverter bridge arms, with one input terminal of each inverter bridge arm connected to the positive terminal of the DC bus, the other input terminal of each inverter bridge arm connected to the negative terminal of the DC bus, and at least one inverter bridge arm having all or part of the switching transistors connected in parallel with a voltage-regulating resistor.

[0161] It should be noted that the more switching transistors connected in parallel with voltage-regulating resistors, the more likely the inverter circuit's performance will be reduced. However, the more switching transistors connected in parallel with voltage-regulating resistors, the more likely the accuracy of fault detection will be guaranteed. Therefore, in order to achieve an effective balance between the inverter circuit's performance and the accuracy of fault detection, this application may limit the number of switching transistors connected in parallel with voltage-regulating resistors to at least one or at least two. That is, at least one inverter bridge arm has at least one or at least two switching transistors connected in parallel with voltage-regulating resistors.

[0162] Optionally, the at least one switch can be any switch on the inverter bridge arm, a switch during the positive half-cycle, a switch during the negative half-cycle, a switch on the upper bridge arm, a switch on the lower bridge arm, a switch on the horizontal bridge arm, a switch on the vertical bridge arm, or a switch whose end is connected to the output potential point of the inverter bridge arm. The specific switch can be determined according to the topology of the inverter bridge arm.

[0163] Optionally, the at least two switching transistors can be any switching transistors on the inverter bridge arm, can be switching transistors in the positive half-cycle, can be switching transistors in the negative half-cycle, can be switching transistors in the upper bridge arm, can be switching transistors in the lower bridge arm, can be switching transistors in the horizontal bridge arm, can be switching transistors in the vertical bridge arm, or can be switching transistors whose ends are connected to the output potential point of the inverter bridge arm. The specific transistors can be determined according to the topology of the inverter bridge arm.

[0164] In this way, this application allows for flexible configuration of which switching transistors on the inverter bridge arm require parallel voltage-regulating resistors based on the inverter bridge arm topology, achieving an effective balance between inverter circuit performance and fault detection accuracy. Furthermore, the method of connecting a voltage-regulating resistor in parallel to a switching transistor with one end connected to the output potential point of the inverter bridge arm ensures both a small number of switching transistors requiring parallel voltage-regulating resistors and consistent inverter circuit performance. In other words, this method achieves a better balance between inverter circuit performance and fault detection accuracy.

[0165] The following description uses examples of NPC-I type three-level topology, NPC-T type three-level topology, T type three-level topology, and active neutral point clamped (ANPC) three-level topology for each inverter bridge arm. Of course, this application is not limited to these topologies.

[0166] For example, consider an inverter circuit where each inverter bridge arm has an NPC-I type three-level topology, and all switches on the inverter bridge arm are connected in parallel with voltage-regulating resistors. Figure 4 As shown. In Figure 4In the NPC-I type three-level topology, there are four switching transistors (i.e., switching transistors T411, T412, T413 and T414), four voltage regulator resistors (i.e., voltage regulator resistors R431, R432, R433 and R434), and two diodes (i.e., diodes D425 and D426). The connection point between the upper and lower bridge arms of the NPC-I type three-level topology is the output potential point OUT of the inverter bridge arm. Among them, switch T411 includes diode D421 and a parallel voltage regulator resistor R431; switch T412 includes diode D422 and a parallel voltage regulator resistor R432; switch T413 includes diode D423 and a parallel voltage regulator resistor R433; switch T414 includes diode D424 and a parallel voltage regulator resistor R434; the collector of switch T411 is connected to the positive input potential point BUS+ of the DC bus, and the emitter of switch T411 is connected to switch T41... The collector of transistor 2 and the negative terminal of diode D425 are connected; the collector of switching transistor T413 is connected to the output potential point OUT of the inverter bridge arm and the emitter of switching transistor T412, respectively; the emitter of switching transistor T413 is connected to the collector of switching transistor T414 and the positive terminal of diode D426, respectively; the emitter of switching transistor T414 is connected to the negative input potential point BUS- of the DC bus; the midpoint clamping input potential point BUSN of the DC bus is connected to the positive terminal of diode D425 and the negative terminal of diode D426, respectively.

[0167] For example, consider an inverter circuit where each inverter bridge arm has an NPC-I type three-level topology, and each of the two switching transistors connected to the output potential point of the inverter bridge arm has a voltage-regulating resistor connected in parallel. Figure 5 As shown. In Figure 5 In the NPC-I type three-level topology, there are four switching transistors (T511, T512, T513, and T514), two voltage regulator resistors (R531 and R532), and two diodes (D525 and D526). Figure 5 and Figure 4 The difference is that only the switching transistors T512 and T513, which are connected to the output potential point of the inverter bridge arm, are each connected in parallel with a voltage regulator resistor R531 and a voltage regulator resistor R532.

[0168] For example, consider an inverter circuit where each inverter bridge arm has an NPC-T three-level topology, and all switches on the inverter bridge arm are connected in parallel with voltage-regulating resistors. Figure 6 As shown. In Figure 6In the NPC-T type three-level topology, there are four switching transistors (i.e., switching transistors T611, T612, T613 and T614), four voltage regulator resistors (i.e., voltage regulator resistors R631, R632, R633 and R634) and two diodes (i.e., diodes D623 and D624). The connection point between the upper and lower bridge arms of the NPC-T type three-level topology is the output potential point of the inverter bridge arm. Among them, switch T611 includes diode D621 and is connected in parallel with voltage regulator resistor R631; switch T612 is connected in parallel with voltage regulator resistor R632; switch T613 is connected in parallel with voltage regulator resistor R633; switch T614 includes diode D622 and is connected in parallel with voltage regulator resistor R634; the collector of switch T611 is connected to the positive input potential point BUS+ of DC bus, and the emitter of switch T611 is connected to the emitter of switch T612, the output potential point of inverter bridge arm, the collector of switch T613, and the collector of switch T614 respectively; the anode of diode D623 is connected to the midpoint clamping input potential point BUSN of DC bus and the cathode of diode D624 respectively, and the cathode of diode D623 is connected to the collector of switch T612; the emitter of switch T614 is connected to the negative input potential point BUS- of DC bus.

[0169] For example, consider an inverter circuit where each inverter bridge arm has an NPC-T type three-level topology, and each of the two switching transistors connected to the output potential point of the inverter bridge arm has a voltage-regulating resistor connected in parallel. Figure 7 As shown. In Figure 7 In the NPC-T type three-level topology, there are four switching transistors (T711, T712, T713, and T714), two voltage regulator resistors (R731 and R732), and two diodes (D723 and D724). Figure 7 and Figure 6 The difference is that only the switching transistors T711 and T714, which are connected to the output potential point of the inverter bridge arm, are each connected in parallel with a voltage regulator resistor R731 and a voltage regulator resistor R732.

[0170] For example, consider an inverter circuit where each inverter bridge arm has a T-type three-level topology, and all switches on the inverter bridge arm are connected in parallel with voltage-regulating resistors. Figure 8 As shown. In Figure 8In the T-type three-level topology, there are four switching transistors (i.e., switching transistors T811, T812, T813, and T814) and four voltage regulator resistors (i.e., voltage regulator resistors R831, R832, ​​R833, and R834). The connection point between the vertical and horizontal bridge arms of the T-type three-level topology is the output potential point of the inverter bridge arm. Among them, switch T811 includes diode D821 and is connected in parallel with voltage regulator resistor R831; switch T812 includes diode D822 and is connected in parallel with voltage regulator resistor R832; switch T813 includes diode D823 and is connected in parallel with voltage regulator resistor R833; switch T814 includes diode D824 and is connected in parallel with voltage regulator resistor R834; the collector of switch T811 is connected to the positive input potential point BUS+ of the DC bus, and the emitter of switch T811 is connected to the collector of switch T813, the output potential point of the inverter bridge arm, and the collector of switch T814; the emitter of switch T812 is connected to the emitter of switch T813, and the collector of switch T812 is connected to the midpoint clamping input potential point BUSN of the DC bus; the emitter of switch T814 is connected to the negative input potential point BUS- of the DC bus.

[0171] For example, consider an inverter circuit where each inverter bridge arm has a T-type three-level topology, and the two switching transistors connected to the output potential point of the inverter bridge arm are each connected in parallel with a voltage-regulating resistor. Figure 9 As shown. In Figure 9 In this T-type three-level topology, there are four switching transistors (T911, T912, T913, and T914) and two regulating resistors (R931 and R932). Figure 9 and Figure 8 The difference is that only the switching transistors T911 and T914, which are connected to the output potential point of the inverter bridge arm, are each connected in parallel with a voltage regulator resistor R931 and a voltage regulator resistor R932.

[0172] For example, consider an inverter circuit where each inverter bridge arm has an ANPC three-level topology, and all switches on the inverter bridge arm are connected in parallel with voltage-regulating resistors. Figure 10 As shown. In Figure 10In the ANPC three-level topology, there are four high-frequency switching transistors (i.e., switching transistors T1011, T1014, T1015, and T1016), two power frequency switching transistors (i.e., switching transistors T1012 and T1013), and six voltage regulator resistors (i.e., voltage regulator resistors R1031, R1032, R1033, R1034, R1035, and R1036). The connection point between the two power frequency switching transistors in the ANPC three-level topology is the output potential point of the inverter bridge arm. Among them, switch T1011 includes diode D1021 and a parallel voltage regulator resistor R1031; switch T1012 includes diode D1022 and a parallel voltage regulator resistor R1032; switch T1013 includes diode D1023 and a parallel voltage regulator resistor R1033; switch T1014 includes diode D1024 and a parallel voltage regulator resistor R1034; switch T1015 includes diode D1025 and a parallel voltage regulator resistor R1035; switch T1016 includes diode D1026 and a parallel voltage regulator resistor R1036; the collector of switch T1011 is connected to the DC bus. The positive input potential point BUS+ is connected to the emitter of switch T1011, which is connected to the collector of switch T1012 and the collector of switch T1015. The collector of switch T1013 is connected to the emitter of switch T1012 and the output potential point of the inverter bridge arm. The emitter of switch T1013 is connected to the collector of switch T1014 and the emitter of switch T1016. The midpoint clamping input potential point BUSN of the DC bus is connected to the emitter of switch T1015 and the collector of switch T1016. The emitter of switch T1014 is connected to the negative input potential point BUS- of the DC bus.

[0173] For example, consider an inverter circuit where each inverter bridge arm has an ANPC three-level topology, and each of the two switching transistors connected to the output potential point of the inverter bridge arm has a voltage-regulating resistor connected in parallel. Figure 11 As shown. In Figure 11 In the ANPC three-level topology, there are six switching transistors (T1111, T1112, T1113, T1114, T1115, and T1116) and two regulating resistors (R1131 and R1132). Figure 11 and Figure 10 The difference is that only the switching transistors T1112 and T1113, which are connected to the output potential point of the inverter bridge arm, are each connected in parallel with a voltage regulator resistor R1131 and a voltage regulator resistor R1132.

[0174] The controller serves as the intelligent control center of the inverter, responsible for monitoring and controlling its operating status. It typically consists of a microcontroller or digital signal processor (DSP), which acquires and processes various signals to control the inverter circuit's operation and output parameters. Furthermore, the controller can detect inverter circuit faults based on the circuit's output signals.

[0175] In a specific implementation, this application can use the voltage difference between the output potential point of at least one inverter bridge arm of the inverter circuit and the reference potential point of the DC bus as the output signal of the inverter circuit. In this way, the controller can output a signal indicating that the inverter is in a fault state based on this voltage difference, thereby enabling fault detection through the output signal of the inverter circuit.

[0176] The following explains how the controller outputs a signal indicating that the inverter is in a fault state based on this voltage difference, using several methods. These methods can be independent or interconnected; no specific restrictions are imposed on this.

[0177] In "Method 1", this application considers the inverter circuit to be in a non-operating state, that is, all switches on each inverter bridge arm of the inverter circuit are in a non-operating or open state (off state). When a certain voltage is applied to a non-operating inverter bridge arm through the DC bus, if all switches on that inverter bridge arm do not fail (e.g., short circuit or reduced equivalent insulation resistance at both ends), the absolute value of the voltage difference between the output potential point of that inverter bridge arm and the reference potential point of the DC bus can be approximately equal to a preset value (e.g., 0V). However, if one or more switches on that inverter bridge arm fail, the absolute value of the voltage difference between the output potential point of that inverter bridge arm and the reference potential point of the DC bus may exceed the preset value.

[0178] Based on this, the controller can detect whether the absolute value of the voltage difference between the output potential point and the reference potential point of at least one inverter bridge arm exceeds a preset value. If the absolute value of the voltage difference exceeds the preset value, the controller outputs a signal indicating that the inverter is in a fault state, thereby realizing fault detection through the output signal of the inverter circuit.

[0179] Optionally, the "preset value" mentioned in "Method 1" can be a value obtained through repeated experimental measurements. In each experimental measurement, it is ensured that the inverter circuit has a fixed circuit topology and fixed component parameters, that the inverter circuit is in a non-operating state, and that the inverter circuit has not malfunctioned. Furthermore, the "preset value" obtained from the experimental measurements will differ depending on the different circuit topologies and component parameters of the inverter circuit.

[0180] Optionally, the "reference potential point of the DC bus" mentioned in "Method 1" may include any of the following: the positive input potential point of the DC bus, the negative input potential point of the DC bus, or the midpoint clamping input potential point of the DC bus.

[0181] The following example uses a specific inverter circuit topology to illustrate "Method 1".

[0182] In one possible implementation, as described above Figure 4 For example, the reference potential points include the DC bus midpoint clamping input potential point BUN, the DC bus positive input potential point BUS+ with a voltage of +100V, the DC bus negative input potential point BUS- with a voltage of -100V, and the DC bus midpoint clamping input potential point BUN with a voltage of 0V. The resistance values ​​of the voltage regulators R431, R432, R433, and R434 are all equal. At this time, the output signal of the inverter circuit is the voltage difference between the inverter bridge arm output potential point OUT and the DC bus midpoint clamping input potential point BUSN. This voltage difference and preset values ​​are shown in Table 1, where the symbol "-" indicates "normal".

[0183] In the second row of Table 1, from Figure 4 It can be seen that when switching transistors T411, T412, T413, and T414, and diodes D425 and D426 are all in "normal" condition, since the resistance values ​​of voltage regulators R431, R432, R433, and R434 are all equal, the voltage difference between the output potential point OUT of the inverter bridge arm and the clamped input potential point BUSN at the midpoint of the DC bus is 0V through the voltage division of these voltage regulators. At this time, the preset value is 0V.

[0184] Table 1

[0185]

[0186] In row 3 of Table 1, from Figure 4 It can be seen that when the switching transistor T411 is "short-circuited" while the other components are "normal," since the resistance values ​​of the voltage regulators R432, R433, and R434 are all equal, the voltage difference between OUT and BUSN through the voltage division of these regulators is one-third of BUS+, i.e., this voltage difference is 33.3V. At this time, the absolute value of this voltage difference, 33.3V, exceeds the preset value of 0V, thus detecting a fault in the inverter circuit. The rest can be understood similarly, and will not be elaborated further.

[0187] It should be noted that checking whether the absolute value of the voltage difference between OUT and BUSN exceeds the preset value can only detect some faults in the inverter circuit. For example, in row 10 of Table 1, when switching transistors T411 and T412 are active, the absolute value of the voltage difference between OUT and BUSN is still equal to the preset value.

[0188] In one possible implementation, as described above Figure 5 For example, the reference potential points include the DC bus midpoint clamping input potential point BUN, the DC bus positive input potential point BUS+ with a voltage of +100V, the DC bus negative input potential point BUS- with a voltage of -100V, the DC bus midpoint clamping input potential point BUN with a voltage of 0V, and the resistance values ​​of the voltage regulator R531 and R532 being equal. At this time, the output signal of the inverter circuit is the voltage difference between the inverter bridge arm output potential point OUT and the DC bus midpoint clamping input potential point BUSN. This voltage difference and preset values ​​are shown in Table 1, where the symbol "-" indicates "normal".

[0189] Table 2

[0190]

[0191] In the second row of Table 2, from Figure 5 It can be seen that when switching transistors T511, T512, T513, and T514, diodes D525 and D526 are all in "normal" condition, the voltage difference between the output potential point OUT of the inverter bridge arm and the midpoint clamping input potential point BUSN of the DC bus is 0V. At this time, the preset value is 0V.

[0192] In row 3 of Table 2, from Figure 5 It can be seen that when the switching transistor T511 is "short-circuited" while the other components are "normal," since the resistance values ​​of the voltage regulator resistors R531 and R532 are equal, the voltage difference between OUT and BUSN through the voltage division of these voltage regulator resistors is half of BUS+, i.e., this voltage difference is 50V. At this time, the absolute value of this voltage difference, 50V, exceeds the preset value of 0V, thus detecting a fault in the inverter circuit. The rest can be understood similarly, and will not be elaborated further.

[0193] It should be noted that checking whether the absolute value of the voltage difference between OUT and BUSN exceeds the preset value can only detect some faults in the inverter circuit. For example, in row 10 of Table 2, when switching transistors T511 and T512 are active, the absolute value of the voltage difference between OUT and BUSN is still equal to the preset value.

[0194] In one possible implementation, as described above Figure 8For example, the reference potential points include the DC bus midpoint clamping input potential point BUN, the DC bus positive input potential point BUS+ with a voltage of +100V, the DC bus negative input potential point BUS- with a voltage of -100V, the DC bus midpoint clamping input potential point BUN with a voltage of 0V, and the resistance values ​​of the voltage regulator R831 and R834 being equal. At this time, the output signal of the inverter circuit is the voltage difference between the inverter bridge arm output potential point OUT and the DC bus midpoint clamping input potential point BUSN. This voltage difference and preset values ​​are shown in Table 3, where the symbol "-" indicates "normal".

[0195] Table 3

[0196]

[0197] In row 2 of Table 3, from Figure 8 It can be seen that when switching transistors T811, T812, T813, and T814 are all in "normal" condition, since the resistance values ​​between voltage regulator resistors R831 and R834 are equal, the voltage difference between the output potential point OUT of the inverter bridge arm and the midpoint clamping input potential point BUSN of the DC bus is 0V through the voltage division of these voltage regulator resistors. At this time, the preset value is 0V.

[0198] In row 3 of Table 3, from Figure 8 It can be seen that when the switching transistor T811 is "short-circuited" while the other components are "normal", OUT is pulled up to BUS+, making the voltage difference between OUT and BUSN 100V. At this time, the absolute value of this voltage difference, 100V, exceeds the preset value of 0V, thus detecting a fault in the inverter circuit.

[0199] In row 6 of Table 3, from Figure 8 As can be seen, when the switching transistor T814 experiences a "short circuit" while the other components are in "normal" condition, OUT is pulled down to BUS-, resulting in a voltage difference of -100V between OUT and BUSN. At this time, the absolute value of this voltage difference, 100V, exceeds the preset value of 0V, thus detecting a fault in the inverter circuit. The rest can be understood similarly, and will not be elaborated further.

[0200] In one possible implementation, as described above Figure 10For example, the reference potential points include the midpoint clamping input potential point BUN of the DC bus, the voltage of the positive input potential point BUS+ of the DC bus is +100V, the voltage of the negative input potential point BUS- of the DC bus is -100V, the voltage of the midpoint clamping input potential point BUN of the DC bus is 0V, and the resistance values ​​of the voltage regulator resistors R1031, R1032, R1033, R1034, R1035, and R1036 are all equal. At this time, the output signal of the inverter circuit is the voltage difference between the output potential point OUT of the inverter bridge arm and the midpoint clamping input potential point BUSN of the DC bus. This voltage difference and preset values ​​are shown in Table 4, where the symbol "-" indicates "normal".

[0201] In row 2 of Table 4, from Figure 10 It can be seen that when switching transistors T1011, T1012, T1013, T1014, T1015, and T1016 are all in "normal" condition, since the resistance values ​​of voltage regulator resistors R1031, R1032, R1033, R1034, R1035, and R1036 are all equal, the voltage difference between the output potential point OUT of the inverter bridge arm and the clamped input potential point BUSN of the DC bus is 0V through the voltage division of these voltage regulator resistors. At this time, the preset value is 0V.

[0202] In row 3 of Table 4, from Figure 10 It can be seen that when the switching transistor T1011 is "short-circuited" while the other components are "normal", since the resistance values ​​of the voltage regulator resistors R1032, R1033, R1034, R1035 and R1036 are all equal, the voltage difference between OUT and BUSN is 40V through the voltage division of these voltage regulator resistors.

[0203] At this point, the absolute value of the voltage difference, 40V, exceeds the preset value of 0V, thus detecting a fault in the inverter circuit. The rest follows the same logic, and will not be elaborated further.

[0204] Table 4

[0205]

[0206] In one possible implementation, as described above Figure 11For example, the reference potential points include the DC bus midpoint clamping input potential point BUN, the DC bus positive input potential point BUS+ with a voltage of +100V, the DC bus negative input potential point BUS- with a voltage of -100V, the DC bus midpoint clamping input potential point BUN with a voltage of 0V, and the resistance values ​​of the voltage regulator resistors R1131 and R1132 being equal. At this time, the output signal of the inverter circuit is the voltage difference between the inverter bridge arm output potential point OUT and the DC bus midpoint clamping input potential point BUSN. This voltage difference and preset values ​​are shown in Table 5, where the symbol "-" indicates "normal".

[0207] In row 2 of Table 5, from Figure 11 It can be seen that when switches T1111, T1112, T1113, T1114, T1115, and T1116 are all in "normal" condition, since the resistance values ​​of voltage regulator resistors R1131 and R1032 are equal, the voltage difference between the output potential point OUT of the inverter bridge arm and the clamped input potential point BUSN of the DC bus is 0V due to the voltage division of these voltage regulator resistors. At this time, the preset value is 0V.

[0208] In row 3 of Table 5, from Figure 11 It can be seen that when the switching transistor T1111 is "short-circuited" while the other components are "normal," since the resistance values ​​of the voltage regulator resistors R1131 and R1132 are equal, the voltage difference between OUT and BUSN is 50V due to the voltage division of these voltage regulator resistors. At this time, the absolute value of this voltage difference, 50V, exceeds the preset value of 0V, thus detecting a fault in the inverter circuit. The rest can be understood similarly, and will not be elaborated further.

[0209] Table 5

[0210]

[0211] In one possible implementation, as described above Figure 5 For example, the reference potential point includes the DC bus midpoint clamping input potential point BUN. When switching transistors T511, T512, T513, and T514, diodes D525 and D526 are all in "normal" condition, the voltage difference between the inverter bridge arm output potential point OUT and the DC bus midpoint clamping input potential point BUSN is 0V. At this time, the preset value is 0V.

[0212] When the leakage current of the switching transistor T511 increases due to aging and the equivalent insulation resistance decreases, the absolute value of the voltage difference between OUT and BUSN exceeds 0V, thus detecting a fault in the inverter circuit.

[0213] When the leakage current of the switching transistor T514 increases due to aging and the equivalent insulation resistance decreases, the absolute value of the voltage difference between OUT and BUSN exceeds 0V, thus detecting a fault in the inverter circuit.

[0214] In "Method 2", this application considers the inverter circuit to be in an operating state under the drive of a drive signal. The drive signal can be used to control each switch on each inverter bridge arm of the inverter circuit to be either in the on state or in the off state. That is, the drive signal can cause the switch to perform a switching action and can drive the switching state of the switch.

[0215] For example, in Figure 9 On the basis of, such as Figure 12 As shown. The DC bus voltage between the positive input potential point BUS+ and the negative input potential point BUS- of the DC bus is U. dc The drive circuit 1210 outputs drive signals, which consist of signals S1, S2, S3, and S4. Signal S1 drives the switching state of switch T911; signal S2 drives the switching state of switch T912; signal S3 drives the switching state of switch T913; and signal S4 drives the switching state of switch T914. If signal S1 is "1", switch T911 is "on"; if signal S1 is "0", switch T911 is "off". If signal S2 is "1", switch T912 is "on"; if signal S2 is "0", switch T912 is "off". If signal S3 is "1", switch T913 is "on"; if signal S3 is "0", switch T913 is "off". When signal S4 is "1", the switching state of switch T914 is "on"; when signal S4 is "0", the switching state of switch T914 is "off". As shown in Table 6, when signals S1 is "1", S2 is "1", S3 is "0", and S4 is "0", switches T911 and T912 are "on", while switches T911 and T912 are "off". At this time, the voltage at the output potential point OUT of the inverter bridge arm is +U. dc / 2 V.

[0216] Table 6

[0217]

[0218] Optionally, the inverter includes a drive circuit. The drive circuit refers to a circuit capable of issuing drive signals to drive the switching transistors to perform switching operations. For example, in... Figure 3 On the basis of, such as Figure 13As shown, the inverter 300 also includes a drive circuit 1310. The drive circuit 1310 outputs a drive signal to drive the switching state of the switching transistors on the inverter bridge arm 321, so that the drive circuit is in the working state.

[0219] Furthermore, in "Method 2," when a certain voltage is applied to a working inverter bridge arm through the DC bus, the voltage difference between the output potential point of that inverter bridge arm and the reference potential point of the DC bus is compared with multiple reference voltages under normal drive conditions, resulting in multiple comparison results. These multiple comparison results are then matched with the comparison results under normal drive conditions. In this case, if the inverter circuit malfunctions, these multiple comparison results cannot perfectly match the comparison results under normal drive conditions; when the inverter circuit is not malfunctioning, these multiple comparison results can perfectly match the comparison results under normal drive conditions.

[0220] In other words, the controller can compare the voltage difference between the output potential point of at least one inverter bridge arm and the reference potential point with multiple reference voltages to obtain multiple comparison results. These multiple comparison results are then matched with the comparison results under normal drive conditions. If at least one of the multiple comparison results is inconsistent with the comparison results under normal drive conditions, the controller outputs a signal indicating that the inverter is in a fault state, thereby enabling fault detection through the output signal of the inverter circuit.

[0221] It should be noted that the comparison result under normal drive conditions can be understood as all or part of the drive signals output by the drive circuit under normal operation. For example, when the drive value under normal drive conditions is "11" as represented by signals S1 and S2 in the second row of Table 6, if multiple comparison results obtained by comparing the magnitudes are "10", "01" or "11", it indicates that the inverter circuit may be faulty; if the multiple comparison results are "11", it indicates that the inverter circuit may not be faulty.

[0222] Optionally, the "multiple reference voltages" mentioned in "Method 2" can be multiple preset voltages measured experimentally and stored in the controller; multiple reference voltages can be obtained by connecting multiple bus capacitors in series with the DC bus voltage; or multiple reference voltages can be obtained by dividing the DC bus voltage with multiple bus resistors, etc., without specific limitations.

[0223] For example, in Figure 4 On the basis of, such as Figure 14 As shown. In Figure 14In this circuit, the DC bus voltage is connected in series with bus capacitors C1411, C1412, C1413, and C1414, and the drive circuit 1420 outputs a drive signal to drive the switching states of switching transistors T411, T412, T413, and T414. There is an input potential point of 3 / 4 Busuer between bus capacitors C1411 and C1412, and an input potential point of 1 / 4 Busuer between bus capacitors C1413 and C1414. The voltages at input potential points 3 / 4 Busuer and 1 / 4 Busuer serve as two reference voltages.

[0224] Optionally, the "multiple reference voltages" mentioned in "Method 2" may include two reference voltages, one of which (referred to as "first reference voltage") is less than half of the DC bus voltage and is the negative terminal voltage of the DC bus, while the other (referred to as "second reference voltage") is greater than half of the DC bus voltage and less than the positive terminal voltage of the DC bus.

[0225] In this way, the controller can compare the voltage difference between the output potential point and the reference potential point of at least one inverter bridge arm with a first reference voltage and a second reference voltage, respectively, to obtain two comparison results (referred to as "first comparison result" and "second comparison result"). Then, the first and second comparison results are matched with the comparison results under normal drive conditions. Specifically, the first comparison result includes cases where the voltage difference between the output potential point and the reference potential point of at least one inverter bridge arm is greater than the first reference voltage, and cases where the voltage difference between the output potential point and the reference potential point of at least one inverter bridge arm is less than the first reference voltage; the second comparison result includes cases where the voltage difference between the output potential point and the reference potential point of at least one inverter bridge arm is greater than the second reference voltage, and cases where the voltage difference between the output potential point and the reference potential point of at least one inverter bridge arm is less than the second reference voltage.

[0226] If either the first comparison result or the second comparison result is inconsistent with the comparison result under normal drive, the controller outputs a signal indicating that the inverter is in a fault state. Therefore, using two reference voltages facilitates fault detection through the inverter circuit's output signal, improving fault detection efficiency.

[0227] Optionally, the first reference voltage is one-quarter of the DC bus voltage; the second reference voltage is three-quarters of the DC bus voltage. This allows for easy comparison of the voltage difference with both one-quarter and three-quarters of the DC bus voltage, providing two comparison results.

[0228] For example, the first reference voltage is Figure 13 The voltage at the input potential point 1 / 4BUS, and the second reference voltage are... Figure 13 The voltage at the input potential point 3 / 4BUS.

[0229] Optionally, the "multiple reference voltages" mentioned in "Method 2" may include three reference voltages, wherein the first reference voltage is less than one-third of the DC bus voltage and greater than the negative terminal voltage of the DC bus, the second reference voltage is greater than one-third of the DC bus voltage and less than two-thirds of the DC bus voltage, and the third reference voltage is greater than two-thirds of the DC bus voltage and less than the positive terminal voltage of the DC bus.

[0230] In this way, the controller can compare the voltage difference between the output potential point and the reference potential point of at least one inverter bridge arm with three reference voltages, obtaining three comparison results. These three comparison results are then matched with the comparison results under normal drive conditions. If at least one of the three comparison results is inconsistent with the comparison results under normal drive conditions, the controller outputs a signal indicating that the inverter is in a fault state. Therefore, using two reference voltages facilitates fault detection through the output signal of the inverter circuit.

[0231] Of course, "multiple reference voltages" in "method 2" can also include one reference voltage or three or more reference voltages, without specific restrictions.

[0232] Optionally, the "reference potential point of the DC bus" in "Method 2" may include the negative input potential point of the DC bus.

[0233] Optionally, in "Method 2," comparing the voltage difference between the output potential point of at least one inverter bridge arm and the reference potential point with multiple reference voltages can be implemented in hardware or software. For example, in hardware implementation, the voltage difference and multiple reference voltages are input to multiple comparators respectively. When the voltage difference is greater than the reference voltage, the comparator outputs "1," otherwise it outputs "0."

[0234] The following example uses a specific inverter circuit topology to illustrate "Method 2".

[0235] In one possible implementation, Figure 14 On the basis of, such as Figure 15As shown. The two ends of sampling resistor R1511 are each connected to the output potential point OUT of the inverter bridge arm and the non-inverting input ("+") of comparator 1521; the input potential point 1 / 4BUS of sampling resistor R1512 is connected to the inverting input ("-") of comparator 1521; the two ends of sampling resistor R1513 are each connected to the output potential point OUT of the inverter bridge arm and the non-inverting input ("+") of comparator 1522; the input potential point 3 / 4BUS of sampling resistor R1514 is connected to the inverting input ("-") of comparator 1522; the controller 1530 is connected to the output terminals of comparator 1521 and comparator 1522 respectively.

[0236] The driver circuit 1420 outputs a drive signal, which consists of signals Sa, Sb, Sc, and Sd. Signal Sa drives the switching state of switch T411; signal Sb drives the switching state of switch T412; signal Sc drives the switching state of switch T413; and signal Sd drives the switching state of switch T414. If signal Sa is "1", switch T411 is "on"; if signal Sa is "0", switch T411 is "off". If signal Sb is "1", switch T412 is "on"; if signal Sb is "0", switch T412 is "off". If signal Sc is "1", switch T413 is "on"; if signal Sc is "0", switch T413 is "off". If signal Sd is "1", then the switching state of switch T414 is "on"; if signal Sd is "0", then the switching state of switch T414 is "off".

[0237] When the drive circuit 1420 drives switch T411 to "conduct" and drives switches T412, T413, and T414 to "turn off," the comparison result under normal drive conditions, composed of signals Sa and Sb, is "10." At this time, taking an example where the reference potential point includes the negative input potential point BUN- of the DC bus, and the resistance values ​​of the four voltage regulator resistors are all the same, if no switch is short-circuited, the voltage difference between the output potential point OUT of the inverter bridge arm and the negative input potential point BUN- of the DC bus is 2 / 3 BUS due to the voltage division between voltage regulator resistors R432, R433, and R434. This voltage difference is greater than 1 / 4 BUS of the input potential point and less than 3 / 4 BUS of the input potential point, causing comparator 1521 to output a comparison result of "1," while comparator 1522 outputs a comparison result of "0." As can be seen, the combination of the two comparison results "10" is consistent with the comparison result "10" under normal drive, indicating that the inverter has not yet malfunctioned.

[0238] However, if the switching transistor T412 short-circuits due to a fault, the output potential point OUT of the inverter bridge arm is pulled up to the positive input potential point BUN+ of the DC bus. This causes the voltage difference between the output potential point OUT of the inverter bridge arm and the negative input potential point BUN- of the DC bus to be greater than the voltage of input potential point 3 / 4BUS and also greater than the voltage of input potential point 1 / 4BUS. Consequently, comparator 1521 and comparator 1522 both output a comparison result of "1". It is evident that the combination of these two comparison results, "11", is inconsistent with the comparison result "10" under normal drive conditions, indicating a fault in the inverter.

[0239] Similarly, when the drive circuit 1420 drives switches T411 and T412 to "conduct" and drives switches T413 and T414 to "turn off", the comparison result under normal drive conditions, composed of signals Sa and Sb, is "11". At this time, taking the reference potential point including the negative input potential point BUN- of the DC bus, and the resistance values ​​of the four voltage regulator resistors being the same, if no switch is short-circuited, the output potential point OUT of the inverter bridge arm is pulled up to the positive input potential point BUN+ of the DC bus. This makes the voltage difference between the output potential point OUT of the inverter bridge arm and the negative input potential point BUN- of the DC bus greater than the voltage of input potential point 3 / 4BUS and also greater than the voltage of input potential point 1 / 4BUS. This causes comparator 1521 to output a comparison result of "1", and comparator 1522 to output a comparison result of "1". It can be seen that the combination of these two comparison results, "11", is consistent with the comparison result "1" under normal drive conditions, indicating that the inverter has not malfunctioned.

[0240] However, if the switching transistor T411 fails to conduct due to a fault, the voltage difference between the output potential point OUT of the inverter bridge arm and the negative input potential point BUN- of the DC bus will be 2 / 3 BUS due to the voltage division between the voltage regulators R431, R433, and R434. This voltage difference is greater than 1 / 4 BUS of the input potential point and less than 3 / 4 BUS of the input potential point, causing comparator 1521 to output a comparison result of "1", while comparator 1522 outputs a comparison result of "0". Therefore, the combination of these two comparison results, "10", is inconsistent with the comparison result "11" under normal drive conditions, indicating a fault in the inverter.

[0241] Based on the content of "Solution 1" above, the following is an exemplary description of a fault detection method, such as... Figure 16 As shown. In Figure 16This fault detection method can be applied to inverters. The inverter includes a DC bus and an inverter circuit. The inverter circuit includes multiple inverter bridge arms. One input terminal of each inverter bridge arm is connected to the positive terminal of the DC bus, and the other input terminal is connected to the negative terminal of the DC bus. At least two switching transistors on at least one of the inverter bridge arms are connected in parallel with a voltage-regulating resistor. The method includes the following steps:

[0242] S1610. Determine that the inverter is in a fault state based on the voltage difference between the output potential point of at least one inverter bridge arm and the reference potential point of the DC bus.

[0243] The reference potential point includes any one of the following: the positive input potential point of the DC bus, the negative input potential point of the DC bus, and the midpoint clamping input potential point of the DC bus.

[0244] It is evident that, compared to fault detection via the inverter's output signal, fault detection via this voltage difference is beneficial in avoiding fault detection delays and improving fault detection efficiency and timeliness, since the voltage difference between the output potential point of at least one inverter bridge arm and the reference potential point of the DC bus is not affected by the output filter circuit.

[0245] Meanwhile, since the voltage at the output potential point of at least one inverter bridge arm may be affected by factors such as aging of the switching transistors, reduced lifespan, or increased operating time, the actual value of the voltage difference may deviate significantly from the true value, resulting in inaccurate fault detection. Therefore, by connecting a voltage regulator resistor in parallel to each of the at least two switching transistors on at least one inverter bridge arm, a voltage stabilizing effect can be achieved, ensuring that the actual value of the voltage difference does not deviate significantly from the true value due to factors such as aging of the switching transistors, thereby improving the accuracy of fault detection.

[0246] Optionally, the at least two switching transistors can be any switching transistors on the inverter bridge arm, can be switching transistors in the positive half-cycle, can be switching transistors in the negative half-cycle, or can be switching transistors whose ends are connected to the output potential point of the inverter bridge arm. The specific type can be determined according to the topology of the inverter bridge arm.

[0247] In this way, this application allows for flexible configuration of which switching transistors on the inverter bridge arm require parallel voltage-regulating resistors based on the inverter bridge arm topology, achieving an effective balance between inverter circuit performance and fault detection accuracy. Furthermore, the method of connecting a voltage-regulating resistor in parallel to a switching transistor with one end connected to the output potential point of the inverter bridge arm ensures both a small number of switching transistors requiring parallel voltage-regulating resistors and consistent inverter circuit performance. In other words, this method achieves a better balance between inverter circuit performance and fault detection accuracy.

[0248] Optionally, determining that the inverter is in a fault state based on the voltage difference between the output potential point of at least one inverter bridge arm and the reference potential point of the DC bus in S1610 may include the following steps:

[0249] If the absolute value of the voltage difference between the output potential point and the reference potential point of at least one inverter bridge arm exceeds a preset value, the inverter is determined to be in a fault state.

[0250] It should be noted that, in conjunction with the content of "Method 1" above, when a certain voltage is applied to a non-operating inverter arm through the DC bus, if none of the switches on that inverter arm are short-circuited or the equivalent insulation resistance at both ends does not decrease, the absolute value of the voltage difference between the output potential point of that inverter arm and the reference potential point of the DC bus can be approximately equal to a preset value (e.g., 0V). However, if one or more switches on that inverter arm are short-circuited or the equivalent insulation resistance at both ends decreases, the absolute value of the voltage difference between the output potential point of that inverter arm and the reference potential point of the DC bus may exceed the preset value. Therefore, whether the absolute value of the voltage difference between the output potential point and the reference potential point of at least one inverter arm exceeds the preset value can be used to detect whether the inverter is faulty.

[0251] Optionally, the reference potential point includes the negative input potential point of the DC bus. In this case, determining that the inverter is in a fault state based on the voltage difference between the output potential point of at least one inverter bridge arm and the reference potential point of the DC bus in S1610 may include the following steps:

[0252] If either the first comparison result or the second comparison result is inconsistent with the comparison result under normal drive, the inverter is determined to be in a fault state.

[0253] The first comparison result is the difference between the voltage difference between the output potential point and the reference potential point of at least one inverter bridge arm and the first reference voltage.

[0254] The second comparison result is the difference between the voltage difference between the output potential of at least one inverter bridge arm and the reference potential point and the second reference voltage.

[0255] The first reference voltage is less than half of the DC bus voltage, and the second reference voltage is greater than half of the DC bus voltage.

[0256] It should be noted that, in conjunction with the content of "Method 2" above, when a certain voltage is applied to a certain inverter bridge arm in operation via the DC bus, the voltage difference between the output potential point of that inverter bridge arm and the reference potential point of the DC bus under normal drive is compared with two reference voltages to obtain two comparison results. These two comparison results are then matched with the comparison results under normal drive. If either of the two comparison results is inconsistent with the drive value, it indicates that the inverter circuit has failed. Therefore, using two reference voltages facilitates the detection of inverter circuit faults based on the voltage difference between the output potential point of at least one inverter bridge arm and the reference potential point of the DC bus, improving fault detection efficiency.

[0257] Optionally, the first reference voltage is one-quarter of the DC bus voltage; the second reference voltage is three-quarters of the DC bus voltage. This allows for easy comparison of the voltage difference with both one-quarter and three-quarters of the DC bus voltage, providing two comparison results.

[0258] In "Scheme 2", the inverter may include a DC bus, an inverter circuit, an output filter circuit, and a controller.

[0259] For example, such as Figure 17 As shown, the inverter 1700 includes a DC bus 1710, an inverter circuit 1720, an output filter circuit 1730, and a controller 1740. The inverter circuit 1720 includes one or more inverter bridge arms 1721; one input terminal of each inverter bridge arm 1721 is connected to the positive terminal of the DC bus 1710, and the other input terminal of each inverter bridge arm 1721 is connected to the negative terminal of the DC bus 1710; the output terminal of each inverter bridge arm 1721 is connected to the input terminal of the output filter circuit 1730; and the output terminal of the output filter circuit 1730 is connected to the input terminal of the controller 1740.

[0260] It should be noted that the "DC bus" and "inverter circuit" involved in "Scheme 2" can be the same as those in the above "Scheme", so they will not be repeated here. The following mainly describes the output filter circuit and controller in detail.

[0261] The output filter circuit in an inverter plays a role in smoothing the output voltage, reducing harmonic interference, and filtering out high-frequency noise and harmonics. For example, by filtering out high-frequency components in the output voltage of the inverter circuit, the output voltage becomes closer to a pure sine wave.

[0262] Output filter circuits can have various topologies, such as single-L filter circuits, RC filter circuits, LC filter circuits, and LCL filter circuits. A single-L filter circuit can consist of an inductor (L) connected in series at the output of the inverter circuit; an RC filter circuit can consist of a capacitor (C) and a resistor (R) connected in series or parallel at the output of the inverter circuit; an LC filter circuit consists of an inductor and a capacitor connected in series or parallel at the output of the inverter circuit; and an LCL filter circuit consists of an inductor, a capacitor, and a resistor connected in series or parallel at the output of the inverter circuit.

[0263] It should be noted that when the inverter circuit is not in operation, the output signal across the capacitor in the output filter circuit can be approximately equal to the output signal of the inverter circuit. In this case, detecting inverter circuit faults by using the output signal across the capacitor in the filter circuit can also avoid fault detection delays and improve fault detection efficiency and timeliness.

[0264] For example, taking an LCL filter circuit as the output filter circuit, such as Figure 18 As shown, the output terminal of inverter circuit 1810 is connected to one end of inductor L1821. The other end of inductor L1821 is connected to one end of inductor L1822 and one end of capacitor C1830, respectively. The other end of capacitor C1830 is grounded to GND. When inverter circuit 1810 is not in operation, the voltage across capacitor C1830 can be equal to the voltage at the output potential point of the inverter bridge arm of inverter circuit 1810.

[0265] When the inverter circuit is in a non-operating state, since the voltage across the capacitor in the output filter circuit can be equal to the voltage at the output potential point of at least one inverter bridge arm, combined with the above-mentioned "Method 1", when a certain voltage is applied to a non-operating inverter bridge arm through the DC bus, if all the switches on that inverter bridge arm are not faulty (e.g., short-circuited or with reduced equivalent insulation impedance), the absolute value of the voltage difference between the voltage across the capacitor in the output filter circuit and the voltage at the reference potential point of the DC bus can be approximately equal to a preset value (e.g., 0V). However, if one or more switches on that inverter bridge arm are faulty, the absolute value of the voltage difference between the voltage across the capacitor in the output filter circuit and the voltage at the reference potential point of the DC bus may exceed this preset value.

[0266] Based on this, the controller can detect whether the absolute value of the voltage difference between the voltage across the capacitor in the output filter circuit and the voltage at the reference potential point of the DC bus exceeds a preset value. If the absolute value of the voltage difference exceeds the preset value, the controller outputs a signal indicating that the inverter is in a fault state, thereby realizing fault detection through the voltage across the capacitor in the output filter circuit.

[0267] Optionally, the "preset value" mentioned in "Scheme 2" can be a value obtained through repeated experimental measurements. In each experimental measurement, it is ensured that the inverter circuit and output filter circuit have fixed circuit topologies and fixed component parameters, that the inverter circuit is in a non-operating state, and that neither the inverter circuit nor the output filter circuit has experienced any faults. Furthermore, the "preset value" obtained from the experimental measurements will differ depending on the different circuit topologies and component parameters of the inverter circuit and / or output filter circuit.

[0268] Optionally, the "reference potential point of the DC bus" mentioned in "Scheme 2" may include any of the following: the positive input potential point of the DC bus, the negative input potential point of the DC bus, and the midpoint clamping input potential point of the DC bus.

[0269] Furthermore, given the specific circuit topology of the inverter circuit and the output filter circuit, those skilled in the art can provide examples of "Scheme 2" in conjunction with the content of "Method 1" above, which will not be elaborated upon further.

[0270] Based on the content of "Solution 2" above, another fault detection method will be illustrated below, such as... Figure 19 As shown. In Figure 19 This fault detection method can be applied to inverters. The inverter may include a DC bus, an inverter circuit, and an output filter circuit. The inverter circuit includes multiple inverter bridge arms, with one input terminal of each bridge arm connected to the positive terminal of the DC bus and the other input terminal connected to the negative terminal of the DC bus. At least two switching transistors on at least one of the inverter bridge arms are connected in parallel with a voltage-regulating resistor. The method includes the following steps:

[0271] S1910. If the absolute value of the target voltage difference exceeds the preset value, the inverter is determined to be in a fault state. The target voltage difference is the difference between the voltage across the capacitor in the output filter circuit and the voltage at the reference potential point of the DC bus.

[0272] The reference potential point includes any one of the following: the positive input potential point of the DC bus, the negative input potential point of the DC bus, and the midpoint clamping input potential point of the DC bus.

[0273] It is evident that, compared to fault detection through the inverter's output signal, when the inverter circuit is in a non-operating state, the voltage across the capacitor in the output filter circuit can be equal to the voltage of the output potential point of at least one inverter bridge arm of the inverter circuit. Furthermore, the voltage difference between the voltage across the capacitor in the output filter circuit and the voltage of the reference potential point of the DC bus is not affected by other components in the output filter circuit. Therefore, fault detection through this voltage difference is beneficial to avoid fault detection delays and improve fault detection efficiency and timeliness.

[0274] Meanwhile, since the voltage at the output potential point of at least one inverter bridge arm may be affected by factors such as aging of the switching transistors, reduced lifespan, or increased operating time, the voltage across the capacitor in the output filter circuit will also be affected. This will cause a large error between the actual value and the true value of the voltage difference, resulting in inaccurate fault detection. Therefore, by connecting a voltage regulator resistor in parallel to each of the at least two switching transistors on at least one inverter bridge arm, a voltage stabilizing effect can be achieved, ensuring that the actual value of the voltage difference does not deviate significantly from the true value due to factors such as aging of the switching transistors, thereby improving the accuracy of fault detection.

[0275] Optionally, the at least two switching transistors can be any switching transistors on the inverter bridge arm, can be switching transistors in the positive half-cycle, can be switching transistors in the negative half-cycle, or can be switching transistors whose ends are connected to the output potential point of the inverter bridge arm. The specific type can be determined according to the topology of the inverter bridge arm.

[0276] In this way, this application allows for flexible configuration of which switching transistors on the inverter bridge arm require parallel voltage-regulating resistors based on the inverter bridge arm topology, achieving an effective balance between inverter circuit performance and fault detection accuracy. Furthermore, the method of connecting a voltage-regulating resistor in parallel to a switching transistor with one end connected to the output potential point of the inverter bridge arm ensures both a small number of switching transistors requiring parallel voltage-regulating resistors and consistent inverter circuit performance. In other words, this method achieves a better balance between inverter circuit performance and fault detection accuracy.

[0277] Optionally, the voltage across the capacitor in the output filter circuit is equal to the voltage at the output potential point of at least one of the multiple inverter bridge arms.

[0278] Optionally, one end of each of at least two switching transistors is connected to the output potential point of at least one inverter bridge arm.

[0279] The steps of the method described in the embodiments of this application can be implemented in hardware or by a processor executing software instructions.

[0280] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this application. It should be understood that the above description is only a specific embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made on the basis of the technical solution of this application should be included within the scope of protection of this application.

Claims

1. An inverter, characterized in that, include: DC bus, inverter circuit and controller; The inverter circuit includes multiple inverter bridge arms, one input terminal of each inverter bridge arm is connected to the positive terminal of the DC bus, and the other input terminal of each inverter bridge arm is connected to the negative terminal of the DC bus. At least two switching transistors on at least one of the plurality of inverter arms are connected in parallel with a voltage-regulating resistor. The controller is configured to output a signal indicating that the inverter is in a fault state based on the voltage difference between the output potential point of the at least one inverter bridge arm and the reference potential point of the DC bus. The reference potential point includes any one of the following: the positive input potential point of the DC bus, the negative input potential point of the DC bus, and the midpoint clamping input potential point of the DC bus; Each of the plurality of inverter bridge arms includes at least two switching transistors on the upper bridge arm and at least two switching transistors on the lower bridge arm. The connection point between the upper and lower bridge arms of each inverter bridge arm is the output potential point of the inverter bridge arm. Each switching transistor on the upper and lower bridge arms of each inverter bridge arm is connected in parallel with a voltage-regulating resistor, or the two switching transistors on the upper and lower bridge arms of each inverter bridge arm that are connected to the output potential point of the inverter bridge arm are connected in parallel with a voltage-regulating resistor. Alternatively, each of the plurality of inverter bridge arms includes at least two switching transistors on a vertical bridge arm and at least two switching transistors on a horizontal bridge arm, the connection point between the vertical bridge arm and the horizontal bridge arm of each inverter bridge arm is the output potential point of the inverter bridge arm, each switching transistor on the vertical bridge arm and each switching transistor on the horizontal bridge arm of each inverter bridge arm is connected in parallel with a voltage-regulating resistor, or the two switching transistors on the vertical bridge arm of each inverter bridge arm connected to the output potential point of the inverter bridge arm are both connected in parallel with a voltage-regulating resistor.

2. The inverter according to claim 1, characterized in that, One end of each of the at least two switching transistors is connected to the output potential point of the at least one inverter bridge arm.

3. The inverter according to claim 1, characterized in that, Each of the plurality of inverter bridge arms includes a first and a second switch on the upper bridge arm, a third and a fourth switch on the lower bridge arm, a first diode, and a second diode. The collector of the first switching transistor is connected to the positive input terminal of the DC bus, and the emitter of the first switching transistor is connected to the negative terminal of the first diode and the collector of the second switching transistor, respectively. The collector of the third switch is connected to the emitter of the second switch and the output potential point of the inverter bridge arm, respectively; the emitter of the third switch is connected to the anode of the second diode and the collector of the fourth switch, respectively. The negative terminal of the second diode is connected to the midpoint clamping input terminal of the DC bus and the positive terminal of the first diode, respectively. The emitter of the fourth switch is connected to the negative input terminal of the DC bus; In this configuration, the first switch, the second switch, the third switch, and the fourth switch are all connected in parallel with a voltage-regulating resistor; or, the second switch and the third switch are each connected in parallel with a voltage-regulating resistor.

4. The inverter according to claim 1, characterized in that, Each of the plurality of inverter bridge arms includes a fifth and a sixth switch on the upper bridge arm, and a seventh, a eighth, a ninth, and a tenth switch on the lower bridge arm. The collector of the fifth switch is connected to the positive input terminal of the DC bus, and the emitter of the fifth switch is connected to the collector of the sixth switch and the collector of the ninth switch, respectively. The collector of the seventh switch is connected to the emitter of the sixth switch and the output potential point of the inverter bridge arm, respectively; the emitter of the seventh switch is connected to the collector of the eighth switch and the emitter of the tenth switch, respectively. The emitter of the eighth switch is connected to the negative input terminal of the DC bus; The emitter of the ninth switch is connected to the midpoint clamping input terminal of the DC bus and the collector of the tenth switch, respectively. The fifth, sixth, seventh, eighth, ninth, and tenth switching transistors are all connected in parallel with voltage-regulating resistors; or, the sixth and seventh switching transistors are each connected in parallel with voltage-regulating resistors.

5. The inverter according to claim 1, characterized in that, Each of the plurality of inverter arms includes an eleventh and fourteenth switch on the vertical arm and a twelfth and thirteenth switch on the horizontal arm. The collector of the eleventh switch is connected to the positive input terminal of the DC bus, and the emitter of the eleventh switch is connected to the collector of the thirteenth switch, the collector of the fourteenth switch, and the output potential point of the inverter bridge arm, respectively. The collector of the twelfth switch is connected to the midpoint clamping input terminal of the DC bus, and the emitter of the twelfth switch is connected to the emitter of the thirteenth switch. The emitter of the fourteenth switch is connected to the negative input terminal of the DC bus; The eleventh, twelfth, thirteenth, and fourteenth switching transistors are all connected in parallel with voltage-regulating resistors; or, the eleventh and fourteenth switching transistors are each connected in parallel with voltage-regulating resistors.

6. The inverter according to any one of claims 1-5, characterized in that, The controller is configured to output a signal indicating that the inverter is in a fault state if the absolute value of the voltage difference between the output potential point of the at least one inverter bridge arm and the reference potential point exceeds a preset value.

7. The inverter according to any one of claims 1-5, characterized in that, The reference potential point includes the negative input potential point of the DC bus; The controller is configured to output a signal indicating that the inverter is in a fault state if either the first comparison result or the second comparison result is inconsistent with the comparison result under normal drive. The first comparison result is a comparison between the voltage difference between the output potential point of the at least one inverter bridge arm and the reference potential point and the first reference voltage. The first comparison result includes cases where the voltage difference between the output potential point of the at least one inverter bridge arm and the reference potential point is greater than the first reference voltage, and cases where the voltage difference between the output potential point of the at least one inverter bridge arm and the reference potential point is less than the first reference voltage. The second comparison result is a comparison between the voltage difference between the output potential point of the at least one inverter bridge arm and the reference potential point and the second reference voltage. The second comparison result includes situations where the voltage difference between the output potential point of the at least one inverter bridge arm and the reference potential point is greater than the second reference voltage, or where the voltage difference between the output potential point of the at least one inverter bridge arm and the reference potential point is less than the second reference voltage; the first reference voltage is less than half of the DC bus voltage, and the second reference voltage is greater than half of the DC bus voltage.

8. The inverter according to claim 7, characterized in that, The first reference voltage is one-quarter of the DC bus voltage; the second reference voltage is three-quarters of the DC bus voltage.

9. An inverter, characterized in that, include: The system includes a DC bus, an inverter circuit, an output filter circuit, and a controller, wherein the inverter circuit is in a non-operating state. The inverter circuit includes multiple inverter bridge arms, one input terminal of each inverter bridge arm is connected to the positive terminal of the DC bus, and the other input terminal of each inverter bridge arm is connected to the negative terminal of the DC bus. At least two switching transistors on at least one of the plurality of inverter arms are connected in parallel with a voltage-regulating resistor. The controller is used to output a signal that the inverter is in a fault state if the absolute value of the target voltage difference exceeds a preset value. The target voltage difference is the difference between the voltage across the capacitor in the output filter circuit and the voltage at the reference potential point of the DC bus. The reference potential point includes any one of the following: the positive input potential point of the DC bus, the negative input potential point of the DC bus, and the midpoint clamping input potential point of the DC bus; Each of the plurality of inverter bridge arms includes at least two switching transistors on the upper bridge arm and at least two switching transistors on the lower bridge arm. The connection point between the upper and lower bridge arms of each inverter bridge arm is the output potential point of the inverter bridge arm. Each switching transistor on the upper and lower bridge arms of each inverter bridge arm is connected in parallel with a voltage-regulating resistor, or the two switching transistors on the upper and lower bridge arms of each inverter bridge arm that are connected to the output potential point of the inverter bridge arm are connected in parallel with a voltage-regulating resistor. Alternatively, each of the plurality of inverter bridge arms includes at least two switching transistors on a vertical bridge arm and at least two switching transistors on a horizontal bridge arm, the connection point between the vertical bridge arm and the horizontal bridge arm of each inverter bridge arm is the output potential point of the inverter bridge arm, each switching transistor on the vertical bridge arm and each switching transistor on the horizontal bridge arm of each inverter bridge arm is connected in parallel with a voltage-regulating resistor, or the two switching transistors on the vertical bridge arm of each inverter bridge arm connected to the output potential point of the inverter bridge arm are both connected in parallel with a voltage-regulating resistor.

10. The inverter according to claim 9, characterized in that, The voltage across the capacitor in the output filter circuit is equal to the voltage at the output potential point of at least one of the plurality of inverter bridge arms.

11. The inverter according to claim 9, characterized in that, One end of each of the at least two switching transistors is connected to the output potential point of the at least one inverter bridge arm.

12. A fault detection method, characterized in that, The method is applied to an inverter, which includes an inverter circuit and a DC bus. The inverter circuit includes multiple inverter bridge arms, one input terminal of each inverter bridge arm is connected to the positive terminal of the DC bus, and the other input terminal of each inverter bridge arm is connected to the negative terminal of the DC bus. At least two switching transistors on at least one of the multiple inverter bridge arms are connected in parallel with a voltage-regulating resistor. Based on the voltage difference between the output potential point of the at least one inverter bridge arm and the reference potential point of the DC bus, a signal indicating that the inverter is in a fault state is output. The reference potential point includes any one of the following: the positive input potential point of the DC bus, the negative input potential point of the DC bus, and the midpoint clamping input potential point of the DC bus; Each of the plurality of inverter bridge arms includes at least two switching transistors on the upper bridge arm and at least two switching transistors on the lower bridge arm. The connection point between the upper and lower bridge arms of each inverter bridge arm is the output potential point of the inverter bridge arm. Each switching transistor on the upper and lower bridge arms of each inverter bridge arm is connected in parallel with a voltage-regulating resistor, or the two switching transistors on the upper and lower bridge arms of each inverter bridge arm that are connected to the output potential point of the inverter bridge arm are connected in parallel with a voltage-regulating resistor. Alternatively, each of the plurality of inverter bridge arms includes at least two switching transistors on a vertical bridge arm and at least two switching transistors on a horizontal bridge arm, the connection point between the vertical bridge arm and the horizontal bridge arm of each inverter bridge arm is the output potential point of the inverter bridge arm, each switching transistor on the vertical bridge arm and each switching transistor on the horizontal bridge arm of each inverter bridge arm is connected in parallel with a voltage-regulating resistor, or the two switching transistors on the vertical bridge arm of each inverter bridge arm connected to the output potential point of the inverter bridge arm are both connected in parallel with a voltage-regulating resistor.

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