High-reliability switch quantity redundant optical transmission system based on FPGA

Abstract

A kind of high reliability switch quantity redundancy optical transmission system based on FPGA, transmitting end, receiving end are all set FPGA chip, high-speed optical module, the transmitting end is also set photoelectric coupler, the FPGA chip on transmitting end is set to shake off module, framing encoding module, high-speed serial transceiver, switch quantity signal is converted into optical signal and is passed to receiving end by optical fiber;Receiving end carries out photoelectric conversion to the optical signal received by its own high-speed optical module, the FPGA chip on receiving end is set high-speed serial transceiver, frame ping-pong recovery module, redundancy processing module, arbitration module, receiving end is also set for the switch quantity signal output by the FPGA of itself is exported to the relay of external. High-speed serial transceiver on FPGA chip is used to carry out frame structure encoding and decoding transmission to switch quantity signal, reduce the probability that data frame is wrongly identified, and can realize fiber redundancy transmission, increase fiber redundancy processing, real-time monitoring optical path communication state, automatically switch optical fiber.

Description

Technical Field

[0001] This invention belongs to the field of optoelectronic transmission technology, specifically relating to a highly reliable switch-quantity redundant optical transmission system based on FPGA. Background Technology

[0002] Switching signals are generally contact signals such as voltage and current. However, transient high voltage, overcurrent, or contact jitter can cause switching signals to malfunction. The following problems may occur during the use of ordinary switching optical transceivers:

[0003] 1. The output of the switch signal is unstable at the moment of power-on startup, which may cause malfunction.

[0004] 2. Transient interference during the input of the switch signal can cause malfunctions in the output of the switch signal at the downstream end.

[0005] 3. When the acquisition of the 1-channel switch signal is incorrect, the output of the switch signal at the back end fails to be valid and cannot be driven;

[0006] 4. The inability to monitor fiber optic link errors in real time leads to intermittent output of switch signals, affecting backend equipment;

[0007] 5. When the optical fiber is disconnected or communication transmission fails, the switch signal output cannot accurately maintain the state before the optical fiber was disconnected, and the switch signal may malfunction randomly.

[0008] 6. Only one optical fiber is used for transmission. If the optical fiber transmission fails, switching actions cannot be performed. Summary of the Invention

[0009] To address the aforementioned technical problems, this invention provides a highly reliable switching redundant optical transmission system based on FPGA.

[0010] The objective of this invention is achieved through the following technical solution. According to this invention, a high-reliability, redundant optical transmission system for switching signals based on an FPGA is proposed, comprising a transmitter and a receiver. Both the transmitter and receiver are equipped with an FPGA chip and a high-speed optical module. The transmitter also includes an optocoupler for isolating, converting, and splitting the input switching signals and transmitting the processed switching signals to the FPGA chip. The FPGA chip on the transmitter is equipped with a debouncing module for real-time oversampling and debouncing of the switching signals, a frame encoding module for framing and encoding the debouncing switching signals, and a high-speed serial transceiver for parallel-to-serial conversion of the framed and encoded switching signals. The converted switching signals are transmitted via... The high-speed optical module at the transmitting end converts the signal into an optical signal and transmits it to the receiving end via optical fiber. The transmitting and receiving ends are connected by a main optical fiber and a backup optical fiber. The receiving end uses its own high-speed optical module to perform photoelectric conversion on the received optical signal. The FPGA chip on the receiving end is equipped with a high-speed serial transceiver that performs serial-to-parallel conversion on the photoelectric converted switch signal, a frame-deframe ping-pong recovery module that performs frame deframe recovery on the serial-to-parallel converted switch signal, a redundancy processing module that switches the optical path between the transmitting and receiving ends, and an adjudication module that judges and decides whether the switch signal is high or low. The receiving end is also equipped with a relay for outputting the switch signal output by its own FPGA to the outside.

[0011] Furthermore, the transmitter introduces external switching signals through a connector. The introduced switching signals are isolated by an optocoupler and converted into LVTTL level standard for use by the main chip FPGA. Each input switching signal is simultaneously acquired through three optocouplers.

[0012] Furthermore, the debouncing module performs real-time oversampling of the input switch signal to the FPGA chip and debouncing the input switch signal. If the external switch signal does not change for more than 20ms, it is determined that the switch signal is stable; otherwise, it is considered that the switch signal is unstable and the previous switch signal state is maintained.

[0013] Furthermore, through the framing and encoding module, the switch signals are transmitted according to a fixed frame format. The data frames have a fixed length, and each data frame contains a frame header identifier, a data field start identifier, a data field end identifier, a frame tail identifier, an idle identifier, and a frame payload. When no data frames are being sent, an idle signal is sent to maintain the continuity of data transmission in the link.

[0014] Furthermore, the 8'hBC in each identifier of the data frame is defined as the 8B / 10B encoded synchronization code K28.5, and the K code identifier is set. The data frame verification adopts cyclic redundancy check CRC-32, and the verification data range is 80 CLKs of the frame payload.

[0015] Furthermore, the high-speed serial transceiver is selected with a line rate of 1.25Gbps, encoding method of 8B / 10B, synchronization code of K28.5, bit width before encoding of 32 bits, and bit width after encoding of 40 bits. The user clock of the high-speed serial transceiver is 31.25MHz. Each data frame output by the framing and encoding module has a total frame length of 100 CLKs, of which 80 CLKs are valid data. The clock frequency occupied by the valid data is 25MHz. Using a clock divider IP core, the local user clock of 31.25MHz is divided by 25MHz, and the 25MHz frequency is used to oversample and debouncing the switch signal.

[0016] Furthermore, the framing and encoding module uses an asynchronous FIFO. The asynchronous FIFO write-side signal has a write clock of 25MHz, and the write enable is to write when the asynchronous FIFO is not full. The write data is a 24-channel debouncing switch signal. The asynchronous FIFO read-side signal has a read clock of 31.25MHz, and the read enable is that the frame payload is not empty and the asynchronous FIFO is not empty. The read data is placed into the high-speed serial transceiver at the transmitter for parallel data transmission.

[0017] Furthermore, the FPGA chip at the receiving end obtains the communication status of the optical link in two ways: the IIC interface monitors the received optical power of the high-speed optical module in real time, and when the received optical power is less than the set threshold, it is considered that the optical path communication is abnormal; the error indication is obtained by using the DC balance signal and polarity signal after 8B / 10B encoding to determine the optical path communication abnormality.

[0018] Furthermore, the frame deframe ping-pong recovery module sets up two-level synchronous FIFOs to store data and realize ping-pong operation: state 1 is to write data to the first-level synchronous FIFO and read data from the second-level synchronous FIFO at the same time. After writing is completed, it enters state 2; state 2 is to write data to the second-level synchronous FIFO and read data from the first-level synchronous FIFO. After writing is completed, it enters state 1. This cycle is repeated to realize frame deframe ping-pong recovery.

[0019] Ping-pong operation includes controlling the read enable, write enable, and reset signals of the two-stage synchronous FIFO:

[0020] Write enable control logic: When the previous frame's 4 frame tail identifiers, the current frame's 10 idle code identifiers, 4 frame header identifiers, and 1 data field start identifier are received consecutively, the data is considered stable, and the write enable is set high. When an optical path communication error is detected, the write enable is set low. After writing 80 CLKs, the write enable is set low.

[0021] Read enable control logic: While writing enable is set high, CRC-32 check is performed on the written data. When 80 CLK data are written, it is determined whether the CRC-32 check passes. If it passes, it means that the written data is completely correct. At this time, read enable is set high. After the synchronous FIFO is emptied, read enable is set low.

[0022] Synchronous FIFO reset control logic: When an optical communication error is detected, the reset position is set high; when the CRC-32 check fails, the reset position is set high.

[0023] Furthermore, the adjudication module adopts a 3-to-2 adjudication module, and the transmitter optocoupler adopts a 1-to-3 optocoupler. The adjudication module processes the 3 switching signals split from the optocoupler and outputs them to the FPGA chip: when 2 or more of the 3 switching signals are high level, the output is high level; when 2 or more of the 3 switching signals are low level, the output is low level.

[0024] Compared with the prior art, the advantages of the present invention are:

[0025] In this invention, a high-speed serial transceiver core (TP) on an FPGA chip is used to perform frame structure encoding and decoding transmission of switch signals. A frame architecture with multiple frame type identifiers, including frame idle code, frame start code, frame end code, and frame CRC check, is designed to reduce the probability of data frames being misidentified. This ensures that the receiving optical transceiver identifies a complete and unique data frame, thereby deframes the frame, recovers the correct switch signal, and improves the reliability of communication transmission.

[0026] During frame decoding, a two-level synchronous FIFO buffer is designed to perform ping-pong operation on the data stream. When there is an optical link error, at least one level of synchronous FIFO buffer data is guaranteed to be correct. This ensures that the switch signal output remains in the state before the error after the optical link error. When resolving optical link errors, the switch signal output remains at the level before the error to prevent malfunctions.

[0027] One-channel switch signal is acquired simultaneously using three optocouplers, achieving link isolation and communication fault tolerance for single-point faults in the switch signal, and avoiding acquisition errors caused by single-point faults at the transmitting end.

[0028] Using FPGA chips to precisely debouncing switch signals prevents glitch signals from being introduced into the switch signals input by the transmitting optical transceiver, which could lead to malfunctions in the output switch signals.

[0029] The receiving end uses a 3-out-of-2 decision mechanism to avoid output errors and malfunctions caused by communication failures of one switch signal.

[0030] This invention enables redundant fiber transmission, increases fiber redundancy processing, monitors the optical path communication status in real time, and can automatically switch fibers based on the optical path communication error status of the primary and backup fibers. During the switching process, the switch output is stable and controllable. When the fiber link communication is abnormal during operation, it can automatically switch to the fiber link with normal communication. When any optical link has an error, it can automatically switch to another optical link to complete the optical transmission of switch signals.

[0031] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0032] Figure 1 This is a block diagram of the transmission architecture according to an embodiment of the present invention;

[0033] Figure 2 This is a schematic diagram of the data frame structure. Detailed Implementation

[0034] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0035] like Figures 1 to 2 As shown, this is an embodiment of a high-reliability switching redundant optical transmission system based on FPGA according to the present invention, including a transmitter and a receiver, and its transmission architecture is as follows. Figure 1 As shown. In this embodiment, the high-reliability switching redundant optical transmission system based on an FPGA chip includes a transmitting optical transceiver and a receiving optical transceiver.

[0036] The transmitting optical transceiver introduces external switching signals through connectors, uses optocouplers to isolate the input switching signals, and converts them to LVTTL level standards for use by the main chip FPGA. In this embodiment, each input switching signal is simultaneously acquired through three optocouplers, splitting each signal into three paths. Therefore, a total of 24 pins are connected to the FPGA chip from the eight externally input switching signals.

[0037] The debouncing module performs real-time oversampling of 24-channel digital input signals. First, it debounces each input signal. If the external digital input signal remains unchanged for more than 20ms, it is considered stable; otherwise, it is considered unstable and its previous state is maintained. After debouncing, the FPGA chip frames and encodes the 24-channel digital input signals. Then, the high-speed serial transceiver (GTX) on the FPGA chip converts the parallel data stream into a high-speed serial data stream, which is then connected to the high-speed optical module at the transmitter for electro-optical conversion. The converted optical signal is then output to an optical fiber through the FC optical interface at the transmitter. The other end of the optical fiber connects to the receiving optical transceiver, thus transmitting the converted optical signal to the receiving optical transceiver.

[0038] The switching signal is transmitted according to a fixed frame format via a framing and encoding module. The dejittered switching signal is then framed and encoded, with the frame format as follows: Figure 2 As shown in Table 1, the identifiers defined in a data frame include the IDLE identifier, frame header identifier, start-of-data-field identifier, end-of-data-field identifier (data-field frame checksum), frame payload, and frame tail identifier. These identifiers, their lengths, and detailed descriptions are provided in Table 1. The identifiers allow us to determine the length and type of the data frame, and also to perform data verification. When there is no data transmission, an IDLE character is transmitted to ensure the continuity of data transmission in the link.

[0039] idle 32'hBC555555 10 Free symbol when no data is transmitted Frame header 32'hBC010101 4 The frame header identifier is used to identify the beginning of valid data. Data domain start 32'hBC020202 1 The data field start identifier is used to identify the beginning of a valid data field. Data domain ends CRC_VALUE 1 The data field end identifier is used to indicate the end of a valid data field. Frame Net Load valid data 80 Transmit switch signals Frame end 32'hBC030303 4 The frame end identifier is used to indicate the end of a frame.

[0040] Table 1

[0041] When transmitting optical signal data, it is transmitted in the form of data frames, which have a fixed length. Each data frame contains a frame header identifier, a data field start identifier, a data field end identifier (data field frame checksum), a frame tail identifier, an idle identifier, and a frame payload. When no data frames are being transmitted, an idle signal is sent to maintain the continuity of data transmission on the link.

[0042] To avoid the presence of 8'hBC in valid data, the 8'hBC in identifiers such as the frame header identifier and frame trailer identifier is defined as the 8B / 10B encoded synchronization code K28.5, and the K code identifier is set. Data frame verification uses Cyclic Redundancy Check (CRC-32), with the verification data range being 80 CLKs of the frame payload.

[0043] The high-speed serial transceiver GTX is selected with a line rate of 1.25Gbps, encoding mode of 8B / 10B, synchronization code of K28.5, bit width before encoding of 32 bits, and bit width after encoding of 40 bits. Based on this, the user clock of the high-speed serial transceiver is calculated to be 31.25MHz.

[0044] As shown in Table 1, the total frame length of the data frame is 100 CLKs, of which 80 CLKs are valid data. The clock frequency occupied by the valid data is calculated to be 25MHz. Using the clock divider TP core, the local user clock of 31.25MHz is divided by 25MHz, and 25MHz is used to oversample and debouncing the switch signal.

[0045] The clock frequency for oversampling the switching signals is 25MHz, and the user clock of the high-speed serial transceiver GTX is 31.25MHz. An asynchronous FIFO is used to solve the cross-clock domain problem, and the framed and encoded switching signals are stored in the asynchronous FIFO. Asynchronous FIFO write-side signals: the write clock is 25MHz, the write enable is to write when the asynchronous FIFO is not full, and the write data is the 24-channel debouncing switching signals; asynchronous FIFO read-side signals: the read clock is 31.25MHz, the read enable is the frame payload in Table 1 and the asynchronous FIFO is not empty, and the read data is put into the parallel data of the high-speed serial transceiver GTX transmit side.

[0046] The receiving optical transceiver sends the optical signal to the high-speed optical module for photoelectric conversion through its own FC optical interface, and then connects to the FPGA high-speed serial transceiver GTX, where the high-speed serial data stream is converted into a parallel data stream.

[0047] The FPGA chip obtains the communication status of the optical link in two ways: the IIC interface monitors the received optical power of the high-speed optical module in real time, and when the received optical power is less than the set threshold, it is considered that the optical path communication is abnormal; after the switching signal is encoded by 8B / 10B, the optical path communication is judged to be abnormal based on the error indication of the DC balance signal and polarity signal that appear with the switching signal.

[0048] The frame deframe ping-pong recovery module on the receiving optical transceiver uses a two-level synchronous FIFO to store data, enabling ping-pong operation: State 1 involves writing data to the first-level synchronous FIFO while simultaneously reading data from the second-level synchronous FIFO. After writing is complete (80 CLKs), it enters State 2. State 2 involves writing data to the second-level synchronous FIFO while reading data from the first-level synchronous FIFO. After writing is complete (80 CLKs), it enters State 1 again, and this cycle repeats to achieve frame deframe ping-pong recovery. The key to the ping-pong operation lies in controlling the read enable, write enable, and reset signals of the two-level synchronous FIFO.

[0049] Write enable control logic: When 19 fixed identifiers are received consecutively, including 4 frame tail identifiers from the previous frame, 10 idle code identifiers from the current frame, 4 frame header identifiers, and 1 data field start identifier, the data is considered stable, and the write enable is set high. When an optical communication error is detected, the write enable is set low. After writing 80 CLKs, the write enable is set low again. Read enable control logic: While the write enable is set high, a CRC-32 check is performed on the written data. When 80 CLKs of data are written, the CRC-32 check is checked. If it passes, it indicates that the written data is completely correct, and the read enable is set high. After the synchronization FIFO is emptied, the read enable is set low. It is particularly important to note that the read enable must not be set low when an optical communication error is detected, because setting the read enable high indicates that the current synchronization FIFO data is completely correct; setting it low will cause data loss from the synchronization FIFO, leading to abnormal output of the switch signal. Synchronous FIFO reset control logic: When an optical communication error is detected, the reset position is set high; when the CRC-32 check fails, the reset position is set high.

[0050] The data read from the synchronous FIFO passes through a 3-to-2 decision module. Since each switch signal at the transmitting end is acquired through a 1-to-3 division, the receiving optical transceiver processes these three switch signals and outputs the results to the FPGA chip: when two or more of the three switch signals are high, a high level is output, indicating that the switch signal is valid; when two or more of the three switch signals are low, a low level is output, indicating that the switch signal is invalid. This 3-to-2 decision avoids single-point failures in the transmitting optical transceiver's switch signal acquisition that could lead to abnormal switch signal output from the receiving optical transceiver, thus improving system reliability. In other embodiments, other 1-to-3 optocouplers can also be used, and the decision module can be configured as needed to determine the number of high and low levels in the switch signals.

[0051] The switching signal output from the FPGA on the receiving optical transceiver is connected to the relay and then connected to the outside via a connector.

[0052] The transmitting optical transceiver uses two optical fibers to simultaneously transmit switch signal data to the receiving optical transceiver. The receiving optical transceiver monitors the optical path communication status of the two optical fibers in real time. When the optical path communication is abnormal, it automatically switches to the optical path with normal communication. The switching time is only 1 CLK (GTX user clock). During the switching process, the output of the switch signal remains unchanged.

[0053] In this embodiment, both the transmitting and receiving optical transceivers have two high-speed serial transceivers (GTX), GTX1 and GTX2, on their FPGA chips. GTX1 on the transmitting and receiving optical transceivers is connected via a backup optical fiber, while GTX2 is connected via a main optical fiber. In other embodiments, multiple optical fibers can be used to connect the transmitting and receiving ends, and correspondingly, each end has a corresponding number of high-speed serial transceivers.

[0054] A redundancy processing module is set on the FPGA chip of the receiving optical transceiver. When two optical fibers are connected at the same time, the fiber connected to GTX2 is the main fiber by default. The redundancy processing module monitors the bit error status of the two optical paths in real time. When a bit error occurs in one optical path, it automatically switches to the other normal optical path. If the abnormal optical path returns to normal at this time, no further switching will be performed.

[0055] In this invention, a high-speed serial transceiver IP core on an FPGA chip is used to perform frame structure encoding and decoding transmission of switch signals. A frame architecture with multiple frame type identifiers, including frame idle code, frame start code, frame end code, and frame CRC check, is designed to reduce the probability of data frames being misidentified. This ensures that the receiving optical transceiver recognizes a complete and unique data frame, thereby deframes and recovers the correct switch signal, improving the reliability of communication transmission.

[0056] During frame decoding, a two-level synchronous FIFO buffer is designed to perform ping-pong operation on the data stream. When there is an optical link error, at least one level of synchronous FIFO buffer data is guaranteed to be correct. This ensures that the switch signal output remains in the state before the error after the optical link error. When resolving optical link errors, the switch signal output remains at the level before the error to prevent malfunctions.

[0057] One-channel switch signal is acquired simultaneously using three optocouplers, achieving link isolation and communication fault tolerance for single-point faults in the switch signal, and avoiding acquisition errors caused by single-point faults at the transmitting end.

[0058] Using FPGA chips to precisely debouncing switch signals prevents glitch signals from being introduced into the switch signals input by the transmitting optical transceiver, which could lead to malfunctions in the output switch signals.

[0059] The receiving end uses a 3-out-of-2 decision mechanism to avoid output errors and malfunctions caused by communication failures of one switch signal.

[0060] This invention enables redundant fiber transmission, increases fiber redundancy processing, monitors the optical path communication status in real time, and can automatically switch fibers based on the optical path communication error status of the primary and backup fibers. During the switching process, the switch output is stable and controllable. When the fiber link communication is abnormal during operation, it can automatically switch to the fiber link with normal communication. When any optical link has an error, it can automatically switch to another optical link to complete the optical transmission of switch signals.

[0061] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A high-reliability switching redundant optical transmission system based on FPGA, comprising a transmitter and a receiver, characterized in that: Both the transmitting and receiving ends are equipped with FPGA chips and high-speed optical modules. The transmitting end also includes an optocoupler for isolating, converting, and splitting the input switch signals, and transmitting the processed switch signals to the FPGA chip. The FPGA chip on the transmitting end includes a debouncing module for real-time oversampling and debouncing of the switch signals, a frame encoding module for framing and encoding the debouncing switch signals, and a high-speed serial transceiver for parallel-to-serial conversion of the frame-encoded switch signals. The switch signals after parallel-to-serial conversion are converted into optical signals by the high-speed optical module on the transmitting end and transmitted through optical fiber to... The receiver and transmitter are connected via a main optical fiber and a backup optical fiber. The receiver uses its own high-speed optical module to perform photoelectric conversion on the received optical signal. The FPGA chip on the receiver is equipped with a high-speed serial transceiver that performs serial-to-parallel conversion on the photoelectric converted switch signal, a frame-deframe ping-pong recovery module that performs frame deframe recovery on the serial-to-parallel converted switch signal, a redundancy processing module that switches the optical path between the transmitter and receiver, and an adjudication module that judges and decides whether the switch signal is high or low. The receiver is also equipped with a relay for outputting the switch signal output by its own FPGA to the outside. Through the framing and encoding module, the switch signals are transmitted according to a fixed frame format. The data frames are of fixed length. Each data frame contains a frame header identifier, a data field start identifier, a data field end identifier, a frame tail identifier, an idle identifier, and a frame payload. When no data frames are being sent, an idle signal is sent to maintain the continuity of data transmission in the link. The frame-de-framing ping-pong recovery module sets up two-level synchronous FIFOs to store data and realize ping-pong operation: state 1 is to write data to the first-level synchronous FIFO and read data from the second-level synchronous FIFO at the same time. After writing is completed, it enters state 2; state 2 is to write data to the second-level synchronous FIFO and read data from the first-level synchronous FIFO. After writing is completed, it enters state 1. This cycle is repeated to realize frame-de-framing ping-pong recovery. Ping-pong operation includes controlling the read enable, write enable, and reset signals of the two-stage synchronous FIFO: Write enable control logic: When the previous frame's 4 frame tail identifiers, the current frame's 10 idle code identifiers, 4 frame header identifiers, and 1 data field start identifier are received consecutively, the data is considered stable, and the write enable is set high. When an optical path communication error is detected, the write enable is set low. After writing 80 CLKs, the write enable is set low. Read enable control logic: While writing enable is set high, CRC-32 check is performed on the written data. When 80 CLK data are written, it is determined whether the CRC-32 check passes. If it passes, it means that the written data is completely correct. At this time, read enable is set high. After the synchronous FIFO is emptied, read enable is set low. Synchronous FIFO reset control logic: When an optical communication error is detected, the reset position is set high; when the CRC-32 check fails, the reset position is set high.

2. The FPGA-based high-reliability switching redundant optical transmission system according to claim 1, characterized in that: The transmitter receives external switching signals via a connector. The received switching signals are isolated by an optocoupler and converted to LVTTL level for use by the main chip FPGA. Each input switching signal is simultaneously acquired via three optocouplers.

3. The FPGA-based high-reliability switching redundant optical transmission system according to claim 1, characterized in that: The debouncing module performs real-time oversampling of the input switch signal to the FPGA chip and debouncing the input switch signal. If the external switch signal does not change for more than 20ms, it is determined that the switch signal is stable; otherwise, it is considered that the switch signal is unstable and the previous switch signal state is maintained.

4. The FPGA-based high-reliability switching redundant optical transmission system according to claim 1, characterized in that: The 8'hBC in each identifier of the data frame is defined as the synchronization code K28.5 encoded in 8B / 10B, and the K code identifier is set. The data frame verification adopts cyclic redundancy check CRC-32, and the verification data range is 80 CLKs of the frame payload.

5. The FPGA-based high-reliability switching redundant optical transmission system according to claim 1, characterized in that: The high-speed serial transceiver is selected with a line rate of 1.25Gbps, encoding method of 8B / 10B, synchronization code of K28.5, bit width before encoding of 32 bits, and bit width after encoding of 40 bits. The user clock of the high-speed serial transceiver is 31.25MHz. Each data frame output by the framing and encoding module has a total frame length of 100 CLKs, of which 80 CLKs are valid data. The clock frequency occupied by the valid data is 25MHz. The local user clock of 31.25MHz is divided by 25MHz using a clock divider IP core. The 25MHz clock is used to oversample and debouncing the switch signal.

6. The FPGA-based high-reliability switching redundant optical transmission system according to claim 5, characterized in that: The framing and encoding module uses an asynchronous FIFO. The asynchronous FIFO write-side signal is: the write clock is 25MHz, the write enable is to write when the asynchronous FIFO is not full, and the write data is a 24-channel debouncing switch signal. The asynchronous FIFO read-side signal is: the read clock is 31.25MHz, the read enable is that the frame payload is not empty and the asynchronous FIFO is not empty, and the read data is put into the high-speed serial transceiver of the transmitter for parallel data transmission.

7. The FPGA-based high-reliability switching redundant optical transmission system according to claim 1, characterized in that: The FPGA chip at the receiving end obtains the communication status of the optical link in two ways: the IIC interface monitors the received optical power of the high-speed optical module in real time, and when the received optical power is less than the set threshold, it is considered that the optical path communication is abnormal; the error indication is obtained by using the DC balance signal and polarity signal after 8B / 10B encoding to determine the optical path communication abnormality.

8. The FPGA-based high-reliability switching redundant optical transmission system according to claim 1, characterized in that: The adjudication module adopts a 3-to-2 adjudication module, and the transmitter optocoupler adopts a 1-to-3 optocoupler. The adjudication module processes the 3 switching signals split from the optocoupler and outputs them to the FPGA chip: when 2 or more of the 3 switching signals are high level, the output is high level; when 2 or more of the 3 switching signals are low level, the output is low level.

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