Synchronization method and electronic system

Abstract

The present disclosure provides a synchronization method and an electronic system. The electronic system includes a first electronic module and a second electronic module. The first electronic module outputs a first time stamp according to a first clock signal, and the second electronic module outputs a second time stamp according to a second clock signal. The synchronization method includes: synchronizing the first clock signal and the second clock signal; notifying the first electronic module that the second clock signal has been synchronized by the second electronic module; resetting the first time stamp by the first electronic module and resetting the second time stamp by the second electronic module, so that the first time stamp and the second time stamp are the same; and outputting the first time stamp and the second time stamp. By resetting the time stamps of the electronic modules in the case of synchronizing the clock signals of the electronic modules, the electronic system ensures that the operations of the electronic modules according to the time stamps are synchronized, and has the advantages of arbitrary adjustment of the precision of the time stamps and low cost.

Description

Technical Field

[0001] This disclosure relates to a synchronization method, and more particularly to a synchronization method for multiple electronic modules in an electronic system. Background Technology

[0002] In existing system architectures with multiple electronic devices, even if these devices synchronize their clocks according to the Precision Time Protocol (PTP) defined by IEEE 1588, ensuring that the master and slave devices output 1PPS (1 pulse per second) signals of the same frequency and phase, problems still arise due to discrepancies in their timestamps. Taking a distributed video wall as an example, where the transmitting and receiving ends of the video (or audio) signals are located in different positions, the inconsistent timestamps of the multiple televisions during transmission cause synchronization issues, resulting in the distributed video wall displaying images that cannot be synchronized. Therefore, improvements to existing technologies are necessary. Summary of the Invention

[0003] This disclosure describes a synchronization method. The synchronization method is applicable to an electronic system, which includes a first electronic module and a second electronic module. The first electronic module outputs a first timestamp based on a first clock signal, and the second electronic module outputs a second timestamp based on a second clock signal. The synchronization method includes: synchronizing the first clock signal and the second clock signal; the second electronic module notifying the first electronic module that the second clock signal has been synchronized; resetting the first timestamp using the first electronic module and resetting the second timestamp using the second electronic module, so that the first timestamp and the second timestamp are identical; and outputting the first timestamp and the second timestamp.

[0004] In some embodiments, the synchronization method further includes: in response to the second electronic module notifying the first electronic module that the second clock signal has been synchronized, the first electronic module notifying the second electronic module to reset the second timestamp at a preset time, wherein the first electronic module also resets the first timestamp at the preset time.

[0005] In some embodiments, the steps of resetting the first timestamp with the first electronic module and resetting the second timestamp with the second electronic module include: resetting a first counting unit in the first electronic module and a second counting unit in the second electronic module; wherein the first counting unit and the second counting unit respectively output the first timestamp and the second timestamp.

[0006] In some embodiments, the synchronization method further includes: the first electronic module notifying the second electronic module to reset at a preset time; wherein the step of resetting the first timestamp with the first electronic module and resetting the second timestamp with the second electronic module includes: resetting a first counting unit in the first electronic module and a second counting unit in the second electronic module at the preset time, such that the first counting unit and the second counting unit respectively output the first timestamp and the second timestamp.

[0007] In some embodiments, the synchronization method further includes: the first electronic module outputting a first audio-visual signal based on the first timestamp, and the second electronic module outputting a second audio-visual signal based on the second timestamp.

[0008] Another embodiment of this disclosure is an electronic system. The electronic system includes a first electronic module and a second electronic module. The first electronic module outputs a first timestamp based on a first clock signal. The second electronic module is coupled to the first electronic module and outputs a second timestamp based on a second clock signal. When the first electronic module and the second electronic module are synchronized, the second electronic module notifies the first electronic module that the second clock signal synchronization is complete. After the second electronic module notifies the first electronic module that the second clock signal synchronization is complete, the first electronic module resets the first timestamp, and the second electronic module resets the second timestamp, so that the first timestamp and the second timestamp are identical and output synchronously.

[0009] In some embodiments, at a first time when the first electronic module and the second electronic module complete synchronization, the second electronic module sends a synchronization completion notification to the first electronic module via a network; at a second time after the first electronic module receives the synchronization completion notification, the first electronic module sends a count reset notification to the second electronic module via the network; at a preset time after the second time, the first electronic module resets the first timestamp to a pre-designed value, and the second electronic module resets the second timestamp to the pre-designed value according to the count reset notification.

[0010] In some embodiments, the first electronic module includes a first network unit, a first counting unit, a first clock synchronization unit, and a first control unit. The first network unit generates a first second pulse signal to generate the first clock signal. The first counting unit generates the first timestamp based on the first clock signal. The first clock synchronization unit is coupled between the first network unit and the first counting unit and generates the first clock signal based on the first second pulse signal, wherein the frequency of the first clock signal is higher than that of the first second pulse signal. The first control unit is coupled between the first network unit and the first counting unit and receives the synchronization completion notification and sends the count reset notification through the first network unit, and outputs a first delayed reset signal to the first counting unit at the preset time, wherein the first delayed reset signal resets the first timestamp to the preset value.

[0011] In some embodiments, the second electronic module includes a second network unit, a second counting unit, a second clock synchronization unit, and a second control unit. The second network unit generates a second second pulse signal to generate the second clock signal. The second counting unit generates the second timestamp based on the second clock signal. The second clock synchronization unit is coupled between the second network unit and the second counting unit and generates the second clock signal based on the second second pulse signal, wherein the frequency of the second clock signal is higher than that of the second second pulse signal. The second control unit is coupled between the second network unit and the second counting unit and sends the synchronization completion notification and receives the count reset notification through the second network unit, and outputs a second delayed reset signal to the second counting unit at the preset time, wherein the second delayed reset signal resets the second timestamp to the preset value.

[0012] In some embodiments, the first electronic module outputs a first audio-visual signal based on the first timestamp, and the second electronic module outputs a second audio-visual signal based on the second timestamp.

[0013] In summary, by resetting multiple timestamps of multiple electronic modules while synchronizing multiple clock signals across multiple electronic modules, the electronic system disclosed herein ensures that the operation of multiple electronic modules (e.g., displaying images) based on timestamps is synchronized. Furthermore, the electronic system disclosed herein offers advantages such as arbitrarily adjustable timestamp accuracy and low cost, thereby expanding its application range. Attached Figure Description

[0014] Figure 1A block diagram of an electronic system is illustrated according to some embodiments of the present disclosure.

[0015] Figure 2 The flowchart illustrates a synchronization method for an electronic module according to some embodiments of the present disclosure.

[0016] Figure 3 The flowchart illustrates a synchronization method for an electronic module according to some embodiments of the present disclosure.

[0017] Figure 4 A block diagram of an electronic system at a first moment is illustrated for some embodiments of the present disclosure.

[0018] Figure 5A A block diagram illustrating an electronic system at a second time according to some embodiments of the present disclosure.

[0019] Figure 5B A timing diagram illustrating a synchronized first clock signal and a second clock signal, and an unreset first timestamp and a second timestamp, is provided for some embodiments of this disclosure.

[0020] Figure 6A A block diagram illustrating an electronic system at a preset time according to some embodiments of the present disclosure.

[0021] Figure 6B A timing diagram illustrating a synchronized first clock signal and a second clock signal, and a reset first timestamp and a second timestamp, is provided for some embodiments of this disclosure.

[0022] Figure 7 A block diagram of an electronic system is illustrated according to some embodiments of the present disclosure.

[0023] Figure 8 This is a schematic diagram illustrating a distributed video wall according to some embodiments of the present disclosure.

[0024] Figure 9 This is a schematic diagram illustrating a distributed video wall according to some embodiments of the present disclosure.

[0025] Figure 10 This is a schematic diagram illustrating a distributed video wall according to some embodiments of the present disclosure.

[0026] The reference numerals in the attached figures are explained as follows:

[0027] 10: First Electronic Module

[0028] 11, 21: Network Units

[0029] 13, 23: Counting Units

[0030] 15, 25: Control Unit

[0031] 17, 27: Clock synchronization unit

[0032] 19, 29: Audio-visual signal processing unit

[0033] 20: Second Electronic Module

[0034] 100: Electronic Systems

[0035] 111, 211: Precision Time Protocol (PTP) processing unit

[0036] 200, 300: Synchronization Method

[0037] 800, 900, 1000: Distributed video walls

[0038] 801[1]~801[4], 901[1]~901[4], 1001[1]~1001[4]: Television

[0039] 902, 1002: Apparatus

[0040] CIV1: First initial count value

[0041] CIV2: Second initial count value

[0042] CLK1: First clock signal

[0043] CLK2: Second clock signal

[0044] CRP1: Count Reset Notification

[0045] DRE1: First Delay Reset Signal

[0046] DRE2: Second Delayed Reset Signal

[0047] NW: Network

[0048] PPS1: First second pulse signal

[0049] PPS2: Second second pulse signal

[0050] TS1: First-hand record

[0051] TS2: Second Timestamp

[0052] TSpd: Pre-design value

[0053] T1: First Time

[0054] T2: Second Time

[0055] Tpd: Preset time

[0056] SFP1: Synchronization Complete Notification

[0057] Si1: First audio / video signal

[0058] Si2: Second audio / video signal

[0059] Si[1]~Si[4]: Audio and video signals

[0060] S201, S301~S303: Steps Detailed Implementation

[0061] The following is a detailed description of the embodiments in conjunction with the accompanying drawings. However, the specific embodiments described are only for explaining this case and are not intended to limit this case. The description of the structural operations is not intended to limit the order of their execution. Any structure that is recombined with elements and produces a device with equivalent function is within the scope of this disclosure.

[0062] Unless otherwise specified, the terms used throughout the specification and claims generally have their ordinary meaning in the context of the art, the content disclosed herein, and the specific content.

[0063] The terms "coupled" or "connected" as used in this article can refer to two or more components making direct physical or electrical contact with each other, or making indirect physical or electrical contact with each other, or to two or more components operating or moving together.

[0064] Please see Figure 1 , Figure 1 This is a block diagram illustrating an electronic system 100 according to some embodiments of the present disclosure. In some embodiments, the electronic system 100 includes a first electronic module 10 and a second electronic module 20. The first electronic module 10 and the second electronic module 20 are configured to communicate with each other via a network NW (not limited to wired or wireless communication) to ensure that two timestamps generated by the first electronic module 10 and the second electronic module 20 are identical and output synchronously.

[0065] like Figure 1 As shown, the first electronic module 10 includes a network unit 11, a counting unit 13, a control unit 15, and a clock synchronization unit 17. The control unit 15 is coupled to the network unit 11 and the counting unit 13, and the clock synchronization unit 17 is coupled between the network unit 11 and the counting unit 13.

[0066] In some embodiments, the first electronic module 10 is used to synchronize its clock with other electronic modules (e.g., the second electronic module 20) according to a communication protocol. For example, the communication protocol is implemented using the Precision Time Protocol (PTP) defined by IEEE 1588. Based on the above, as... Figure 1 As shown, in some embodiments, network unit 11 includes a PTP processing unit 111. The PTP processing unit 111 in network unit 11 generates a first second pulse signal PPS1. Clock synchronization unit 17 generates a first clock signal CLK1 based on the first second pulse signal PPS1. Specifically, the first second pulse signal PPS1 has only one pulse per second, while the first clock signal CLK1 can have multiple pulses per second. In other words, in some embodiments, the frequency of the first clock signal CLK1 is higher than the frequency of the first second pulse signal PPS1. However, this disclosure is not limited to this. In other embodiments, the first clock signal CLK1 may also have only one pulse per second, that is, the frequency of the first clock signal CLK1 is equal to the frequency of the first second pulse signal PPS1. In other words, in other embodiments, clock synchronization unit 17 can be omitted from the first electronic module 10, and the first second pulse signal PPS1 can be directly used as the first clock signal CLK1 for the counting unit 13 to receive.

[0067] Furthermore, the counting unit 13 is used to generate a first timestamp TS1 based on the first clock signal CLK1 and a first initial count value CIV1. Specifically, as each pulse in the first clock signal CLK1 is triggered, the counting unit 13 performs calculations based on the first initial count value CIV1 to generate the first timestamp TS1. For example, assuming that the first clock signal CLK1 has 100 pulses per second and the first initial count value CIV1 is 100, the first timestamp TS1 will start from 100 and increment by 1 every 0.01 seconds.

[0068] In some embodiments, the second electronic module 20 has a structure similar to that of the first electronic module 10. For example... Figure 1 As shown, the second electronic module 20 includes a network unit 21, a counting unit 23, a control unit 25, and a clock synchronization unit 27. Specifically, the control unit 25 is coupled to the network unit 21 and the counting unit 23, and the clock synchronization unit 27 is coupled between the network unit 21 and the counting unit 23. The second electronic module 20 is used to synchronize its clock with other electronic modules (e.g., the first electronic module 10) according to the aforementioned communication protocol (i.e., PTP as defined by IEEE 1588).

[0069] Based on the above, such as Figure 1As shown, network unit 21 includes a PTP processing unit 211. The PTP processing unit 211 in network unit 21 generates a second second pulse signal PPS2. Clock synchronization unit 27 generates a second clock signal CLK2 based on the second second pulse signal PPS2. Specifically, the second second pulse signal PPS2 has only one pulse per second, while the second clock signal CLK2 can have multiple pulses per second. In other words, the frequency of the second clock signal CLK2 is higher than the frequency of the second second pulse signal PPS2. However, this disclosure is not limited to this. In other embodiments, the second clock signal CLK2 may also have only one pulse per second, that is, the frequency of the second clock signal CLK2 is equal to the frequency of the second second pulse signal PPS2. In other words, in other embodiments, clock synchronization unit 27 can be omitted from the second electronic module 20, and the second second pulse signal PPS2 can be directly used as the second clock signal CLK2 for the counting unit 23 to receive. Furthermore, the counting unit 23 generates a second timestamp TS2 based on the second clock signal CLK2 and a second initial count value CIV2. The operation of counting unit 23 is similar to that of counting unit 13, so it will not be described in detail here.

[0070] As can be seen from the above description of the first electronic module 10 and the second electronic module 20, the first electronic module 10 is used to output the first timestamp TS1 according to the first clock signal CLK1, and the second electronic module 20 is used to output the second timestamp TS2 according to the second clock signal CLK2.

[0071] In some embodiments, network unit 11 and network unit 21 are used to assign the first electronic module 10 and the second electronic module 20 as a master and a slave respectively according to the aforementioned PTP communication protocol, so as to synchronize the clocks of the first electronic module 10 and the second electronic module 20. Specifically, the second electronic module 20, as the slave, is used to exchange timestamps with the first electronic module 10, as the master, through the network NW to calculate a packet transmission delay time (e.g., 10 nanoseconds) and / or a time deviation (e.g., the time difference between the pulses of the first clock signal CLK1 and the second clock signal CLK2) between the master and the slave, and to adjust the second second pulse signal PPS2 according to the packet transmission delay time and / or the time deviation, so that the second second pulse signal PPS2 maintains the same frequency and phase as the first second pulse signal PPS1. In other embodiments, the above-mentioned master and slave assignments can also be assigned by the user during environmental settings.

[0072] As explained above, the first-second pulse signal PPS1 and the second-second pulse signal PPS2 are synchronized. Since they are synchronized, it can also be concluded that the first clock signal CLK1 and the second clock signal CLK2 are synchronized (i.e., they have the same frequency and phase). After the synchronization of the first clock signal CLK1 and the second clock signal CLK2 is completed, it can be ensured that the two timestamps generated by the first electronic module 10 and the second electronic module 20 are also output synchronously. Therefore, according to the above, the second electronic module 20 can be used to synchronize with the first electronic module 10 via the network NW.

[0073] In some embodiments, the two timestamps generated by the first electronic module 10 and the second electronic module 20 are output synchronously, but their timestamp numbers are different. For example, the first timestamp TS1 generated by the first electronic module 10 at a specific time is 101, but the second timestamp TS2 generated by the second electronic module 20 at the same specific time is 300. In some embodiments, the two timestamps generated by the first electronic module 10 and the second electronic module 20 are reset after the first clock signal CLK1 and the second clock signal CLK2 are synchronized, so that the two timestamps generated by the first electronic module 10 and the second electronic module 20 are output synchronously and have the same timestamp number. For example, the first timestamp TS1 generated by the first electronic module 10 and the second timestamp TS2 generated by the second electronic module 20 are both 101 at a specific time. Accordingly, this disclosure further provides a synchronization method 200 for electronic modules, as described below.

[0074] Please see Figure 2 , Figure 2 The flowchart illustrates a synchronization method 200 according to some embodiments of the present disclosure. In some embodiments, the synchronization method 200 includes step S201. The synchronization method 200 may be performed by, for example... Figure 1 The electronic system 100 shown is used to execute this, but is not limited thereto. In step S201, in response to the synchronization of the first clock signal CLK1 and the second clock signal CLK2, the first timestamp TS1 and the second timestamp TS2 are reset so that the first timestamp TS1 and the second timestamp TS2 are identical and output synchronously. However, Figure 2 The embodiments described are merely illustrative and are not intended to limit the scope of this disclosure. The following will use... Figure 3 The following is an example to further illustrate the point.

[0075] Please see Figure 3 , Figure 3The flowchart illustrates a synchronization method 300 according to some embodiments of the present disclosure. In some embodiments, the synchronization method 300 includes steps S301 to S303. The synchronization method 300 may be performed by, for example... Figure 1 The electronic system 100 shown is used to perform this function, but is not limited to it. For ease of explanation, the following will be accompanied by... Figure 4 , Figure 5A and Figure 6A Let's explain synchronization method 300.

[0076] In step S301, the second electronic module 20 notifies the first electronic module 10 that the second electronic module 20 has completed synchronization with the first electronic module 10. Please refer to [link / reference]. Figure 4 , Figure 4 This is a block diagram illustrating an electronic system 100 at a first time T1, according to some embodiments of this disclosure. In some embodiments, such as Figure 4 As shown, at the first time T1 when the first electronic module 10 and the second electronic module 20 complete synchronization, the control unit 25 of the second electronic module 20 sends a synchronization completion notification SFP1 to the first electronic module 10 via the network unit 21 and the network NW. Accordingly, the control unit 15 of the first electronic module 10 receives the synchronization completion notification SFP1 via the network unit 11 to know that the second electronic module 20 has completed synchronization with the first electronic module 10. In some embodiments, the second electronic module 20 notifies the first electronic module 10 that the second clock signal CLK2 has completed synchronization with the first clock signal CLK1.

[0077] In step S302, in response to the notification from the second electronic module 20, the first electronic module 10 notifies the second electronic module 20 to reset at a preset time Tpd. Please refer to [link to relevant documentation]. Figure 5A , Figure 5A This is a block diagram illustrating an electronic system 100 at a second time T2, according to some embodiments of this disclosure. In some embodiments, such as Figure 5A As shown, at a second time T2 after the first electronic module 10 receives the synchronization completion notification SFP1, the control unit 15 of the first electronic module 10 sends a count reset notification CRP1 to the second electronic module 20 via the network unit 11 and the network NW. Accordingly, the control unit 25 of the second electronic module 20 receives the count reset notification CRP1 via the network unit 21. The preset time disclosed in this application can be a specific point in time or a period of time.

[0078] Furthermore, at the first time T1 and the second time T2, the first clock signal CLK1 and the second clock signal CLK2 are synchronized; however, the first timestamp TS1 and the second timestamp TS2 may be different. For example, please refer to [link to example]. Figure 5B , Figure 5BTiming diagrams illustrating synchronized first clock signals CLK1 and CLK2, and unreset first timestamps TS1 and TS2, according to some embodiments of this disclosure. Figure 5B It can be seen that when the first clock signal CLK1 and the second clock signal CLK2 have the same frequency and phase due to synchronization, the four first timestamps TS1 corresponding to four pulses of the first clock signal CLK1 are 101, 102, 103, and 104, respectively. However, the four second timestamps TS2 corresponding to the same four pulses of the first clock signal CLK1 are 102, 103, 104, and 105, respectively. Therefore, the first timestamps TS1 and the second timestamps TS2 are output synchronously but are different, which means that although subsequent video and / or audio signals are output synchronously, they correspond to different timestamps.

[0079] In step S303, the first timestamp TS1 and the second timestamp TS2 are reset at a preset time Tpd to make the first timestamp TS1 and the second timestamp TS2 identical and output synchronously. Please refer to [link to relevant documentation]. Figure 6A , Figure 6A This is a block diagram illustrating an electronic system 100 at a preset time Tpd according to some embodiments of this disclosure. In some embodiments, such as Figure 6A As shown, at a preset time Tpd after the second time T2, the first electronic module 10 resets the first timestamp TS1 to a pre-designed value TSpd, and the second electronic module 20 resets the second timestamp TS2 to the pre-designed value TSpd according to the count reset notification CRP1.

[0080] In some embodiments, the first electronic module 10 resets the first timestamp TS1 by resetting the counting unit 13 at a preset time Tpd. For example... Figure 6A As shown, the control unit 15 of the first electronic module 10 outputs a first delay reset signal DRE1 to the counting unit 13 at a preset time Tpd. The counting unit 13 resets the first initial count value CIV1 according to the first delay reset signal DRE1, so that the first timestamp TS1 is reset to the pre-designed value TSpd. In other words, the first delay reset signal DRE1 is used to reset the first timestamp TS1 to the pre-designed value TSpd.

[0081] In some embodiments, the second electronic module 20 resets the second timestamp TS2 by resetting the counting unit 23 at a preset time Tpd. For example... Figure 6AAs shown, the control unit 25 of the second electronic module 20 outputs a second delay reset signal DRE2 to the counting unit 23 at a preset time Tpd. The counting unit 23 resets the second initial count value CIV2 according to the second delay reset signal DRE2, so that the second timestamp TS2 is reset to the pre-designed value TSpd. In other words, the second delay reset signal DRE2 is used to reset the second timestamp TS2 to the pre-designed value TSpd.

[0082] Accordingly, the first timestamp TS1 output by the first electronic module 10 is the same as the second timestamp TS2 output by the second electronic module 20 and is output synchronously. For details, please refer to... Figure 6B , Figure 6B Timing diagrams illustrating synchronized first clock signals CLK1 and CLK2, and reset first timestamps TS1 and TS2, according to some embodiments of this disclosure. Figure 6B It can be seen that when the first clock signal CLK1 and the second clock signal CLK2 have the same frequency and phase due to synchronization, the first timestamps TS1 corresponding to four pulses of the first clock signal CLK1 are 101, 102, 103, and 104, respectively, and the second timestamps TS2 corresponding to the same four pulses of the first clock signal CLK1 are also 101, 102, 103, and 104, respectively. Therefore, the first timestamps TS1 and the second timestamps TS2 are identical and output synchronously, which ensures that subsequent video and / or audio signals not only have synchronous output but also correspond to the same timestamps.

[0083] It is worth noting that in other embodiments, the control unit (e.g., Figure 1 The control units 15 and 25 in the control unit can also be coupled to the clock synchronization unit (e.g., Figure 1 The clock synchronization units 17 and 27 in the first electronic module 10 and the second electronic module 20 respectively enable the control unit 15 and the control unit 25 to change the frequency of the first clock signal CLK1 and the frequency of the second clock signal CLK2, thereby adjusting the timestamp accuracy of the first electronic module 10 and the second electronic module 20 respectively. For example, when the frequency of the first clock signal CLK1 is 100 Hz, the first electronic module 10 can output 100 first timestamps TS1 every second. When the frequency of the first clock signal CLK1 increases from 100 Hz to 1000 Hz, the first electronic module 10 can output 1000 first timestamps TS1 every second. In some practical applications of this disclosure, the timestamp accuracy of the first electronic module 10 and / or the second electronic module 20 can reach the nanosecond (ns) level.

[0084] In the foregoing embodiments, the second electronic module 20 can send a synchronization completion notification SFP1 to the first electronic module 10, and the first electronic module 10 can send a count reset notification CRP1 to the second electronic module 20. However, this disclosure is not limited thereto. In other embodiments, the first electronic module 10 is assigned as a slave, and the second electronic module 20 is assigned as a master. Accordingly, the first electronic module 10 can send a synchronization completion notification SFP1 to the second electronic module 20, and the second electronic module 20 can send a count reset notification CRP1 to the first electronic module 10. As can be seen from the above description, the electronic module acting as a slave in the electronic system 100 is used to send a synchronization completion notification SFP1 to the electronic module acting as a master in the electronic system 100, and the electronic module acting as a master in the electronic system 100 is used to send a count reset notification CRP1 to the electronic module acting as a slave in the electronic system 100.

[0085] In the foregoing embodiments, the first electronic module 10 and the second electronic module 20 can each be implemented as electronic circuits, chip modules, electronic devices, or electronic equipment. Further, in some embodiments, the first electronic module outputs a first audio-visual signal based on a first timestamp, and the second electronic module outputs a second audio-visual signal based on a second timestamp. Please refer to [link to relevant documentation]. Figure 7 The first timestamp TS1 and the second timestamp TS2 can be output to the audio-visual signal processing unit 19 and the audio-visual signal processing unit 29, respectively. The audio-visual signal processing unit 19 outputs a first audio-visual signal Si1 based on the first timestamp TS1, and the audio-visual signal processing unit 29 outputs a second audio-visual signal Si2 based on the second timestamp TS2. However, this is not the only limitation. In some embodiments, the image processing unit can be integrated with the counting unit, that is, the functions of the aforementioned image processing unit and counting unit can be implemented by a single chip.

[0086] In the foregoing embodiments, control unit 15 and control unit 25 can each be implemented by a central processing unit, a microprocessor (MPU), or other suitable components. Clock synchronization unit 17 and clock synchronization unit 27 can each be implemented by a component with frequency adjustment function. Furthermore, counting unit 13 and counting unit 23 can each be implemented by a programmable logic array (FPGA), a system-on-a-chip (SoC), or other components with counting function.

[0087] It should be understood that the number of electronic modules included in the electronic system disclosed herein is not limited to the number shown in the foregoing embodiments. In some embodiments, the number of electronic modules in the electronic system may be greater than two.

[0088] In some practical applications of this disclosure, the electronic systems described herein can be used in distributed video walls. Please refer to... Figure 8 , Figure 8 This is a schematic diagram illustrating a distributed video wall 800 according to some embodiments of the present disclosure. Figure 8 As shown, the distributed video wall 800 includes multiple televisions 801[1] to 801[4], and each of the multiple televisions 801[1] to 801[4] is equipped with the aforementioned electronic module. For example, television 801[1] is equipped with a first electronic module 10 (which can be regarded as the master end), while each of the multiple televisions 801[2] to 801[4] is equipped with a second electronic module 20 (which can be regarded as the slave end). After the aforementioned operation, the multiple timestamps inside the multiple televisions 801[1] to 801[4] of the distributed video wall 800 are the same and are output synchronously. Therefore, the image displayed by the distributed video wall 800 is complete, and there will be no problem of image discontinuity due to asynchronous timestamps.

[0089] The practical applications of the electronic systems disclosed herein are not limited to those described above; the following will be used in conjunction with... Figure 9 and Figure 10 To illustrate. Please refer to [link / reference]. Figure 9 , Figure 9 This is a schematic diagram illustrating a distributed video wall 900 according to some embodiments of the present disclosure. Figure 9 As shown, the distributed video wall 900 includes multiple televisions 901[1] to 901[4] and a device 902 (e.g., a signal extension device, signal switching device, TV box, set-top box, or other electronic device capable of signal processing) that works in coordination with the multiple televisions 901[1] to 901[4]. Each of the multiple televisions 901[1] to 901[4] and the device 902 is equipped with the aforementioned electronic module. For example, the device 902 is equipped with a first electronic module 10 (which can be regarded as the master end), while each of the multiple televisions 901[1] to 901[4] is equipped with a second electronic module 20 (which can be regarded as the slave end). After the aforementioned operation, the image displayed by the distributed video wall 900 is complete, and there will be no problem of image discontinuity due to timestamp asynchrony.

[0090] Please see Figure 10 , Figure 10 This is a schematic diagram illustrating a distributed video wall 1000 according to some embodiments of the present disclosure. Figure 10 As shown, the distributed video wall 1000 includes multiple televisions 1001[1] to 1001[4] and a device 1002 (e.g., an electronic device capable of signal processing, such as a signal extender, signal switch, television box, or set-top box) that operates in coordination with the multiple televisions 1001[1] to 1001[4]. Figure 10In this embodiment, the first electronic module 10 and multiple second electronic modules 20 can be configured as chip modules in the device 1002, wherein the first electronic module 10 can be regarded as the master end, and the other multiple second electronic modules 20 can be regarded as the slave end and can be electrically coupled to multiple televisions 1001[1]~1001[4]. After the aforementioned operation, the multiple timestamps of the first electronic module 10 and the multiple second electronic modules 20 are the same and output synchronously. In this way, when multiple televisions 1001[1]~1001[4] receive multiple audio and video signals Si[1]~Si[4] through multiple second electronic modules 20, the images displayed by multiple televisions 1001[1]~1001[4] can be displayed synchronously. However, this is not a limitation. In the case of multiple televisions, the first electronic module mentioned above can also be the master end coupled to one of the multiple televisions, and the other second electronic modules are respectively coupled to the slave ends of the other multiple televisions.

[0091] As can be seen from the embodiments described above, by resetting multiple timestamps of multiple electronic modules while synchronizing multiple clock signals of multiple electronic modules, the electronic system of this disclosure can ensure that the operation (e.g., displaying images) of multiple electronic modules according to the timestamps is synchronized. Furthermore, the electronic system of this disclosure also has the advantages of arbitrarily adjusting the accuracy of the timestamps and low cost, thereby expanding its application range.

[0092] Although the present disclosure has been described above with reference to embodiments, it is not intended to limit the present disclosure. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the appended claims.

Claims

1. A synchronization method, characterized in that, The synchronization method is applicable to an electronic system, wherein the electronic system includes a first electronic module and a second electronic module, the first electronic module being used to output a first timestamp according to a first clock signal, and the second electronic module being used to output a second timestamp according to a second clock signal, and the synchronization method includes: Synchronize the first clock signal with the second clock signal; The second electronic module notifies the first electronic module that the second clock signal has been synchronized. The first timestamp is reset using the first electronic module, and the second timestamp is reset using the second electronic module, so that the first timestamp and the second timestamp are identical; and Output the first timestamp and the second timestamp.

2. The synchronization method as described in claim 1, characterized in that, Including: In response to the second electronic module notifying the first electronic module that the second clock signal has been synchronized, the first electronic module notifies the second electronic module to reset the second timestamp at a preset time, wherein the first electronic module also resets the first timestamp at the preset time.

3. The synchronization method as described in claim 1, characterized in that, The steps of resetting the first timestamp with the first electronic module and resetting the second timestamp with the second electronic module include: Reset a first counting unit in the first electronic module and a second counting unit in the second electronic module; The first counting unit and the second counting unit respectively output the first timestamp and the second timestamp.

4. The synchronization method as described in claim 1, characterized in that, Including: The first electronic module notifies the second electronic module to reset at a preset time; The steps of resetting the first timestamp with the first electronic module and resetting the second timestamp with the second electronic module include: At the preset time, a first counting unit in the first electronic module and a second counting unit in the second electronic module are reset, so that the first counting unit and the second counting unit respectively output the first timestamp and the second timestamp.

5. The synchronization method as described in claim 1, characterized in that, Including: The first electronic module outputs a first audio-visual signal based on the first timestamp, and the second electronic module outputs a second audio-visual signal based on the second timestamp.

6. An electronic system, characterized in that, include: A first electronic module for outputting a first timestamp according to a first clock signal; as well as A second electronic module, coupled to the first electronic module, is used to output a second timestamp based on a second clock signal. When the first electronic module synchronizes with the second electronic module, the second electronic module notifies the first electronic module that the second clock signal synchronization is complete. After the second electronic module notifies the first electronic module that the second clock signal has been synchronized, the first electronic module resets the first timestamp, and the second electronic module resets the second timestamp, so that the first timestamp and the second timestamp are the same and output synchronously.

7. The electronic system as claimed in claim 6, characterized in that: At a first moment when the first electronic module and the second electronic module complete synchronously, the second electronic module sends a synchronization completion notification to the first electronic module via a network; At a second time after the first electronic module receives the synchronization completion notification, the first electronic module sends a count reset notification to the second electronic module through the network; At a preset time after the second time, the first electronic module resets the first timestamp to a pre-designed value, and the second electronic module resets the second timestamp to the pre-designed value according to the count reset notification.

8. The electronic system as claimed in claim 7, characterized in that, The first electronic module includes: A first network unit is used to generate a first second pulse signal to generate the first clock signal; A first counting unit is used to generate the first timestamp based on the first clock signal; A first clock synchronization unit, coupled between the first network unit and the first counting unit, is used to generate a first clock signal based on the first second pulse signal, wherein the frequency of the first clock signal is higher than that of the first second pulse signal; and A first control unit, coupled to the first network unit and the first counting unit, is used to receive the synchronization completion notification and send the count reset notification through the first network unit, and to output a first delayed reset signal to the first counting unit at the preset time, wherein the first delayed reset signal is used to reset the first timestamp to the preset value.

9. The electronic system as claimed in claim 7, characterized in that, The second electronic module includes: A second network unit is used to generate a second second pulse signal to generate the second clock signal; A second counting unit is used to generate the second timestamp based on the second clock signal; A second clock synchronization unit, coupled between the second network unit and the second counting unit, is used to generate a second clock signal based on the second second pulse signal, wherein the frequency of the second clock signal is higher than that of the second second pulse signal; and A second control unit, coupled to the second network unit and the second counting unit, is used to send the synchronization completion notification and receive the count reset notification through the second network unit, and to output a second delayed reset signal to the second counting unit at the preset time, wherein the second delayed reset signal is used to reset the second timestamp to the preset value.

10. The electronic system as claimed in claim 6, characterized in that, The first electronic module outputs a first audio-visual signal based on the first timestamp, and the second electronic module outputs a second audio-visual signal based on the second timestamp.

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