A low noise figure logarithmic detection video processing circuit

Abstract

This invention provides a low-noise-floor logarithmic detection video processing circuit, relating to the field of logarithmic detection video signal processing technology. The invention adds a diode clamping circuit to the logarithmic detection video processing circuit. After debiasing and slope transformation of the logarithmic detection video processing signal, the diode clamping circuit removes the noise floor, ensuring that the logarithmic detection video processing signal remains unchanged. This effectively reduces the noise floor of the logarithmic detection video processing signal without sacrificing its leading and trailing edges. Furthermore, a voltage follower circuit is connected after the diode clamping circuit to ensure the voltage following characteristics of the logarithmic detection video processing signal and improve the output current capability of the logarithmic detection video processing circuit, achieving effective processing of the logarithmic detection video processing signal and improving the signal-to-noise ratio of the logarithmic detection video processing signal without degrading its leading and trailing edges.

Description

Technical Field

[0001] This invention relates to the field of logarithmic detection video signal processing technology, and in particular to a low-noise logarithmic detection video processing circuit. Background Technology

[0002] The logarithmic detector video processing circuit mainly performs sorting of the logarithmic detector output signal, eliminates the output bias of the logarithmic detector, and transforms the negative slope output of the detector into a positive slope output.

[0003] Traditional detection video processing circuits mainly utilize operational amplifiers to perform bias cancellation and slope transformation on the signal. By combining operational amplifiers with capacitor circuits to form an active filter, the detection video signal can be filtered.

[0004] However, traditional detector video processing circuits cannot process narrow-width pulse signals. On the one hand, when the filtering effect is deep, the filtering effect on the background noise is more obvious, but it will prolong the leading and trailing edge times of the detector output, making narrow-width pulses indistinguishable and thus affecting the use. On the other hand, when the filtering effect is shallow, the distinguishing characteristics of narrow-width pulses can be guaranteed, but the filtering of signal background noise is not obvious.

[0005] Therefore, there is an urgent need for a solution to filter out the noise floor of narrow-width pulse signals. Summary of the Invention

[0006] This invention provides a low-noise logarithmic detection video processing circuit that can filter out the noise floor of narrow-width logarithmic detection video processing signals, effectively reducing the noise floor of the logarithmic detection video processing signals.

[0007] In a first aspect, the present invention provides a low-noise-floor logarithmic detection video processing circuit, comprising: a debiasing circuit, a slope transformation circuit, a diode clamping circuit, and a voltage follower circuit connected in sequence; the input terminal of the debiasing circuit receives a logarithmic detection video signal, and the output terminal of the debiasing circuit is connected to the input terminal of the slope transformation circuit; the debiasing circuit removes the bias signal of the logarithmic detection video signal and filters the logarithmic detection video signal to output a first output signal; the output terminal of the slope transformation circuit is connected to the input terminal of the diode clamping circuit; the slope transformation circuit transforms the slope of the first output signal and filters the first output signal to output a second output signal; the output terminal of the diode clamping circuit is connected to the input terminal of the voltage follower circuit; the diode clamping circuit filters out the noise floor voltage of the second output signal and outputs a third output signal; the output terminal of the voltage follower circuit is the output terminal of the low-noise-floor logarithmic detection video processing circuit; the voltage follower circuit maintains the voltage of the third output signal and outputs the processed logarithmic detection video signal.

[0008] In one possible implementation, the debiasing circuit includes a first amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor, as well as a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, and a fifth capacitor. The first terminal of the first resistor is the input terminal of the debiasing circuit. The output terminal of the first amplifier is the output terminal of the debiasing circuit. The second terminal of the first resistor, connected to the first terminal of the fifth resistor and the first terminal of the second capacitor, is then connected to the positive input terminal of the first amplifier. The second terminal of the fifth resistor and the second terminal of the second capacitor are connected to ground. The first terminal of the second resistor is connected to VCC1, and the second terminal of the second resistor is connected to the first terminal of the first capacitor. The first terminals of the third resistor and the fourth resistor are connected together. The second terminal of the first capacitor is connected to the second terminal of the third resistor and then grounded. The second terminal of the fourth resistor is connected to the negative input terminal of the first amplifier. The third capacitor is connected in parallel between the negative input terminal and the output terminal of the first amplifier. The sixth resistor is connected in parallel between the negative input terminal and the output terminal of the first amplifier. The positive input terminal of the power supply of the first amplifier is connected to VCC. The first terminal of the fourth capacitor is connected to the positive input terminal of the power supply of the first amplifier, and the second terminal of the fourth capacitor is grounded. The negative input terminal of the power supply of the first amplifier is connected to VEE. The first terminal of the fifth capacitor is connected to the negative input terminal of the power supply of the first amplifier, and the second terminal of the fifth capacitor is grounded.

[0009] In one possible implementation, the slope conversion circuit includes: a second amplifier, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, and a twelfth resistor, as well as a sixth capacitor, a seventh capacitor, an eighth capacitor, and a ninth capacitor; the first terminal of the seventh resistor is the input terminal of the slope conversion circuit, the output terminal of the second amplifier is the output terminal of the slope conversion circuit, and the second terminal of the seventh resistor is connected to the negative input terminal of the second amplifier; the first terminal of the eighth resistor is connected to VCC2, the second terminal of the eighth resistor is connected to the first terminal of the tenth resistor, and the second terminal of the tenth resistor is connected to the positive input terminal of the second amplifier; the first terminal of the ninth resistor is connected to the eighth resistor... The second terminal is connected, and the second terminal of the ninth resistor is grounded; the sixth capacitor is connected in parallel with the ninth resistor; the first terminal of the eleventh resistor is connected to the positive input terminal of the second amplifier, and the second terminal of the eleventh resistor is connected to the second terminal of the ninth resistor and then grounded; the seventh capacitor and the twelfth resistor are connected in parallel between the negative input terminal and the output terminal of the second amplifier; the positive input terminal of the power supply of the second amplifier is connected to VCC, the first terminal of the eighth capacitor is connected to the positive input terminal of the power supply of the second amplifier, and the second terminal of the eighth capacitor is grounded; the negative input terminal of the power supply of the second amplifier is connected to VEE, the first terminal of the ninth capacitor is connected to the negative input terminal of the power supply of the second amplifier, and the second terminal of the ninth capacitor is grounded.

[0010] In one possible implementation, the diode clamping circuit includes a first diode, a tenth capacitor, and a thirteenth resistor; the anode of the first diode is the input terminal of the diode clamping circuit, and the cathode of the first diode is connected to the first terminal of the tenth capacitor and the first terminal of the thirteenth resistor respectively to form the output terminal of the diode clamping circuit; the second terminal of the tenth capacitor and the second terminal of the thirteenth resistor are connected to ground.

[0011] In one possible implementation, the voltage follower circuit includes a third amplifier, a fourteenth resistor, a fifteenth resistor, an eleventh capacitor, a twelfth capacitor, a thirteenth capacitor, and a fourteenth capacitor; the first terminal of the fourteenth resistor is the input terminal of the voltage follower circuit, the output terminal of the third amplifier is the output terminal of the voltage follower circuit, and the second terminal of the fourteenth resistor is connected to the positive input terminal of the third amplifier; the first terminal of the eleventh capacitor is connected to the positive input terminal of the third amplifier, and the second terminal of the eleventh capacitor is grounded; the twelfth capacitor and the fifteenth resistor are connected in parallel between the negative input terminal and the output terminal of the third amplifier; the positive power input terminal of the third amplifier is connected to VCC, the first terminal of the thirteenth capacitor is connected to the positive power input terminal of the third amplifier, and the second terminal of the thirteenth capacitor is grounded; the negative power input terminal of the third amplifier is connected to VEE, the first terminal of the fourteenth capacitor is connected to the negative power input terminal of the third amplifier, and the second terminal of the fourteenth capacitor is grounded.

[0012] In one possible implementation, the capacitance values ​​of the fourth, fifth, eighth, ninth, thirteenth, and fourteenth capacitors are 0.1uF; and the capacitance values ​​of the first, second, third, sixth, seventh, tenth, eleventh, and twelfth capacitors are 0.5pF.

[0013] In one possible implementation, the voltage value of the first output signal can be calculated using the following formula;

[0014]

[0015] Wherein, OUT1 is the voltage value of the first output signal, IN is the voltage value of the logarithmic detection video signal, R2 is the second resistor, R3 is the third resistor, R4 is the fourth resistor, R6 is the sixth resistor, and VCC1 is the voltage value of the first DC source.

[0016] In one possible implementation, the voltage value of the second output signal can be calculated using the following formula;

[0017]

[0018] Wherein, OUT1 is the voltage value of the first output signal, OUT2 is the voltage value of the second output signal, R7 is the seventh resistor, R8 is the eighth resistor, R9 is the ninth resistor, R12 is the twelfth resistor, and VCC2 is the voltage value of the second DC source.

[0019] In one possible implementation, the voltage value of the third output signal can be calculated using the following formula;

[0020] OUT3 = OUT2 - VF;

[0021] Wherein, OUT3 is the voltage value of the third output signal, OUT2 is the voltage value of the second output signal, and VF is the threshold voltage of the first diode.

[0022] In one possible implementation, the voltage value of the processed logarithmic detection video signal can be calculated using the following formula;

[0023] OUT = OUT3;

[0024] Wherein, OUT3 is the voltage value of the third output signal, and OUT is the voltage value of the processed logarithmic detection video signal.

[0025] This invention provides a low-noise-floor logarithmic detection video processing circuit. The invention adds a diode clamping circuit to the logarithmic detection video processing circuit. After debiasing and slope transformation of the logarithmic detection video processing signal, the diode clamping circuit removes the noise floor, ensuring that the logarithmic detection video processing signal remains unchanged. This effectively reduces the noise floor of the logarithmic detection video processing signal without sacrificing its leading and trailing edges. Furthermore, a voltage follower circuit is connected after the diode clamping circuit to ensure the voltage following characteristics of the logarithmic detection video processing signal and improve the output current capability of the logarithmic detection video processing circuit, achieving effective processing of the logarithmic detection video processing signal and improving the signal-to-noise ratio of the logarithmic detection video processing signal without degrading its leading and trailing edges. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of a low-noise logarithmic detection video processing circuit provided in an embodiment of the present invention;

[0028] Figure 2This is a schematic diagram of another low-noise logarithmic detection video processing circuit provided in an embodiment of the present invention. Detailed Implementation

[0029] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of the invention. However, those skilled in the art will understand that the invention can be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods are omitted so as not to obscure the description of the invention with unnecessary detail.

[0030] In the description of this invention, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. The term "and / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. Furthermore, "at least one" and "more than one" refer to two or more. The terms "first," "second," etc., do not limit the quantity or order of execution, and "first," "second," etc., do not necessarily imply differences.

[0031] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner to facilitate understanding.

[0032] Furthermore, the terms "comprising" and "having," and any variations thereof, used in the description of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or modules is not limited to the steps or modules listed, but may optionally include other steps or modules not listed, or may optionally include other steps or modules inherent to such process, method, product, or device.

[0033] To make the objectives, technical solutions, and advantages of the present invention clearer, the following description will be provided in conjunction with the accompanying drawings and specific embodiments.

[0034] As described in the background section, existing detection video processing circuits are currently unable to effectively process narrow-width pulse signals.

[0035] To solve this technical problem, such as Figure 1As shown, this embodiment of the invention provides a low-noise logarithmic detection video processing circuit. This low-noise logarithmic detection video processing circuit includes: a debiasing circuit, a slope conversion circuit, a diode clamping circuit, and a voltage follower circuit connected in sequence.

[0036] In this embodiment, the input terminal of the debiasing circuit receives the logarithmic detection video signal, and the output terminal of the debiasing circuit is connected to the input terminal of the slope transformation circuit. The debiasing circuit removes the bias signal of the logarithmic detection video signal and filters the logarithmic detection video signal to output the first output signal.

[0037] In this embodiment, the output terminal of the slope conversion circuit is connected to the input terminal of the diode clamping circuit; the slope conversion circuit converts the slope of the first output signal and filters the first output signal to output the second output signal.

[0038] In this embodiment, the output terminal of the diode clamping circuit is connected to the input terminal of the voltage follower circuit; the diode clamping circuit filters out the noise floor voltage of the second output signal and outputs the third output signal.

[0039] In this embodiment, the output of the voltage follower circuit is the output of the low-noise logarithmic detection video processing circuit; the voltage follower circuit maintains the voltage of the third output signal and outputs the processed logarithmic detection video signal.

[0040] This invention provides a low-noise-floor logarithmic detection video processing circuit. A diode clamping circuit is added to the logarithmic detection video processing circuit. After debiasing and slope transformation of the logarithmic detection video processing signal, the diode clamping circuit removes the noise floor, ensuring that the logarithmic detection video processing signal remains unchanged. This effectively reduces the noise floor of the logarithmic detection video processing signal without sacrificing its leading and trailing edges. Furthermore, a voltage follower circuit is connected after the diode clamping circuit to ensure the voltage following characteristics of the logarithmic detection video processing signal and improve the output current capability of the logarithmic detection video processing circuit. This achieves effective processing of the logarithmic detection video processing signal, improving the signal-to-noise ratio of the logarithmic detection video processing signal without degrading its leading and trailing edges.

[0041] Optional, such as Figure 2 As shown, the debiasing circuit includes a first amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor, as well as a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, and a fifth capacitor.

[0042] In this circuit, the first terminal of the first resistor is the input terminal of the debiasing circuit; the output terminal of the first amplifier is the output terminal of the debiasing circuit; the second terminal of the first resistor is connected to the first terminal of the fifth resistor and the first terminal of the second capacitor, and then connected to the positive input terminal of the first amplifier; the second terminal of the fifth resistor is connected to the second terminal of the second capacitor and then grounded; the first terminal of the second resistor is connected to VCC1; the second terminal of the second resistor is connected to the first terminal of the first capacitor, the first terminal of the third resistor, and the first terminal of the fourth resistor; the second terminal of the first capacitor is connected to the second terminal of the third resistor and then grounded; the second terminal of the fourth resistor is connected to the negative input terminal of the first amplifier; the third capacitor is connected in parallel between the negative input terminal and the output terminal of the first amplifier; the sixth resistor is connected in parallel between the negative input terminal and the output terminal of the first amplifier; the positive input terminal of the power supply of the first amplifier is connected to VCC; the first terminal of the fourth capacitor is connected to the positive input terminal of the power supply of the first amplifier, and the second terminal of the fourth capacitor is grounded; the negative input terminal of the power supply of the first amplifier is connected to VEE; the first terminal of the fifth capacitor is connected to the negative input terminal of the power supply of the first amplifier, and the second terminal of the fifth capacitor is grounded.

[0043] Optional, such as Figure 2 As shown, the slope conversion circuit includes: a second amplifier, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, and a twelfth resistor, as well as a sixth capacitor, a seventh capacitor, an eighth capacitor, and a ninth capacitor.

[0044] In this circuit, the first terminal of the seventh resistor is the input terminal of the slope conversion circuit, and the output terminal of the second amplifier is also the output terminal of the slope conversion circuit. The second terminal of the seventh resistor is connected to the negative input terminal of the second amplifier. The first terminal of the eighth resistor is connected to VCC2, the second terminal of the eighth resistor is connected to the first terminal of the tenth resistor, and the second terminal of the tenth resistor is connected to the positive input terminal of the second amplifier. The first terminal of the ninth resistor is connected to the second terminal of the eighth resistor, and the second terminal of the ninth resistor is grounded. The sixth capacitor is connected in parallel with the ninth resistor. The first terminal of the eleventh resistor is connected to the positive input terminal of the second amplifier, and the second terminal of the eleventh resistor is connected to the second terminal of the ninth resistor and then grounded. The seventh capacitor and the twelfth resistor are connected in parallel between the negative input terminal and the output terminal of the second amplifier. The positive input terminal of the power supply of the second amplifier is connected to VCC, the first terminal of the eighth capacitor is connected to the positive input terminal of the power supply of the second amplifier, and the second terminal of the eighth capacitor is grounded. The negative input terminal of the power supply of the second amplifier is connected to VEE, the first terminal of the ninth capacitor is connected to the negative input terminal of the power supply of the second amplifier, and the second terminal of the ninth capacitor is grounded.

[0045] Optional, such as Figure 2 As shown, the diode clamping circuit includes a first diode, a tenth capacitor, and a thirteenth resistor.

[0046] In this circuit, the anode of the first diode is the input terminal of the diode clamping circuit, and the cathode of the first diode is connected to the first terminal of the tenth capacitor and the first terminal of the thirteenth resistor to form the output terminal of the diode clamping circuit. The second terminal of the tenth capacitor and the second terminal of the thirteenth resistor are connected to ground.

[0047] Optional, such as Figure 2 As shown, the voltage follower circuit includes a third amplifier, a fourteenth resistor, a fifteenth resistor, an eleventh capacitor, a twelfth capacitor, a thirteenth capacitor, and a fourteenth capacitor.

[0048] In this circuit, the first terminal of the fourteenth resistor is the input terminal of the voltage follower circuit, and the output terminal of the third amplifier is the output terminal of the voltage follower circuit. The second terminal of the fourteenth resistor is connected to the positive input terminal of the third amplifier. The first terminal of the eleventh capacitor is connected to the positive input terminal of the third amplifier, and the second terminal of the eleventh capacitor is grounded. The twelfth capacitor and the fifteenth resistor are connected in parallel between the negative input terminal and the output terminal of the third amplifier. The positive power input terminal of the third amplifier is connected to VCC. The first terminal of the thirteenth capacitor is connected to the positive power input terminal of the third amplifier, and the second terminal of the thirteenth capacitor is grounded. The negative power input terminal of the third amplifier is connected to VEE. The first terminal of the fourteenth capacitor is connected to the negative power input terminal of the third amplifier, and the second terminal of the fourteenth capacitor is grounded.

[0049] For example, the capacitance values ​​of the fourth, fifth, eighth, ninth, thirteenth, and fourteenth capacitors are 0.1uF;

[0050] For example, the capacitance values ​​of the first capacitor, second capacitor, third capacitor, sixth capacitor, seventh capacitor, tenth capacitor, eleventh capacitor and twelfth capacitor are 0.5pF.

[0051] As one possible implementation, such as Figure 2 As shown, the voltage value of the first output signal can be calculated using the following formula.

[0052]

[0053] Wherein, OUT1 is the voltage value of the first output signal, IN is the voltage value of the logarithmic detection video signal, R2 is the second resistor, R3 is the third resistor, R4 is the fourth resistor, R6 is the sixth resistor, and VCC1 is the voltage value of the first DC source.

[0054] It should be noted that the second and third resistors in the debiasing circuit are voltage divider resistors, the first and fourth resistors have the same resistance value, and the fifth and sixth resistors have the same resistance value.

[0055] As one possible implementation, such as Figure 2As shown, the voltage value of the second output signal can be calculated using the following formula.

[0056]

[0057] Wherein, OUT1 is the voltage value of the first output signal, OUT2 is the voltage value of the second output signal, R7 is the seventh resistor, R8 is the eighth resistor, R9 is the ninth resistor, R12 is the twelfth resistor, and VCC2 is the voltage value of the second DC source.

[0058] It should be noted that in the slope transformation circuit, the eighth and ninth resistors are voltage divider resistors, the first and tenth resistors have the same resistance value, and the eleventh and twelfth resistors have the same resistance value.

[0059] As one possible implementation, such as Figure 2 As shown, the voltage value of the third output signal can be calculated using the following formula.

[0060] OUT3 = OUT2 - VF;

[0061] Wherein, OUT3 is the voltage value of the third output signal, OUT2 is the voltage value of the second output signal, and VF is the threshold voltage of the first diode.

[0062] It should be noted that the first diode can be a 1N4148. In this embodiment of the invention, the threshold voltage of the first diode is used to filter out the noise floor of the logarithmic detection video processing signal, effectively reducing the noise floor of the logarithmic detection video processing signal. This embodiment of the invention can also use the threshold voltage to select a diode that is more suitable for the logarithmic detection video processing signal.

[0063] As one possible implementation, such as Figure 2 As shown, the voltage value of the processed logarithmic detection video signal can be calculated using the following formula.

[0064] OUT = OUT3;

[0065] Wherein, OUT3 is the voltage value of the third output signal, and OUT is the voltage value of the processed logarithmic detection video signal.

[0066] It should be noted that the fourteenth and fifteenth resistors have the same resistance value. The thirteenth resistor has a resistance value greater than 2 kΩ. The fourth, fifth, eighth, ninth, thirteenth, and fourteenth capacitors are filter capacitors with a capacitance value of 0.1uF. The first, second, third, sixth, seventh, tenth, eleventh, and twelfth capacitors have a capacitance value of 0.5pF.

[0067] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A low-noise logarithmic detector video processing circuit, characterized in that, include: The debiasing circuit, slope conversion circuit, diode clamping circuit, and voltage follower circuit are connected in sequence. The input terminal of the debiasing circuit receives the logarithmic detection video signal, and the output terminal of the debiasing circuit is connected to the input terminal of the slope transformation circuit; the debiasing circuit removes the bias signal of the logarithmic detection video signal, filters the logarithmic detection video signal, and outputs a first output signal. The output terminal of the slope transformation circuit is connected to the input terminal of the diode clamping circuit; the slope transformation circuit transforms the slope of the first output signal and filters the first output signal to output a second output signal. The output terminal of the diode clamping circuit is connected to the input terminal of the voltage follower circuit; the diode clamping circuit filters out the noise floor voltage of the second output signal and outputs the third output signal. The output terminal of the voltage follower circuit is the output terminal of the low-noise logarithmic detection video processing circuit; the voltage follower circuit maintains the voltage of the third output signal and outputs the processed logarithmic detection video signal.

2. The low-noise logarithmic detector video processing circuit according to claim 1, characterized in that, The debiasing circuit includes a first amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, and a sixth resistor, as well as a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, and a fifth capacitor. The first terminal of the first resistor is the input terminal of the debiasing circuit; the output terminal of the first amplifier is the output terminal of the debiasing circuit. After the second end of the first resistor is connected to the first end of the fifth resistor and the first end of the second capacitor, it is connected to the positive input terminal of the first amplifier. The second terminal of the fifth resistor is connected to the second terminal of the second capacitor and then grounded. The first end of the second resistor is connected to VCC1, and the second end of the second resistor is connected to the first end of the first capacitor, the first end of the third resistor, and the first end of the fourth resistor. The second end of the first capacitor is connected to the second end of the third resistor and then grounded. The second end of the fourth resistor is connected to the negative input terminal of the first amplifier. The third capacitor is connected in parallel between the negative input terminal and the output terminal of the first amplifier; The sixth resistor is connected in parallel between the negative input terminal and the output terminal of the first amplifier; The positive power input terminal of the first amplifier is connected to VCC, the first terminal of the fourth capacitor is connected to the positive power input terminal of the first amplifier, and the second terminal of the fourth capacitor is grounded. The negative power input terminal of the first amplifier is connected to VEE, the first terminal of the fifth capacitor is connected to the negative power input terminal of the first amplifier, and the second terminal of the fifth capacitor is grounded.

3. The low-noise logarithmic detector video processing circuit according to claim 1, characterized in that, The slope conversion circuit includes: a second amplifier, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, and a twelfth resistor, as well as a sixth capacitor, a seventh capacitor, an eighth capacitor, and a ninth capacitor; The first end of the seventh resistor is the input terminal of the slope conversion circuit, the output terminal of the second amplifier is the output terminal of the slope conversion circuit, and the second end of the seventh resistor is connected to the negative input terminal of the second amplifier. The first end of the eighth resistor is connected to VCC2, the second end of the eighth resistor is connected to the first end of the tenth resistor, and the second end of the tenth resistor is connected to the positive input terminal of the second amplifier. The first end of the ninth resistor is connected to the second end of the eighth resistor, and the second end of the ninth resistor is grounded; The sixth capacitor is connected in parallel with the ninth resistor; The first end of the eleventh resistor is connected to the positive input terminal of the second amplifier, and the second end of the eleventh resistor is connected to the second end of the ninth resistor and then grounded. The seventh capacitor and the twelfth resistor are connected in parallel between the negative input terminal and the output terminal of the second amplifier. The positive power input terminal of the second amplifier is connected to VCC, the first terminal of the eighth capacitor is connected to the positive power input terminal of the second amplifier, and the second terminal of the eighth capacitor is grounded. The negative power input terminal of the second amplifier is connected to VEE, the first terminal of the ninth capacitor is connected to the negative power input terminal of the second amplifier, and the second terminal of the ninth capacitor is grounded.

4. The low-noise logarithmic detector video processing circuit according to claim 1, characterized in that, The diode clamping circuit includes a first diode, a tenth capacitor, and a thirteenth resistor; The anode of the first diode is the input terminal of the diode clamping circuit, and the cathode of the first diode is connected to the first terminal of the tenth capacitor and the first terminal of the thirteenth resistor respectively to form the output terminal of the diode clamping circuit. The second terminal of the tenth capacitor and the second terminal of the thirteenth resistor are connected to ground.

5. The low-noise logarithmic detector video processing circuit according to claim 1, characterized in that, The voltage follower circuit includes a third amplifier, a fourteenth resistor, a fifteenth resistor, an eleventh capacitor, a twelfth capacitor, a thirteenth capacitor, and a fourteenth capacitor; The first end of the fourteenth resistor is the input terminal of the voltage follower circuit, the output terminal of the third amplifier is the output terminal of the voltage follower circuit, and the second end of the fourteenth resistor is connected to the positive input terminal of the third amplifier. The first terminal of the eleventh capacitor is connected to the positive input terminal of the third amplifier, and the second terminal of the eleventh capacitor is grounded. The twelfth capacitor and the fifteenth resistor are connected in parallel between the negative input terminal and the output terminal of the third amplifier. The positive power input terminal of the third amplifier is connected to VCC, the first terminal of the thirteenth capacitor is connected to the positive power input terminal of the third amplifier, and the second terminal of the thirteenth capacitor is grounded. The negative power input terminal of the third amplifier is connected to VEE, the first terminal of the fourteenth capacitor is connected to the negative power input terminal of the third amplifier, and the second terminal of the fourteenth capacitor is grounded.

6. The low-noise logarithmic detector video processing circuit according to claim 1, characterized in that, The capacitance values ​​of the fourth, fifth, eighth, ninth, thirteenth, and fourteenth capacitors are 0.1uF; The capacitance values ​​of the first, second, third, sixth, seventh, tenth, eleventh, and twelfth capacitors are all 0.5pF.

7. The low-noise-floor logarithmic detection video processing circuit according to any one of claims 1 to 6, characterized in that, The voltage value of the first output signal can be calculated using the following formula; OUT1= ; Where OUT1 is the voltage value of the first output signal. The voltage value of the logarithmic detection video signal. For the second resistor, The third resistor, The fourth resistor, The sixth resistor, This is the voltage value of the first DC source.

8. The low-noise logarithmic detection video processing circuit according to any one of claims 1 to 6, characterized in that, The voltage value of the second output signal can be calculated using the following formula; OUT2= ; Wherein, OUT1 is the voltage value of the first output signal, and OUT2 is the voltage value of the second output signal. The seventh resistor, This is the eighth resistor. The ninth resistor, The twelfth resistor, This is the voltage value of the second DC source.

9. The low-noise-floor logarithmic detection video processing circuit according to any one of claims 1 to 6, characterized in that, The voltage value of the third output signal can be calculated using the following formula; OUT3= ; Wherein, OUT3 is the voltage value of the third output signal, and OUT2 is the voltage value of the second output signal. This is the threshold voltage of the first diode.

10. The low-noise-floor logarithmic detection video processing circuit according to any one of claims 1 to 6, characterized in that, The voltage value of the processed logarithmic detection video signal can be calculated using the following formula; OUT= ; Wherein, OUT3 is the voltage value of the third output signal, and OUT is the voltage value of the processed logarithmic detection video signal.

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