Method for forming semiconductor structure and semiconductor structure, method for forming memory

Abstract

Embodiments of the present disclosure provide a semiconductor structure forming method, a semiconductor structure and a memory forming method. The semiconductor structure forming method comprises: providing a base comprising a substrate and a first contact structure and a second contact structure in the substrate, the substrate comprising an array region and a peripheral region, the first contact structure being located in the array region, and the second contact structure being located in the peripheral region; sequentially forming, on a surface of the substrate, a barrier layer covering the peripheral region, a stack structure covering the barrier layer and the array region, the stack structure comprising a plurality of sacrificial layers and support layers alternately stacked in a direction perpendicular to the surface of the substrate; forming a capacitor hole penetrating through the stack structure and exposing the first contact structure, and a first electrode layer covering an inner wall of the capacitor hole; sequentially forming, from a top layer of the stack structure, an opening in each support layer, and removing the sacrificial layer covered by the support layer through the opening in each support layer; and sequentially forming a dielectric layer covering a surface of the first electrode layer, and a second electrode layer covering the dielectric layer.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of semiconductor technology, and in particular to a method for forming a semiconductor structure and a method for forming a semiconductor structure and a memory. Background Technology

[0002] For semiconductor structures containing capacitors, these capacitors are typically clustered in the array region of the semiconductor structure, while a large number of logic circuits exist in the peripheral region of the semiconductor structure to work in conjunction with the capacitors. For example, a Dynamic Random Access Memory (DRAM) cell includes a capacitor structure for storing charge and transistors for accessing the charge in the capacitor structure; the capacitor structure is clustered in the array region, and correspondingly, a large number of logic circuits exist in the peripheral region to control the capacitor structure to access the charge. However, in the semiconductor structure forming process of related technologies, the contact structure in the logic circuits in the peripheral region may be damaged, leading to logic circuit failure. Summary of the Invention

[0003] In view of this, the present disclosure provides a method for forming a semiconductor structure and a method for forming a semiconductor structure and a memory.

[0004] This disclosure provides a method for forming a semiconductor structure, the method comprising:

[0005] A substrate is provided, the substrate including a substrate, at least one first contact structure and at least one second contact structure located within the substrate, the substrate including an array region and a peripheral region, the first contact structure being located in the array region and the second contact structure being located in the peripheral region;

[0006] A barrier layer covering the peripheral region and a stacked structure covering the barrier layer and the array region are sequentially formed on the surface of the substrate. The stacked structure includes a plurality of sacrificial layers and support layers that are alternately stacked along a direction perpendicular to the surface of the substrate.

[0007] A capacitor hole is formed that penetrates the stacked structure and exposes the first contact structure, and a first electrode layer covers the inner wall of the capacitor hole;

[0008] An opening is formed sequentially in each support layer from the top layer of the stacked structure downwards, and the sacrificial layer covered by the support layer is removed through the opening in each support layer;

[0009] A dielectric layer covering the surface of the first electrode layer and a second electrode layer covering the dielectric layer are formed sequentially.

[0010] In some embodiments, the step of sequentially forming a barrier layer covering the peripheral region and a stacked structure covering the barrier layer and the array region on the substrate surface includes: depositing a pre-barrier layer on the substrate surface; etching a portion of the pre-barrier layer covering the array region to form a barrier layer covering the peripheral region; and depositing a sacrificial layer and a support layer alternately stacked in a direction perpendicular to the substrate surface on the surface of the barrier layer and on a portion of the substrate surface corresponding to the array region.

[0011] In some embodiments, the support layer is formed of a first material, the barrier layer is formed of a second material, and the etching selectivity ratio between the first material and the second material is greater than a first threshold.

[0012] In some embodiments, the barrier layer includes a first barrier layer and a second barrier layer covering the first barrier layer.

[0013] In some embodiments, forming a capacitor hole that penetrates the stacked structure and exposes the first contact structure, and a first electrode layer covering the inner wall of the capacitor hole, includes: forming a first mask layer over the stacked structure; patterning the first mask layer; etching the stacked structure to form a capacitor hole that penetrates the stacked structure and exposes the first contact structure; and depositing a first conductive material on the inner wall of the capacitor hole to form a first electrode layer.

[0014] In some embodiments, the substrate includes a base support layer covering each of the first contact structures and each of the second contact structures; the etching of the stacked structure to form a capacitor via penetrating the stacked structure and exposing the first contact structures includes: etching the stacked structure to form a via penetrating the stacked structure and exposing the base support layer; etching the base support layer exposed in the via to form a capacitor via exposing the first contact structures; and removing polymer adhering to the inner wall of the via during the formation of the via.

[0015] In some embodiments, the polymer includes a first polymer and a second polymer attached to the surface of the first polymer; the removal of the polymer attached to the inner wall of the through hole during the formation of the through hole includes: after the formation of the through hole, cleaning the through hole with a cleaning gas to remove the second polymer; and during the etching of the base support layer, using ions generated during etching to bombard and remove the first polymer.

[0016] In some embodiments, the cleaning gas includes at least one of the following: oxygen, argon, and chlorine.

[0017] In some embodiments, the method further includes: sequentially removing the second electrode layer, the dielectric layer, and the barrier layer located above the peripheral region, and exposing the second contact structure.

[0018] This disclosure provides a semiconductor structure, including: a substrate, a plurality of first contact structures, a plurality of second contact structures, a barrier layer, and a plurality of memory structures;

[0019] The substrate includes an array region and a peripheral region, the first contact structure is located in the array region, and the second contact structure is located in the peripheral region;

[0020] The storage structure is located above the first contact structure and is electrically connected to the first contact structure in a one-to-one correspondence.

[0021] The barrier layer is located above the peripheral area.

[0022] In some embodiments, the barrier layer includes a first barrier layer and a second barrier layer stacked sequentially, wherein the first barrier layer and the second barrier layer are made of different materials.

[0023] In some embodiments, the ratio of the thickness of the first barrier layer to the thickness of the second barrier layer is greater than or equal to 2 and less than or equal to 4.

[0024] In some embodiments, an insulating layer is further disposed between the barrier layer and the second contact structure, wherein the etching selectivity ratio between the materials of the insulating layer and the barrier layer is greater than a second threshold.

[0025] In some embodiments, the storage structure includes a first electrode layer, a dielectric layer, and a second electrode layer, wherein the dielectric layer covers the surface of the barrier layer.

[0026] This disclosure provides a method for forming a memory, the method comprising:

[0027] A substrate is provided, the substrate including an array region and a peripheral region, the array region including a plurality of transistors, a plurality of word lines, a plurality of bit lines and a plurality of first contact structures arranged in an array, the peripheral region including peripheral devices and a plurality of second contact structures; wherein each word line extends along a first direction and is connected to the gate of a column of transistors arranged along the first direction, each bit line extends along a second direction and is electrically connected to one of the source or drain of a row of transistors arranged along the second direction, the first direction intersects the second direction, and the first contact structure is electrically connected to the other of the source or drain of the transistor;

[0028] Based on the substrate, using the above-described semiconductor structure formation method, a capacitor structure electrically connected to the first contact structure is formed on the substrate.

[0029] In this embodiment, a substrate is provided, comprising a substrate, at least one first contact structure and at least one second contact structure located within the substrate. The substrate includes an array region and a peripheral region, with the first contact structure located in the array region and the second contact structure located in the peripheral region. A barrier layer covering the peripheral region and a stacked structure covering the barrier layer and the array region are sequentially formed on the substrate surface. The stacked structure includes a plurality of sacrificial layers and support layers alternately stacked in a direction perpendicular to the substrate surface. A capacitor aperture penetrating the stacked structure and exposing the first contact structure is formed, along with a first electrode layer covering the inner wall of the capacitor aperture. An opening is sequentially formed in each support layer from the top layer of the stacked structure downwards, and the sacrificial layer covered by the support layer is removed through the opening in each support layer. A dielectric layer covering the surface of the first electrode layer and a second electrode layer covering the dielectric layer are sequentially formed. Thus, since a barrier layer covering the peripheral region is formed on the substrate surface before the stacked structure is formed, this barrier layer can protect the portion of the substrate corresponding to the peripheral region during the formation of the first electrode layer, dielectric layer, and second electrode layer, thereby reducing damage to the second contact structure located in the peripheral region, and further reducing damage to the logic circuits in the peripheral region, improving the yield of semiconductor products. Attached Figure Description

[0030] Figure 1A A schematic diagram illustrating the implementation process of a method for forming a semiconductor structure according to an embodiment of this disclosure;

[0031] Figure 1B A schematic diagram of the composition structure of a substrate provided in an embodiment of this disclosure;

[0032] Figure 1C This is a schematic diagram illustrating the formation of a barrier layer and a stacked structure in a method for forming a semiconductor structure according to an embodiment of the present disclosure;

[0033] Figure 1D This is a schematic diagram illustrating the formation of a capacitor hole in a method for forming a semiconductor structure according to an embodiment of this disclosure;

[0034] Figure 1E This is a schematic diagram of the formation of a first electrode layer in a method for forming a semiconductor structure according to an embodiment of the present disclosure;

[0035] Figure 1F This is a schematic diagram of the composition structure after removing the sacrificial layer in a method for forming a semiconductor structure according to an embodiment of the present disclosure;

[0036] Figure 1G This is a schematic diagram illustrating the formation of an opening in a target support layer in a method for forming a semiconductor structure according to an embodiment of this disclosure.

[0037] Figure 1HA schematic diagram of an opening layout provided in an embodiment of this disclosure;

[0038] Figure 1I This is a schematic diagram of the composition of a semiconductor structure formed in a method for forming a semiconductor structure according to an embodiment of the present disclosure;

[0039] Figure 1J This is a schematic diagram of the formation of a second mask layer in a method for forming a semiconductor structure according to an embodiment of the present disclosure;

[0040] Figure 1K This is a schematic diagram of the composition of a semiconductor structure formed in a method for forming a semiconductor structure according to an embodiment of the present disclosure;

[0041] Figure 2A This is a schematic diagram of the formation of a barrier layer in a method for forming a semiconductor structure according to an embodiment of the present disclosure;

[0042] Figure 2B This is a schematic diagram of the barrier layer formed in a method for forming a semiconductor structure according to an embodiment of the present disclosure;

[0043] Figure 2C This is a schematic diagram of the composition of the barrier layer in a method for forming a semiconductor structure according to an embodiment of the present disclosure;

[0044] Figure 3A This is a schematic diagram of a first mask layer provided in an embodiment of the present disclosure;

[0045] Figure 3B This is a schematic diagram of the structure of a basic support layer provided in an embodiment of the present disclosure;

[0046] Figure 3C This is a schematic diagram illustrating polymer adhesion to the inner wall of a through-hole, provided as an embodiment of this disclosure.

[0047] Figure 3D A schematic diagram showing a hole appearing in the first electrode layer according to an embodiment of this disclosure;

[0048] Figure 3E This is a schematic diagram illustrating the removal of the first sacrificial layer according to an embodiment of the present disclosure;

[0049] Figure 3F A schematic diagram illustrating the early removal of a second sacrificial layer as provided in an embodiment of this disclosure;

[0050] Figure 3G A cross-sectional schematic diagram of a polymer provided in an embodiment of this disclosure;

[0051] Figure 4A This is a schematic diagram of the composition of a semiconductor structure provided in an embodiment of the present disclosure;

[0052] Figure 4B This is a schematic diagram of the composition of a semiconductor structure provided in an embodiment of the present disclosure;

[0053] Figure 4C This is a schematic diagram of the composition of a semiconductor structure provided in an embodiment of the present disclosure;

[0054] Figure 5 This is a schematic diagram illustrating the implementation process of a memory formation method provided in an embodiment of the present disclosure. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of this disclosure clearer, the technical solutions of this disclosure are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this disclosure. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0056] In the following description, references to "some embodiments" describe a subset of all possible embodiments; however, it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict. In the following description, the terms "first, second, third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein.

[0057] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0058] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0059] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0060] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0061] This disclosure provides a method for forming a semiconductor structure, such as... Figure 1A As shown, the method includes steps S101 to S105, wherein:

[0062] Step S101: Provide a substrate, the substrate including a base, at least one first contact structure and at least one second contact structure located within the base, the base including an array region and a peripheral region, the first contact structure being located in the array region and the second contact structure being located in the peripheral region.

[0063] Here, the substrate can be a silicon substrate, a silicon-on-insulator substrate, etc. In some embodiments, the substrate can be a single-layer substrate or a multi-layer substrate, such as a single-crystal silicon single-layer substrate, a polycrystalline silicon single-layer substrate, a polycrystalline silicon and metal multilayer substrate, etc. In some embodiments, the substrate may also include other semiconductor elements or semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb), or include other semiconductor alloys, such as gallium arsenide phosphide (GaAsP), indium aluminum arsenide (AlInAs), gallium aluminum arsenide (AlGaAs), indium gallium arsenide (GaInAs), indium gallium phosphide (GaInP), and / or indium gallium arsenide phosphide (GaInAsP) or combinations thereof.

[0064] The first and second contact structures may include conductive contact pads, such as metal contact pads, the material of which may be, but is not limited to, tungsten. The first contact structure can be used to contact the capacitor structure to be formed in the array region to conduct electricity between the capacitor structure and other active structures in the array region. The second contact structure can be used to contact the active structures in the peripheral region to form logic circuits in the peripheral region. In implementation, the first and second contact structures may be enclosed within the substrate or exposed on the substrate surface; this is not limited thereto.

[0065] Figure 1B This is a schematic diagram of the composition structure of a substrate provided in an embodiment of the present disclosure, as shown below. Figure 1B As shown, the substrate 100 includes a substrate 110, at least one first contact structure 120 and at least one second contact structure 130 located within the substrate. The substrate 110 is divided into an array region 110a and a peripheral region 110b. The first contact structure 120 is located in the array region 110a and the second contact structure 130 is located in the peripheral region 110b.

[0066] Step S102: A barrier layer covering the peripheral area and a stacked structure covering the barrier layer and the array area are sequentially formed on the substrate surface. The stacked structure includes multiple sacrificial layers and support layers that are alternately stacked along a direction perpendicular to the substrate surface.

[0067] Here, the barrier layer is used to protect the peripheral areas when the stacked structure is etched in subsequent processes. The material of the barrier layer may be at least one of spin-on hardmask (SOH) and silicon oxynitride (SiON).

[0068] Multiple sacrificial layers and multiple support layers are alternately stacked along a direction perpendicular to the substrate surface. The number of sacrificial and support layers can be selected by those skilled in the art according to actual needs. In some embodiments, the stacked structure has at least three support layers and at least two sacrificial layers to enhance the stability of the array region's capacitor structure. The material of the sacrificial layer may include, but is not limited to, oxide materials, such as silicon dioxide; the material of the support layer may include, but is not limited to, nitride materials, such as silicon nitride. In practice, the materials of the sacrificial layer and the support layer are different, so that in subsequent processes, part of the sacrificial layer can be removed while the support layer is retained; or part of the support layer can be removed while the sacrificial layer is retained.

[0069] In some embodiments, the support layer is formed of a first material, and the barrier layer is formed of a second material, wherein the etching selectivity ratio between the first and second materials is greater than a first threshold. Here, the first threshold can be determined based on the etching conditions in the actual etching process, and this disclosure does not limit it. For example, the first threshold can be greater than or equal to 10, such as 10, 20, 30, or 100. Thus, because the etching selectivity ratio between the first and second materials is greater than the first threshold, the barrier layer can be retained when the support layer is etched in subsequent processes, thereby protecting the peripheral area covered by the barrier layer.

[0070] In some embodiments, the barrier layer includes a first barrier layer and a second barrier layer stacked sequentially, and the first barrier layer and the second barrier layer are made of different materials. For example, the first barrier layer may be made of SiO2, and the second barrier layer may be made of SiON.

[0071] In some embodiments, the ratio of the thickness of the first barrier layer to the thickness of the second barrier layer is greater than or equal to 2 and less than or equal to 4. For example, the thickness of the first barrier layer may be 30 nanometers (nm), the thickness of the second barrier layer may be 10 nm, and the ratio of the thickness of the first barrier layer to the thickness of the second barrier layer may be 3:1.

[0072] Figure 1C This is a schematic diagram illustrating the formation of a barrier layer and a stacked structure in a method for forming a semiconductor structure according to an embodiment of this disclosure, as shown below. Figure 1C As shown, a barrier layer 210 covering the peripheral region 110b and a stacked structure 220 covering the barrier layer 210 and the array region 110a are sequentially formed on the surface of the substrate 110. The stacked structure 220 includes a plurality of sacrificial layers 221 and support layers 222 that are alternately stacked in a direction perpendicular to the surface of the substrate 110.

[0073] Step S103: A capacitor hole is formed that penetrates the stacked structure and exposes the first contact structure, and a first electrode layer is formed that covers the inner wall of the capacitor hole.

[0074] Here, the capacitor aperture can penetrate the support layer and sacrificial layer in the corresponding portion of the stacked structure along any suitable direction intersecting the substrate surface, and expose the first contact structure. In some embodiments, the capacitor aperture can penetrate the stacked structure in a direction perpendicular to the substrate surface.

[0075] In some implementations, when the first contact structure is exposed on the substrate surface, each support layer and sacrificial layer can be etched sequentially downwards from the top layer of the stacked structure until the substrate surface, thereby forming a capacitor hole that exposes the first contact structure.

[0076] In some implementations, where the first contact structure is enclosed within a substrate, each support layer and sacrificial layer can be etched sequentially downwards from the top of the stacked structure, and portions of the substrate can be etched until a capacitor hole exposing the first contact structure is formed.

[0077] After forming the capacitor hole, materials such as titanium nitride can be deposited on the inner wall of the capacitor hole to form a first electrode layer covering the inner wall of the capacitor hole, and the first electrode layer is in contact with each first contact structure.

[0078] See Figure 1D and Figure 1E ,like Figure 1D As shown, a capacitor hole 310 can be formed first, penetrating the stacked structure 220 and exposing the first contact structure 120. Then, as... Figure 1E As shown, a first electrode layer 320 is formed covering the inner wall of the capacitor hole 310.

[0079] Step S104: Starting from the top layer of the stacked structure, openings are formed sequentially in each support layer downwards, and the sacrificial layer covered by the support layer is removed through the openings in each support layer.

[0080] Here, starting from the top layer of the stacked structure, at least one opening can be formed in the first support layer, and the first sacrificial layer covered by the first support layer can be removed through the opening of the first support layer to expose the second support layer covered by the first sacrificial layer; then, at least one opening can be formed in the second support layer, and the second sacrificial layer covered by the second support layer can be removed through the opening of the second support layer, and so on, openings can be formed in each support layer in sequence, and the sacrificial layer covered by the support layer can be removed through the opening of each support layer.

[0081] In practice, openings in each support layer can be formed by etching portions of each support layer separately; each sacrificial layer can be etched separately to remove it until a first electrode layer supported by the partial support layers is formed. For example... Figure 1FAs shown, after each sacrificial layer is removed, the first electrode layer 320 is supported by the remaining support layer 222. The etching processes for the support layer and the sacrificial layer can be the same or different. In practice, those skilled in the art can select any suitable etching process according to the actual situation, including but not limited to at least one of dry etching and wet etching processes, which are not limited here. For example, a dry etching process can be used to etch a portion of each support layer to form an opening in each support layer; a wet etching process can be used to etch the sacrificial layer to remove each sacrificial layer.

[0082] In some embodiments, such as Figure 1G As shown, for the target support layer 222c in the stacked structure 220, an opening 223 can be formed in the target support layer 222c based on a set opening pattern. The target sacrificial layer 221c covered by the support layer 222c can then be removed through this opening 223. Next, the target sacrificial layer 221c can be etched through the opening 223 to remove it. Here, the opening pattern can be preset according to actual conditions, and this embodiment of the present disclosure is not limited in this regard. For example, the pattern of the opening pattern can be as follows: Figure 1H As shown, the pattern of the opening layout can define at least one region 31 corresponding to an opening, and each region corresponding to an opening may intersect with at least one region 32 corresponding to a nearby capacitor hole.

[0083] In some implementations, the sacrificial layer covered by the support layer can be removed by wet etching through the opening in the support layer. The wet etching process can be selected based on the specific circumstances; for example, acid etching or similar processes can be used to wet-etch the sacrificial layer.

[0084] Step S105: A dielectric layer covering the surface of the first electrode layer and a second electrode layer covering the dielectric layer are formed sequentially.

[0085] Here, a dielectric layer material with a high dielectric constant can be deposited on the surface of the first electrode layer to form a dielectric layer; then, a material such as titanium nitride is deposited on the surface of the dielectric layer to form a second electrode layer. In implementation, any suitable deposition process, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD), can be used; there is no limitation.

[0086] It is understood that the first electrode layer, the dielectric layer, and the second electrode layer can together constitute a capacitor structure. In some embodiments, the first electrode layer can serve as the lower electrode of the capacitor structure, and the second electrode layer can serve as the upper electrode of the capacitor structure. In some embodiments, the first electrode layer can serve as the upper electrode of the capacitor structure, and the second electrode layer can serve as the lower electrode of the capacitor structure.

[0087] See Figure 1I After removing each sacrificial layer, a dielectric layer 330 covering the surface of the first electrode layer 320 can be deposited, and a second electrode layer 340 covering the dielectric layer 330 can be deposited on the surface of the dielectric layer 330.

[0088] In some embodiments, after removing the sacrificial layer in the stacked structure, a dielectric material can be deposited on the surface of the first electrode layer to form a dielectric layer, and a second conductive material can be filled into the voids of the stacked structure to form a second electrode layer covering the dielectric layer. Here, the second conductive material can be any suitable conductive material, and the embodiments of this disclosure are not limited thereto. For example, the second conductive material can include, but is not limited to, materials such as titanium nitride.

[0089] In some embodiments, a dielectric material may be deposited on the surface of the first electrode layer and on the surface of each support layer to form a dielectric layer.

[0090] In this embodiment, a substrate is provided, comprising a substrate, at least one first contact structure and at least one second contact structure located within the substrate. The substrate includes an array region and a peripheral region, with the first contact structure located in the array region and the second contact structure located in the peripheral region. A barrier layer covering the peripheral region and a stacked structure covering the barrier layer and the array region are sequentially formed on the substrate surface. The stacked structure includes a plurality of sacrificial layers and support layers alternately stacked in a direction perpendicular to the substrate surface. A capacitor aperture penetrating the stacked structure and exposing the first contact structure is formed, along with a first electrode layer covering the inner wall of the capacitor aperture. An opening is sequentially formed in each support layer from the top layer of the stacked structure downwards, and the sacrificial layer covered by the support layer is removed through the opening in each support layer. A dielectric layer covering the surface of the first electrode layer and a second electrode layer covering the dielectric layer are sequentially formed. Thus, since a barrier layer covering the peripheral region is formed on the substrate surface before the stacked structure is formed, this barrier layer can protect the portion of the substrate corresponding to the peripheral region during the formation of the first electrode layer, dielectric layer, and second electrode layer, thereby reducing damage to the second contact structure located in the peripheral region, and further reducing damage to the logic circuits in the peripheral region, improving the yield of semiconductor products.

[0091] In some embodiments, the above method may further include: step S106, sequentially removing the second electrode layer, dielectric layer, and barrier layer located above the peripheral region, and exposing the second contact structure. For example... Figure 1J As shown, a second mask layer 350 can be formed on the surface of the second electrode layer 340, covering a portion of the second electrode layer corresponding to the array region and exposing a portion of the second electrode layer corresponding to the peripheral region; the first mask layer 350 is patterned, and the portion of the second electrode layer covering the peripheral region, the portion of the dielectric layer covering the portion of the second electrode layer, and the portion of the barrier layer are etched. After etching, the second mask layer 350 is removed to obtain the following result: Figure 1K The semiconductor structure shown exposes a second contact structure 130 located in the peripheral region. In practical applications, the semiconductor structure can be further processed to form the final semiconductor product. The second mask layer may include, but is not limited to, at least one of photoresist layers, hard mask layers, and polysilicon layers.

[0092] In some embodiments, step S102 may include the following steps S111 to S113:

[0093] Step S111: A pre-barrier layer is deposited on the substrate surface.

[0094] Step S112: Etch a portion of the pre-blocking layer covering the array area to form a blocking layer covering the outer perimeter area.

[0095] Step S113: On the surface of the barrier layer and the corresponding portion of the substrate surface of the array region, a sacrificial layer and a support layer are deposited and stacked alternately in a direction perpendicular to the substrate surface.

[0096] Figure 2A This is a schematic diagram of the formation of a barrier layer in a method for forming a semiconductor structure according to an embodiment of this disclosure, as shown below. Figure 2A As shown, a pre-blocking layer 211 can be deposited and formed on the substrate 110. Then, a third mask layer 212 can be formed above the pre-blocking layer 211 and patterned. A portion of the pre-blocking layer covering the array region 110a is etched, while a portion of the pre-blocking layer covering the peripheral region 110b is retained. After etching, the third mask layer 212 is removed to obtain the desired result. Figure 2B The barrier layer 210 is shown. The third mask layer 212 may include, but is not limited to, at least one of photoresist layer, hard mask layer, polysilicon layer, etc.

[0097] During implementation, any suitable etching method can be used to etch part of the blocking layer in the coverage array area, and any suitable deposition process can be used to deposit the sacrificial layer and the support layer; there are no limitations here.

[0098] In some embodiments, see Figure 2C The barrier layer 210 includes a first barrier layer 210a and a second barrier layer 210b covering the first barrier layer 210a. In practice, the first and second barrier layers are made of different materials. For example, the first barrier layer can be made of SiO₂, and the second barrier layer can be made of SiON. Here, the first and second barrier layers can provide better protection for the portion of the substrate corresponding to the peripheral region and the second contact structure within that portion of the substrate.

[0099] In some embodiments, the ratio of the thickness of the first barrier layer to the thickness of the second barrier layer is greater than or equal to 2 and less than or equal to 4. For example, the thickness of the first barrier layer may be 30 nanometers (nm), the thickness of the second barrier layer may be 10 nm, and the ratio of the thickness of the first barrier layer to the thickness of the second barrier layer may be 3:1.

[0100] In some embodiments, step S103 may include steps S121 to S122:

[0101] Step S121: A first mask layer is formed above the stacked structure, the first mask layer is patterned, and the stacked structure is etched to form a capacitor hole that penetrates the stacked structure and exposes the first contact structure.

[0102] Step S122: Deposit a first conductive material on the inner wall of the capacitor hole to form a first electrode layer.

[0103] Here, the first mask layer may include, but is not limited to, at least one of photoresist layer, hard mask layer, polysilicon layer, etc. Figure 3A This is a schematic diagram of a first mask layer provided in an embodiment of the present disclosure, such as... Figure 3A As shown, at least one region 32 corresponding to a capacitor hole can be defined in the pattern of the first mask layer.

[0104] Here, the first conductive material can be any suitable conductive material, and this disclosure does not limit this. For example, the first conductive material can include, but is not limited to, materials such as titanium nitride. In implementation, the first conductive material and the second conductive material can be the same or different, and this disclosure does not limit this.

[0105] In some embodiments, the etching of the stacked structure in step S121 above to form a capacitor hole that penetrates the stacked structure and exposes the first contact structure may include: sequentially forming a polycrystalline doped layer covering the stacked structure and a hard mask layer covering the polycrystalline doped layer along a direction perpendicular to the substrate surface; forming a first mask layer above the hard mask layer, patterning the first mask layer, etching the hard mask layer, and transferring the pattern corresponding to the first mask layer to the hard mask layer; etching the polycrystalline doped layer based on the pattern on the hard mask layer corresponding to the first mask layer, and transferring the pattern to the polycrystalline doped layer; and etching the stacked structure based on the pattern on the polycrystalline doped layer to form a capacitor hole that penetrates the stacked structure and exposes the first contact structure.

[0106] In some embodiments, a first conductive material may be deposited on the surface of the stacked structure after the capacitor via is formed; the first conductive material on the support layer covering the top layer of the stacked structure is etched back to form a structure as shown in the figure. Figure 1E The first electrode layer 320 shown covers the inner wall of the capacitor hole 310.

[0107] In some embodiments, such as Figure 3B As shown, the substrate includes a base support layer 115 covering each first contact structure 120 and each second contact structure 130. The etching of the stacked structure described in step S121 to form a capacitor via penetrating the stacked structure and exposing the first contact structure may include the following steps S131 to S132:

[0108] Step S131: Etch the stacked structure to form a through-hole that penetrates the stacked structure and exposes the base support layer.

[0109] Here, the material of the base support layer may include, but is not limited to, nitride materials, such as silicon nitride. In some embodiments, the base support layer may be made of the same material as the support layer in the laminated structure. In some embodiments, the base support layer and the support layer in the laminated structure may be made of different materials.

[0110] By etching each support layer and each sacrificial layer in the stacked structure, through-holes can be formed that penetrate the stacked structure and expose the underlying support layer.

[0111] Step S132: Etch the exposed base support layer in the through hole to form a capacitor hole that exposes the first contact structure, and remove the polymer that adhered to the inner wall of the through hole during the formation of the through hole.

[0112] Here, after etching the stacked structure, the exposed base support layer can be etched to form a capacitor hole that exposes the first contact structure.

[0113] See Figure 3CDuring the etching process of the support layer 222 and sacrificial layer 221 in the stacked structure 220, some byproducts are formed, such as fluorine-containing etching gas C. x H y F z Silicon-containing byproduct C x H y Si z At least one of the following, where x, y, and z are all positive integers; after the via 311 is etched, the remaining byproducts may form polymer 312 that adheres to the inner wall of the via 311.

[0114] It should be noted that, see Figure 3D If polymer 312 is not removed, the electrode layer in the area where polymer 312 is located will be difficult to deposit during the subsequent process of forming the first electrode layer 320, resulting in voids in the formed first electrode layer 320. See also Figure 3E If the first electrode layer 320 has a hole 321, during the subsequent removal of the first sacrificial layer 221a, the etching gas or the pickling solution used for etching (such as liquid hydrofluoric acid (DHF), a mixed solution of diluted hydrofluoric acid and ammonia (NH4OH), or a mixed solution of diluted hydrofluoric acid (DHF) and tetramethylammonium hydroxide (TMAH)) will react through the hole 321 and the second sacrificial layer 221b located below the first sacrificial layer 221a in the part of the stacked structure corresponding to the peripheral area, causing the second sacrificial layer 221b to be removed prematurely (e.g., Figure 3F As shown, during the etching of the first support layer 222a above the second sacrificial layer 221b, the barrier layer 210 covered by the second sacrificial layer 221b will be partially or completely etched, ultimately causing the bottom support layer and barrier layer to be destroyed. This may result in the second contact structure in the peripheral area covered by the barrier layer being destroyed during the removal of the sacrificial layer, thereby damaging the logic circuit in the peripheral area and resulting in a low yield of semiconductor products.

[0115] Therefore, in the semiconductor structure formation method provided in this embodiment, the polymer attached to the inner wall of the via is removed before the first electrode layer is formed. In this way, after the polymer attached to the inner wall of the via is removed, the number of holes in the formed first electrode layer can be reduced, thereby enhancing the protection of the barrier layer, and further enhancing the protection of the logic circuit in the peripheral area, thereby further improving the yield of semiconductor products.

[0116] In some embodiments, such as Figure 3GAs shown, polymer 312 includes a first polymer 312a and a second polymer 312b attached to the surface of the first polymer 312a; the removal of polymer attached to the inner wall of the through hole during the formation of the through hole in step S132 may include the following steps S141 to S142:

[0117] Step S141: After forming the through hole, the through hole is cleaned with cleaning gas to remove the second polymer.

[0118] In step S142, during the etching of the base support layer, the first polymer is removed by bombarding with ions generated during etching.

[0119] In some embodiments, the cleaning gas may include at least one of the following: oxygen, argon, and chlorine.

[0120] In some implementations, a cleaning gas can be used to flush the vias located at the edge of the array region and adjacent to the peripheral region.

[0121] In the above embodiments, after forming the via, the via is first cleaned with a cleaning gas to remove the second polymer adhering to the surface of the first polymer, thus exposing the first polymer. Then, during the etching of the base support, the first polymer is removed by bombardment using etching-generated particles. In this way, targeted removal methods are used for the first and second polymers respectively, resulting in better removal of both polymers. This further reduces the number of holes in the formed first electrode layer, thereby enhancing the protection of the logic circuitry in the peripheral area and improving the yield of the semiconductor product.

[0122] This disclosure provides a semiconductor structure. Figure 4A This is a schematic diagram illustrating the composition of a semiconductor structure provided in an embodiment of this disclosure. Figure 4A As shown, the semiconductor structure includes: a substrate 110, a plurality of first contact structures 120, a plurality of second contact structures 130, a barrier layer 210, and a plurality of memory structures 150; wherein,

[0123] The substrate 110 includes an array region 110a and a peripheral region 110b, a first contact structure 120 is located in the array region 110a, and a second contact structure 130 is located in the peripheral region 110b.

[0124] The storage structure 150 is located above the first contact structure 120 and is electrically connected to the first contact structure 120 in a one-to-one correspondence.

[0125] The barrier layer 210 is located above the outer perimeter area 110b.

[0126] In some embodiments, such as Figure 4BAs shown, the barrier layer 210 may include a first barrier layer 210a and a second barrier layer 210b stacked sequentially, and the first barrier layer 210a and the second barrier layer 210b are made of different materials.

[0127] In some embodiments, the ratio of the thickness of the first barrier layer to the thickness of the second barrier layer is greater than or equal to 2 and less than or equal to 4.

[0128] In some embodiments, such as Figure 4C As shown, an insulating layer 160 is further disposed between the barrier layer 210 and the second contact structure 130, and the etching selectivity ratio between the materials of the insulating layer 160 and the barrier layer 210 is greater than a second threshold. Here, the second threshold can be determined according to the etching conditions in the actual etching process, and the embodiments of this disclosure are not limited thereto. For example, the second threshold can be greater than or equal to 10, such as 10, 20, 30, or 100. In some embodiments, the insulating layer may include a base support layer.

[0129] In some embodiments, such as Figure 4A As shown, the storage structure 150 includes a first electrode layer 320, a dielectric layer 330, and a second electrode layer 340, with the dielectric layer 330 covering the surface of the barrier layer 210.

[0130] This disclosure provides a method for forming a memory. Figure 5 This is a schematic diagram illustrating the implementation flow of a method for forming a memory according to an embodiment of this disclosure. Figure 5 As shown, the method includes the following steps S501 to S502:

[0131] Step S501: Provide a substrate, the substrate including an array region and a peripheral region, the array region including a plurality of transistors arranged in an array, a plurality of word lines, a plurality of bit lines and a plurality of first contact structures, the peripheral region including peripheral devices and a plurality of second contact structures; wherein, each word line extends along a first direction and is connected to the gate of a column of transistors arranged along the first direction, each bit line extends along a second direction and is electrically connected to one of the source or drain of a row of transistors arranged along the second direction, the first direction and the second direction intersect, and the first contact structure is electrically connected to the other of the source or drain of the transistor;

[0132] Step S502: Based on the substrate, using the semiconductor structure formation method described in the above embodiments, a capacitor structure electrically connected to the first contact structure is formed on the substrate.

[0133] The above-described semiconductor structure embodiments and memory formation method embodiments have similar beneficial effects to the semiconductor structure formation method embodiments. For technical details not disclosed in the semiconductor structure embodiments and memory formation method embodiments of this disclosure, please refer to the description of the semiconductor structure formation method embodiments of this disclosure for understanding.

[0134] In the several embodiments provided in this disclosure, it should be understood that the disclosed structures and methods can be implemented in a non-target manner. The structural embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the various components shown or discussed are coupled or directly coupled to each other.

[0135] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0136] The features disclosed in the several method or structural embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or structural embodiments.

[0137] The above description is only some implementation methods of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present disclosure should be included within the protection scope of the present disclosure.

Claims

1. A method for forming a semiconductor structure, characterized in that, The method includes: A substrate is provided, the substrate including a substrate, at least one first contact structure and at least one second contact structure located within the substrate, the substrate including an array region and a peripheral region, the first contact structure being located in the array region and the second contact structure being located in the peripheral region; A barrier layer covering the peripheral region and a stacked structure covering the barrier layer and the array region are sequentially formed on the surface of the substrate. The stacked structure includes a plurality of sacrificial layers and support layers that are alternately stacked along a direction perpendicular to the surface of the substrate. A capacitor hole is formed that penetrates the stacked structure and exposes the first contact structure, and a first electrode layer covers the inner wall of the capacitor hole; An opening is formed sequentially in each support layer from the top layer of the stacked structure downwards, and the sacrificial layer covered by the support layer is removed through the opening in each support layer; A dielectric layer covering the surface of the first electrode layer and a second electrode layer covering the dielectric layer are formed sequentially; The step of sequentially forming a barrier layer covering the peripheral region and a stacked structure covering the barrier layer and the array region on the substrate surface includes: A pre-barrier layer is deposited on the surface of the substrate; A portion of the pre-blocking layer covering the array region is etched to form a blocking layer covering the peripheral region; Sacrificial and support layers are deposited alternately stacked in a direction perpendicular to the substrate surface on the surface of the barrier layer and on the corresponding portion of the substrate surface of the array region.

2. The method according to claim 1, characterized in that, The support layer is formed of a first material, the barrier layer is formed of a second material, and the etching selectivity ratio between the first material and the second material is greater than a first threshold.

3. The method according to claim 1, characterized in that, The barrier layer includes a first barrier layer and a second barrier layer covering the first barrier layer.

4. The method according to claim 1, characterized in that, The formation of a capacitor hole penetrating the stacked structure and exposing the first contact structure, and a first electrode layer covering the inner wall of the capacitor hole, includes: A first mask layer is formed above the stacked structure, the first mask layer is patterned, and the stacked structure is etched to form a capacitor hole that penetrates the stacked structure and exposes the first contact structure. A first conductive material is deposited on the inner wall of the capacitor hole to form a first electrode layer.

5. The method according to claim 4, characterized in that, The substrate includes a base support layer covering each of the first contact structure and each of the second contact structures; The etching of the stacked structure to form a capacitor hole that penetrates the stacked structure and exposes the first contact structure includes: The stacked structure is etched to form through-holes that penetrate the stacked structure and expose the base support layer; The exposed base support layer in the through hole is etched to form a capacitor hole that exposes the first contact structure, and the polymer that adhered to the inner wall of the through hole during the formation of the through hole is removed.

6. The method according to claim 5, characterized in that, The polymer includes a first polymer and a second polymer adhered to the surface of the first polymer; the removal of the polymer adhered to the inner wall of the through-hole during the formation of the through-hole includes: After the through hole is formed, the through hole is cleaned with a cleaning gas to remove the second polymer; During the etching of the base support layer, the first polymer is removed by bombarding with ions generated during the etching process.

7. The method according to claim 6, characterized in that, The cleaning gas includes at least one of the following: oxygen, argon, and chlorine.

8. The method according to any one of claims 1 to 7, characterized in that, The method further includes: sequentially removing the second electrode layer, the dielectric layer, and the barrier layer located above the peripheral region, and exposing the second contact structure.

9. A semiconductor structure, characterized in that, include: The substrate, multiple first contact structures, multiple second contact structures, a barrier layer, and multiple memory structures; The substrate includes an array region and a peripheral region, the first contact structure is located in the array region, and the second contact structure is located in the peripheral region; The storage structure is located above the first contact structure and is electrically connected to the first contact structure in a one-to-one correspondence. The barrier layer is located above the peripheral area; The barrier layer is formed by depositing a pre-barrier layer on the substrate surface; etching a portion of the pre-barrier layer covering the array region to form a barrier layer covering the peripheral region; and depositing sacrificial and support layers alternately stacked in a direction perpendicular to the substrate surface on the surface of the barrier layer and on the corresponding portion of the substrate surface of the array region.

10. The structure according to claim 9, characterized in that, The barrier layer comprises a first barrier layer and a second barrier layer stacked sequentially, and the first barrier layer and the second barrier layer are made of different materials.

11. The structure according to claim 10, characterized in that, The ratio of the thickness of the first barrier layer to the thickness of the second barrier layer is greater than or equal to 2 and less than or equal to 4.

12. The structure according to claim 9 or 10, characterized in that, An insulating layer is further disposed between the barrier layer and the second contact structure, and the etching selectivity ratio between the materials of the insulating layer and the barrier layer is greater than a second threshold.

13. The structure according to claim 9 or 10, characterized in that, The storage structure includes a first electrode layer, a dielectric layer, and a second electrode layer, wherein the dielectric layer covers the surface of the barrier layer.

14. A method for forming a memory, characterized in that, The method includes: A substrate is provided, the substrate including an array region and a peripheral region, the array region including a plurality of transistors, a plurality of word lines, a plurality of bit lines and a plurality of first contact structures arranged in an array, the peripheral region including peripheral devices and a plurality of second contact structures; wherein each word line extends along a first direction and is connected to the gate of a column of transistors arranged along the first direction, each bit line extends along a second direction and is electrically connected to one of the source or drain of a row of transistors arranged along the second direction, the first direction intersects the second direction, and the first contact structure is electrically connected to the other of the source or drain of the transistor; Based on the substrate, a capacitor structure electrically connected to the first contact structure is formed on the substrate using the semiconductor structure formation method as described in any one of claims 1 to 8.

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