Method, apparatus, and medium for logic simulation

Abstract

A method and apparatus for simulating a logic circuit. The method includes staging the logic circuit and performing parallel computation of a plurality of logic gates in each stage using test vectors in a same time frame by a GPU to ultimately obtain a set of logic simulation outputs. Compared to a conventional serial simulation performed by a CPU, such as hardcoding, parallel simulation of a plurality of logic gates in a staged circuit by a GPU can substantially reduce the time of logic simulation.

Description

Technical Field

[0001] This disclosure relates to the field of electronics, and more specifically to methods, apparatus and devices for simulating integrated circuits. Background Technology

[0002] Various electronic design automation (EDA) tools have been developed to complete the design process for very large scale integration (VLSI) chips, including functional design, synthesis, verification, and physical design (including placement, routing, layout, and design rule checking). In the design process of integrated circuits such as digital integrated circuits, a crucial stage is logic circuit simulation, which verifies the correctness of the circuit design before tape-out. Logic circuit simulation typically includes two stages: logic simulation and fault simulation. Logic simulation is a technique that derives the output of a logic circuit based on its structure and given input stimuli. It is a commonly used technique in digital circuit design, using a computer to simulate the behavior of the circuit to verify its correctness. It can also be used to check the correctness of test vectors (containing input stimuli and expected outputs). Logic simulation can be performed at different levels of abstraction, such as behavioral level, register transfer level (RTL), gate level, and transistor level.

[0003] Conventional logic simulations, including hard-coded logic simulations and event-driven logic simulations, are typically executed serially on a central processing unit (CPU). Integrated circuits often contain tens of millions of logic gates, and conventional logic simulations consume a considerable amount of time. Summary of the Invention

[0004] In view of the above problems, embodiments of this disclosure are intended to provide a method, storage medium, program product, and electronic device for logic simulation.

[0005] According to a first aspect of this disclosure, a method for logic simulation is provided. The method includes receiving hierarchical data of a logic circuit. The hierarchical data represents multiple levels of the logic circuit, the multiple levels being divided based on the connection relationships of multiple logic gates in the logic circuit. The method also includes generating a logic simulation output set based on the hierarchical data and a test vector set for the logic circuit. Generating the logic simulation output set involves parallel computation of the logic output values ​​of multiple logic gates located in the same level of the circuit within the same time frame, the logic output values ​​of the multiple logic gates being associated with the logic simulation output set. By using an accelerator such as a graphics processing unit (GPU) to parallel computation of the outputs of multiple logic gates in the same time frame, processing time can be significantly reduced compared to conventional serial computation by a CPU. Furthermore, by hierarchically processing the logic simulation circuit, the correctness of the logic simulation can be ensured because the multiple logic gates processed in parallel are located in the same level of the circuit and are not causally related to each other in terms of the logic simulation results.

[0006] In one possible implementation of the first aspect, the test vector set includes a first test vector and a second test vector, and the logic simulation output set includes a first output subset and a second output subset. Generating the logic simulation output set further includes generating the first output subset based on the hierarchical data and the first test vector; and generating the second output subset based on the hierarchical data and the second test vector. The generation of the first output subset and the generation of the second output subset are performed in parallel. In addition to performing parallel computation on multiple logic gates within the same level in the same time frame, the logic simulation time can be further reduced by performing parallel logic simulation on multiple test vectors.

[0007] In one possible implementation of the first aspect, generating the first output subset includes, based on hierarchical data and a first test vector, parallel computing of a first plurality of outputs of multiple logic gates located in the same level of circuitry within the same time frame, wherein the first plurality of outputs are associated with the first output subset. In addition to performing parallel computing on multiple logic gates within the same level within the same time frame, the logic simulation time can be further reduced by also performing parallel logic simulation on multiple test vectors.

[0008] In one possible implementation of the first aspect, generating the logic simulation output set further includes determining whether a first-level circuit in the logic circuit will be computed in a first time frame; if it is determined that the first-level circuit will be computed, then a first output set of the first-level circuit is computed, and the logic simulation output set is associated with the first output set; and if it is determined that the first-level circuit will not be computed, then the output set of the first-level circuit in the time frame preceding the first time frame is used as the first output set of the first-level circuit in the first time frame. By determining whether the hierarchical circuits in the logic circuit need to be computed in some time frames, the computation time of the logic gates of the entire hierarchical circuit can be omitted when computation is not required, thereby further reducing the total time of logic simulation and also reducing the consumption of computing resources so that limited computing resources can be used to process other logic gates that need to be computed. This further reduces the total time of logic simulation.

[0009] In one possible implementation of the first aspect, determining whether a first-level circuit in the logic circuit will be computed in a first time frame includes at least one of the following: determining whether the value of a first hierarchical flag bit corresponding to the first-level circuit in the first time frame is a first value, wherein the first value of the first hierarchical flag bit indicates that the input set of the first-level circuit in the first time frame is at least partially different from the input set of the first-level circuit in a previous time frame; and determining whether all inputs or combinations of factors of the first-level circuit in the first time frame have changed compared to all inputs or combinations of factors of the first-level circuit in a previous time frame. By using the flag bit, it is possible to simply and effectively determine whether logic gates in the hierarchical circuit need to be computed. Due to the simplicity and effectiveness of using the flag bit determination method, the time required to determine whether the logic circuit needs to be computed can also be reduced. This further reduces the total time of logic simulation.

[0010] In one possible implementation of the first aspect, calculating the first output set of the first-level circuit includes: determining whether a first logic gate in the first-level circuit will be calculated in a first time frame; if it is determined that the first logic gate will be calculated, then calculating the first output of the first logic gate; and if it is determined that the first logic gate will not be calculated, then using the output of the first logic gate in a time frame preceding the first time frame as the first output of the first logic gate in the first time frame, with the logic simulation output set associated with the first output. By determining whether some logic gates in the logic circuit need to be calculated in some time frames, the calculation time of these logic gates can be omitted when they do not need to be calculated, thereby further reducing the total logic simulation time and also reducing the consumption of computing resources so that limited computing resources can be used to process other logic gates that need to be calculated. This further reduces the total logic simulation time.

[0011] In one possible implementation of the first aspect, determining whether a first logic gate in a first-level circuit will be computed in a first time frame includes at least one of the following: determining whether all inputs of the first logic gate in the first time frame have changed compared to all inputs of the first logic gate in a previous time frame; and determining whether all inputs or combinations of factors of the first logic gate in the first time frame have changed compared to all inputs or combinations of factors of the first logic gate in a previous time frame. By using the flag bit, it is possible to simply and effectively determine whether a logic gate in a hierarchical circuit needs to be computed. Due to the simplicity and effectiveness of using the flag bit determination method, the time required to determine whether a logic circuit needs to be computed can also be reduced. This further reduces the total time of logic simulation.

[0012] In one possible implementation of the first aspect, generating the logic simulation output set based on hierarchical data and a test vector set for the logic circuit further includes: calculating the output of each level of the circuit frame by frame in turn; and generating the logic simulation output set based on the output of each level of the circuit in the last time frame. By calculating the logic output of each level frame by frame in turn, the accuracy of the causality of logical operations in the logic simulation can be ensured, thereby improving the accuracy of the logic simulation.

[0013] In one possible implementation of the first aspect, calculating the output of each level circuit frame by frame includes: determining whether the number of calculations of the output of the level circuit including sequential logic gates in a time frame exceeds a threshold number; if the number of calculations of the output of the level circuit including sequential logic gates in a time frame exceeds the threshold number, a fault indication is generated, indicating that a logic simulation failure has occurred. By setting a loop threshold number, it is possible to avoid the logic simulation from getting stuck in an erroneous loop or an infinite loop targeting sequential logic gates, and to report logic simulation errors in a timely manner, thereby reducing the logic simulation time.

[0014] According to a second aspect of this disclosure, a computer-readable storage medium is provided. The computer-readable storage medium stores a plurality of programs configured to be executed by one or more processors, the programs including instructions for performing the method of the first aspect.

[0015] According to a third aspect of this disclosure, a computer program product is provided. The computer program product includes a plurality of programs configured to be executed by one or more processors, and the plurality of programs include instructions for performing the method of the first aspect.

[0016] According to a fourth aspect of this disclosure, an electronic device is provided. The electronic device includes: one or more processors; and a memory including computer instructions. When executed by the one or more processors of the electronic device, the computer instructions cause the electronic device to perform the method of the first aspect.

[0017] According to a fifth aspect of this disclosure, an electronic device is provided. The electronic device includes a receiving unit and a generating unit. The receiving unit is used to receive hierarchical data of a logic circuit, the hierarchical data representing multiple levels of the logic circuit, the multiple levels being divided based on the connection relationships of multiple logic gates in the logic circuit. The generating unit is used to generate a logic simulation output set based on the hierarchical data and a test vector set for the logic circuit, wherein generating the logic simulation output set includes parallel computation of the logic output values ​​of multiple logic gates located in the same level of the circuit within the same time frame, the logic output values ​​of the multiple logic gates being associated with the logic simulation output set. Generally, using accelerators such as GPUs to parallel compute the outputs of multiple logic gates in the same time frame can significantly reduce processing time compared to the conventional serial computation of CPUs. Furthermore, by hierarchically processing the logic simulation circuit, the correctness of the logic simulation can be ensured because the multiple logic gates processed in parallel are located in the same level of the circuit and are not causally related to each other in terms of the logic simulation results.

[0018] In one possible implementation of the fifth aspect, the test vector set includes a first test vector and a second test vector, and the logic simulation output set includes a first output subset and a second output subset. The generation unit is also used to generate the first output subset based on the hierarchical data and the first test vector; and to generate the second output subset based on the hierarchical data and the second test vector. The generation of the first output subset and the second output subset are performed in parallel. In addition to performing parallel computation on multiple logic gates within the same level in the same time frame, the logic simulation time can be further reduced by performing parallel logic simulation on multiple test vectors.

[0019] In one possible implementation of the fifth aspect, the generation unit is further configured to: compute, in parallel, a first plurality of outputs of multiple logic gates located in the same level of circuit within the same time frame, based on hierarchical data and a first test vector, wherein the first plurality of outputs are associated with a first subset of outputs. In addition to performing parallel computation on multiple logic gates within the same level within the same time frame, the logic simulation time can be further reduced by also performing parallel logic simulation on multiple test vectors.

[0020] In one possible implementation of the fifth aspect, the generation unit is further configured to: determine whether the first-level circuit in the logic circuit will be computed in the first time frame; if it is determined that the first-level circuit will be computed, then compute the first output set of the first-level circuit, with the logic simulation output set associated with the first output set; and if it is determined that the first-level circuit will not be computed, then use the output set of the first-level circuit in the time frame preceding the first time frame as the first output set of the first-level circuit in the first time frame. By determining whether the hierarchical circuit in the logic circuit needs to be computed in some time frames, the computation time of the logic gates of the entire hierarchical circuit can be omitted when computation is not required, thereby further reducing the total time of logic simulation and also reducing the consumption of computing resources so that limited computing resources can be used to process other logic gates that need to be computed. This further reduces the total time of logic simulation.

[0021] In one possible implementation of the fifth aspect, the generation unit is further configured to determine whether the value of the first hierarchical flag bit corresponding to the first-level circuit in the first time frame is a first value, wherein the first value of the first hierarchical flag bit indicates that the input set of the first-level circuit in the first time frame is at least partially different from the input set of the first-level circuit in the previous time frame; and to determine whether the total number of inputs or combinations of factors of the first-level circuit in the first time frame has changed compared to the total number of inputs or combinations of factors of the first-level circuit in the previous time frame. By using the flag bit, it is possible to simply and effectively determine whether the logic gates in the hierarchical circuit need to be computed. Due to the simplicity and effectiveness of the flag bit determination method, the time required to determine whether the logic circuit needs to be computed can also be reduced. This further reduces the total time of logic simulation.

[0022] In one possible implementation of the fifth aspect, the generation unit is further configured to determine whether a first logic gate in the first-level circuit will be computed in a first time frame; if it is determined that the first logic gate will be computed, then the first output of the first logic gate is computed; and if it is determined that the first logic gate will not be computed, then the output of the first logic gate in the previous time frame is used as the first output of the first logic gate in the first time frame, and the logic simulation output set is associated with the first output. By determining whether some logic gates in the logic circuit need to be computed in some time frames, the computation time of these logic gates can be omitted when they do not need to be computed, thereby further reducing the total time of logic simulation and also reducing the consumption of computing resources so that limited computing resources can be used to process other logic gates that need to be computed. This further reduces the total time of logic simulation.

[0023] In one possible implementation of the fifth aspect, the generation unit is further configured to determine whether all inputs of the first logic gate in the first time frame have changed compared to all inputs of the first logic gate in a previous time frame, including: determining whether the value of the first logic gate flag bit corresponding to the first logic gate in the first time frame is a first value, wherein the first value of the first logic gate flag bit indicates that the inputs of the first logic gate in the first time frame are at least partially different from the inputs of the first logic gate in a previous time frame; and determining whether all inputs or combinations of factors of the first logic gate in the first time frame have changed compared to all inputs or combinations of factors of the first logic gate in a previous time frame. By using the flag bit, it is possible to simply and effectively determine whether logic gates in a hierarchical circuit need to be computed. Due to the simplicity and effectiveness of using the flag bit determination method, the time required to determine whether logic circuits need to be computed can also be reduced. This further reduces the total time of logic simulation.

[0024] In one possible implementation of the fifth aspect, based on hierarchical data and a test vector set for the logic circuit, the generation unit is further configured to: sequentially calculate the output of each level of the circuit frame by frame; and generate a logic simulation output set based on the output of each level of the circuit in the last time frame. By calculating the logic output of each level frame by frame, the accuracy of the causality of logical operations in the logic simulation can be ensured, thereby improving the accuracy of the logic simulation.

[0025] In one possible implementation of the fifth aspect, the generation unit is further configured to determine whether the number of calculations of the output of the hierarchical circuit including sequential logic gates in a time frame exceeds a threshold number; if the number of calculations of the output of the hierarchical circuit including sequential logic gates in a time frame exceeds the threshold number, a fault indication is generated, indicating that a logic simulation failure has occurred. By setting a loop threshold number, it is possible to prevent the logic simulation from getting stuck in an erroneous loop or an infinite loop targeting sequential logic gates, and to report logic simulation errors in a timely manner, thereby reducing the logic simulation time.

[0026] It should be understood that the description in the Summary of the Invention section is not intended to limit the key or essential features of the embodiments of this disclosure, nor is it intended to restrict the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0027] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. In the drawings, the same or similar reference numerals denote the same or similar elements, wherein:

[0028] Figure 1A schematic diagram of a simulation system 100 for logic circuits according to some embodiments of the present disclosure is shown.

[0029] Figure 2 A schematic block diagram illustrating the simulation flow of a logic circuit according to some embodiments of the present disclosure is shown.

[0030] Figure 3 Example circuit diagrams of illustrative logic circuits according to some embodiments of the present disclosure are shown.

[0031] Figure 4 It shows Figure 3 A hierarchical diagram of the logic circuits in the diagram.

[0032] Figure 5 It shows Figure 3 A schematic diagram of the logic circuits in the time frame.

[0033] Figure 6 A schematic diagram of a simulation process executed by a general-purpose processor according to some embodiments of the present disclosure is shown.

[0034] Figure 7 A schematic flowchart of a logic simulation method according to some embodiments of the present disclosure is shown.

[0035] Figure 8 A schematic diagram of a simulation process executed by a graphics processor according to some embodiments of the present disclosure is shown.

[0036] Figure 9 Some embodiments according to this disclosure are shown. Figure 8 A schematic diagram of the combinational logic calculation process in the process.

[0037] Figure 10 Some embodiments according to this disclosure are shown. Figure 8 A schematic diagram illustrating the implementation logic calculation process in the process.

[0038] Figure 11 A schematic block diagram illustrating some examples of logic simulation according to some embodiments of the present disclosure is shown.

[0039] Figure 12 Schematic block diagrams illustrating some examples of logic simulation according to other embodiments of this disclosure are shown.

[0040] Figure 13 A schematic block diagram of an electronic device according to some embodiments of the present disclosure is shown.

[0041] Figure 14 A block diagram of an example device that can be used to implement some embodiments of the present disclosure is shown. Detailed Implementation

[0042] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0043] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "an embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc., may refer to different or the same objects. The term "and / or" indicates at least one of the two items associated therewith. For example, "A and / or B" means A, B, or A and B. Other explicit and implicit definitions may also be included below.

[0044] It should be understood that the technical solutions provided in the embodiments of this application may not be repeated in the following description of specific embodiments, but it should be regarded as that there are mutual references between these specific embodiments and they can be combined with each other.

[0045] As mentioned above, conventional logic simulation consumes a considerable amount of simulation time. For example, in conventional hard-coded logic simulation, the hard code sequentially calculates the logic values ​​of each logic gate in the logic circuit, starting from the original input. This is typically executed serially on the CPU and consumes a considerable amount of simulation time because the CPU mainly calculates the logic simulation value of each logic gate sequentially until the final logic simulation output set is obtained.

[0046] In some embodiments of this disclosure, after reading the netlist file, the processor hierarchically categorizes the logic gates in the logic circuit described in the netlist file according to their type, placing sequential logic gates, raw input ports, and raw output ports into the first-level circuit, and combinational logic gates into the second-level circuit. By using an accelerator such as a GPU to compute the outputs of multiple logic gates in parallel within the same time frame, processing time can be significantly reduced compared to the conventional serial computation of a CPU. Furthermore, by hierarchically categorizing the logic simulation circuit, the correctness of the logic simulation can be ensured because the multiple logic gates processed in parallel reside in the same level of circuit and are not causally related to each other in terms of the logic simulation results.

[0047] Figure 1A schematic diagram of a simulation system 100 for logic circuits according to some embodiments of the present disclosure is shown. In one embodiment, the simulation system 100 includes, for example, an electronic device 10 and an ATPG device 20. In one embodiment, the electronic device 10 is, for example, a computer. The electronic device 10 includes a general-purpose processor 14, such as a CPU, and an accelerator 12, such as a GPU, wherein the general-purpose processor 14 and the accelerator 12 may each include a cache. Alternatively, in some embodiments, the cache may also be independent of the general-purpose processor 14 and the accelerator 12, and the scope of the present disclosure is not limited thereto. Accelerators such as GPUs typically include a large number of computing units, and for certain types of data processing, accelerators have significant advantages over general-purpose processors such as CPUs. For example, a GPU may have hundreds or thousands of processing engines or threads, which are suitable for parallel processing of data with the same or similar data formats, such as parallel processing of image pixels. In some embodiments of the present disclosure, GPUs are used to compute multiple logic gates in the same level of a circuit in parallel. For example, if a circuit in a level includes 100 logic gates, by using a GPU for parallel computation, the processing time can theoretically be reduced to about 1 / 100th of the serial computation time compared to serial computation. Although GPUs are used to describe parallel computing in this disclosure, it is to be understood that this is merely illustrative and not intended to limit the scope of this disclosure. In some embodiments, other accelerators such as field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs) may be used to implement parallel computing of logic gates.

[0048] ATPG device 20 is configured to generate ATPG data for logic simulation and transmit the ATPG data to electronic device 10. Although in Figure 1 While the electronic device 10 and the ATPG device 20 are defined independently, in some embodiments, the ATPG device 20 may be integrated with the electronic device 10, and this disclosure does not limit this. The electronic device 10 may include input devices, communication devices, displays, audio devices, and other components not shown herein. The electronic device 10 may, for example, include a desktop computer, laptop, workstation, server, or other device with computing capabilities. The netlist file describing the logic circuit can be transmitted to the electronic device 10 via various wired or wireless means. Alternatively, the electronic device 10 may also read the netlist file using a storage medium storing the netlist file. The ATPG device 20 can generate different ATPG data for different logic circuits.

[0049] Figure 2 A schematic diagram of a simulation process 200 according to some embodiments of the present disclosure is shown. In one embodiment, the simulation process 200 consists of... Figure 1The electronic device 10 executes the simulation, therefore the description of the electronic device 10 can be applied to the simulation process 200. The simulation process may include, for example, logic simulation 210 and fault simulation (not shown). Logic simulation 210 uses ATPG data 202 from ATPG device 20 and a netlist file 204 obtained wirelessly, via wired connection, or by reading from a storage medium. The netlist file 204 includes data describing the various logic gates (including sequential and combinational logic gates), raw inputs, raw outputs, and coupling relationships between the various components in the logic circuit. The electronic device 10 can execute logic simulation 210 to generate a logic simulation output set. The specific process of logic simulation 210 is described below.

[0050] Figure 3 Example circuit diagrams of schematic logic circuitry 30 according to some embodiments of the present disclosure are shown. Logic circuitry 30 is for illustrative purposes only and is not intended to limit the scope of the disclosure. It will be understood that other configurations of logic circuitry are also possible. Logic circuitry 30 may, for example, include a first raw data input PI1, an AND gate 31, a first flip-flop U1, a second raw data input PI2, an inverter 32, a second flip-flop U2, a first buffer 33, a second buffer 34, and a raw output PO. The input of AND gate 31 is coupled to the first raw data input PI1 and the output of the first flip-flop U1. The clock port C1 of the first flip-flop U1 is configured to receive a first clock signal, the reset terminal of the first flip-flop U1 is coupled to the output of the second buffer 34, and the output of the first flip-flop U1 is coupled to the raw output PO. The input of inverter 32 is coupled to the second raw data input PI2, and the output of inverter 32 is coupled to the input of the second flip-flop U2. The clock port C2 of the second flip-flop U2 is configured to receive a second clock signal, and the output of the second flip-flop U2 is coupled to the input of the first buffer 33, and the output of the first buffer 33 is coupled to the input of the second buffer 34. The logic circuit 30 includes a first type of sequential logic gates and a second type of combinational logic gates. The first type of sequential logic gates includes a first buffer U1 and a second buffer U2, while the second type of combinational logic gates includes an AND gate 31, an inverter 32, a first buffer 33, and a second buffer 34.

[0051] Figure 4 It shows Figure 3The diagram illustrates the hierarchical structure of the logic circuits. In some embodiments of this disclosure, during logic simulation, the processor divides the logic circuit into two levels based on the coupling relationships of the logic gates described in the netlist file. The first level includes sequential logic gates, raw inputs, and raw outputs, while the second level includes combinational logic gates. In other embodiments, the second level can be further hierarchically defined based on the relationship between the combinational logic gates and the first level circuit, as well as the relationships between the combinational logic gates themselves. For example, the second level may include a first sub-level circuit, a second sub-level circuit, ..., an Nth sub-level circuit, where N represents an integer greater than 1, and the specific value of N depends on the logic circuit to be simulated. In one embodiment, the first sub-level circuit includes combinational logic gates directly coupled to the first level circuit, the second sub-level circuit includes combinational logic gates directly coupled to the first sub-level circuit, and so on.

[0052] exist Figure 4 In the illustrated embodiment, the logic circuit 30 can be divided into three levels, wherein Figure 4 The diagram shows that level 0 corresponds to the first-level circuit, level 1 corresponds to the first sub-level circuit of the second-level circuit, and level 2 corresponds to the second sub-level circuit of the second-level circuit. The first-level circuit includes a raw output PO, a first raw data input PI1, a second raw data input PI2, a first flip-flop U1, and a second flip-flop U2. The first sub-level circuit includes an AND gate 31, a first buffer 33, and an inverter 32. The second sub-level circuit includes a second buffer 34. In some cases, the clock signal is not directly applied to the clock port of the sequential logic gate, but rather applied to the clock port of the sequential logic gate of the first-level circuit via one or more combinational logic gates. In this case, the second-level circuit may include combinational logic gates between the raw clock input port and the clock port of the sequential logic gate.

[0053] Although Figure 4 The illustration shows one specific implementation of the hierarchical structure, but this does not limit the scope of this disclosure. Other hierarchical methods can also be used. In one embodiment, the raw inputs, raw outputs, and sequential logic gates can be divided into different levels. For example, the raw outputs can be concentrated in the last level of the combinational logic gates, or they can be distributed in the next level after their respective drivers.

[0054] Figure 5 It shows Figure 3 A schematic diagram of the logic circuits in the time frame. Figure 4The diagram illustrates the hierarchical structure of a logic circuit within a single time frame. However, logic simulation typically involves multiple time frames, rather than a single frame, to simulate the logic output under different inputs. Furthermore, for sequential logic gates, a single logic level on the clock port is usually insufficient to determine whether they have been triggered; multiple successive logic levels are required. For example, a register requires a transition from low (logic "0") to high (logic "1") on the clock port to be triggered. Therefore, for logic circuits with sequential logic gates, multiple time frames are needed to determine whether triggering has occurred.

[0055] Clock signals are typically provided in pulse form and include a series of high and low pulses such as "...10101010...". Figure 5 As shown in the upper middle section, in one embodiment, a segment of a clock signal of "010" can be used to determine whether a trigger exists. For example, the latter half of a clock signal that is "0" (low level) can be selected as the first "0" of the aforementioned "010" segment, a series of consecutive complete "1"s (high level) of the clock signal can be used as the "1" of the aforementioned "010" segment, and the first half of a series of consecutive "0"s of the clock signal can be used as the second "0" of the aforementioned "010" segment. In this way, one clock cycle corresponds to one cycle used to determine whether a trigger exists. This clock cycle includes three logic values, and therefore corresponds to three time frames. Alternatively, a segment of a clock signal of "101" can also be used to determine whether a trigger exists.

[0056] Figure 5 The diagram shows a time frame unfolding of logic circuit 30 corresponding to three time frames in one cycle. Frame 0 corresponds to the first "0" of the aforementioned "010" segment, frame 1 corresponds to the "1" of the aforementioned "010" segment, and frame 2 corresponds to the second "0" of the aforementioned "010" segment. Since logic simulation typically involves multiple raw input sets to determine the simulation results of the logic circuit under different inputs, for example, the logic input value for the first raw data input PI1 is, for example, the first logic input set, which may include, for example, a 64-bit value. Therefore, M cycles may be required for simulation, where M represents an integer greater than 1, such as 64. Figure 5 In terms of frame expansion, logic circuit 30 needs to be expanded into 3M time frames. The expansion of logic circuit 30 in each time frame has a substantially the same hierarchical form, so it will not be described again here.

[0057] Figure 6 A schematic diagram of a method 600 for simulation executed by a general-purpose processor according to some embodiments of the present disclosure is shown. In one embodiment, the simulation process 600 may be executed by a general-purpose processor such as a CPU for logic simulation, for example, it may be... Figure 2At least part of an implementation of the logic simulation 210 in the above, therefore, for Figures 1-5 The various aspects described herein are applicable to method 600 and will not be elaborated further. The general-purpose processor 14 may receive, for example, a netlist file describing the logic circuitry via wired, wireless, or storage medium access. The netlist file includes various data describing the logic gates, raw inputs and outputs, and connections between components. Although method 600 is implemented herein using a general-purpose processor, this is merely illustrative and not a limitation of the disclosure. In some embodiments, at least a portion or all of method 600 may be executed by an accelerator.

[0058] In 602, the CPU constructs a circuit interconnection matrix based on netlist data and hierarchically classifies the circuits. In one embodiment, the netlist file may be, for example, a gate-level circuit netlist file. Specifically, the CPU can classify logic circuits according to... Figure 4 The method shown constructs a circuit interconnect matrix based on netlist data and hierarchically classifies the logic circuits.

[0059] At 604, the CPU transfers hierarchical data to the GPU. For example, the CPU can transfer the interconnect matrix and hierarchical data to memory in the GPU. Although the interconnect matrix and hierarchical data are shown separately herein, this is merely illustrative and not intended to limit the scope of this disclosure. In other embodiments, the interconnect matrix may be incorporated into the hierarchical data.

[0060] In 606, the CPU sets time frame 0 as the current frame. Because the logic gates in a logic simulation are interdependent, time frames can be used to calculate the output of each logic gate frame by frame to ensure correct simulation. At the start of the simulation, the CPU can set time frame 0 as the current time frame.

[0061] At 608, the CPU obtains initial values ​​for the current time frame based on the test vector and transmits them to the GPU. In one embodiment, the test vector may include test stimulus values ​​provided to the various raw inputs of the logic circuit. It is understood that the test stimulus values ​​received by the same raw input may be the same or different in different time frames. The test vector therefore includes initial values ​​for the raw inputs in different time frames. In some embodiments, since the test vector may have a high data volume, only the initial values ​​of the raw inputs of the test vector for the current time frame may be provided to the GPU. In other embodiments, if the GPU has sufficient memory, the initial values ​​of the raw inputs for all time frames or a subset of time frames may also be provided to the GPU. This disclosure does not limit this.

[0062] At 610, the CPU copies the flag bit array to the GPU. In some embodiments, the flag bit array may include a hierarchical flag bit array and a logic gate flag bit array, wherein the hierarchical flag bit array is used to indicate whether each corresponding level circuit needs to be computed in a time frame, and the logic gate flag bit array is used to indicate whether each corresponding logic gate needs to be computed in a time frame. In cases where computation is not required, the output of the previous time frame can be used as the output of the current time frame. This reduces the GPU's computation time and power consumption. It is understood that in some embodiments, the flag bit array is not mandatory, and the GPU can perform computations for each level circuit and logic gate in each time frame; this disclosure does not impose any limitations on this.

[0063] At 612, the CPU invokes the GPU to simulate the current time frame. The GPU's logic simulation will be described in detail below. At 614, the CPU receives the final values ​​of the logic gates in the current time frame from the GPU. After receiving the final values ​​of the logic gates for all time frames, the CPU can obtain a logic simulation output set. The logic simulation output set may include at least some or all of the final values ​​of the logic gates in all time frames. In some embodiments, the CPU may output the logic simulation output set to an external device, such as a display or memory.

[0064] At step 616, the CPU determines if the current time frame is the last time frame. If it is, it proceeds to step 620 to end the logic simulation. If it is not the last time frame, it proceeds to step 618. At step 618, the CPU sets the next time frame as the current time frame and loops through steps 608-616 until it reaches the last time frame and ends the logic simulation.

[0065] While an exemplary process executed by a CPU is shown herein, it is merely illustrative and not intended to limit the scope of this disclosure. In some embodiments, method 600 may also include other steps or may not have... Figure 6 Part of the steps shown, such as 610.

[0066] Figure 7 A schematic flowchart of a logic simulation method 700 according to some embodiments of the present disclosure is shown. In one embodiment, method 700 may be executed by an accelerator such as a GPU for logic simulation, for example, it may be... Figure 2 At least part of an implementation of the logic simulation 210 in the above, therefore, for Figures 1-5The various aspects described herein can be applied to method 700 and will not be repeated here. Although method 700 is described below using a GPU as the execution entity, this is merely illustrative and not intended to limit the scope of this disclosure. In other embodiments, method 700 may be executed using an accelerator such as an FPGA.

[0067] In 702, the GPU receives hierarchical data of the logic circuit. This hierarchical data represents multiple levels of the logic circuit. These multiple levels are based on the connection relationships between multiple logic gates within the logic circuit, for example... Figure 4 As shown. In one embodiment, the raw inputs, raw outputs, and sequential logic gates are classified into a first-level circuit, i.e., level 0 circuit, while the combinational logic gates are classified into a second-level circuit. Further, the combinational logic gates can be further divided into first sub-level circuits, second sub-level circuits, and so on, based on their connection relationships. Although one hierarchical approach is shown herein, it is merely illustrative and not intended to limit the scope of this disclosure. In other embodiments, the raw inputs, raw outputs, and sequential logic gates can be classified into different levels of circuits based on their respective connection relationships. Furthermore, the second-level circuit, including combinational logic gates, can also be divided into different sub-level circuits. This disclosure does not impose any limitations on this.

[0068] In 704, the GPU generates a logic simulation output set based on hierarchical data and a test vector set for the logic circuit, as described in detail below. Generating the logic simulation output set involves parallel computation of the logic output values ​​of multiple logic gates located in the same level of the circuit within the same time frame, with the logic output values ​​of the multiple logic gates associated with the logic simulation output set. For example, the GPU can use its three processing engines or threads to compute these values ​​in parallel. Figure 4 The logic outputs of AND gate 31, first buffer 33, and inverter 32 in the first-level circuit of the simulation occur within the same time frame. The outputs of these three logic gates in this time frame may further affect subsequent level circuits, such as the output of second buffer 34, and will affect the logic outputs of subsequent time frames. Therefore, the logic output values ​​of these three logic gates actually affect the final logic simulation output set. In other words, the logic simulation output set depends at least in part on the logic outputs of these three logic gates in this time frame.

[0069] Figure 8 A schematic diagram of a simulation process 800 executed by a graphics processor according to some embodiments of the present disclosure is shown. In one embodiment, process 800 may be at least a portion of 704, for example. Therefore, process 800 may be executed by an accelerator such as a GPU for logic simulation, for example, it may be... Figure 2 At least part of an implementation of the logic simulation 210 in the above, therefore, for Figures 1-5 and Figure 7 The aforementioned aspects are applicable to process 800 and will not be elaborated upon here.

[0070] In step 802, the GPU calls procedure 900 to calculate the values ​​of combinational logic gates in the circuit. See, for example... Figure 4 Within a single time frame, after receiving the raw input at level 0, the GPU can compute the output logic values ​​of the subsequent level 1 and level 2 combinational logic gates. See below for the detailed computation process. Figure 9 Description. This step can be omitted if there are no combinational logic gates in the logic circuit.

[0071] In step 804, how does the GPU determine whether the next stage of computation is needed? (See, for example...) Figure 5 After calculating the logic output of the second buffer 34 in the second level of frame 0, the GPU determines whether the next level needs to be calculated. For example, if the GPU determines that the sequential logic gates in the level 0 circuit of the following frame 1 need to be calculated, it proceeds to 806. If no calculation is required, for example, by checking the flag array or reaching the last level of the time frame, the output of the combinational logic is returned to the CPU.

[0072] In step 806, the GPU calls procedure 1000 to calculate the values ​​of sequential logic gates in the circuit. As mentioned above, since sequential logic gates and combinational logic gates are hierarchically classified at different levels, it is necessary to calculate the logic outputs of the sequential logic gates here. In one embodiment, this can be achieved using... Figure 10 The process shown in step 1000 is used to calculate the logic output of a sequential logic gate. This step can be omitted if no sequential logic gate exists in the logic circuit.

[0073] At step 808, the GPU determines if the loop count has exceeded the limit. In some cases, the computation of sequential logic may exceed the loop count limit, resulting in an inability to obtain a correct or definite logic output. Therefore, in some embodiments, constraints can be placed on the number of computations of sequential logic gates in logic simulation. When the threshold number is exceeded, it indicates that there may be an error in the computation of the sequential logic gate. In this case, the process can proceed to step 810, where the GPU reports an error. For example, the GPU can send the error message to the CPU, and the CPU can display the error message on the screen or log it to the simulation log. If the threshold number is not exceeded, the GPU returns to step 802 to calculate the logic output value of the next-level combinational logic gate. At step 812, the GPU returns the calculated logic output to the CPU. In some embodiments, steps 800 may not include steps 808 and 810, for example, in cases where the logic circuit does not have sequential logic gates or other situations where error reporting is not required.

[0074] Figure 9 Some embodiments according to this disclosure are shown. Figure 8A schematic diagram of the combinational logic computation process 900 in the diagram. In one embodiment, process 900 may be at least a part of 802, for example. Therefore, process 900 can be executed by an accelerator such as a GPU for logic simulation, for example, it may be... Figure 2 At least part of an implementation of the logic simulation 210 in the above, therefore, for Figures 1-5 and Figures 7-8 The aforementioned aspects are applicable to process 900 and will not be elaborated upon here.

[0075] In 902, the GPU sets the combinational logic leader to the current level. For example, the GPU will... Figure 4 Level 1 is set as the current level. At 904, the GPU determines whether the current level needs computation. In one embodiment, the GPU can determine whether the current level needs computation by determining the hierarchical flag corresponding to the current level. If the hierarchical flag is a first value, it indicates that the input set of the hierarchical circuit in this time frame is at least partially different from the input set of the hierarchical circuit in the previous time frame. Due to the different inputs, the output set of the hierarchical circuit may also be at least partially different from the output set of the previous frame. In this case, the GPU can determine that the current level needs computation. If the hierarchical flag is a second value different from the first value, the GPU can determine that the current level does not need computation. In one embodiment, the GPU can use the output set of the current level in the previous frame as the output set of the current frame and proceed to 908, thereby saving computational resources and computation time. Although the hierarchical flag is used herein to determine whether computation is needed, this is merely illustrative and not intended to limit the scope of this disclosure. Alternatively, recomputation can be determined based on whether the various logical inputs received by the current level in the current frame have changed compared to the various logical inputs in the previous frame. If at least a portion of the input changes, it can be determined that the current level needs to be recalculated.

[0076] Furthermore, in some embodiments, even if the GPU determines that the current level needs to be computed, further computational judgments can be made for each logic gate in the current level. Similar to hierarchical circuits, the GPU can store an array of logic gate identifier bits corresponding to each logic gate in each level. By consulting the relevant values ​​in the logic gate identifier bit array, it can be determined whether each logic gate needs to be computed in the current time frame. In one embodiment, if the logic gate identifier bit corresponding to a logic gate is a first value, it indicates that the input set of the logic gate in the current time frame is at least partially different from the input set of the logic gate in the previous time frame. Since the inputs are different, the output set of the logic gate may also be at least partially different from the output set of the previous frame. In this case, the GPU can determine that the logic gate needs to be computed. If the logic gate identifier bit is a second value different from the first value, the GPU can determine that the logic gate does not need to be computed. In one embodiment, the GPU can use the output set of the logic gate in the previous frame as the output set of the logic gate in the current frame and proceed to 908, thereby saving computational resources and computation time. While logic gate flags are used herein to determine whether computation is required, this is merely illustrative and not intended to limit the scope of this disclosure. Alternatively, recomputation may be determined based on whether the logic inputs received by the current stage in the current frame have changed compared to the logic inputs in the previous frame. If at least a portion of all inputs have changed, it can be determined that the logic gate needs to be recomputed.

[0077] It is understood that although the above illustration uses hierarchical flags and logic gate flags, this is merely illustrative and not intended to limit the scope of this disclosure. In some embodiments, the GPU may perform the computation directly without determining whether computation is required, for example, when the time to look up the flags exceeds the time required to compute the logic gates themselves.

[0078] In step 906, when it is determined that the logical output of a logic gate needs to be calculated, the GPU calculates the value of the logic gate handled by the current thread and updates the flag array. In one embodiment, for example, when the logical output of a logic gate is completed, if the logical output of that logic gate is different from the logical output in the previous time frame, this indicates that the value of the logic gate has changed, and the flag array needs to be updated. First, the flag corresponding to that logic gate is set to a second value, indicating that the gate has been calculated. Then, the flag positions corresponding to all logic gates in the direct fan-out region (i.e., directly driven by that logic gate) are set to a first value, indicating that they need to be calculated. In addition, the GPU also sets the hierarchical flag positions of the logic gates in the direct fan-out region to a first value, indicating that these hierarchical circuits need to be calculated in the next round. The operation on the flags here does not require atomic operations. Furthermore, in some embodiments, such as when there are no flags, it is not necessary to update the flag array.

[0079] At 908, the GPU waits for all GPU threads to reach this point. Different threads within the GPU can execute simulation calculations of different combinational logic gates within the same level in the same timeframe in parallel. To avoid logic errors, the GPU can wait at 908 for all combinational logic gates in the same level to complete their logic calculations before proceeding to 910. At 910, the GPU determines whether the current level is the last level of combinational logic gates. If it is not the last level of combinational logic gates, for example, in... Figure 4 If there is a second level after level 1, it indicates that there are other levels of combinational logic gates that have not yet been computed. Therefore, at 912, the GPU sets the next level as the current level and repeats 904-910. If it is the last level of logic gate, the GPU returns to 914. Figure 8 804 in the figure. Although one calculation process for a combinational logic gate is shown herein, it is merely illustrative and not intended to limit the scope of this disclosure. In other embodiments, some steps in process 900 may be omitted, for example, updating the flag bit array may be omitted. Furthermore, process 900 may also have other steps not shown in the figures, which are not limiting in this disclosure.

[0080] Figure 10 Some embodiments according to this disclosure are shown. Figure 8 A schematic diagram of a sequential logic computation process 1000 in the process described above. In one embodiment, process 1000 may be at least a portion of 806, for example. Therefore, process 1000 can be executed by an accelerator such as a GPU for logic simulation, for example, it may be... Figure 2 At least part of an implementation of the logic simulation 210 in the above, therefore, for Figures 1-5 and Figures 7-9 The aforementioned aspects are applicable to process 1000 and will not be elaborated upon here.

[0081] In step 1002, the GPU sets the level of the sequential logic gate to the current level. For example, the GPU will... Figure 5 In frame 1, level 0 is set as the current level. In step 1004, the GPU determines whether computation is required at the current level. In one embodiment, the GPU can determine this by determining the level flag corresponding to the current level. If the level flag is a first value, it indicates that the combination of factors for the hierarchical circuit in this time frame is at least partially different from the same combination in a previous time frame. Since the output of a sequential logic gate depends not only on its input but also on its output, clock signal, and control signals in the previous time frame, the combination of factors is used here to include the input set from the original input or the previous level driver, the output set of the sequential logic gate in the previous frame, the clock signal, and the control signals.

[0082] Because the combination of factors differs, the output set of this level of circuit may also differ at least partially from the output set of the previous frame. In this case, the GPU can determine that the current level needs to be computed. If the level flag is a second value different from the first value, the GPU can determine that the current level does not need to be computed. In one embodiment, the GPU can use the output set of the current level in the previous frame as the output set of the current frame and proceed to 1008, thereby saving computational resources and computation time. Although the level flag is used herein to determine whether computation is required, this is merely illustrative and not intended to limit the scope of this disclosure. Alternatively, recomputation can be determined based on whether the combination of factors in the current level in the current frame has changed compared to the combination of factors in the previous frame. When at least a portion of all inputs has changed, it can be determined that the current level needs to be recomputed.

[0083] Furthermore, in some embodiments, even if the GPU determines that the current level needs to be computed, further computational judgments can be made for each logic gate in the current level. Similar to hierarchical circuits, the GPU can store an array of logic gate identifier bits corresponding to each logic gate in each level. By consulting the relevant values ​​in the logic gate identifier bit array, it can be determined whether each logic gate needs to be computed in the current time frame. In one embodiment, if the logic gate identifier bit corresponding to a logic gate is a first value, it indicates that the input set of the logic gate in the current time frame is at least partially different from the input set of the logic gate in the previous time frame. Since the inputs are different, the output set of the logic gate may also be at least partially different from the output set of the previous frame. In this case, the GPU can determine that the logic gate needs to be computed. If the logic gate identifier bit is a second value different from the first value, the GPU can determine that the logic gate does not need to be computed. In one embodiment, the GPU can use the output set of the logic gate in the previous frame as the output set of the logic gate in the current frame and proceed to 1008, thereby saving computational resources and computation time. While logic gate flags are used herein to determine whether computation is required, this is merely illustrative and not intended to limit the scope of this disclosure. Alternatively, recomputation may be determined based on whether the logic inputs received by the current stage in the current frame have changed compared to the logic inputs in the previous frame. If at least a portion of all inputs have changed, it can be determined that the logic gate needs to be recomputed.

[0084] It is understood that although the above illustration uses hierarchical flags and logic gate flags, this is merely illustrative and not intended to limit the scope of this disclosure. In some embodiments, the GPU may perform the computation directly without determining whether computation is required, for example, when the time to look up the flags exceeds the time required to compute the logic gates themselves.

[0085] In step 1006, the GPU calculates the value of the logic gate currently handled by the thread and updates the flag array. When it is determined that the logic output of a logic gate needs to be calculated, the GPU calculates the value of the logic gate currently handled by the thread and updates the flag array. In one embodiment, for example, when the logic output of a logic gate is completed, if the logic output of that logic gate is different from the logic output in the previous time frame, this indicates that the value of the logic gate has changed, and the flag array needs to be updated. First, the flag bit corresponding to the logic gate is set to the second value, indicating that the gate has been calculated. Then, the flag bits corresponding to all logic gates in the direct fan-out region (i.e., directly driven by the logic gate) of that logic gate are set to the first value, indicating that they need to be calculated. In addition, the GPU also sets the hierarchical flag bits of the logic gates in the direct fan-out region to the first value, indicating that these hierarchical circuits need to be calculated in the next round. The operation on the flag bits here does not require atomic operations. Furthermore, in some embodiments, such as when there are no flag bits, it is not necessary to update the flag array.

[0086] At step 1008, the GPU waits for all GPU threads to execute to this point. Different threads in the GPU can execute simulation calculations of different sequential logic gates in the same level within the same time frame in parallel. To avoid logic errors, the GPU can wait at step 1008 for the logic calculations of all sequential logic gates in the same level to complete before proceeding to step 1010. At step 1010, the GPU returns to step 808 or 802. In the case where sequential logic gates are divided into multiple levels, the GPU can also determine whether the current level is the last level of sequential logic gates. If it is not the last level of sequential logic gates, it indicates that there are other levels of sequential logic gates that have not been calculated. Therefore, the GPU sets the next level as the current level and repeats steps 1002-1008. Although one calculation process for sequential logic gates is shown herein, it is merely illustrative and not intended to limit the scope of this disclosure. In other embodiments, some steps in process 1000 may be omitted, for example, updating the flag bit array may not be necessary. Furthermore, process 1000 may also have other steps not shown in the figures, which are not limiting in this disclosure.

[0087] Figure 11 Schematic block diagrams illustrating some examples of logic simulations according to some embodiments of the present disclosure are shown. Figure 11As shown, the test vector set can include p test vectors, where p is an integer greater than 1. Test vector 1 has r time frames, test vector 2 has s time frames, and test vector p has t time frames, where r, s, and t are all integers greater than 0 and can be the same or different from each other. In one embodiment, when the number of logic gates in the logic circuit is large (e.g., the number of logic gates is greater than a threshold number), a "logic gate parallelism" approach can be used to allocate different logic gates to different threads of the GPU for computation. However, in this case, it is serial for the test vectors. That is, after performing parallel logic simulation of multiple logic gates for one test vector, parallel logic simulation of multiple logic gates is performed for the next test vector, until logic simulation is completed for all test vectors in the test vector set.

[0088] Although parallel logic simulation is illustrated herein with test vectors presented serially, this is merely illustrative and not intended to limit the scope of this disclosure. Parallel logic simulation can also be performed with test vectors in parallel. For example, in some cases, for the logic simulation of a logic circuit, the test vector set can have multiple test vectors, each of which can have multiple time frames, and the number of time frames for the test vectors in the test vector set can be the same or different. For example, the test vector set can include a first test vector and a second test vector, and the logic simulation output set can include a first output subset and a second output subset. Generating the logic simulation output set further includes generating a first output subset based on hierarchical data and the first test vector; and generating a second output subset based on hierarchical data and the second test vector. The generation of the first output subset and the generation of the second output subset are performed in parallel.

[0089] For example, Figure 12Schematic block diagrams illustrating some examples of logic simulation according to other embodiments of this disclosure are shown. If the number of logic gates in the logic circuit is large (e.g., above a first threshold number) and the number of test vectors included in the test vector set is also large (e.g., above a second threshold number), threads in the GPU can be divided into multiple uniform thread blocks, each containing multiple threads, each thread block responsible for computing one test vector. Thread blocks for different test vectors run in parallel; for example, each thread block processes the logic simulation for a corresponding test vector in parallel. For the same test vector, the logic simulation of multiple logic gates within a thread block by multiple threads is also executed in parallel. For example, based on hierarchical data and a first test vector, a first plurality of outputs of multiple logic gates located in the same level of the circuit in the same time frame are computed in parallel, the first plurality of outputs being associated with a first subset of outputs. In other words, the logic simulation output set including the first subset of outputs may depend on the first plurality of outputs. This can further reduce the time of logic simulation. Although parallel logic simulation is shown herein in a test vector parallel manner, this is merely illustrative and not intended to limit the scope of this disclosure. Alternatively, when the number of logic gates in the logic circuit is less than a first threshold, but the number of test vectors in the test vector set is greater than a second threshold, a "test vector parallel" approach can be used for logic simulation. That is, the GPU uses multiple GPU threads to simulate each test vector in parallel, with each thread responsible for simulating one test vector.

[0090] While examples of using multiple test vectors for serial and parallel simulations have been shown above, these are merely examples and not intended to limit the scope of this disclosure. In some embodiments, multiple test vectors can be used for hybrid simulations. That is, for a subset of the test vectors, the above methods can be used. Figure 12 The parallel logic simulation is illustrated. However, after some GPU threads have completed the parallel simulation, the remaining test vectors can be used to continue the logic simulation. Alternatively, some test vectors can be used for serial logic simulation first, followed by parallel logic simulation. In yet other embodiments, test vectors can also be used for logic simulation in a serial-then-parallel-then-serial manner. This disclosure does not limit the specific hybrid approach. The simulation time can be dynamically adjusted based on factors such as the number of test vectors, the number of threads in the GPU, and processing power to minimize the logic simulation time.

[0091] Figure 13 A schematic block diagram of an electronic device 1300 according to some embodiments of the present disclosure is shown. The electronic device 1300 may include multiple modules for performing, for example... Figures 6-12 The corresponding steps in the methods discussed herein. For example... Figure 13As shown, in one embodiment, the electronic device 1300 includes a receiving unit 1302 and a generating unit 1304. The receiving unit 1302 receives hierarchical data of a logic circuit, representing multiple levels of the logic circuit, which are divided based on the connection relationships of multiple logic gates within the logic circuit. The generating unit 1304 generates a logic simulation output set based on the hierarchical data and a test vector set for the logic circuit. Generating the logic simulation output set involves parallel computation of the logic output values ​​of multiple logic gates located in the same level of the circuit within the same time frame, with the logic output values ​​of the multiple logic gates associated with the logic simulation output set. By using an accelerator such as a GPU to parallel compute the outputs of multiple logic gates within the same time frame, processing time can be significantly reduced compared to the conventional serial computation of a CPU. Furthermore, by hierarchically processing the logic simulation circuit, the correctness of the logic simulation can be ensured because the multiple logic gates processed in parallel are located in the same level of the circuit and are not causally related to each other in terms of the logic simulation results.

[0092] In one embodiment, the test vector set includes a first test vector and a second test vector, and the logic simulation output set includes a first output subset and a second output subset. The generation unit 1304 is further configured to generate a first output subset based on the hierarchical data and the first test vector; and to generate a second output subset based on the hierarchical data and the second test vector. The generation of the first output subset and the generation of the second output subset are performed in parallel. In addition to performing parallel computation on multiple logic gates within the same level in the same time frame, the logic simulation time can be further reduced by performing parallel logic simulation on multiple test vectors.

[0093] In one embodiment, the generation unit 1304 is further configured to: compute, in parallel, a first plurality of outputs of multiple logic gates located in the same level circuit within the same time frame, based on hierarchical data and a first test vector, wherein the first plurality of outputs are associated with a first subset of outputs. In addition to performing parallel computation on multiple logic gates within the same level within the same time frame, the logic simulation time can be further reduced by also performing parallel logic simulation on multiple test vectors.

[0094] In one embodiment, the generation unit 1304 is further configured to: determine whether a first-level circuit in the logic circuit will be computed in a first time frame; if it is determined that the first-level circuit will be computed, compute a first output set of the first-level circuit, with the logic simulation output set associated with the first output set; and if it is determined that the first-level circuit will not be computed, use the output set of the first-level circuit in a time frame preceding the first time frame as the first output set of the first-level circuit in the first time frame. By determining whether the hierarchical circuit in the logic circuit needs to be computed in some time frames, the computation time of the logic gates of the entire hierarchical circuit can be omitted when computation is not required, thereby further reducing the total time of logic simulation and reducing the consumption of computing resources so that limited computing resources can be used to process other logic gates that need to be computed. This further reduces the total time of logic simulation.

[0095] In one embodiment, the generation unit 1304 is further configured to determine whether the value of a first hierarchical flag bit corresponding to the first hierarchical circuit in the first time frame is a first value, wherein the first value of the first hierarchical flag bit indicates that the input set of the first hierarchical circuit in the first time frame is at least partially different from the input set of the first hierarchical circuit in a previous time frame; and to determine whether all inputs or combinations of factors of the first hierarchical circuit in the first time frame have changed compared to all inputs or combinations of factors of the first hierarchical circuit in a previous time frame. By using the flag bit, it is possible to simply and effectively determine whether logic gates in the hierarchical circuit need to be computed. Due to the simplicity and effectiveness of the flag bit determination method, the time required to determine whether logic circuits need to be computed can also be reduced. This further reduces the total time of logic simulation.

[0096] In one embodiment, the generation unit 1304 is further configured to determine whether a first logic gate in the first-level circuit will be computed in a first time frame; if it is determined that the first logic gate will be computed, then the first output of the first logic gate is computed; and if it is determined that the first logic gate will not be computed, then the output of the first logic gate in the previous time frame is used as the first output of the first logic gate in the first time frame, and the logic simulation output set is associated with the first output. By determining whether some logic gates in the logic circuit need to be computed in some time frames, the computation time of these logic gates can be omitted when they do not need to be computed, thereby further reducing the total time of logic simulation and also reducing the consumption of computing resources so that limited computing resources can be used to process other logic gates that need to be computed. This further reduces the total time of logic simulation.

[0097] In one embodiment, the generation unit 1304 is further configured to determine whether all inputs of the first logic gate in the first time frame have changed compared to all inputs of the first logic gate in a previous time frame, including: determining whether the value of the first logic gate identifier bit corresponding to the first logic gate in the first time frame is a first value, wherein the first value of the first logic gate identifier bit indicates that the inputs of the first logic gate in the first time frame are at least partially different from the inputs of the first logic gate in a previous time frame; and determining whether all inputs or combinations of factors of the first logic gate in the first time frame have changed compared to all inputs or combinations of factors of the first logic gate in a previous time frame. By using the identifier bit, it is possible to simply and effectively determine whether logic gates in a hierarchical circuit need to be computed. Due to the simplicity and effectiveness of the identifier bit determination method, the time required to determine whether logic circuits need to be computed can also be reduced. This further reduces the total time of logic simulation.

[0098] In one embodiment, based on hierarchical data and a test vector set for the logic circuit, the generation unit 1304 is further configured to: sequentially calculate the output of each level of the circuit frame by frame; and generate a logic simulation output set based on the output of each level of the circuit in the last time frame. By calculating the logic output of each level frame by frame, the accuracy of the causality of logical operations in the logic simulation can be ensured, thereby improving the accuracy of the logic simulation.

[0099] In one embodiment, the generation unit 1304 is further configured to determine whether the number of calculations of the output of the hierarchical circuit including sequential logic gates in a time frame exceeds a threshold number; if the number of calculations of the output of the hierarchical circuit including sequential logic gates in a time frame exceeds the threshold number, a fault indication is generated, indicating that a logic simulation failure has occurred. By setting a loop threshold number, it is possible to avoid the logic simulation from getting stuck in an erroneous loop or an infinite loop targeting sequential logic gates, and to report logic simulation errors in a timely manner, thereby reducing the logic simulation time.

[0100] Figure 14A schematic block diagram of an example device 1400 that can be used to implement embodiments of the present disclosure is shown. Device 1400 can be used to implement electronic device 10 or 1300. As shown, device 1400 includes a computing unit 1401, which can perform various appropriate actions and processes according to computer program instructions stored in random access memory (RAM) 1403 and / or read-only memory (ROM) 1402, or computer program instructions loaded from storage unit 1408 into RAM 1403 and / or ROM 1402. Various programs and data required for the operation of device 1400 may also be stored in RAM 1403 and / or ROM 1402. The computing unit 1401 and RAM 1403 and / or ROM 1402 are interconnected to each other via bus 1404. Input / output (I / O) interface 1405 is also connected to bus 1404.

[0101] Multiple components in device 1400 are connected to I / O interface 1405, including: input unit 1406, such as a keyboard, mouse, etc.; output unit 1407, such as various types of displays, speakers, etc.; storage unit 1408, such as a disk, optical disk, etc.; and communication unit 1409, such as a network card, modem, wireless transceiver, etc. Communication unit 1409 allows device 1400 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0102] The computing unit 1401 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 1401 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 1401 performs the various methods and processes described above, such as methods 600, 700, 800, 900, and / or 1000. For example, in some embodiments, methods 600, 700, 800, 900, and / or 1000 may be implemented as computer software programs tangibly contained in a machine-readable medium, such as storage unit 1408. In some embodiments, part or all of the computer program may be loaded and / or installed on device 1400 via RAM and / or ROM and / or communication unit 1409. When a computer program is loaded into RAM and / or ROM and executed by computing unit 1401, one or more steps of methods 600, 700, 800, 900, and / or 1000 described above can be performed. Alternatively, in other embodiments, computing unit 1401 can be configured to perform methods 600, 700, 800, 900, and / or 1000 by any other suitable means (e.g., by means of firmware).

[0103] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0104] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0105] Furthermore, although the operations are depicted in a specific order, this should be understood as requiring that such operations be performed in the specific order shown or in sequential order, or requiring that all illustrated operations be performed to achieve the desired result. In certain environments, multitasking and parallel processing may be advantageous. Similarly, although several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented individually or in any suitable sub-combination in multiple implementations.

[0106] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

Claims

1. A method for logic simulation, characterized in that, The method includes: Receive hierarchical data of a logic circuit, wherein the hierarchical data represents multiple levels of the logic circuit, and the multiple levels of the logic circuit are divided based on the connection relationships of multiple logic gates in the logic circuit; and Based on the hierarchical data and the test vector set for the logic circuit, a logic simulation output set is generated. Generating the logic simulation output set includes parallel computation of the logic output values ​​of multiple logic gates located in the same level circuit within the same time frame, and the logic output values ​​of the multiple logic gates are associated with the logic simulation output set.

2. The method according to claim 1, characterized in that, The test vector set includes a first test vector and a second test vector, and the logic simulation output set includes a first output subset and a second output subset. Generating the logic simulation output set further includes: A first output subset is generated based on the hierarchical data and the first test vector; A second output subset is generated based on the hierarchical data and the second test vector. The generation of the first output subset and the generation of the second output subset are performed in parallel.

3. The method according to claim 2, characterized in that, Generating the first output subset includes: Based on the hierarchical data and the first test vector, the first plurality of outputs of multiple logic gates located in the same level circuit in the same time frame are computed in parallel, and the first plurality of outputs are associated with the first subset of outputs.

4. The method according to any one of claims 1-3, characterized in that, The generated logic simulation output set also includes: Determine whether the first-level circuit in the logic circuit will be computed in the first time frame; If it is determined that the first-level circuit will be computed, then the first output set of the first-level circuit is computed, and the logic simulation output set is associated with the first output set; and If it is determined that the first-level circuit will not be computed, then the output set of the first-level circuit in the time frame preceding the first time frame is used as the first output set of the first-level circuit in the first time frame.

5. The method according to claim 4, characterized in that, Determining whether the first-level circuit in the logic circuit will be computed in the first time frame includes at least one of the following: Determine whether the value of the first hierarchical identifier corresponding to the first hierarchical circuit in the first time frame is a first value. The first value of the first hierarchical identifier indicates that the input set of the first hierarchical circuit in the first time frame is at least partially different from the input set of the first hierarchical circuit in the time frame preceding the first time frame. as well as Determine whether the combination of all inputs or factors of the first-level circuit in the first time frame has changed compared to the combination of all inputs or factors of the first-level circuit in the previous time frame. The combination of factors of the first-level circuit includes the inputs, clock signals, control signals, and outputs of the sequential logic gates in the first-level circuit in the first time frame and in the previous time frame.

6. The method according to claim 4, characterized in that, Calculating the first output set of the first-level circuit includes: Determine whether the first logic gate in the first level circuit will be computed in the first time frame; If it is determined that the first logic gate will be computed, then the first output of the first logic gate is computed; and If it is determined that the first logic gate will not be computed, then the output of the first logic gate in the time frame preceding the first time frame is used as the first output of the first logic gate in the first time frame, and the logic simulation output set is associated with the first output.

7. The method according to claim 6, characterized in that, Determining whether a first logic gate in the first-level circuit will be computed in the first time frame includes at least one of the following: Determining whether all inputs of the first logic gate in the first time frame have changed compared to all inputs of the first logic gate in a time frame preceding the first time frame includes: determining whether the value of the first logic gate identifier corresponding to the first logic gate in the first time frame is a first value, wherein the first value of the first logic gate identifier indicates that the input of the first logic gate in the first time frame is at least partially different from the input of the first logic gate in a time frame preceding the first time frame; and Determine whether the total number of inputs or factor combinations of the first logic gate in the first time frame has changed compared to the total number of inputs or factor combinations of the first logic gate in the previous time frame. The factor combinations of the first logic gate include the inputs, clock signals, control signals, and outputs of the sequential logic gate in the first time frame and the previous time frame.

8. The method according to any one of claims 1-3, characterized in that, Based on the hierarchical data and the test vector set for the logic circuit, generating the logic simulation output set further includes: The output of each circuit level is calculated frame by frame according to the time frame; and The logic simulation output set is generated based on the outputs of each level of circuit in the last time frame.

9. The method according to claim 8, characterized in that, The output of each circuit level is calculated frame by frame, including: Determine whether the number of computations performed on the output of a hierarchical circuit, including sequential logic gates, within a time frame exceeds a threshold number; If the number of calculations of the output of the hierarchical circuit including sequential logic gates in a time frame exceeds the threshold number, a fault indication is generated, indicating that the logic simulation has failed.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a plurality of programs configured to be executed by one or more processors, the plurality of programs including instructions for performing the method of any one of claims 1-9.

11. A computer program product, characterized in that, The computer program product includes a plurality of programs configured to be executed by one or more processors, the plurality of programs including instructions for performing the method of any one of claims 1-9.

12. An electronic device, characterized in that, The electronic device includes: One or more processors; The electronic device includes a memory containing computer instructions that, when executed by the one or more processors of the electronic device, cause the electronic device to perform the method of any one of claims 1-9.

13. An electronic device, characterized in that, The electronic device includes: A receiving unit is configured to receive hierarchical data of a logic circuit, wherein the hierarchical data represents multiple levels of the logic circuit, and the multiple levels of the logic circuit are divided based on the connection relationships of multiple logic gates in the logic circuit; and A generation unit is configured to generate a logic simulation output set based on the hierarchical data and a test vector set for the logic circuit, wherein generating the logic simulation output set includes parallel computation of the logic output values ​​of multiple logic gates located in the same level circuit within the same time frame, and the logic output values ​​of the multiple logic gates are associated with the logic simulation output set.

14. The electronic device according to claim 13, characterized in that, The test vector set includes a first test vector and a second test vector, and the logic simulation output set includes a first output subset and a second output subset. The generation unit is further configured to: A first output subset is generated based on the hierarchical data and the first test vector; A second output subset is generated based on the hierarchical data and the second test vector. The generation of the first output subset and the generation of the second output subset are performed in parallel.

15. The electronic device according to claim 14, characterized in that, The generation unit is also used for: Based on the hierarchical data and the first test vector, the first plurality of outputs of multiple logic gates located in the same level circuit in the same time frame are computed in parallel, and the first plurality of outputs are associated with the first subset of outputs.

16. The electronic device according to any one of claims 13-15, characterized in that, The generation unit is also used for: Determine whether the first-level circuit in the logic circuit will be computed in the first time frame; If it is determined that the first-level circuit will be computed, then the first output set of the first-level circuit is computed, and the logic simulation output set is associated with the first output set; as well as If it is determined that the first-level circuit will not be computed, then the output set of the first-level circuit in the time frame preceding the first time frame is used as the first output set of the first-level circuit in the first time frame.

17. The electronic device according to claim 16, characterized in that, The generation unit is also used for: Determine whether the first logic gate in the first level circuit will be computed in the first time frame; If it is determined that the first logic gate will be computed, then the first output of the first logic gate is computed; as well as If it is determined that the first logic gate will not be computed, then the output of the first logic gate in the time frame preceding the first time frame is used as the first output of the first logic gate in the first time frame, and the logic simulation output set is associated with the first output.

18. The electronic device according to any one of claims 13-15, characterized in that, Based on the hierarchical data and the test vector set for the logic circuit, the generation unit is further configured to: The output of each circuit level is calculated frame by frame according to the time frame; and The logic simulation output set is generated based on the outputs of each level of circuit in the last time frame.

19. The electronic device according to claim 18, characterized in that, The generation unit is also used for: Determine whether the number of computations performed on the output of a hierarchical circuit, including sequential logic gates, within a time frame exceeds a threshold number; If the number of calculations of the output of the hierarchical circuit including sequential logic gates in a time frame exceeds the threshold number, a fault indication is generated, indicating that the logic simulation has failed.

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