Test circuit, test method and test device

Abstract

This disclosure provides a test circuit, test method, and test equipment, relating to the field of semiconductor technology. The test circuit includes a ring oscillator circuit and several test units. The ring oscillator circuit includes multiple logic gate units cascaded sequentially to form a ring loop. Each test unit includes a first transistor, a second transistor, a first delay circuit, and a second delay circuit. The input terminals of the first and second delay circuits are connected to the input terminals of the corresponding logic gate units of the test unit. The duration of the effective level of the first delay circuit is longer than the duration of the effective level of the second delay circuit. The gate of the first transistor is connected to the output terminal of the first delay circuit, its source is connected to the first test terminal, and its drain is connected to the drain of the second transistor. The gate of the second transistor is connected to the output terminal of the second delay circuit, and its source is connected to the second test terminal. This disclosure can accurately measure the drive current of the transistors in the test unit.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a test circuit, test method and test equipment. Background Technology

[0002] Metal-oxide-semiconductor field-effect transistors (MOS) are widely used in the semiconductor technology field. Based on the different types of charge carriers, MOS is divided into PMOS and NMOS. Among them, the inverter is a complementary metal-oxide-semiconductor (CMOS) logic gate with an inverting function.

[0003] In existing CMOS technology, to achieve optimal noise margin, the device widths of PMOS and NMOS transistors are typically adjusted so that the switching voltage of the logic gates formed by the transistors is at half the operating voltage. When measuring the drive current of a PMOS transistor, the gate, source, and drain are brought out separately, and half the operating voltage is applied to the source and gate. The channel current measured at the drain can then be used as the drive current of the PMOS transistor. Similarly, the drive current of an NMOS transistor can also be measured.

[0004] However, different transistors have different transconductances, so the midpoint of the transfer curve of the logic gate formed by the transistors is not at half the operating voltage. Furthermore, during the logic level switching time, the transistor will successively experience the saturation and linear regions. Therefore, a single DC test under a fixed bias voltage cannot reflect its accurate drive current. Summary of the Invention

[0005] This disclosure provides a test circuit, test method, and test equipment that can improve the accuracy of transistor drive current testing.

[0006] In a first aspect, embodiments of this disclosure provide a test circuit, including a ring oscillation circuit and a plurality of test units; The ring oscillator circuit includes multiple logic gate units that are cascaded in sequence to form a ring loop; The test unit includes a first transistor, a second transistor, a first delay circuit, and a second delay circuit. The first transistor and the second transistor have different channel types. The input terminals of the first delay circuit and the second delay circuit are connected to the input terminals of the logic gate unit corresponding to the test unit. The duration of the effective level of the first delay circuit is longer than the duration of the effective level of the second delay circuit. The gate of the first transistor is connected to the output terminal of the first delay circuit, the source of the first transistor is connected to the first test terminal, and the drain of the first transistor is connected to the drain of the second transistor. The gate of the second transistor is connected to the output of the second delay circuit, and the source of the second transistor is connected to the second test terminal.

[0007] In some embodiments, the first delay circuit includes a first logic gate unit and a first oscillation circuit; the first input terminal of the first logic gate unit is connected to the input terminal of the logic gate unit corresponding to the test unit and the input terminal of the first oscillation circuit, respectively; the second input terminal of the first logic gate unit is connected to the output terminal of the first oscillation circuit; and the output terminal of the first logic gate unit is connected to the gate of the first transistor. The second delay circuit includes a second logic gate unit and a second oscillation circuit; the first input terminal of the second logic gate unit is connected to the input terminal of the second oscillation circuit, the second input terminal of the second logic gate unit is connected to the output terminal of the second oscillation circuit, and the output terminal of the second logic gate unit is connected to the gate of the second transistor.

[0008] In some embodiments, the first logic gate unit and the second logic gate unit are both OR gates, the first transistor is an NMOS, and the second transistor is a PMOS; Alternatively, both the first logic gate unit and the second logic gate unit can be AND gates, the first transistor can be a PMOS, and the second transistor can be an NMOS.

[0009] In some embodiments, the first logic gate unit includes a first NOR gate and a first NOT gate, the two input terminals of the first NOR gate are respectively the first input terminal and the second input terminal of the first logic gate unit, the output terminal of the first NOR gate is connected to the input terminal of the first NOT gate, and the output terminal of the first NOT gate is the output terminal of the first logic gate unit. The second logic gate unit includes a second NOR gate and a second NOT gate. The two input terminals of the second NOR gate are the first input terminal and the second input terminal of the second logic gate unit, respectively. The output terminal of the second NOR gate is connected to the input terminal of the second NOT gate, and the output terminal of the second NOT gate is the output terminal of the second logic gate unit. The first transistor is a PMOS and the second transistor is an NMOS.

[0010] In some embodiments, the first logic gate unit includes a first NAND gate and a first NOT gate, the two input terminals of the first NAND gate are respectively the first input terminal and the second input terminal of the first logic gate unit, the output terminal of the first NAND gate is connected to the input terminal of the first NOT gate, and the output terminal of the first NOT gate is the output terminal of the first logic gate unit; The second logic gate unit includes a second NAND gate and a second NOT gate. The two input terminals of the second NAND gate are the first input terminal and the second input terminal of the second logic gate unit, respectively. The output terminal of the second NAND gate is connected to the input terminal of the second NOT gate, and the output terminal of the second NOT gate is the output terminal of the second logic gate unit. The first transistor is a PMOS and the second transistor is an NMOS.

[0011] In some embodiments, the first oscillation circuit includes N NOT gates cascaded in sequence, and the second oscillation circuit includes M NOT gates cascaded in sequence. In this case, N and M are both odd numbers, and N > M.

[0012] In some embodiments, the total propagation delay t1 of the N NOT gates in the first oscillation circuit satisfies the following condition: T'+nT <t1<(1 / 2+n)T The total propagation delay t2 of the M NOT gates in the second oscillation circuit satisfies the following condition: T' <t2<1 / 2T Where T' represents the rise time or fall time of the input signal corresponding to the first oscillation circuit and the second oscillation circuit, T represents the period of the input signal, and n is an integer greater than zero.

[0013] In some embodiments, the M NOT gates in the second oscillation circuit are the M NOT gates cascaded sequentially in the first oscillation circuit, and the first-stage NOT gates in the second oscillation circuit are connected to the first-stage NOT gates in the first oscillation circuit by X NOT gates; where X is an odd number, and X... <N。

[0014] In some embodiments, each of the logic gate units includes a NOT gate, the NOT gate including a third transistor and a fourth transistor, the third transistor and the fourth transistor having different channel types; The source of the third transistor is connected to the first ground terminal, and the source of the fourth transistor is connected to the first power supply.

[0015] In some embodiments, the first-stage logic gate unit of the ring oscillator circuit is a NAND gate unit, and the NAND gate unit includes a first input terminal and a second input terminal; The first input terminal is used to receive an enable control signal; the second input terminal is connected to the output terminal of the last logic gate unit of the ring oscillator circuit.

[0016] In some embodiments, the test unit further includes a load circuit; The common drain of the first transistor and the second transistor is connected to the input terminal of the load circuit, and the output terminal of the load circuit is left floating.

[0017] In some embodiments, the load circuit includes a plurality of logic gate units cascaded in sequence.

[0018] In some embodiments, the test circuit further includes a current measuring element; The current measuring element is connected to the second test terminal and is used to measure the current value flowing into or out of the second test terminal.

[0019] In some embodiments, the number of logic gates in the ring oscillator circuit is odd, and the number of test units is less than or equal to the number of logic gates.

[0020] Secondly, embodiments of this disclosure provide a testing method applied to the testing circuit provided in the first aspect, the method comprising: Provide an enable control signal for the ring oscillator circuit; When both the first logic gate unit and the second logic gate unit are OR gates, and the first transistor is an NMOS and the second transistor is a PMOS, the current value flowing out of the second test terminal is detected, and the current value flowing out of the second test terminal is determined as the driving current of the second transistor. Alternatively, when both the first logic gate and the second logic gate are AND gates, and the first transistor is a PMOS and the second transistor is an NMOS, the current value flowing into the second test terminal is detected, and the current value flowing into the second test terminal is determined as the driving current of the second transistor.

[0021] Thirdly, embodiments of this disclosure provide a testing device, including: at least one processor and a memory; The memory stores computer-executed instructions; The at least one processor executes computer execution instructions stored in the memory, causing the at least one processor to perform the test method as provided in the second aspect.

[0022] The test circuit, test method, and test equipment provided in this disclosure employ a ring oscillator circuit, a first delay circuit, and a second delay circuit. The input terminals of the first delay circuit and the second delay circuit are connected to the input terminals of the logic gate units in the ring oscillator circuit. By connecting the source of the first transistor in each test unit to the first test terminal and the gate to the output terminal of the first delay circuit, and by connecting the source of the second transistor to an independent second test power supply and the gate to the output terminal of the second delay circuit, the accurate driving current of the second transistor in each test unit can be measured at the aforementioned second test terminal. This helps to obtain the influence of ion doping distribution on the effective current of CMOS devices and points the way for further improvement of CMOS circuit delay. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of a ring oscillator circuit provided in an embodiment of the present disclosure; Figure 2 This is provided by the embodiments of this disclosure. Figure 1 A schematic diagram of the current between adjacent inverters in the ring oscillator circuit shown; Figure 3 This is provided by the embodiments of this disclosure. Figure 1 Another schematic diagram of the current between adjacent inverters in the ring oscillator circuit shown; Figure 4 This is a schematic diagram of the structure of a test circuit provided in an embodiment of this disclosure. Figure 1 ; Figure 5 This is a schematic diagram of another ring oscillator circuit provided in an embodiment of this disclosure; Figure 6 This is a schematic diagram of the structure of a test circuit provided in an embodiment of this disclosure. Figure 2 ; Figure 7 This is an embodiment of the present disclosure. Figure 6 A schematic diagram of the first delay circuit in the test circuit shown. Figure 8 This is an embodiment of the present disclosure. Figure 6 A schematic diagram of the second delay circuit in the test circuit shown; Figure 9 This is a schematic diagram of the structure of a test circuit provided in an embodiment of this disclosure. Figure 3 ; Figure 10 This is an embodiment of the present disclosure. Figure 9 The timing diagram of the test circuit shown is shown. Figure 11 This is a schematic diagram of the structure of a test circuit provided in an embodiment of this disclosure. Figure 4 ; Figure 12This is a schematic diagram of the structure of a test circuit provided in an embodiment of this disclosure. Figure 5 ; Figure 13 This is an embodiment of the present disclosure. Figure 12 A schematic diagram of the first delay circuit in the test circuit shown. Figure 14 This is an embodiment of the present disclosure. Figure 12 A schematic diagram of the second delay circuit in the test circuit shown; Figure 15 This is a schematic diagram of the structure of a test circuit provided in an embodiment of this disclosure. Figure 6 ; Figure 16 This is an embodiment of the present disclosure. Figure 15 The timing diagram of the test circuit shown is shown. Figure 17 This is a schematic diagram of the structure of a test circuit provided in an embodiment of this disclosure. Figure 7 . Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure. Furthermore, although the disclosure in this disclosure is based on one or several exemplary examples, it should be understood that each aspect of these disclosures can also constitute a complete implementation method on its own.

[0025] It should be noted that the brief descriptions of terms in this disclosure are only for the convenience of understanding the embodiments described below, and are not intended to limit the embodiments of this disclosure. Unless otherwise stated, these terms should be understood in their ordinary and common meaning.

[0026] The terms "first," "second," etc., used in this disclosure, the specification, claims, and the accompanying drawings are used to distinguish similar or related objects or entities and do not necessarily imply a specific order or sequence, unless otherwise specified. It should be understood that such terms can be used interchangeably where appropriate, for example, in situations where implementation can proceed in an order other than those given in the illustrations or description of embodiments of this disclosure.

[0027] Furthermore, the terms “comprising” and “having”, and any variations thereof, are intended to cover but not exclusively include, for example, a product or device that includes a series of components is not necessarily limited to those that are explicitly listed, but may include other components that are not explicitly listed or that are inherent to such product or device.

[0028] The term "module" as used in the embodiments of this disclosure refers to any known or subsequently developed hardware, software, firmware, artificial intelligence, fuzzy logic, or combination of hardware and / or software code capable of performing the functions associated with that element.

[0029] MOS transistors can be classified into PMOS (P-channel) and NMOS (N-channel) based on their channel type. A MOS transistor consists of four terminals: gate (G), source (S), drain (D), and substrate (bulk). For an NMOS transistor, it conducts when the voltage Vgs between the gate (G) and source (S) exceeds a certain value. For a PMOS transistor, it conducts when the voltage Vgs between the gate (G) and source (S) falls below a certain value.

[0030] MOS transistors are widely used in the semiconductor technology field. For example, PMOS and NMOS transistors connected in series can form an inverter (or NOT gate), which is a CMOS transistor with an inverting function. Measuring the drive current of PMOS and NMOS transistors in a CMOS transistor can be used for auxiliary analysis of the CMOS. For example, the parasitic capacitance of the CMOS transistor can be analyzed based on the drive current of PMOS and NMOS transistors to determine the effect of ion doping on the parasitic capacitance of the CMOS transistor, thereby obtaining higher speed circuits.

[0031] In existing test circuits, the four terminals of the MOS are individually brought out, and the current of the MOS device is tested under operating voltage conditions. Meanwhile, in existing CMOS technology, in order to obtain optimal noise margin, the device widths of PMOS and NMOS are usually adjusted to keep the switching voltage of the logic gate composed of transistors at half the operating voltage.

[0032] Currently, when measuring the drive current of a PMOS, half of the operating voltage is typically applied to the source and gate of the PMOS. The channel current measured at the drain in this case can be used as the drive current of the PMOS. Similarly, the drive current of an NMOS can also be measured.

[0033] However, in actual level transitions, the midpoint of the logic gate's transition curve is not always at half the operating voltage because the transconductance of NMOS and PMOS is not consistent. Furthermore, even if the level transition occurs at half the operating voltage, the corresponding time is very short, and the PMOS remains in the linear region, the low Vgs region, and the oversaturation region (high Vds) for a considerable period. Therefore, when half the operating voltage is applied to the source and gate of a PMOS, the channel current measured at the drain does not accurately reflect the PMOS's drive current; the same applies to NMOS. Here, Vds represents the voltage between the drain (D) and source (S) of the MOS.

[0034] For example, in some traditional testing methods, a ring oscillator circuit can be used to test the drive current of a MOS at the moment of level transition.

[0035] Reference Figure 1 As shown, Figure 1 This is a schematic diagram of a ring oscillator circuit provided in an embodiment of this disclosure.

[0036] In some embodiments, the aforementioned ring oscillator circuit can be obtained by connecting multiple inverters in cascade. Figure 1 An exemplary ring oscillator circuit consisting of five cascaded inverters is provided, but in practical applications, the ring oscillator circuit can include an odd number of inverters, and this disclosure does not impose any restrictions.

[0037] It should be noted that, Figure 1 The document details the specific structure of one of the inverters; the structures of the other inverters are identical, and therefore not included in the [details of the document]. Figure 1 The annotation is in Chinese.

[0038] from Figure 1 As can be seen, the output of each inverter is connected to the input of the next inverter, thus forming a ring oscillator circuit with a loop.

[0039] Figure 1 Each inverter in the circuit consists of a PMOS and an NMOS transistor connected together. The gate G of the PMOS transistor is connected to the gate G of the NMOS transistor, and the two connected gates G serve as the input terminals of the inverter. The drain D of the PMOS transistor is connected to the drain D of the NMOS transistor, and the two connected drains D serve as the output terminals of the inverter. The source S of the PMOS transistor is connected to the first power supply VDD2, and the source S of the NMOS transistor is connected to the first ground terminal GND2.

[0040] Figure 1In the ring oscillator circuit shown, the outputs of some inverters exhibit a flat flip from high to low level, while the outputs of others exhibit a flat flip from low to high level. This allows us to capture the moment of level transition and use the current at that moment as the drive current for the PMOS or NMOS transistor.

[0041] Reference Figure 2 As shown, Figure 2 This is provided by the embodiments of this disclosure. Figure 1 A schematic diagram of the current between adjacent inverters in the ring oscillator circuit shown.

[0042] As the input voltage V of the preceding inverter INV_1 transitions from high to low, the PMOS in INV_1 gradually turns on and generates a current I. This current I flows to the common gate of the NMOS and PMOS in the following inverter INV_2. Under the influence of current I, the gate voltage of the NMOS in INV_2 rises, reaching a high level. However, during this process, the NMOS in INV_1 is not completely turned off; some current I still flows from the PMOS in INV_1 through the still-operational NMOS in INV_1 into the ground terminal GND.

[0043] Since both currents I1 and I2 flow out from the VDD terminal, the drive current of the PMOS measured at the VDD port will be larger than the actual drive current of the PMOS. This leads to an overestimation of the equivalent capacitance of the ring oscillator and an underestimation of its equivalent resistance, thus failing to obtain the effect of ion doping on the parasitic capacitance of the CMOS.

[0044] Reference Figure 3 As shown, Figure 3 This is provided by the embodiments of this disclosure. Figure 1 Another schematic diagram of the current between adjacent inverters in the ring oscillator circuit shown.

[0045] During the transition from low to high level at the input of the preceding inverter INV_1, the NMOS in INV_1 gradually turns on and generates a current I3. This current I3 lowers the common gate voltage of the following inverter INV_2 to 0. However, during this process, the PMOS in the preceding inverter is not completely turned off, and a portion of the current I4 still flows from the partially turned-off PMOS in INV_1 through the NMOS in the preceding inverter to the ground terminal GND.

[0046] Because currents I3 and I4 flow into GND together, the NMOS drive current measured at the GND port will be larger than the actual NMOS drive current. This will also lead to an overestimation of the equivalent capacitance of the ring oscillator and an underestimation of its equivalent resistance, thus failing to obtain the effect of ion doping on the CMOS parasitic capacitance.

[0047] To address the aforementioned technical problems, this disclosure provides a test circuit employing a ring oscillator circuit, a first delay circuit, and a second delay circuit. The input terminals of the first and second delay circuits are connected to the input terminals of the logic gate units in the ring oscillator circuit. By connecting the source of the NMOS in each test unit to the first test terminal and its gate to the output terminal of the first delay circuit, and connecting the source of the PMOS to an independent second test terminal and its gate to the output terminal of the second delay circuit, the accurate drive current of the PMOS in each test unit can be measured at the second test terminal. Alternatively, by connecting the source of the PMOS in each test unit to the first test terminal and its gate to the output terminal of the first delay circuit, and connecting the source of the NMOS to an independent second test terminal and its gate to the output terminal of the second delay circuit, the accurate drive current of the NMOS in each test unit can be measured at the second test terminal. Detailed embodiments are described below.

[0048] Reference Figure 4 As shown, Figure 4 This is a schematic diagram of the structure of a test circuit provided in an embodiment of this disclosure. Figure 1 In one feasible implementation, the test circuit 100 includes a ring oscillator circuit 101 and a plurality of test units 1021 to test units 1025.

[0049] Reference Figure 4 As shown, the ring oscillator circuit 101 includes multiple logic gate units that are cascaded in sequence to form a ring loop, such as logic gate unit 1011 to logic gate unit 1015. Each logic gate unit includes an input terminal and an output terminal.

[0050] Optionally, the above logic gate unit can be a logic gate with inverting function, including but not limited to: NOT gate, NAND gate, NOR gate, XOR gate, XNOR gate, and controlled NOT gate, etc.

[0051] Optionally, the NOT gate mentioned above can be an inverter composed of PMOS and NMOS connected together.

[0052] Understandable Figure 4 The ring oscillator circuit 101 in the example provides 5 logic gate units, but in actual applications, the number of logic gate units can be odd as long as it is odd. Here, there is no restriction on the number of logic gate units.

[0053] Figure 4 The test circuit 100 in the example provides 5 test units, namely test unit 1021 to test unit 1025. However, in actual applications, the number of test units can be less than or equal to the number of logic gate units. This embodiment of the present disclosure does not limit the number of test units.

[0054] In some embodiments of this disclosure, the ring oscillator circuit 101 described above can be of two types. In one embodiment of the ring oscillator circuit, such as... Figure 1 As shown, each logic gate unit can be a NOT gate, also known as an inverter. Therefore, the input of each logic gate unit is the input of the NOT gate, and the output of each logic gate unit is the output of the NOT gate. In this way, the output of each NOT gate in the ring oscillator circuit 101 is connected to the input of the next NOT gate.

[0055] In another implementation of the ring oscillator circuit, the structure of the first-level logic gate unit can differ from the structure of the remaining logic gate units. For example... Figure 5 As shown, Figure 5 This is a schematic diagram of another ring oscillator circuit provided in an embodiment of this disclosure.

[0056] exist Figure 5 In the ring oscillator circuit 101, the first-stage logic gate unit 1011 can be a NAND gate, such as a two-input NAND gate (NAND2); while the remaining logic gate units can be NOT gates (hereinafter referred to as inverters).

[0057] In this circuit, one input terminal of the NAND gate serves as the enable input terminal En of the ring oscillator circuit 101, the other input terminal serves as the input terminal of the first-level logic gate unit 1011, and the output terminal of the NAND gate serves as the output terminal of the first-level logic gate unit 1011.

[0058] Reference Figure 5 As shown, the output of the NAND gate is connected to the input of the second-stage logic gate unit, and the other input of the NAND gate is connected to the output of the last-stage logic gate unit, thus forming a ring oscillation circuit.

[0059] In some embodiments, the enable input terminal En is used to control the oscillation of the ring oscillator circuit 101. In the initial state, when the enable control signal input to the enable input terminal En is a low-level signal, Figure 5 The ring oscillator circuit 101 shown does not oscillate; when the enable control signal input to the enable input terminal En is a high-level signal, Figure 5 The ring oscillator circuit 101 shown starts oscillating, that is, the first-level logic gate unit starts working, and the level at the input terminal flips.

[0060] As can be seen, in this embodiment of the present disclosure, the oscillation of the ring oscillation circuit 101 can be flexibly controlled by combining the above-mentioned enable control signal and NAND gate. When it is not necessary to test the flip current, the ring oscillation circuit 101 can be stopped from oscillating by the enable control signal, thereby helping to save power.

[0061] In an optional embodiment, each logic gate unit in the ring oscillator circuit 101 described above includes a NOT gate, which includes a third transistor and a fourth transistor of different channel types, such as the third transistor being an NMOS and the fourth transistor being a PMOS.

[0062] In some implementations, the NAND gate can be composed of two PMOS and two NMOS transistors. The common source of the two PMOS transistors in the NAND gate can be connected to the first power supply VDD2 as the power supply terminal of the NAND gate.

[0063] Reference Figure 5 As shown, in the ring oscillator circuit 101, the power supply terminals of the NAND gates and the sources of the fourth transistors of each NAND gate are all connected to the same first power supply VDD2 to provide power to the ring oscillator circuit 101. Since the ring oscillator circuit 101 can oscillate without NAND gates, when there are no NAND gates in the ring oscillator circuit 101, the sources of the fourth transistors of each NAND gate are all connected to the same first power supply VDD2.

[0064] exist Figure 5 In any of the NOT gates shown, the gate G of the fourth PMOS transistor is connected to the gate G of the third NMOS transistor, and serves as the input terminal of the corresponding NOT gate. The drain D of the fourth PMOS transistor is connected to the drain D of the third NMOS transistor, and serves as the output terminal of the corresponding NOT gate. The source S of the third NMOS transistor is connected to the first ground terminal GND2.

[0065] Reference Figure 6 , Figure 6 This is a schematic diagram of the structure of a test circuit provided in an embodiment of this disclosure. Figure 2 In some embodiments, the above-described test circuit includes... Figure 1 or Figure 5 The circuit shown is a ring oscillator circuit, and several test units are also shown.

[0066] For example, Figure 6 The structure of one of the test units 1021 is shown in the figure. It can be understood that the structures of the other test units are consistent with the structure of test unit 1021.

[0067] Each of the aforementioned test units includes a first NMOS transistor, a second PMOS transistor, a first delay circuit, and a second delay circuit. The input terminals of the first and second delay circuits are connected to the input terminals of the corresponding logic gate units of the test unit. The gate of the first transistor is connected to the output terminal of the first delay circuit, the source is connected to the first test terminal GND1, and the drain is connected to the drain of the second transistor. The gate of the second transistor is connected to the output terminal of the second delay circuit, and the source is connected to the second test terminal VDD1.

[0068] The duration of the effective level of the first delay circuit is longer than the duration of the effective level of the second delay circuit.

[0069] In some embodiments, the second test terminal VDD1 is independent of the first power supply VDD2 connected to each logic gate unit in the ring oscillator circuit 101, and the first test terminal GND1 can be independent of the first ground terminal GND2 connected to each logic gate unit in the ring oscillator circuit 101, or it can be the same ground terminal.

[0070] Optionally, the test circuit 100 may further include a first selection switch. During the test, the first selection switch can be used to disconnect the connection between the first power supply VDD2 and the second test terminal VDD1, so that the first power supply VDD2 and the second test terminal VDD1 are independent of each other.

[0071] In addition, each of the above test units also includes a load circuit; the common drain of the first transistor and the second transistor is connected to the input terminal of the load circuit, and the output terminal of the load circuit is left floating.

[0072] Optionally, the load circuit described above includes multiple logic gate units cascaded in sequence.

[0073] The logic gates in the load circuit are identical to those in the ring oscillator circuit. For example, when the logic gate in the ring oscillator circuit is a NOT gate, the logic gate in the load circuit is also a NOT gate.

[0074] It is understandable that when the logic gate unit in the above load circuit is an NOT gate, the above load circuit can simulate the Miller effect of parasitic capacitance when the next level logic gate unit is used as the load of the current logic gate unit. In addition, the above load circuit can also adjust the level switching time of the logic gate unit. If the above load circuit does not exist, the level switching of the above logic gate unit will be very fast, which will make it difficult to measure the drive current of the test unit. That is, the above load circuit can be equivalent to a parasitic capacitor.

[0075] In some embodiments, the test circuit 100 may further include a current measuring element. When the input voltage of the test unit flips, the current measuring element measures the current value of the current flowing out of the second test terminal VDD1. The measured current value is the drive current of the PMOS in the test unit.

[0076] Understandably, during the testing process, since the PMOS in the multiple test units of the above test circuit will be turned on sequentially, the measured drive current is the average drive current value of the PMOS in the multiple test units. This can effectively eliminate the influence of process error on the measurement results.

[0077] The test circuit provided in this embodiment employs a ring oscillator circuit, a first delay circuit, and a second delay circuit. The input terminals of the first and second delay circuits are connected to the input terminals of the logic gate units in the ring oscillator circuit. By connecting the gate of the NMOS in each test unit to the output terminal of the first delay circuit, and connecting the source of the PMOS to an independent second test terminal with its gate connected to the output terminal of the second delay circuit, the accurate drive current of the PMOS in each test unit can be measured at the second test terminal. This helps to obtain the influence of ion doping distribution on the effective current of the CMOS device, pointing the way for further improvement of the delay of the CMOS circuit.

[0078] Based on the content described in the above embodiments, in some embodiments, reference is made to... Figure 7 , Figure 7 This is an embodiment of the present disclosure. Figure 6 The diagram shows the structure of the first delay circuit in the test circuit. In some embodiments, the first delay circuit includes a first logic gate unit 701 and a first oscillation circuit 702; the first input terminal Input1 of the first logic gate unit 701 is connected to the input terminal of the corresponding logic gate unit in the ring oscillation circuit and the input terminal of the first oscillation circuit 702, respectively; the second input terminal Input2 of the first logic gate unit 701 is connected to the output terminal of the first oscillation circuit 702; the output terminal Va of the first logic gate unit 701 is connected to the gate of the first transistor NMOS.

[0079] In some implementations, the first logic gate unit 701 described above is an OR gate.

[0080] Optionally, the first logic gate unit 701 includes a first NOR_1 gate and a first NOT_1 gate, wherein the two input terminals of the first NOR_1 gate are the first input terminal Input1 and the second input terminal Input2 of the first logic gate unit 701, respectively. The output terminal of the first NOR gate NOR_1 is connected to the input terminal of the first NOT gate NOT_1, and the output terminal of the first NOT gate NOT_1 serves as the output terminal Va of the first logic gate unit 701.

[0081] In some embodiments, the first oscillation circuit 702 includes N cascaded NOT gates in sequence, where N is an odd number.

[0082] With reference to Figure 8 , Figure 8 which is in the embodiments of the present disclosure Figure 6 is a schematic structural diagram of the second delay circuit in the illustrated test circuit. In some embodiments, the aforementioned second delay circuit includes a second logic gate unit 801 and a second oscillation circuit 802; the first input terminal Input1 of the second logic gate unit 801 is respectively connected to the input terminal of the corresponding logic gate unit in the ring oscillation circuit and the input terminal of the second oscillation circuit 802, the second input terminal Input2 of the second logic gate unit 801 is connected to the output terminal of the second oscillation circuit 802; and the output terminal Vb of the second logic gate unit 801 is connected to the gate of the second transistor PMOS.

[0083] In some embodiments, the aforementioned second logic gate unit 801 is an OR gate.

[0084] Optionally, the second logic gate unit 801 includes a second NOR gate NOR_2 and a second NOT gate NOT_2, the two input terminals of the second NOR gate NOR_2 are respectively the first input terminal Input1 and the second input terminal Input2 of the second logic gate unit 801, the output terminal of the second NOR gate NOR_2 is connected to the input terminal of the second NOT gate NOT_2, and the output terminal of the second NOT gate NOT_2 serves as the output terminal Vb of the second logic gate unit 801.

[0085] In some embodiments, the second oscillation circuit 802 includes M cascaded NOT gates in sequence, where M is an odd number and N>M.

[0086] It can be understood that since the number of NOT gates in the first oscillation circuit 702 is greater than the number of NOT gates in the second oscillation circuit 802, the duration for maintaining the valid level of the first delay circuit is longer than the duration for maintaining the valid level of the second delay circuit.

[0087] Optionally, in some embodiments, the M NOT gates in the second oscillation circuit may be M NOT gates cascaded in sequence in the first oscillation circuit, and X NOT gates are connected between the first-stage NOT gate in the second oscillation circuit and the first-stage NOT gate in the first oscillation circuit; where X is an odd number and X<N, which can simplify the circuit structure of the test circuit and save test costs.

[0088] For example, assuming there are 3 NOT gates in the second oscillation circuit and 7 NOT gates in the first oscillation circuit, the second oscillation circuit can share the 3 NOT gates cascaded in the first oscillation circuit, and the first-stage NOT gate in the second oscillation circuit can be connected to the first-stage NOT gate in the first oscillation circuit with 1 or 3 NOT gates.

[0089] Reference Figure 9 , Figure 9 This is a schematic diagram of the structure of a test circuit provided in an embodiment of this disclosure. Figure 3 .exist Figure 9 In the first oscillation circuit and the second oscillation circuit share three NOT gates. The first-stage NOT gate in the second oscillation circuit is connected to the first-stage NOT gate in the first oscillation circuit by one NOT gate.

[0090] like Figure 9 As shown, the sources of the PMOS in each test unit are all connected to a common VDD1 terminal, which is separate from the power supply of all other devices.

[0091] In the initial state, the En signal level is 0. At this time, the ring oscillator circuit 101 does not oscillate. The two input levels of NOR_1 and NOR_2 remain different at all times. Therefore, the output potentials of NOR_1 and NOR_2 are always 0.

[0092] When the En signal level is 1, the output voltages of each stage of the ring oscillator circuit 101 begin to oscillate. When Input changes from 1 to 0, this corresponds to the situation where the PMOS in INV needs to be turned on. Therefore, in this case, the potentials of the two input terminals of NOR_1 and NOR_2 will be 0 simultaneously, and the output voltages of NOR_1 and NOR_2 will briefly become high. After the signal transmission delay tPD of each INV, the output voltages of NOR_1 and NOR_2 will return to 0.

[0093] To better understand this embodiment, please refer to... Figure 10 , Figure 10 This is an embodiment of the present disclosure. Figure 9 The timing diagram of the test circuit shown is shown.

[0094] exist Figure 10In the circuit, when Input changes from 1 to 0, in interval A, the NMOS is on and the PMOS is off; in interval B, both the NMOS and PMOS are off; in interval C, the NMOS is completely off, so no additional short-circuit current flows from VDD1 to GND1, and the PMOS state begins to toggle, with the current flowing from the VDD1 port becoming the effective drive current for the PMOS; in interval D, the NMOS is completely off, and the PMOS remains on, but since the source-drain voltage Vds = 0 for the PMOS, no additional current is generated. In interval E, the NMOS is completely off, and the gate-source voltage Vgs of the PMOS gradually decreases to 0, turning the PMOS off, but Vds remains 0, so no additional current is generated. In interval F, the PMOS turns off, and the NMOS gradually turns on, resetting the load circuit to its initial state, awaiting the next cycle.

[0095] like Figure 10 As shown, the total propagation delay t1 (7 × tPD) of the 7 NOT gates in the first oscillation circuit satisfies the following condition: T'+nT <t1<(1 / 2+n)T The total propagation delay t2(3×tPD) of the three NOT gates in the second oscillation circuit satisfies the following condition: T' <t2<1 / 2T Where T' represents the rise time or fall time of the input signal corresponding to the first oscillation circuit and the second oscillation circuit, T represents the period of the input signal, and n is an integer greater than zero.

[0096] In some embodiments, the test circuit further includes a current measuring element connected to VDD1 for measuring the current flowing out of VDD1.

[0097] It is understandable that when there are multiple test units in the above test circuit, the PMOS in each test unit will be turned on in sequence. Therefore, the obtained drive current is the average value of the drive current of multiple PMOS, which can effectively eliminate the influence of process error on the result.

[0098] Optionally, in some embodiments, the M NOT gates in the second oscillation circuit can be the M NOT gates cascaded sequentially in the first oscillation circuit, and X NOT gates are connected between the first-stage NOT gate in the second oscillation circuit and the first-stage NOT gate in the first oscillation circuit; wherein, when X is 0 or even, the above-mentioned second logic gate unit includes a second NOR_2, and the output terminal of the second NOR_2 is the output terminal Vb of the second logic gate unit.

[0099] Reference Figure 11 , Figure 11This is a schematic diagram of the structure of a test circuit provided in an embodiment of this disclosure. Figure 4 .exist Figure 11 In the first oscillation circuit and the second oscillation circuit share three NOT gates, and the first-stage NOT gate in the second oscillation circuit is connected to the first-stage NOT gate in the first oscillation circuit by zero NOT gates.

[0100] Reference Figure 12 , Figure 12 This is a schematic diagram of the structure of a test circuit provided in an embodiment of this disclosure. Figure 5 In some embodiments, the above-described test circuit includes... Figure 1 or Figure 5 The circuit shown is a ring oscillator circuit, and several test units are also shown.

[0101] For example, Figure 12 The structure of one of the test units 1021 is shown in the figure. It can be understood that the structures of the other test units are consistent with the structure of test unit 1021.

[0102] Each of the aforementioned test units includes a first PMOS crystal, a second NMOS transistor, a first delay circuit, and a second delay circuit. The input terminals of the first and second delay circuits are connected to the input terminals of the corresponding logic gate units of the test unit. The gate of the first transistor is connected to the output terminal of the first delay circuit, the source is connected to the first test terminal VDD1, and the drain is connected to the drain of the second transistor. The gate of the second transistor is connected to the output terminal of the second delay circuit, and the source is connected to the second test terminal GND1.

[0103] The duration of the effective level of the first delay circuit is longer than the duration of the effective level of the second delay circuit.

[0104] In some embodiments, the second test terminal GND1 is independent of the first ground terminal GND2 connected to each logic gate unit in the ring oscillator circuit 101, and the first test terminal VDD1 can be independent of the first power supply VDD2 connected to each logic gate unit in the ring oscillator circuit 101, or it can be the same power supply.

[0105] Optionally, the test circuit 100 also includes a second selection switch. During the test, the second selection switch can be used to disconnect the connection between the second test terminal GND1 and the first ground terminal GND2, so that the second test terminal GND1 and the first ground terminal GND2 are independent of each other.

[0106] In addition, each of the above test units also includes a load circuit; the common drain of the first transistor and the second transistor is connected to the input terminal of the load circuit, and the output terminal of the load circuit is left floating.

[0107] Optionally, the load circuit described above includes multiple logic gate units cascaded in sequence.

[0108] The logic gates in the load circuit are identical to those in the ring oscillator circuit. For example, when the logic gate in the ring oscillator circuit is a NOT gate, the logic gate in the load circuit is also a NOT gate.

[0109] It is understandable that when the logic gate unit in the above load circuit is an NOT gate, the above load circuit can simulate the Miller effect of parasitic capacitance when the next level logic gate unit is used as the load of the current logic gate unit. In addition, the above load circuit can also adjust the level switching time of the logic gate unit. If the above load circuit does not exist, the level switching of the above logic gate unit will be very fast, which will make it difficult to measure the drive current of the test unit. That is, the above load circuit can be equivalent to a parasitic capacitor.

[0110] In some embodiments, the test circuit 100 may further include a current measuring element. When the input voltage of the test unit flips, the current measuring element measures the current value flowing into the second test terminal GND1. The measured current value is the drive current of the NMOS in the test unit.

[0111] It is understandable that during the testing process, since the NMOS in the multiple test units of the above test circuit will be turned on sequentially, the measured drive current is the average drive current value of the NMOS in the multiple test units. This can effectively eliminate the influence of process error on the measurement results.

[0112] The test circuit provided in this embodiment employs a ring oscillator circuit, a first delay circuit, and a second delay circuit. The input terminals of the first and second delay circuits are connected to the input terminals of the logic gate units in the ring oscillator circuit. By connecting the source of the PMOS in each test unit to the first test terminal and the gate to the output terminal of the first delay circuit, and connecting the gate of the NMOS to the output terminal of the second delay circuit and the source to an independent second test terminal, the accurate drive current of the NMOS in each test unit can be measured at the second test terminal. This helps to obtain the influence of ion doping distribution on the effective current of the CMOS device and points the way for further improvement of the delay of the CMOS circuit.

[0113] Based on the content described in the above embodiments, in some embodiments, reference is made to... Figure 13 , Figure 13 This is an embodiment of the present disclosure. Figure 12The diagram shows the structure of the first delay circuit in the test circuit. In some embodiments, the first delay circuit includes a first logic gate unit 1201 and a first oscillation circuit 1202; the first input terminal Input1 of the first logic gate unit 1201 is connected to the input terminal of the corresponding logic gate unit in the ring oscillation circuit and the input terminal of the first oscillation circuit 1202, respectively; the second input terminal Input2 of the first logic gate unit 1201 is connected to the output terminal of the first oscillation circuit 1202; the output terminal Va of the first logic gate unit 1201 is connected to the gate of the first transistor PMOS.

[0114] In some implementations, the first logic gate unit 1201 is an AND gate.

[0115] Optionally, the first logic gate unit 1201 includes a first NAND gate NAND_1 and a first NOT gate NOT_1. The two input terminals of the first NAND gate NAND_1 are the first input terminal Input1 and the second input terminal Input2 of the first logic gate unit 1201, respectively. The output terminal of the first NAND gate NAND_1 is connected to the input terminal of the first NOT gate NOT_1, and the output terminal of the first NOT gate NOT_1 is the output terminal Va of the first logic gate unit 1201.

[0116] In some implementations, the first oscillation circuit 1202 includes N NOT gates cascaded in sequence, where N is an odd number.

[0117] Reference Figure 14 , Figure 14 This is an embodiment of the present disclosure. Figure 12 The diagram shows the structure of the second delay circuit in the test circuit. In some embodiments, the second delay circuit includes a second logic gate unit 1301 and a second oscillation circuit 1302; the first input terminal Input1 of the second logic gate unit 1301 is connected to the input terminal of the corresponding logic gate unit in the ring oscillation circuit and the input terminal of the second oscillation circuit 1302, respectively; the second input terminal Input2 of the second logic gate unit 1301 is connected to the output terminal of the second oscillation circuit 1302; the output terminal Vb of the second logic gate unit 1301 is connected to the gate of the second transistor NMOS.

[0118] In some implementations, the second logic gate unit 1301 is an AND gate.

[0119] Optionally, the second logic gate unit 1301 includes a second NAND gate NAND_2 and a second NOT gate NOT_2, two input terminals of the second NAND gate NAND_2 are respectively the first input terminal Input1 and the second input terminal Input2 of the second logic gate unit 1301, an output terminal of the second NAND gate NAND_2 is connected to an input terminal of the second NOT gate NOT_2, and an output terminal of the second NOT gate NOT_2 is the output terminal Vb of the second logic gate unit 1301.

[0120] In some embodiments, the second oscillation circuit 1302 includes M NOT gates cascaded in sequence. M is an odd number, and N is greater than M.

[0121] It can be understood that, since the number of NOT gates in the first oscillation circuit 1202 is greater than the number of NOT gates in the second oscillation circuit 1302, the maintenance duration of the valid level of the first delay circuit is greater than the maintenance duration of the valid level of the second delay circuit.

[0122] Optionally, in some embodiments, the M NOT gates in the second oscillation circuit may be M NOT gates cascaded in sequence in the first oscillation circuit, and at least X NOT gates are connected between the first-stage NOT gate in the second oscillation circuit and the first-stage NOT gate in the first oscillation circuit; where X is an odd number and X is less than N, which can simplify the circuit structure of the test circuit and save test costs.

[0123] For example, assuming that there are 3 NOT gates in the second oscillation circuit and 7 NOT gates in the first oscillation circuit, the second oscillation circuit can share 3 cascaded NOT gates in the first oscillation circuit, and 1 or 3 NOT gates are connected between the first-stage NOT gate in the second oscillation circuit and the first-stage NOT gate in the first oscillation circuit.

[0124] Reference is made to Figure 15 , Figure 15 which is a schematic structural diagram of a test circuit provided by the embodiments of the present disclosure Figure 6 . In Figure 15 , the first oscillation circuit and the second oscillation circuit share 3 NOT gates therein, and 1 NOT gate is connected between the first-stage NOT gate in the second oscillation circuit and the first-stage NOT gate in the first oscillation circuit.

[0125] As shown in Figure 15 , the source electrodes of the NMOS in each test unit are all connected to the common GND1 terminal, which is separated from the ground terminals of all other devices.

[0126] In the initial state, the level of the En signal is 0, at this time the ring oscillation circuit 101 does not oscillate, the two input levels of NAND_1 and NAND_2 are kept different all the time, so the output potentials of NAND_1 and NAND_2 are always 0.

[0127] When the En signal level is 1, the output voltages of each stage of the ring oscillator circuit 101 begin to oscillate. When Input changes from 0 to 1, this corresponds to the situation where the NMOS in INV needs to be turned on. In this case, the potentials of the two input terminals of NAND_1 and NAND_2 will be 1 simultaneously, and the output voltages of NAND_1 and NAND_2 will briefly go low. After the signal transmission delay tPD of each INV, the output voltages of NAND_1 and NAND_2 will return to 1.

[0128] To better understand this embodiment, please refer to... Figure 16 , Figure 16 This is an embodiment of the present disclosure. Figure 15 The timing diagram of the test circuit shown is shown.

[0129] exist Figure 16 In the circuit, when the Input changes from 0 to 1, in interval A, the NMOS is off and the PMOS is on; in interval B, both the NMOS and PMOS are off; in interval C, the PMOS is completely off, so no additional short-circuit current flows from VDD1 to GND1, and the NMOS state begins to flip, with the current flowing into GND1 becoming the effective drive current for the NMOS; in interval D, the PMOS is completely off, and the NMOS remains on. In interval E, the PMOS is completely off, the gate-source voltage Vgs of the NMOS gradually decreases to 0, and the NMOS is off, but Vds remains 0, so no additional current is generated. In interval F, the NMOS is off, and the PMOS gradually turns on, resetting the load circuit to its initial state, awaiting the next cycle.

[0130] like Figure 16 As shown, the total propagation delay t1 (7 × tPD) of the 7 NOT gates in the first oscillation circuit satisfies the following condition: T'+nT <t1<(1 / 2+n)T; The total propagation delay t2(3×tPD) of the three NOT gates in the second oscillation circuit satisfies the following condition: T' <t2<1 / 2T; Where T' represents the rise time or fall time of the input signal corresponding to the first oscillation circuit and the second oscillation circuit, T represents the period of the input signal, and n is an integer greater than zero.

[0131] In some embodiments, the test circuit further includes a current measuring element connected to GND1 for measuring the current flowing into GND1.

[0132] It is understandable that when the above test circuit includes multiple test units, the NMOS in each test unit is turned on sequentially. Therefore, the obtained drive current is the average value of the drive current of multiple NMOS, which can effectively eliminate the influence of process error on the results.

[0133] Optionally, in some embodiments, the M NOT gates in the second oscillation circuit can be the M NOT gates cascaded sequentially in the first oscillation circuit, and at least X NOT gates are connected between the first-stage NOT gate in the second oscillation circuit and the first-stage NOT gate in the first oscillation circuit; wherein, when X is 0 or even, the second logic gate unit includes a second NAND gate NAND_2, and the output terminal of the second NAND gate NAND_2 is the output terminal Vb of the second logic gate unit.

[0134] Reference Figure 17 , Figure 17 This is a schematic diagram of the structure of a test circuit provided in an embodiment of this disclosure. Figure 7 .exist Figure 17 In the first oscillation circuit and the second oscillation circuit share three NOT gates, and the first-stage NOT gate in the second oscillation circuit is connected to the first-stage NOT gate in the first oscillation circuit by zero NOT gates.

[0135] Based on the test circuit 100 described in the above embodiments, this disclosure also provides a test method applied to the test circuit 100 described in the above embodiments.

[0136] When both the first and second logic gate units in the above-mentioned test circuit 100 are OR gates, and the first transistor is an NMOS and the second transistor is a PMOS, the above-mentioned test method includes: S1 provides an enable control signal for the ring oscillator circuit.

[0137] S2. Detect the current value flowing out of the second test terminal and determine the current value flowing out of the second test terminal as the driving current of the second transistor.

[0138] When both the first and second logic gate units in the above-mentioned test circuit 100 are AND gates, and the first transistor is a PMOS and the second transistor is an NMOS, the above-mentioned test method includes: S1 provides an enable control signal for the ring oscillator circuit.

[0139] S2. Detect the current value flowing into the second test terminal and determine the current value flowing into the second test terminal as the driving current of the second transistor.

[0140] The testing method provided in this disclosure, when applied to the testing circuit provided in the above embodiments, can measure the accurate driving current of NMOS in each test unit, or measure the accurate driving current of PMOS in each test unit, thereby helping to obtain the influence of ion doping distribution on the effective current of CMOS devices and pointing the way for further improvement of CMOS circuit delay.

[0141] Furthermore, based on the content described in the above embodiments, this disclosure also provides a testing device, which includes at least one processor and a memory; wherein the memory stores computer execution instructions; the at least one processor executes the computer execution instructions stored in the memory to implement the various steps in the testing method described in the above embodiments, which will not be repeated here.

[0142] It should be understood that, in the several embodiments provided in this disclosure, the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or modules, and may be electrical, mechanical, or other forms.

[0143] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0144] Furthermore, the functional modules in the various embodiments of this disclosure can be integrated into one processing unit, or each module can exist physically separately, or two or more modules can be integrated into one unit. The aforementioned modular unit can be implemented in hardware or in a combination of hardware and software functional units.

[0145] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A test circuit, characterized in that, It includes a ring oscillator circuit and several test units; The ring oscillator circuit includes multiple logic gate units that are cascaded in sequence to form a ring loop; The test unit includes a first transistor, a second transistor, a first delay circuit, and a second delay circuit. The first transistor and the second transistor have different channel types. The input terminals of the first delay circuit and the second delay circuit are connected to the input terminals of the logic gate unit corresponding to the test unit. The duration of the effective level of the first delay circuit is longer than the duration of the effective level of the second delay circuit. The gate of the first transistor is connected to the output terminal of the first delay circuit, the source of the first transistor is connected to the first test terminal, and the drain of the first transistor is connected to the drain of the second transistor. The gate of the second transistor is connected to the output of the second delay circuit, and the source of the second transistor is connected to the second test terminal.

2. The test circuit according to claim 1, characterized in that, The first delay circuit includes a first logic gate unit and a first oscillation circuit; the first input terminal of the first logic gate unit is connected to the input terminal of the logic gate unit corresponding to the test unit and the input terminal of the first oscillation circuit, respectively; the second input terminal of the first logic gate unit is connected to the output terminal of the first oscillation circuit; the output terminal of the first logic gate unit is connected to the gate of the first transistor. The second delay circuit includes a second logic gate unit and a second oscillation circuit; The first input terminal of the second logic gate unit is connected to the input terminal of the second oscillation circuit, and the second input terminal of the second logic gate unit is connected to the output terminal of the second oscillation circuit; the output terminal of the second logic gate unit is connected to the gate of the second transistor.

3. The test circuit according to claim 2, characterized in that, Both the first logic gate unit and the second logic gate unit are OR gates, the first transistor is an NMOS, and the second transistor is a PMOS; Alternatively, both the first logic gate unit and the second logic gate unit can be AND gates, the first transistor can be a PMOS, and the second transistor can be an NMOS.

4. The test circuit according to claim 2, characterized in that, The first logic gate unit includes a first NOR gate and a first NOT gate. The two input terminals of the first NOR gate are the first input terminal and the second input terminal of the first logic gate unit, respectively. The output terminal of the first NOR gate is connected to the input terminal of the first NOT gate, and the output terminal of the first NOT gate is the output terminal of the first logic gate unit. The second logic gate unit includes a second NOR gate and a second NOT gate. The two input terminals of the second NOR gate are the first input terminal and the second input terminal of the second logic gate unit, respectively. The output terminal of the second NOR gate is connected to the input terminal of the second NOT gate, and the output terminal of the second NOT gate is the output terminal of the second logic gate unit. The first transistor is a PMOS and the second transistor is an NMOS.

5. The test circuit according to claim 2, characterized in that, The first logic gate unit includes a first NAND gate and a first NOT gate. The two input terminals of the first NAND gate are the first input terminal and the second input terminal of the first logic gate unit, respectively. The output terminal of the first NAND gate is connected to the input terminal of the first NOT gate, and the output terminal of the first NOT gate is the output terminal of the first logic gate unit. The second logic gate unit includes a second NAND gate and a second NOT gate. The two input terminals of the second NAND gate are the first input terminal and the second input terminal of the second logic gate unit, respectively. The output terminal of the second NAND gate is connected to the input terminal of the second NOT gate, and the output terminal of the second NOT gate is the output terminal of the second logic gate unit. The first transistor is a PMOS and the second transistor is an NMOS.

6. The test circuit according to claim 2, characterized in that, The first oscillation circuit includes N NOT gates cascaded in sequence, and the second oscillation circuit includes M NOT gates cascaded in sequence. In this case, N and M are both odd numbers, and N > M.

7. The test circuit according to claim 6, characterized in that, The total propagation delay t1 of the N NOT gates in the first oscillation circuit satisfies the following condition: T'+nT <t1<(1 / 2+n)T; The total propagation delay t2 of the M NOT gates in the second oscillation circuit satisfies the following condition: T' <t2<1 / 2T; Where T' represents the rise time or fall time of the input signal corresponding to the first oscillation circuit and the second oscillation circuit, T represents the period of the input signal, and n is an integer greater than zero.

8. The test circuit according to claim 6, characterized in that, The M NOT gates in the second oscillation circuit are the M NOT gates cascaded sequentially in the first oscillation circuit, and the first-stage NOT gates in the second oscillation circuit are connected to the first-stage NOT gates in the first oscillation circuit by X NOT gates; where X is an odd number, and X... <N。 9. The test circuit according to claim 3, characterized in that, Each of the logic gate units includes a NOT gate, the NOT gate including a third transistor and a fourth transistor, the third transistor and the fourth transistor having different channel types; The source of the third transistor is connected to the first ground terminal, and the source of the fourth transistor is connected to the first power supply.

10. The test circuit according to claim 9, characterized in that, The first-stage logic gate unit of the ring oscillator circuit is a NAND gate unit, which includes a first input terminal and a second input terminal. The first input terminal is used to receive an enable control signal; the second input terminal is connected to the output terminal of the last logic gate unit of the ring oscillator circuit.

11. The test circuit according to any one of claims 1-10, characterized in that, The test unit also includes a load circuit; The common drain of the first transistor and the second transistor is connected to the input terminal of the load circuit, and the output terminal of the load circuit is left floating.

12. The test circuit according to claim 11, characterized in that, The load circuit includes a plurality of logic gate units cascaded in sequence.

13. The test circuit according to any one of claims 1-10, characterized in that, The test circuit also includes a current measuring element; The current measuring element is connected to the second test terminal and is used to measure the current value flowing into or out of the second test terminal.

14. The test circuit according to any one of claims 1-10, characterized in that, The number of logic gates in the ring oscillator circuit is odd, and the number of test units is less than or equal to the number of logic gates.

15. A testing method, characterized in that, The method, applied to the test circuit according to any one of claims 1 to 14, comprises: Provide an enable control signal for the ring oscillator circuit; When both the first logic gate unit and the second logic gate unit are OR gates, and the first transistor is an NMOS and the second transistor is a PMOS, the current value flowing out of the second test terminal is detected, and the current value flowing out of the second test terminal is determined as the driving current of the second transistor. Alternatively, if both the first and second logic gate units are AND gates, and the first transistor is a PMOS, When the second transistor is an NMOS, the current value flowing into the second test terminal is detected, and the current value flowing into the second test terminal is determined as the driving current of the second transistor.

16. A testing device, characterized in that, include: At least one processor and memory; The memory stores computer-executed instructions; The at least one processor executes computer execution instructions stored in the memory, causing the at least one processor to perform the test method as described in claim 15.

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