A data interaction system and method based on FPGA

Abstract

In a FPGA-based data interaction system and method provided in the specification, at least comprising FPGA and other components, the FPGA is used to respond to the first data needed to be transmitted to the other components, to determine whether the FPGA writes the first data into the storage unit by detecting the state of the obtained storage unit, to restore the state to the idle state after writing and to send the transmission information to the other components, the other components determine the second data according to the transmission information, detect the state of the storage unit, and write the second data into the storage unit when the state is the idle state, and restore the state to the idle state after writing. The storage unit in the FPGA is used to replace the dual-port RAM, the data interaction between the FPGA and the other components is realized, the hardware cost is reduced and the circuit connection is simplified, and through detecting the state of the storage unit, the conflict of simultaneously writing data by the components in the system is avoided.

Description

Technical Field

[0001] This specification relates to the field of communication technology, and in particular to a data interaction system and method based on FPGA. Background Technology

[0002] With the rapid development of communication technology, Field Programmable Gate Arrays (FPGAs) are widely used in various fields such as communications and industrial control due to their hardware programmability. In systems using FPGAs, other components frequently need to interact with the FPGA, and the way this data interaction occurs affects the data processing efficiency of each component. Furthermore, data processing efficiency is a key factor influencing the real-time performance and overall performance of systems using FPGAs.

[0003] Currently, in systems using FPGAs, the data interaction between the FPGA and other components is usually conducted asynchronously using dual-port RAM as the data communication medium. This is achieved by storing the output results of the FPGA after processing the data in the dual-port RAM. However, the introduction of dual-port RAM results in high hardware costs and complex circuit implementation.

[0004] Based on this, this specification provides a data interaction system and method based on FPGA. Summary of the Invention

[0005] This specification provides an FPGA-based data interaction system and method to partially solve the aforementioned problems existing in the prior art.

[0006] The following technical solution is adopted in this specification:

[0007] This specification provides a data interaction system based on FPGA, the system comprising:

[0008] The FPGA is used to respond to first data that needs to be transmitted to the other components, detect the state of the storage unit within the FPGA; when the storage unit is in an idle state, adjust the state of the storage unit to a write state, and restore the storage unit to an idle state after writing the first data to the storage unit; when the storage unit is in a write state, wait for the storage unit to restore to an idle state, adjust the state of the storage unit to a write state, and restore the storage unit to an idle state after writing the first data to the storage unit; and send transmission information to the other components.

[0009] The other components are configured to, in response to the transmission information, read the first data from the storage unit and process the first data to obtain the second data; detect the state of the storage unit of the FPGA; when the storage unit is in an idle state, adjust the state of the storage unit to a write state, and restore the storage unit to an idle state after writing the second data into the storage unit; when the storage unit is in a write state, wait for the storage unit to restore to an idle state, adjust the state of the storage unit to a write state, and restore the storage unit to an idle state after writing the second data into the storage unit.

[0010] Optionally, the other components are also configured to send processing completion information to the FPGA after the second data is written to the storage unit;

[0011] The FPGA is also used to receive the processing completion information and execute services based on the second data stored in the storage unit.

[0012] Optionally, the FPGA includes at least a first pin and a second pin, which are respectively connected to the other components;

[0013] The FPGA is used to detect the level of the second pin and determine whether the level falls within a preset level range. If yes, it is determined that the other components are writing data to the storage unit and the storage unit is in a write state. If no, it is determined that the storage unit is in an idle state.

[0014] The other components are configured to adjust the level of the second pin to the preset level range when the storage unit is in an idle state, so as to write the second data into the storage unit, and to adjust the level of the second pin after the second data has been written, so that the level of the second pin does not fall into the preset level range.

[0015] Optionally, the FPGA is configured to adjust the level of the first pin to the preset level range when it is determined that the storage cell is in an idle state, so as to write the first data into the storage cell, and to adjust the level of the first pin after the first data is written so that the level of the first pin does not fall into the preset level range.

[0016] The other components are used to detect the level of the first pin and determine whether the level falls within a preset level range. If yes, it is determined that the FPGA is writing data to the storage unit and the storage unit is in a write state. If no, it is determined that the storage unit is in an idle state.

[0017] Optionally, the other components are also configured to detect the state of the FPGA's storage unit in response to the second data to be transmitted to the FPGA; when the storage unit is in an idle state, adjust the state of the storage unit to a write state, and restore the storage unit to an idle state after writing the second data to the storage unit; when the storage unit is in an idle state, wait for the storage unit to restore to an idle state, adjust the state of the storage unit to a write state, and restore the storage unit to an idle state after writing the second data to the storage unit.

[0018] Optionally, the FPGA writes the first data into the storage unit via an internal bus, and the other components write the second data into the storage unit via a preset SDIO interface.

[0019] Optionally, there may be multiple other components, and for each other component, the other component is connected to the first pin and the second pin respectively;

[0020] For each other component, the other component is also used to determine the level of the second pin and whether the level falls within a preset level range. If yes, it is determined that at least one other component in the system is writing data to the storage unit and the storage unit is in a write state. If no, it is determined that the storage unit is in an idle state.

[0021] This specification provides a data interaction method based on FPGA, which is applied to the FPGA in a system. The method includes:

[0022] In response to the first data that needs to be transmitted to the other components, the state of the FPGA's storage unit is detected;

[0023] When the storage unit is in an idle state, the state of the storage unit is adjusted to a write state, and the storage unit is restored to an idle state after the first data is written to the storage unit;

[0024] When the storage unit is in a write state, wait for the storage unit to return to an idle state, then adjust the state of the storage unit to a write state, and restore the storage unit to an idle state after writing the first data into the storage unit.

[0025] This specification provides a data interaction method based on FPGA, which is applied to other components in the system. The method includes:

[0026] The response requires the transmission of the second data to the FPGA, and the status of the FPGA's memory cells is detected.

[0027] When the storage unit is in an idle state, the state of the storage unit is adjusted to a write state, and the storage unit is restored to an idle state after the second data is written to the storage unit;

[0028] When the storage unit is in a write state, wait for the storage unit to return to an idle state, then adjust the state of the storage unit to a write state, and after writing the second data into the storage unit, restore the storage unit to an idle state.

[0029] This specification provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements an FPGA-based data interaction method.

[0030] The above-mentioned technical solutions adopted in this specification can achieve the following beneficial effects: In the FPGA-based data interaction system provided in this specification, at least an FPGA and other components are included. The FPGA is used to respond to the first data that needs to be transmitted to the other components, detect the state of the storage unit in the FPGA, and determine whether the FPGA should write the first data to the storage unit according to the state. After writing, the state is restored to an idle state and transmission information is sent to the other components. The other components determine the second data according to the transmission information and detect the state of the storage unit. If the state is an idle state, the second data is written to the storage unit and the state is restored to an idle state after writing.

[0031] By using the storage cells in the FPGA to replace the dual-port RAM, data interaction between the FPGA and other components is realized, reducing hardware costs and avoiding circuit connections between the FPGA and the storage cells. At the same time, by detecting the status of the storage cells, conflicts caused by simultaneous data writing by the storage cells are avoided. Attached Figure Description

[0032] The accompanying drawings, which are included to provide a further understanding of this specification and form part of this specification, illustrate exemplary embodiments and are used to explain this specification, but do not constitute an undue limitation thereof. In the drawings:

[0033] Figure 1 This is a schematic diagram of the structure of an FPGA-based data interaction system provided in this specification;

[0034] Figure 2 This specification provides a schematic diagram of a data interaction system structure with multiple other components.

[0035] Figure 3 This specification provides a flowchart illustrating an FPGA-based data interaction method applied to an FPGA in a data interaction system.

[0036] Figure 4 This document provides a flowchart illustrating the application of an FPGA-based data interaction method to other components in a data interaction system.

[0037] Figure 5 This is a schematic diagram of an FPGA-based data interaction device provided in this specification;

[0038] Figure 6 This is a schematic diagram of an FPGA-based data interaction device provided in this specification. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of this specification clearer, the technical solutions of this specification will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this specification, and not all of them. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this specification.

[0040] Currently, in FPGA-based systems, the introduction of dual-port RAM increases system hardware costs and complicates system circuit implementation due to the large number of address lines, data lines, and control signal lines in dual-port RAM. Therefore, this specification provides an FPGA-based data interaction system. In this system, the storage function of dual-port RAM is implemented through the FPGA's internal storage unit; the status of the storage unit is detected by components via pin connections; the FPGA writes first data to the storage unit via its internal bus, and other components write second data to the storage unit via a designated SDIO interface. Based on the above, the FPGA and other components in the system can interact with each other via the storage unit, replacing dual-port RAM.

[0041] The technical solutions provided in the various embodiments of this specification are described in detail below with reference to the accompanying drawings.

[0042] Figure 1This is a schematic diagram of an FPGA-based data interaction system provided in this specification. The system consists of an FPGA and other components. Based on this, in the FPGA-based data interaction system provided in this specification, a storage unit is defined within the FPGA to store data that needs to be transmitted to other components. The FPGA implements data writing functionality through its internal bus, and other components implement data writing functionality through a pre-configured SDIO interface. Furthermore, each component in this data interaction system needs to detect the status of the storage unit based on the levels of a first pin and a second pin. Of course, this specification does not limit the specific business logic that this data interaction system is used for; it can be configured according to actual needs.

[0043] In one or more embodiments of this specification, in order to replace dual-port RAM and reduce hardware costs and circuit complexity, data interaction between the FPGA and other components is achieved through a storage unit within the FPGA. At the same time, the state of the storage unit is detected by detecting the levels of the first and second pins.

[0044] Specifically, the FPGA response needs to transmit the first data to other components and detect the status of the memory cells within the FPGA.

[0045] Determine if the storage cell is in an idle state. If so, adjust the state of the storage cell to write state and write the first data into the storage cell. After writing is completed, restore the state of the storage cell to the idle state. If not, wait for the state of the storage cell to be restored to the idle state until the writing of the first data is completed. The FPGA writes the first data into the storage cell through the internal bus.

[0046] After the write operation is complete, the FPGA sends transmission information to other components and restores the state of the storage cell to an idle state. The transmission information is used to inform other components that "the FPGA has completed the writing of the first data".

[0047] Other components respond to the transmission information sent by the FPGA, read the first data written by the FPGA from the storage unit, and determine the second data based on the first data.

[0048] Other components detect the state of the storage unit to determine whether it is idle. If so, they adjust the state of the storage unit to write and write the second data into the storage unit. After writing, they restore the state of the storage unit to idle. If not, they wait for the storage unit to return to idle until the writing of the second data is completed. The other components write the second data into the storage unit through the configured SDIO interface. The SDIO interface can provide different operating modes, such as single-wire mode, four-wire mode, and eight-wire mode, to meet the interface requirements of different types of other components. This specification does not limit the specific operating mode of the SDIO interface and can be set according to requirements. This specification also does not limit the specific type of other components, such as microcontrollers, central processing units, etc.

[0049] After the write operation is completed, a processing completion message is sent to the FPGA, and the state of the storage cell is restored to the idle state. The transmission message is used to inform the FPGA that "other components have completed the writing of the second data".

[0050] The FPGA receives the processing completion information and executes the service based on the second data written to the storage unit.

[0051] Figure 1 The FPGA-based data interaction system shown consists of an FPGA and other components. The FPGA's internal memory cells replace the storage function of dual-port RAM, reducing hardware costs. Furthermore, the FPGA's internal bus enables read / write operations on the memory cells, eliminating the need for circuit connections. The SDIO interface facilitates read / write operations on the memory cells for other components, reducing data and address lines and simplifying the circuit connections for read / write functionality. In summary, the configuration of FPGA memory cells, internal bus, and SDIO interface ensures synchronous read / write operations (but not simultaneous writes) between the FPGA and other components to improve data transmission speed while reducing hardware resource overhead and simplifying the complexity of the data interaction system's circuit implementation.

[0052] It's important to note that the control unit and storage unit within an FPGA are separate and can operate in parallel. For example, within one clock cycle, the control unit might be calculating the next operation, while the storage unit can read or write data within the same clock cycle. In other words, besides allocating a portion of the FPGA's storage units to implement dual-port RAM functionality, other FPGA units can perform other functions without interfering with each other. Therefore, by using a portion of the FPGA's storage units to replace the dual-port RAM's storage function, and storing the first and second data for data interaction between the FPGA and other components, hardware costs and circuit connections are reduced.

[0053] In addition, by setting the first and second pins, and connecting the first and second pins of the FPGA and other components, the status of each component in the data interaction system can be detected, avoiding conflicts caused by simultaneous writing by the FPGA and other components.

[0054] Specifically, the FPGA detects the level of the second pin to determine if it falls within a preset level range. If it does, it determines that other components are writing second data to the memory cell, and the memory cell is in a write state. If not, it determines that the memory cell is in an idle state. When the memory cell is in an idle state, other components can adjust the level of the second pin to the preset level range to write the second data to the memory cell, and after the second data is written, adjust the level of the second pin to prevent it from falling within the preset level range. This specification does not limit the specific preset level range; it can be set according to requirements.

[0055] Other components detect the level of the first pin and determine whether the level falls within a preset level range. If so, it is determined that the FPGA is writing data to the memory cell, and the memory cell is in a write state. If not, it is determined that the memory cell is in an idle state. When it is determined that the memory cell is in an idle state, the FPGA can adjust the level of the first pin to the preset level range to write the first data to the memory cell, and after the first data is written, adjust the level of the first pin so that it does not fall within the preset level range.

[0056] It should be noted that the above-described method for detecting the status of a storage unit is relatively simple. Besides detecting the voltage levels of the first and second pins, the status log of the storage unit can also be obtained through polling. Specifically, the log records a write status before each data write operation and an idle status after data is written. This log informs all components in the system of the current status of the storage unit. For example, if all components currently record the storage unit as idle in their logs, then the storage unit is in an idle state and data writing can be performed.

[0057] In addition, if other components are not unique, data interaction between components can be achieved by setting an SDIO interface for each other component. To avoid simultaneous data writing by various components in the data interaction system, each component in the data interaction system must be connected to at least the first and second pins of the FPGA for detecting the status of the memory cell. All other components besides the FPGA should also be configured with an SDIO interface for data interaction with the memory cell. If there are multiple other components, each other component is connected to the first and second pins of the FPGA, as follows:

[0058] Specifically, for each other component, the other component is also used to detect the level of the second pin and determine whether the level falls within a preset level range. If so, it is determined that at least one other component in the system is writing data to the storage unit, that is, the storage unit is in a write state. If not, it is determined that the storage unit is in an idle state.

[0059] like Figure 2 As shown, taking two other components as an example, for each other component, it should be connected to at least the first and second pins of the FPGA.

[0060] It should be noted that when the data interaction system includes several other components that need to interact with the FPGA, data interaction between the FPGA and other components can also be achieved through circuit design. This specification does not limit this, and the specific settings can be configured according to requirements. For example, taking a high level as the preset level range, a high level on the first pin of the FPGA indicates that data is being written to the FPGA's forward memory cell; a high level on the second pin of the FPGA indicates that at least one other component in the data interaction system is writing data to its forward memory cell. For each other component, a high level on the second pin of that other component indicates that data is being written to its forward memory cell; a high level on the first pin of that other component indicates that data is being written to the FPGA or at least one other component in the data interaction system is writing data to its forward memory cell. The determination that at least one component is writing data to its forward memory cell, i.e., determining that at least one of the levels on the first pin of the FPGA and the second pins of each other component is at least high, can be implemented using an OR gate. The preset level range mentioned above can also be a low level, in which case the determination that at least one of the levels on the first pin of the FPGA and the second pins of each other component is at least low can be implemented using an AND gate. Of course, this is only to illustrate that this manual does not limit the number of components that interact with the FPGA; the specific number can be set according to actual needs.

[0061] Figure 3 This specification provides a data interaction method based on FPGA, and a flowchart illustrating its application in an FPGA-based data interaction system, including the following steps:

[0062] S200: In response to the first data that needs to be transmitted to the other components, detect the state of the FPGA's storage unit.

[0063] S202: When the storage unit is in an idle state, the state of the storage unit is adjusted to a write state, and the storage unit is restored to an idle state after the first data is written to the storage unit.

[0064] S204: When the storage unit is in a write state, wait for the storage unit to return to an idle state, then adjust the state of the storage unit to a write state, and restore the storage unit to an idle state after writing the first data into the storage unit.

[0065] Similarly, the specific details of steps S200 to S204 in the above method can be found in the previous system description, and will not be described in detail here.

[0066] based on Figure 3 This specification provides an FPGA-based data interaction method applied to an FPGA in a data interaction system. In response to the first data to be transmitted to other components, the FPGA detects the state of its memory cells. If the memory cell is in an idle state, the FPGA can adjust its state to a write state and write the first data. After writing, the memory cell is restored to an idle state. If the memory cell is in a write state, it waits for the state to return to an idle state before adjusting its state to a write state and writing the first data again. After writing, the memory cell is restored to an idle state. By using memory cells partitioned within the FPGA, the storage function of dual-port RAM is replaced. Furthermore, by detecting the state of the memory cells and the FPGA's internal bus, the FPGA's read and write functions are realized, reducing hardware costs and avoiding circuit connections during data interaction.

[0067] Figure 4 This specification provides a flowchart illustrating the application of an FPGA-based data interaction method with other components in a data interaction system, including the following steps:

[0068] S300: In response to the second data that needs to be transmitted to the FPGA, detect the state of the FPGA's storage unit.

[0069] S302: When the storage unit is in an idle state, the state of the storage unit is adjusted to a write state, and the storage unit is restored to an idle state after the second data is written to the storage unit.

[0070] S304: When the storage unit is in a write state, wait for the storage unit to return to an idle state, then adjust the state of the storage unit to a write state, and restore the storage unit to an idle state after writing the second data into the storage unit.

[0071] Similarly, the specific details of steps S300 to S304 in the above method can be found in the previous system description, and will not be described in detail here.

[0072] based on Figure 4 This specification provides an FPGA-based data interaction method applied to other components in a data interaction system. Responding to second data that needs to be transmitted to the FPGA, the method detects the state of the FPGA's storage cells. If the storage cell is in an idle state, other components can adjust its state to a write state and write the second data. After writing, the storage cell's state is restored to an idle state. If the storage cell is in a write state, the method waits for its state to return to an idle state before adjusting it to a write state and writing the second data. After writing, the storage cell's state is restored to an idle state. By using storage cells partitioned within the FPGA, the storage function of dual-port RAM is replaced. Furthermore, by detecting the storage cell's state and using the configured SDIO interface, read and write functions for other components are achieved, reducing hardware costs and simplifying the circuit connections for implementing read and write functions.

[0073] According to one or more embodiments of this specification, a data interaction method based on FPGA is provided. Based on the same idea, this specification also provides a corresponding data interaction device based on FPGA, such as... Figure 5 and Figure 6 As shown.

[0074] Figure 5 This is a schematic diagram of an FPGA-based data interaction device provided in this specification. The device is applied to an FPGA in a system that executes the FPGA-based data interaction method, and includes:

[0075] The first detection module 400 responds to the first data that needs to be transmitted to the other components and detects the state of the FPGA's storage unit;

[0076] The first write module 401 adjusts the state of the storage unit to a write state when the storage unit is in an idle state, and restores the storage unit to an idle state after writing the first data into the storage unit.

[0077] The second write module 402, when the storage unit is in the write state, waits for the storage unit to return to the idle state, adjusts the state of the storage unit to the write state, and restores the storage unit to the idle state after writing the first data into the storage unit.

[0078] Figure 6 This is a schematic diagram of an FPGA-based data interaction device provided in this specification. The device is applied to other components in a system that executes the FPGA-based data interaction method, including:

[0079] The second detection module 500 responds to the second data that needs to be transmitted to the FPGA and detects the state of the FPGA's storage unit;

[0080] The third write module 501 adjusts the state of the storage unit to write state when the storage unit is in an idle state, and restores the storage unit to an idle state after writing the second data into the storage unit.

[0081] The fourth write module 502, when the storage unit is in the write state, waits for the storage unit to return to the idle state, adjusts the state of the storage unit to the write state, and restores the storage unit to the idle state after writing the second data into the storage unit.

[0082] This specification also provides a computer-readable storage medium storing a computer program that can be used to execute the above-described... Figure 4 A data interaction method based on FPGA is provided.

[0083] Of course, in addition to software implementation, this specification does not exclude other implementation methods, such as logic devices or a combination of hardware and software. In other words, the execution subject of the following processing flow is not limited to each logic unit, but can also be hardware or logic devices.

[0084] In the 1990s, improvements to a technology could be clearly distinguished as either hardware improvements (e.g., improvements to the circuit structure of diodes, transistors, switches, etc.) or software improvements (improvements to the methodology). However, with technological advancements, many methodological improvements today can be considered direct improvements to the hardware circuit structure. Designers almost always obtain the corresponding hardware circuit structure by programming the improved methodology into the hardware circuit. Therefore, it cannot be said that a methodological improvement cannot be implemented using hardware physical modules. For example, a Programmable Logic Device (PLD) (such as a Field Programmable Gate Array (FPGA)) is such an integrated circuit whose logic function is determined by the user programming the device. Designers can program and "integrate" a digital system onto a PLD themselves, without needing chip manufacturers to design and manufacture dedicated integrated circuit chips. Furthermore, nowadays, instead of manually manufacturing integrated circuit chips, this programming is mostly implemented using "logic compiler" software. Similar to the software compiler used in program development, the original code before compilation must be written in a specific programming language, called a Hardware Description Language (HDL). There are many HDLs, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, and RHDL (Ruby Hardware Description Language). Currently, the most commonly used are VHDL (Very-High-Speed ​​Integrated Circuit Hardware Description Language) and Verilog. Those skilled in the art should understand that by simply performing some logic programming on the method flow using one of these hardware description languages ​​and programming it into an integrated circuit, the hardware circuit implementing the logical method flow can be easily obtained.

[0085] The controller can be implemented in any suitable manner. For example, it can take the form of a microprocessor or processor and a computer-readable medium storing computer-readable program code (e.g., software or firmware) executable by the (micro)processor, logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers. Examples of controllers include, but are not limited to, the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicon Labs C8051F320. A memory controller can also be implemented as part of the control logic of the memory. Those skilled in the art will also recognize that, in addition to implementing the controller in purely computer-readable program code form, the same functionality can be achieved by logically programming the method steps to make the controller take the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers. Therefore, such a controller can be considered a hardware component, and the means included therein for implementing various functions can also be considered as structures within the hardware component. Alternatively, the means for implementing various functions can be considered as both software modules implementing the method and structures within the hardware component.

[0086] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, a computer can be, for example, a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or any combination of these devices.

[0087] For ease of description, the above devices are described in terms of function, divided into various units. Of course, in implementing this specification, the functions of each unit can be implemented in one or more software and / or hardware.

[0088] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0089] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0090] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0091] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0092] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0093] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0094] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0095] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0096] This specification can be described in the general context of computer-executable instructions that are executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform a specific task or implement a specific abstract data type. This specification can also be practiced in distributed computing environments, where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0097] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0098] The above description is merely an embodiment of this specification and is not intended to limit this specification. Various modifications and variations can be made to this specification by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this specification should be included within the scope of the claims of this specification.

Claims

1. A data interaction system based on FPGA, characterized in that, The system includes at least an FPGA and other components, including: The FPGA is used to respond to first data that needs to be transmitted to the other components, detect the state of the storage unit within the FPGA; when the storage unit is in an idle state, adjust the state of the storage unit to a write state, and restore the storage unit to an idle state after writing the first data to the storage unit; when the storage unit is in a write state, wait for the storage unit to restore to an idle state, adjust the state of the storage unit to a write state, and restore the storage unit to an idle state after writing the first data to the storage unit; and send transmission information to the other components. The other components are configured to, in response to the transmission information, read the first data from the storage unit and process the first data to obtain the second data; detect the state of the storage unit of the FPGA; when the storage unit is in an idle state, adjust the state of the storage unit to a write state, and restore the storage unit to an idle state after writing the second data into the storage unit; when the storage unit is in a write state, wait for the storage unit to restore to an idle state, adjust the state of the storage unit to a write state, and restore the storage unit to an idle state after writing the second data into the storage unit.

2. The system as described in claim 1, characterized in that, The other components are also used to send processing completion information to the FPGA after the second data is written to the storage unit; The FPGA is also used to receive the processing completion information and execute services based on the second data stored in the storage unit.

3. The system as described in claim 1, characterized in that, The FPGA includes at least a first pin and a second pin, which are respectively connected to the other components; The FPGA is used to detect the level of the second pin and determine whether the level falls within a preset level range. If yes, it is determined that the other components are writing data to the storage unit and the storage unit is in a write state. If no, it is determined that the storage unit is in an idle state. The other components are configured to adjust the level of the second pin to the preset level range when the storage unit is in an idle state, so as to write the second data into the storage unit, and to adjust the level of the second pin after the second data has been written, so that the level of the second pin does not fall into the preset level range.

4. The system as described in claim 3, characterized in that, The FPGA is configured to adjust the level of the first pin to the preset level range when it is determined that the memory cell is in an idle state, so as to write the first data into the memory cell, and to adjust the level of the first pin after the first data is written so that the level of the first pin does not fall into the preset level range. The other components are used to detect the level of the first pin and determine whether the level falls within a preset level range. If yes, it is determined that the FPGA is writing data to the storage unit and the storage unit is in a write state. If no, it is determined that the storage unit is in an idle state.

5. The system as described in claim 1, characterized in that, The other components are also configured to, in response to second data to be transmitted to the FPGA, detect the state of the FPGA's storage unit; when the storage unit is in an idle state, adjust the state of the storage unit to a write state, and restore the storage unit to an idle state after writing the second data into the storage unit; when the storage unit is in an idle state, wait for the storage unit to restore to an idle state, adjust the state of the storage unit to a write state, and restore the storage unit to an idle state after writing the second data into the storage unit.

6. The system as described in claim 1, characterized in that, The FPGA writes the first data into the storage unit via its internal bus, while the other components write the second data into the storage unit via a preset SDIO interface.

7. The system as described in claim 4, characterized in that, There are multiple other components, and for each other component, the other component is connected to the first pin and the second pin respectively; For each other component, the other component is also used to detect the level of the second pin and determine whether the level falls within a preset level range. If yes, it is determined that at least one other component in the system is writing data to the storage unit and the storage unit is in a write state. If no, it is determined that the storage unit is in an idle state.

8. A data interaction method based on FPGA, characterized in that, The method is applied to the FPGA in the system, and the method includes: In response to the first data that needs to be transmitted to other components, the state of the FPGA's storage unit is detected; When the storage unit is in an idle state, the state of the storage unit is adjusted to a write state, and the storage unit is restored to an idle state after the first data is written to the storage unit; When the storage unit is in a write state, wait for the storage unit to return to an idle state, then adjust the state of the storage unit to a write state, and restore the storage unit to an idle state after writing the first data into the storage unit.

9. A data interaction method based on FPGA, characterized in that, The method is applied to other components in the system, and the method includes: The response requires the transmission of the second data to the FPGA, and the status of the FPGA's storage cells is detected. When the storage unit is in an idle state, the state of the storage unit is adjusted to a write state, and the storage unit is restored to an idle state after the second data is written to the storage unit; When the storage unit is in a write state, wait for the storage unit to return to an idle state, then adjust the state of the storage unit to a write state, and after writing the second data into the storage unit, restore the storage unit to an idle state.

10. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, which, when executed by a processor, implements the method described in claim 9.

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