Command scheduling method, flash memory device, and command scheduling system

Abstract

The embodiment of the application relates to the application field of storage devices, and discloses a command scheduling method, a flash memory device and a command scheduling system. The method comprises the following steps: obtaining a first read command in a first flash memory command queue; issuing a flash memory operation instruction corresponding to the first read command to a first plane, and obtaining at least one command after the first read command in the first flash memory command queue; when a second plane corresponding to a certain read command in the command is in an idle state, issuing the flash memory operation instruction of the corresponding read command to the second plane in parallel, so that at least two planes corresponding to the first flash memory command queue perform read operations in parallel. When the number of requirements of the flash memory command queue exceeds the hardware limit, the application can perform subsequent commands in the same flash memory command queue in parallel in advance, so that different planes sharing the same flash memory command queue can perform read operations in parallel, thereby improving the parallelism of flash memory read operations.

Description

Technical Field

[0001] This application relates to the field of storage device applications, and in particular to a command scheduling method, a flash memory device, and a command scheduling system. Background Technology

[0002] Flash memory devices, such as solid-state drives (SSDs), are storage devices that use semiconductor flash memory (NAND flash) as their medium. Their main components include the flash memory medium, the flash memory controller, and dynamic random access memory (DRAM). A key function of the flash memory controller is to act as a driver for the flash memory chips, performing storage operations, primarily erasing, writing, and reading.

[0003] As flash memory becomes increasingly complex, fixed flash controllers are finding it increasingly difficult to meet the flexible control requirements of flash memory. Some flash controllers have begun to add coprocessors (Coprocessing Center Process Unit, S-CPU) to optimize the flexibility of flash memory operation through a combination of hardware and software.

[0004] Currently, the flash controller supports asynchronous planar read parallel operations. After the upper-layer driver sends the command to the flash command queue, the coprocessor schedules all flash command queues in parallel so that multiple planes can perform read operations in parallel.

[0005] In the process of developing this application, the inventors discovered that the prior art has at least the following problems: In solid-state drives, especially for large-capacity solid-state drives, when the product of the number of flash memory chips and the number of planes of a flash memory chip is greater than the number of flash command queues, since the number of flash command queues cannot meet the needs of all planes to perform read operations in parallel, some planes can only share the same flash command queue, and different planes sharing the same flash command queue cannot perform read operations in parallel, thereby reducing the parallelism of the flash controller in performing read operations and failing to fully utilize the read bandwidth. Summary of the Invention

[0006] This application provides a command scheduling method, a flash memory device, and a command scheduling system, which can process subsequent commands in the same flash memory command queue in parallel in advance when the demand of the flash memory command queue exceeds the hardware limit, thereby improving the parallelism of flash memory read operations.

[0007] The embodiments of this application provide the following technical solutions:

[0008] In a first aspect, embodiments of this application provide a command scheduling method, which is applied to a flash memory device. The flash memory device includes flash memory chips and a flash memory command queue, and each flash memory chip includes several planes.

[0009] When the product of the number of flash memory chips and the number of planes contained in a flash memory chip is greater than the number of flash command queues,

[0010] Command scheduling methods include:

[0011] Retrieve the first read command from the first flash command queue;

[0012] Send the flash memory operation instruction corresponding to the first read command to the first plane, and obtain at least one command after the first read command in the first flash memory command queue, wherein the first plane is the plane corresponding to the first read command;

[0013] When the second plane corresponding to a certain read command in the command is in an idle state, the flash memory operation instruction corresponding to the read command is sent to the second plane in parallel so that at least two planes corresponding to the first flash memory command queue can perform read operations in parallel.

[0014] Secondly, embodiments of this application provide a flash memory device, including:

[0015] A flash memory controller is used to execute the command scheduling method of the first aspect;

[0016] At least one flash memory medium is communicatively connected to the flash memory controller.

[0017] Thirdly, embodiments of this application provide a command scheduling system, including:

[0018] The main processor is used to issue commands to the hardware modules;

[0019] The hardware module is used to sequentially load the commands sent by the main processor into different flash memory command queues;

[0020] Such as the flash memory device in the second aspect, used for parallel scheduling of flash command queues and processing read commands in each flash command queue.

[0021] Fourthly, embodiments of this application also provide a non-volatile computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, cause the processor to execute the command scheduling method as described in the first aspect.

[0022] The beneficial effects of this application embodiment are as follows: Unlike the prior art, this application embodiment provides a command scheduling method applied to a flash memory device. The flash memory device includes flash memory chips and a flash memory command queue. Each flash memory chip includes several planes, and the product of the number of flash memory chips and the number of planes contained in a flash memory chip is greater than the number of flash memory command queues. The method includes: obtaining a first read command from a first flash memory command queue; issuing a flash memory operation instruction corresponding to the first read command to a first plane, and obtaining at least one command after the first read command in the first flash memory command queue, wherein the first plane is the plane corresponding to the first read command; when a second plane corresponding to a certain read command in the commands is in an idle state, issuing a flash memory operation instruction corresponding to the read command to the second plane in parallel, so that at least two planes corresponding to the first flash memory command queue execute read operations in parallel.

[0023] By acquiring subsequent commands in advance during the processing of the first read command in the flash command queue, and issuing the corresponding flash operation instructions to the plane in parallel when the plane corresponding to the subsequent read command is in an idle state, this application can process subsequent commands in the same flash command queue in parallel in advance when the product of the number of flash chips and the number of planes contained in a flash chip is greater than the number of flash command queues, that is, when the required number of flash command queues exceeds the hardware limit. This allows different planes sharing the same flash command queue to execute read operations in parallel, thereby improving the parallelism of flash read operations. Attached Figure Description

[0024] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0025] Figure 1 This is a schematic diagram of the structure of a flash memory device provided in an embodiment of this application;

[0026] Figure 2 This is a schematic diagram of the structure of a flash memory controller provided in an embodiment of this application;

[0027] Figure 3 This is a schematic diagram of a command scheduling method provided in an embodiment of this application;

[0028] Figure 4 This is a schematic diagram of the allocation of a flash command queue provided in an embodiment of this application;

[0029] Figure 5 This is a schematic diagram of another flash command queue allocation provided in an embodiment of this application;

[0030] Figure 6 This is a schematic diagram of an instruction sequence and its corresponding flash memory plane-level behavior timing provided in an embodiment of this application;

[0031] Figure 7 This is a flowchart illustrating a command scheduling method provided in an embodiment of this application;

[0032] Figure 8 yes Figure 7 A detailed flowchart of step S702;

[0033] Figure 9 yes Figure 7 Detailed flowchart of step S703;

[0034] Figure 10 This is a complete flowchart illustrating a command scheduling method provided in an embodiment of this application;

[0035] Figure 11 This is a schematic diagram of another instruction sequence and corresponding flash plane-level behavior timing provided in an embodiment of this application;

[0036] Figure 12 This is a schematic diagram of another flash memory device provided in an embodiment of this application;

[0037] Figure 13 This is a schematic diagram of the structure of a command scheduling system provided in an embodiment of this application. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0039] It should be noted that, unless there is a conflict, the various features in the embodiments of this application can be combined with each other, all of which are within the protection scope of this application. Furthermore, although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than the module division in the device or the order in the flowchart. Moreover, the terms "first," "second," and "third" used in this application do not limit the data or execution order, but only distinguish identical or similar items with essentially the same function and effect.

[0040] The technical solution of this application will be described in detail below with reference to the accompanying drawings:

[0041] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of a flash memory device provided in an embodiment of this application;

[0042] like Figure 1 As shown, the flash memory device 100 includes a flash memory medium 110 and a controller 120 connected to the flash memory medium 110. The flash memory device 100 communicates with the host 200 via wired or wireless means to enable data exchange.

[0043] Flash memory medium 110, as the storage medium of flash memory device 100, is also called flash memory, NAND Flash, Flash memory or Flash chip. It is a type of storage device and is a non-volatile memory that can retain data for a long time even without a current supply. Its storage characteristics are equivalent to hard disk, which makes flash memory medium 110 the basis for the storage medium of various portable digital devices.

[0044] The controller 120 includes a processor 121, a cache 122, a flash memory controller 123, and an interface 124.

[0045] The processor 121 is connected to the cache 122, the flash memory controller 123, and the interface 124, respectively. The processor 121 can be connected to the cache 122, the flash memory controller 123, and the interface 124 via a bus or other means. The processor is used to run non-volatile software programs, instructions, and modules stored in the cache 122, thereby implementing any method embodiment of this application. Furthermore, through firmware development, it is also used to handle the core processing of the flash translation layer (FTL).

[0046] The buffer 122 is mainly used to buffer the read / write commands sent by the host 200 and the read or write data obtained from the flash memory medium 110 according to the read / write commands sent by the host 200.

[0047] The flash memory controller 123 is connected to the flash memory medium 110, the processor 121, and the cache 122. It is used to access the back-end flash memory medium 110 and manage various parameters and data I / O of the flash memory medium 110.

[0048] Interface 124 connects host 200, processor 121, and cache 122. It is used to receive data sent by host 200 or processor 121 to realize data transmission between host 200 and processor 121. Interface 124 can be a SATA-2 interface, SATA-3 interface, SAS interface, MSATA interface, PCI-E interface, NGFF interface, CFast interface, SFF-8639 interface, or M.2 NVME / SATA protocol.

[0049] Please see Figure 2 , Figure 2 This is a schematic diagram of the structure of a flash memory controller provided in an embodiment of this application;

[0050] In this embodiment of the application, in order to improve the overall write and read speed of the flash memory device, the flash memory controller is provided with multiple channels (CH), which support parallel operation.

[0051] like Figure 2 As shown, the flash memory controller includes multiple channels, such as channel 0 (CH 0), channel 1 (CH 1), ..., channel 15 (CH 15). Each channel (CH) includes a First-In-First-Out (FIFO) queue. Each channel (CH) has at least one flash memory chip (Die). For example, channel 0 (CH 0) has flash memory chip 0 (Die 0), flash memory chip 1 (Die 1), flash memory chip 2 (Die 2), and flash memory chip 3 (Die 3); channel 1 (CH 1) has flash memory chip 4 (Die 4), flash memory chip 5 (Die 5), flash memory chip 6 (Die 6), and flash memory chip 7 (Die 7), ...; channel 15 (CH 15) has flash memory chip 60 (Die 60), flash memory chip 61 (Die 61), flash memory chip 62 (Die 62), and flash memory chip 63 (Die 62). 63), in which multiple flash memory chips (dies) under the same channel share a set of control buses.

[0052] The First-In-First-Out (FIFO) queue is used to cache read and / or write commands, following the FIFO rule: the first command written to the queue is also the first command retrieved from the queue. A flash memory chip contains multiple flash dies, which are the basic units for receiving and executing flash commands. Each flash dies can only execute one command independently at a time.

[0053] Understandably, a key function of a flash memory controller is to act as a driver for flash memory chips (dies) to perform storage operations, primarily including erasing, writing, and reading. Erasing operations on flash memory media are performed in blocks, while writing and reading operations are performed in pages. A block typically contains hundreds or thousands of pages.

[0054] Specifically, after the flash memory controller issues the erase command and address, the flash memory medium begins to perform the erase operation, which usually takes several milliseconds.

[0055] Specifically, after the flash memory controller issues a write command, address, and transmits write data, the flash memory medium begins to perform the write operation, which typically takes hundreds of microseconds to several milliseconds.

[0056] Specifically, after the flash memory controller issues a read command and address, the flash memory begins the read operation, which typically takes tens of microseconds. Once the read operation is complete, the data is temporarily stored in the flash memory's buffer space. The flash memory controller can then begin transferring the read data, and the read command ends once the transfer is complete.

[0057] Furthermore, when the flash memory performs erase, write, or read operations, it is in a busy state and no longer accepts other erase or read / write commands. At this time, the flash memory controller can send a ReadStatus command to confirm whether the flash memory has completed the corresponding operation, and then confirm whether it can continue to send subsequent operation commands to the flash memory.

[0058] Specifically, after the flash memory controller sends commands and data to a flash memory chip (Die), the flash memory chip (Die) executes the commands and enters a busy state. The flash memory controller can send commands and data to other flash memory chips (Dies) through the control bus. After sending commands and data to other flash memory chips (Dies), the flash memory controller can send a Read Status command to check whether the flash memory chips (Dies) that were previously in a busy state have completed the corresponding commands. If they have completed them, subsequent commands can be sent to this flash memory chip (Die). In this way, the bus bandwidth can be fully utilized and the overall performance can be improved.

[0059] To improve the overall write or read speed of flash memory, the blocks within the flash memory are evenly divided into multiple planes. Flash memory typically includes 2, 4, 6, or 8 planes. Taking a flash memory with 4 planes as an example: Block 0, Block 4, Block 8, Block 12... are assigned to plane 0; Block 1, Block 5, Block 9, Block 13... are assigned to plane 1; Block 2, Block 6, Block 10, Block 14... are assigned to plane 2; and Block 3, Block 7, Block 11, Block 15... are assigned to plane 3.

[0060] Flash memory supports multi-plane parallel operations, such as simultaneously performing erase, write, or read operations on blocks 0, 1, 6, and 11. For batch or sequential read scenarios, multi-plane parallel read commands can typically be sent to the flash memory to improve read bandwidth. However, for random read scenarios, because the flash memory receives read commands at random times and in random plane positions, it is usually impossible to assemble multi-plane parallel read commands for distribution.

[0061] To improve read bandwidth in random read scenarios, more and more flash memory devices support asynchronous planar read parallel operations. For example, when a read command is issued to planar A and planar A has already started executing read operations and cannot continue to execute other commands, read commands can be issued to other plans, and different plans can execute read operations in parallel.

[0062] However, as flash memory performance improves and its functionality becomes more powerful and complex, fixed flash memory controllers are finding it increasingly difficult to meet the flexible control requirements of flash memory. Some flash memory controllers have begun to add coprocessors (Coprocessing Center Process Units, S-CPUs) to optimize the flexibility of flash memory operations through a combination of hardware and software. Flash memory controllers typically add several coprocessors (S-CPUs), each responsible for processing commands for one or more channels (CHs). After the upper-layer driver sends commands to the coprocessor, the coprocessor further parses the commands into a sequence of hardware instructions, which are then sent to a hardware queue (FIFO) for sequential execution. The coprocessor (S-CPU) is a processor developed and used to assist the central processing unit (CPU) in performing processing tasks that it cannot execute or that are inefficient or ineffective.

[0063] Please see Figure 3 , Figure 3 This is a schematic diagram of a command scheduling method provided in an embodiment of this application;

[0064] In this embodiment of the application, since the main processor is located in the host and the coprocessor (S-CPU) is located in the flash memory controller of the flash memory device, the two belong to different systems and commands (SQ) cannot be directly transmitted. Therefore, a command receiving module is set between the main processor and the coprocessor (S-CPU). The command receiving module is used to send the commands issued by the main processor to the coprocessor (S-CPU).

[0065] Each coprocessor (S-CPU) corresponds to at least one channel (CH). A channel (CH) includes multiple flash command queues (FQ SQFIFO). The number of flash command queues is limited by hardware and chip resources. The number of flash command queues in a channel (CH) is usually 32.

[0066] like Figure 3 As shown, the main processor issues n commands through a hardware first-in-first-out queue (FIFO). The commands in the hardware FIFO are in the following order: command 0 (SQ 0), command 1 (SQ 1), command 2 (SQ2), ..., command n (SQn). Each command contains channel (CH) information and flash queue (FQ) information.

[0067] The command receiving module determines the corresponding channel within the flash memory device based on the channel information of each command. For example, the channel corresponding to the command within the flash memory device could be channel 0 (CH 0), channel 1 (CH 1), ..., or channel 15 (CH 15). It also determines the corresponding flash command queue within the channel based on the flash queue information of the command. For example, the corresponding flash command queue within the channel could be flash command queue 0 (FQ 0 SQ FIFO), flash command queue 1 (FQ 1 SQ FIFO), ..., or flash command queue 31 (FQ 1 SQ FIFO). Therefore, the command receiving module routes each command to a different flash command queue, where the corresponding coprocessor (S-CPU) processes the command.

[0068] For flash memory devices that do not support asynchronous plane read operations, each flash command queue typically corresponds to one flash memory chip; for flash memory devices that support asynchronous plane read operations, each flash command queue typically corresponds to one physical plane within the flash memory chip.

[0069] In scenarios that support asynchronous planar read operations, based on the relationship between the product of the number of flash memory chips in the flash memory device and the number of planes contained in a flash memory chip, and the number of flash command queues, there are two cases:

[0070] When the product of the number of flash memory chips in a flash memory device and the number of planes contained in a flash memory chip is less than or equal to the number of flash command queues, for example, when the number of dies * the number of planes ≤ 32, the flash command queues are allocated one by one according to the planes, and the coprocessor (S-CPU) schedules all flash command queues in parallel in a time-slice polling manner.

[0071] Please see Figure 4 , Figure 4 This is a schematic diagram of the allocation of a flash command queue provided in an embodiment of this application;

[0072] Figure 4 The following example illustrates a flash memory device comprising eight flash memory chips (Die 0-Die 7), each containing four planes (Plane 0-Plane 3), and 32 flash command queues (FQ SQ FIFO).

[0073] like Figure 4As shown, several commands (SQ 0, SQ 1, SQ 2, SQ 3, SQ 4, ...) in a flash command queue (FQ SQ FIFO) correspond to the same plane. Flash command queue 0 (FQ 0 SQ FIFO) - Flash command queue 3 (FQ 3 SQ FIFO) correspond to planes 0 (Plane 0) - 3 (Plane 3) of flash chip 0 (Die 0), respectively; Flash command queue 4 (FQ 4 SQ FIFO) - Flash command queue 7 (FQ 7 SQ FIFO) correspond to planes 0 (Plane 0) - 3 (Plane 3) of flash chip 1 (Die 1), respectively; ...; Flash command queue 28 (FQ 28 SQ FIFO) - Flash command queue 31 (FQ31 SQ FIFO) correspond to planes 0 (Plane 0) - 3 (Plane 3) of flash chip 7 (Die 7), respectively.

[0074] The coprocessor (S-CPU) schedules flash command queues 0-31 in parallel using a time-slice polling method, enabling the flash memory to perform read operations in parallel using 8 dies * 4 planes.

[0075] When the product of the number of flash memory chips in a flash memory device and the number of planes contained in a single flash memory chip exceeds the number of flash command queues (for example, when the number of dies * the number of planes > 32), the number of flash command queues required for all planes to perform read operations in parallel exceeds the hardware-limited number of flash command queues. In this case, the number of flash command queues that the hardware can provide is insufficient to meet the needs of all planes performing read operations in parallel, and commands from some planes need to be sent to the same flash command queue.

[0076] Please see Figure 5 , Figure 5 This is a schematic diagram of another flash command queue allocation provided in an embodiment of this application;

[0077] Figure 5 The following example illustrates a flash memory device comprising 16 flash memory chips (Die 0-Die 15), each flash memory chip containing 4 planes (Plane 0-Plane 3), and 32 flash command queues (FQ SQ FIFO).

[0078] like Figure 5As shown, flash command queue 0 (FQ 0 SQ FIFO) corresponds to plane 0 and plane 2 of flash chip 0 (Die 0); flash command queue 1 (FQ 1 SQ FIFO) corresponds to plane 1 and plane 3 of flash chip 0 (Die 0); flash command queue 2 (FQ 2 SQ FIFO) corresponds to plane 0 and plane 2 of flash chip 1 (Die 1); ...; flash command queue 31 (FQ 31 SQ FIFO) corresponds to plane 1 and plane 3 of flash chip 15 (Die 15).

[0079] That is, plane 0 and plane 2 of each flash memory chip (Die) share the same flash command queue (FQ SQ FIFO), and plane 1 and plane 3 of each flash memory chip (Die) share the same flash command queue (FQ SQ FIFO).

[0080] In this case, although the coprocessor (S-CPU) can schedule flash command queues 0-31 in parallel, and the flash memory can perform read operations in parallel at a ratio of 16 dies * 4 planes, the 32 flash command queues can only support a parallelism of 16 dies * 2 planes, which cannot fully utilize the read bandwidth of the flash memory.

[0081] Please see Figure 6 , Figure 6 This is a schematic diagram of an instruction sequence and its corresponding flash memory plane-level behavior timing provided in an embodiment of this application;

[0082] Specifically, Figure 6 According to Figure 5 The instruction sequence obtained by scheduling the flash command queue in the flash memory is shown in the schematic diagram of the timing of the behavior at the flash plane level. Figure 6 Only the relevant instruction sequence and plane-level behavior timing diagram of flash chip 0 (Die 0) are shown, and the timing of the plane execution status query command is omitted.

[0083] Figure 6 The 'a' part in the text represents the sequence of instructions issued sequentially by the coprocessor (S-CPU) scheduling command. Figure 6 Part b in the diagram is a timing diagram of the flash memory plane-level behavior corresponding to the instruction sequence in part a. Here, Rd-cmd represents a read instruction, Rd-Data represents a read data transfer instruction, tRead represents the duration of the read operation within the flash memory, and Data represents the duration of the data transfer.

[0084] like Figure 6 As shown in part a, Die 0Plane 0SQ 0Rd-cmd represents the read instruction for command 0 (SQ 0) corresponding to plane 0 (Plane 0) within flash memory chip 0 (Die 0), and Die 0 Plane 0SQ 0Rd-Data represents the read data transfer instruction for command 0 (SQ 0) corresponding to plane 0 (Plane 0) within flash memory chip 0 (Die 0). The remaining instruction sequences are similar and will not be elaborated further here. Figure 6 As shown in part b, plane 2 in flash memory chip 0 (Die 0) can only start reading operations after the data transfer operation in plane 0 (Plane 0) is completed; plane 3 in flash memory chip 0 (Die 0) can only start reading operations after the data transfer operation in plane 1 (Plane 1) is completed. Therefore, plane 0 (Die 0) and plane 2 (Plane 2) in flash memory chip 0 (Die 0) cannot perform reading operations in parallel, and plane 1 (Plane 1) and plane 3 (Plane 3) cannot perform reading operations in parallel.

[0085] It can be seen that in scenarios that support asynchronous planar read operations, when the product of the number of flash memory chips in the flash memory device and the number of planars contained in a flash memory chip is greater than the number of flash command queues limited by the hardware, the number of flash command queues that the hardware can provide cannot meet the needs of all planars to execute read operations in parallel. Some planars can only use the same flash command queue, which will reduce the utilization rate of the parallelism of flash read operations.

[0086] For example, when a flash memory device includes 16 flash memory chips, each chip contains 4 planes, and the hardware-limited number of flash command queues is 32, the product of the number of flash memory chips and the number of planes per chip is 16 * 4 = 64. This means that 64 flash command queues are needed for the planes in the flash memory to perform read operations in complete parallelism. Since the hardware only has 32 flash command queues, only two planes can share one queue, resulting in a 50% reduction in the parallelism of flash read operations.

[0087] Based on this, this application provides a command scheduling method to process subsequent commands in the same flash command queue in parallel in advance when the required number of flash command queues exceeds the hardware limit, so that different planes sharing the same flash command queue can perform read operations in parallel, thereby improving the parallelism of flash execution of read operations.

[0088] Please see Figure 7 , Figure 7 This is a flowchart illustrating a command scheduling method provided in an embodiment of this application;

[0089] This command scheduling method is applied to a flash memory device. Specifically, the flash memory device includes a flash memory controller, and the flash memory controller includes a coprocessor. The command scheduling method is applied to the coprocessor.

[0090] In this embodiment, the flash memory device includes flash memory chips and flash memory command queues, with each flash memory chip comprising a plurality of planes. In this embodiment, the number of flash memory chips, the number of planes contained in a flash memory chip, and the number of flash memory command queues can all be set by those skilled in the art according to actual conditions, and are not limited in this embodiment. For example, the number of flash memory chips is 16, the number of planes contained in a flash memory chip is 4, and the number of flash memory command queues is 32.

[0091] like Figure 7 As shown, the command scheduling method includes:

[0092] Step S701: Obtain the first read command in the first flash memory command queue;

[0093] Specifically, the coprocessor retrieves the first command from any flash command queue, for example, the first command from the first flash command queue, and determines whether the first command is a read command. If the first command is a read command, it proceeds to step S702 for subsequent processes. Here, the first flash command queue is any flash command queue in the flash memory device. Each flash command queue corresponds to at least two planes in a flash memory chip, meaning that commands from at least two planes reside in the same flash command queue. For example: Figure 5 The flash command queue 0 corresponds to plane 0 and plane 2 in flash chip 0.

[0094] If the first command is not a read command, for example, if the first command is an erase command or a write command, then the first command is retrieved from the flash memory command queue, and the corresponding erase command processing flow or write command processing flow is executed. The erase command processing flow and write command processing flow are not described in detail here.

[0095] Step S702: Send the flash memory operation instruction corresponding to the first read command to the first plane, and obtain at least one command after the first read command in the first flash memory command queue;

[0096] Specifically, the first plane is the plane corresponding to the first read command. When the first command in the first flash command queue is a read command, the coprocessor sends the flash operation instruction corresponding to the first read command to the first plane corresponding to the first read command in the first flash command queue, and obtains at least one command in the first flash command queue that follows the first read command.

[0097] For details, please refer to Figure 8 , Figure 8 yes Figure 7 A detailed flowchart of step S702;

[0098] like Figure 8 As shown, step S702: Send the flash memory operation instruction corresponding to the first read command to the first plane, and obtain at least one command after the first read command in the first flash memory command queue, including:

[0099] Step S721: Convert the first read command to obtain the flash memory operation instruction corresponding to the first read command;

[0100] Specifically, the coprocessor retrieves the first read command from the first flash command queue and converts it to obtain the flash operation instruction corresponding to the first read command. The flash operation instruction includes a read instruction and a read data transfer instruction. The read instruction is used to instruct the plane to start executing the read operation, and the read data transfer instruction is used to instruct the plane to transfer the read data.

[0101] Step S722: Send the read instruction corresponding to the first read command to the first plane so that the first plane can start to execute the read operation according to the read instruction corresponding to the first read command.

[0102] Specifically, the coprocessor issues a read instruction corresponding to the first read command to the first plane, so that the first plane can perform a read operation according to the read instruction.

[0103] Furthermore, after the coprocessor issues the read instruction to the first plane, the coprocessor acquires at least one command following the first read command from the first flash memory command queue. The number of commands acquired can be set by those skilled in the art according to actual circumstances, and is not limited in this embodiment.

[0104] In this embodiment of the application, after the step of obtaining at least one command following the first read command in the first flash memory command queue, the method further includes: determining whether to issue a flash memory operation instruction based on the command type of each command. The command type includes a read command, an erase command, or a write command.

[0105] The process of determining whether to issue a flash memory operation instruction based on the command type of each command includes steps S1-S6:

[0106] Step S1: Determine whether each command is a read command;

[0107] Specifically, the coprocessor sequentially determines whether each of the at least one acquired command is a read command. If a command is a read command, proceed to step S2; if a command is not a read command, i.e., it is an erase command or a write command, proceed to step S3.

[0108] Step S2: Determine whether the second plane corresponding to the read command is in an idle state;

[0109] Specifically, if a command is a read command, the coprocessor determines whether the second plane corresponding to the read command is in an idle state by judging whether the second plane is currently processing the command. Each read command corresponds to a plane, and the second plane is the plane corresponding to a certain read command in the first flash command queue after the first read command. The second plane is different from the first plane.

[0110] If the second plane is currently processing a command, the coprocessor determines that the second plane corresponding to the read command is not in an idle state, i.e., it is in a busy state, and proceeds to step S3; if the second plane is not currently processing a command, the coprocessor determines that the second plane corresponding to the read command is in an idle state, and proceeds to step S6.

[0111] Step S3: Determine whether the read data transfer operation corresponding to all read commands in the first flash memory command queue has been completed;

[0112] Specifically, read operations include data reading operations and data transfer operations. If a command is an erase command or a write command, the coprocessor determines whether the data transfer operations corresponding to all read commands in the first flash memory command queue have been completed; or, if a command is a read command and the second plane corresponding to the read command is not in an idle state, the coprocessor determines whether the data transfer operations corresponding to all read commands in the first flash memory command queue have been completed.

[0113] If the coprocessor determines that the read data transfer operation corresponding to all read commands in the first flash memory command queue has not been completed, then proceed to step S4; if the coprocessor determines that the read data transfer operation corresponding to all read commands in the first flash memory command queue has been completed, then proceed to step S5.

[0114] Step S4: After the read waiting time for performing a read data operation on any plane is reached, send a query status command to that plane;

[0115] Specifically, if the coprocessor determines that the read data transfer operation corresponding to all read commands in the first flash memory command queue has not been completed, the coprocessor sends a query status command to any plane corresponding to the first flash memory command queue after the read waiting time for the read data operation has elapsed. The query status command is used to confirm whether the plane has completed the read data operation. The read waiting time can be set by those skilled in the art according to actual conditions, and is not limited in this embodiment.

[0116] Step S5: Execute the erase command or write command;

[0117] Specifically, if the coprocessor determines that the read data transfer operation corresponding to all read commands in the first flash memory command queue has been completed, it indicates that all read commands in the first flash memory command queue have been processed, and the coprocessor executes the erase command or write command.

[0118] Step S6: Send the corresponding read command flash operation instruction to the second plane in parallel, so that at least two planes corresponding to the flash command queue can perform read operations in parallel.

[0119] Specifically, if the second plane is idle, the coprocessor retrieves the read command from the first flash memory command queue and issues the corresponding read instruction to the second plane in parallel, so that the first plane and the second plane corresponding to the first flash memory command queue can perform the read operation in parallel. This step is similar to step S703 and will not be described again here.

[0120] Step S703: When the second plane corresponding to a certain read command in the command is in an idle state, the flash memory operation instruction of the corresponding read command is sent to the second plane in parallel so that at least two planes corresponding to the first flash memory command queue can perform read operations in parallel.

[0121] Specifically, when the second plane corresponding to a certain read command in at least one of the acquired commands is in an idle state, the coprocessor sends the read instruction corresponding to the read command to the second plane in parallel, so that at least two planes corresponding to the first flash command queue can perform read operations in parallel.

[0122] Please see Figure 9 , Figure 9 yes Figure 7 Detailed flowchart of step S703;

[0123] like Figure 9 As shown, step S703: When the second plane corresponding to a certain read command in the command is in an idle state, the flash memory operation instruction corresponding to the read command is sent to the second plane in parallel, so that at least two planes corresponding to the first flash memory command queue can perform read operations in parallel, including:

[0124] Step S731: If the second plane corresponding to the Nth read command in the command is not currently processing a command, then the second plane is determined to be in an idle state;

[0125] Specifically, if a read command among at least one of the acquired commands corresponds to a plane that is not currently processing commands, the coprocessor determines that the plane is in an idle state. For example, if the plane corresponding to the Nth read command is the second plane, and the second plane is not currently processing commands, the coprocessor determines that the second plane is in an idle state. Here, N is a positive integer.

[0126] Step S732: Convert the Nth read command to obtain the flash memory operation instruction corresponding to the Nth read command;

[0127] Specifically, when the plane corresponding to a certain read command is determined to be in an idle state, the coprocessor retrieves the read command from the first flash memory command queue and converts it to obtain the corresponding flash memory operation instruction. For example, when the second plane is in an idle state, the coprocessor converts the Nth read command to obtain the read instruction and read data transfer instruction corresponding to the Nth read command.

[0128] Step S733: Send the flash memory operation instruction corresponding to the Nth read command to the second plane in parallel, so that the second plane can start to execute the read operation according to the flash memory operation instruction corresponding to the Nth read command.

[0129] Specifically, the coprocessor sends the read instruction corresponding to the read command in parallel to the corresponding plane, so that the corresponding plane can execute the read operation according to the read instruction. For example, the coprocessor sends the read instruction corresponding to the Nth read command in parallel to the second plane, so that the second plane can start executing the read operation according to the read instruction. Furthermore, the plane is in a busy state after it starts executing the read operation.

[0130] In this embodiment of the application, after the step of issuing the flash memory operation instruction corresponding to the Nth read command in parallel to the second plane, the method further includes steps S7-S13:

[0131] Step S7: Determine whether there are any subsequent commands in the current first flash memory command queue;

[0132] Specifically, if there are subsequent commands in the current first flash memory command queue, proceed to step S8; if there are no subsequent commands in the current first flash memory command queue, that is, the current first flash memory command queue is empty, proceed to step S11.

[0133] Step S8: Determine whether the next command after the Nth read command is a read command;

[0134] Specifically, if the next command after the Nth read command is a read command, then the command is determined to be the (N+1)th read command, and proceed to step S9; if the next command after the Nth read command is an erase command or a write command, then proceed to step S11.

[0135] Step S9: Determine whether the third plane corresponding to the (N+1)th read command is in an idle state;

[0136] Specifically, if the third plane corresponding to the (N+1)th read command is in an idle state, proceed to step S10; if the third plane corresponding to the (N+1)th read command is in a busy state, proceed to step S11. Here, the third plane is the plane corresponding to the (N+1)th read command, and it is different from the second plane.

[0137] Step S10: Send the flash memory operation instruction corresponding to the N+1th read command to the third plane in parallel;

[0138] Specifically, the coprocessor retrieves the (N+1)th read command from the first flash memory command queue and sends the corresponding read instruction to the third plane in parallel, so that the first plane, the second plane, and the third plane corresponding to the first flash memory command queue can perform the read operation in parallel.

[0139] Step S11: Determine whether the read data transfer operation corresponding to all read commands in the first flash memory command queue has been completed;

[0140] Specifically, when the current first flash memory command queue is empty, or the next command after the Nth read command is an erase command or a write command, or the plane corresponding to the N+1th read command is in a busy state, the coprocessor determines whether the read data transfer operation corresponding to all read commands in the first flash memory command queue has been completed.

[0141] If the read data transfer operation corresponding to all read commands in the first flash memory command queue has not been completed, proceed to step S12; if the read data transfer operation corresponding to all read commands in the first flash memory command queue has been completed, proceed to step S13.

[0142] Step S12: After the read waiting time for performing a read data operation is reached on any plane corresponding to the first flash command queue, send a query status command to that plane;

[0143] Specifically, if the read data transfer operation corresponding to all read commands in the first flash memory command queue has not been completed, the coprocessor will send a query status command to any plane corresponding to the first flash memory command queue after the read waiting time for the read data operation has expired, in order to confirm whether the plane has completed the read data operation.

[0144] Furthermore, if the plane that has reached the read waiting time has not completed the read data operation, the coprocessor continues to send a query status command to the plane until the plane completes the read data operation; if the plane that has reached the read waiting time has completed the read data operation, the coprocessor sends a read data transfer instruction to the plane to enable the plane to perform a read data transfer operation, thereby completing the current read command and returning to step S7.

[0145] Step S13: Execute the erase command or write command.

[0146] Specifically, if the coprocessor determines that all read commands in the first flash memory command queue have completed their read data transfer operations, then the coprocessor executes an erase command or a write command.

[0147] In this embodiment of the application, the method further includes: after a read data transmission operation is performed on a certain plane, if other planes corresponding to the first flash command queue are all in an idle state, then the first read command in the current first flash command queue is retrieved again, and a flash operation instruction is sent to the corresponding plane.

[0148] Specifically, after a read data transfer operation is performed on a plane corresponding to the first flash memory command queue, if all other planes corresponding to the first flash memory command queue are idle, the coprocessor retrieves the first read command from the current first flash memory command queue and issues a flash operation instruction to the plane corresponding to the first read command. Then, it retrieves at least one command after the first read command from the current first flash memory command queue and proceeds to step S703. It can be understood that the current first flash memory command queue is the first flash memory command queue that has already retrieved several commands.

[0149] In this embodiment of the application, the method further includes: after a read data transmission operation is performed on a certain plane, if at least one plane corresponding to the first flash command queue is in a busy state, then the next command in the first flash command queue is obtained; when the next command is a read command and the third plane corresponding to the next command is in an idle state, the flash operation instruction corresponding to the next command is sent to the third plane in parallel.

[0150] Specifically, after a read data transfer operation is performed on a plane corresponding to the first flash command queue, if at least one plane corresponding to the first flash command queue is in a busy state, for example, when the read waiting time for the read data operation on at least one plane has not been reached, the coprocessor obtains the next command in the first flash command queue, and when the next command is a read command and the third plane corresponding to the next command is in an idle state, it sends the flash operation instruction corresponding to the next command to the third plane in parallel.

[0151] In this embodiment, the number of flash command queues is at least two, and the method further includes: scheduling each flash command queue in parallel based on time-slice polling. Specifically, the coprocessor processes several commands in one flash command queue within one time slice, and processes several commands in the next flash command queue within the next time slice; when not all commands in a flash command queue have been executed, the commands in that flash command queue are continued to be executed after polling all flash command queues. The number of time slices and flash command queues can be set by those skilled in the art according to actual conditions, and is not limited in this embodiment.

[0152] Please see Figure 10 , Figure 10 This is a complete flowchart illustrating a command scheduling method provided in an embodiment of this application;

[0153] Figure 10 The following explanation is based on the example of one command being acquired each time, and one flash command queue corresponding to two planes.

[0154] like Figure 10 As shown, the complete flow of this command scheduling method includes:

[0155] Step S1001: Determine whether the first flash memory command queue is empty;

[0156] Specifically, it determines whether there are any subsequent commands in the current first flash memory command queue. If there are no subsequent commands in the current first flash memory command queue, i.e., the first flash memory command queue is empty, the process ends; if there are subsequent commands in the current first flash memory command queue, i.e., the first flash memory command queue is not empty, then proceed to step S1002.

[0157] Step S1002: Determine whether the first command in the first flash memory command queue is a read command;

[0158] Specifically, if the first command in the first flash memory command queue is not a read command, for example, if the first command is an erase command or a write command, then proceed to step S1003; if the first command in the first flash memory command queue is a read command, then proceed to step S1004.

[0159] Step S1003: Execute the erase command or write command processing flow;

[0160] Specifically, if the first command is an erase command or a write command, the coprocessor will retrieve the first command from the flash memory command queue and execute the corresponding erase command processing flow or write command processing flow.

[0161] Step S1004: Send the flash memory operation instruction corresponding to the first read command to the first plane;

[0162] Specifically, the coprocessor retrieves the first read command from the first flash memory command queue and issues the corresponding read instruction to the first plane, so that the first plane can perform a read operation according to the read instruction.

[0163] Step S1005: Determine if there are any subsequent commands in the current first flash memory command queue;

[0164] Specifically, if there are subsequent commands in the current first flash memory command queue, proceed to step S1006; if there are no subsequent commands in the current first flash memory command queue, that is, the current first flash memory command queue is empty, proceed to step S1009.

[0165] Step S1006: Determine whether the next command in the first flash memory command queue is a read command;

[0166] Specifically, if the next command after the first read command in the first flash memory command queue is a read command, then the command is recorded as the second read command, and the process proceeds to step S1007; if the next command after the first read command in the first flash memory command queue is an erase command or a write command, then the process proceeds to step S1009.

[0167] Step S1007: Determine whether the second plane corresponding to the second read command is in an idle state;

[0168] Specifically, if the second plane corresponding to the second read command is in an idle state, proceed to step S1008; if the second plane corresponding to the second read command is in a busy state, proceed to step S1009.

[0169] Step S1008: Send the read instruction corresponding to the second read command to the second plane in parallel;

[0170] Specifically, the coprocessor retrieves the second read command from the first flash memory command queue and issues the corresponding read instruction to the second plane in parallel, so that the first plane and the second plane corresponding to the first flash memory command queue can perform the read operation in parallel. Further, after completing step S1008, the process returns to step S1005 to process the remaining commands in the first flash memory command queue.

[0171] Step S1009: Determine whether the read data transfer operation corresponding to all read commands in the first flash memory command queue has been completed;

[0172] Specifically, when the current first flash command queue is empty, or the next command after the first read command in the first flash command queue is an erase command or a write command, or the plane corresponding to the second read command is in a busy state, the coprocessor determines whether the read data transfer operation corresponding to all read commands in the first flash command queue has been completed.

[0173] If the read data transfer operation corresponding to all read commands in the first flash memory command queue has not been completed, then proceed to step S1010; if the read data transfer operation corresponding to all read commands in the first flash memory command queue has been completed, then the coprocessor determines that all commands in the first flash memory command queue have been processed and ends the process. Further, the coprocessor selects a flash memory command queue from other flash memory command queues of the flash memory device and repeats the complete process of the command scheduling method.

[0174] Step S1010: Determine whether the read waiting time for a certain plane to perform a read data operation has been reached;

[0175] Specifically, if the read waiting time for any plane corresponding to the first flash memory command queue to perform a read data operation is reached, then proceed to step S1011; if the read waiting time for any plane corresponding to the first flash memory command queue to perform a read data operation is not reached, then repeat step S1010 until the read waiting time for any plane to perform a read data operation is reached, then proceed to step S1011.

[0176] Step S1011: Send a query status command to the plane where the read waiting time has been reached;

[0177] Specifically, the coprocessor sends a status query command to the plane where the read wait time has been reached to confirm whether the plane has completed the data read operation.

[0178] For example, if the read waiting time for the first plane to perform a read data operation is reached, the coprocessor sends a status query command to the first plane to confirm whether the first plane has completed the read data operation.

[0179] Understandably, if the read waiting time for the second plane to perform the read data operation has not been reached at this time, then after completing step S1013 and returning to step S1001 or step S1005 to start the next round of the process, we will go to step S1010 to determine whether the read waiting time for a certain plane to perform the read data operation has been reached. If the read waiting time for the second plane to perform the read data operation is reached in the next round of step S1010, then the coprocessor sends a query status command to the second plane.

[0180] Step S1012: Determine whether the plane has completed the data reading operation;

[0181] Specifically, if the state of the plane that has reached the read waiting time is in the Ready state, the coprocessor determines that the plane has completed the read data operation and proceeds to step S1013; if the state of the plane that has reached the read waiting time is not in the Ready state, the coprocessor determines that the plane has not completed the read data operation and continues to send a query status command to the plane until the state of the plane is in the Ready state, that is, the plane has completed the read data operation.

[0182] Step S1013: Send a read data transmission command to the plane;

[0183] Specifically, if the plane that has been waiting for the read time has completed the read data operation, the coprocessor sends a read data transfer instruction to that plane so that the plane can perform a read data transfer operation, thereby completing the current read command and returning to step S1005.

[0184] For example, the first flash command queue corresponds to two planes, namely the first plane and the second plane. If the plane where the read waiting time is reached is the first plane, and the first plane has completed the read data operation, then the coprocessor sends a read data transfer instruction to the first plane in step S1013 so that the first plane can perform the read data transfer operation, thereby completing the processing of the first read command.

[0185] At this time, the first plane is in an idle state. If the second plane has no command being processed, the coprocessor determines that the second plane is in an idle state and returns to step S1001. If the coprocessor has sent the read instruction corresponding to the second read command to the second plane, and the second plane has a command being processed, the coprocessor determines that the second plane is in a busy state and returns to step S1005.

[0186] Understandable, Figure 10 Fetching only one command in advance after the first read command in the same flash command queue can reduce the computational power consumption of coprocessing, but this application is not limited to fetching only one command in advance. When the coprocessing computing power is sufficient, those skilled in the art can fetch multiple subsequent commands in advance according to the actual situation and select appropriate read commands for parallel processing in advance.

[0187] at the same time, Figure 10 This application takes the example of two planes sharing the same flash command queue, but it is not limited to this. When the product of the number of flash chips and the number of planes contained in a flash chip is larger, the required read parallelism is higher. Those skilled in the art can set more planes to share the same flash command queue according to the actual situation.

[0188] In this embodiment, by querying subsequent read commands in the flash command queue in advance when processing the current read command in a certain flash command queue, and processing the subsequent read commands in parallel in advance when it is confirmed that the plane corresponding to the subsequent read command is different from that of the current read command, this application can process subsequent commands in the same flash command queue in parallel in advance when the product of the number of flash chips and the number of planes contained in a flash chip is greater than the number of flash command queues, that is, when the required number of flash command queues exceeds the hardware limit. This allows different planes sharing the same flash command queue to perform read operations in parallel, thereby improving the parallelism of flash memory performing read operations in continuous read scenarios or random read scenarios.

[0189] Please see Figure 11 , Figure 11 This is a schematic diagram of another instruction sequence and corresponding flash plane-level behavior timing provided in an embodiment of this application;

[0190] In this embodiment of the application, the flash memory device includes 16 flash memory chips, each flash memory chip contains 4 planes (Plane 0-Plane 3), and the number of flash command queues is 32, with two planes sharing one flash command queue.

[0191] The main processor sequentially issues commands to each plane (Plane 0-Plane 3) within flash memory chip 0 (Die 0): Plane 0 Command 0 (SQ 0), Plane 1 Command 0 (SQ 0), Plane 2 Command 0 (SQ 0), Plane 3 Command 0 (SQ 0), Plane 0 Command 1 (SQ 1), Plane 1 Command 1 (SQ 1), Plane 2 Command 1 (SQ 1), Plane 3 Command 1 (SQ 1), Plane 0 Command 2 (SQ 2), Plane 1 Command 2 (SQ 2), Plane 2 Command 2 (SQ 2), Plane 3 Command 2 (SQ 2), ...

[0192] Furthermore, the hardware module sequentially loads the aforementioned commands into different flash memory command queues. Specifically, the commands in flash memory command queue 0 are, in order: Plane 0 SQ0, Plane 1 SQ0, Plane 0 SQ1, Plane 1 SQ1, Plane 0 SQ2, Plane 1 SQ2, ...; the commands in flash memory command queue 1 are, in order: Plane 2 SQ0, Plane 3 SQ0, Plane 2 SQ1, Plane 3 SQ1, Plane 2 SQ2, Plane 3 SQ2, ...

[0193] Furthermore, the coprocessor schedules each flash command queue and converts the read commands within it into flash operation instructions (i.e., Figure 11 The instruction sequence in the memory is used to send flash memory operation instructions to the corresponding plane.

[0194] Specifically, Figure 11 This diagram illustrates the sequence of instructions issued by the coprocessor and the timing of behavior at the flash memory plane level in a continuous read scenario. Figure 11 Only the relevant instruction sequence and plane-level behavior timing diagram of flash chip 0 (Die 0) are shown, and the timing of the plane execution status query command is omitted.

[0195] Figure 11 The 'a' part in the diagram represents the sequence of instructions issued sequentially by the coprocessor scheduling command. Figure 11 Part b in the diagram is a timing diagram of the flash memory plane-level behavior corresponding to the instruction sequence in part a. Here, Rd-cmd represents a read instruction, Rd-Data represents a read data transfer instruction, tRead represents the duration of the read operation within the flash memory, and Data represents the duration of the data transfer.

[0196] like Figure 11 As shown in section a, the coprocessor can issue read instructions for planes 0, 1, 2, and 3 in parallel. For example... Figure 11 As shown in part b, planes 0, 1, 2, and 3 within flash memory chip 0 (Die0) can perform read operations in parallel, without each plane needing to wait for other planes to complete data transfer operations.

[0197] Combination Figure 6In a continuous read scenario where the product of the number of flash memory chips and the number of planes contained in a flash memory chip is greater than the number of flash command queues, this application improves the parallelism of flash read operations by nearly 1 times by querying subsequent read commands in the flash command queue in advance when processing the current read command in a certain flash command queue, and processing the subsequent read commands in parallel in advance when it is confirmed that the planes corresponding to the subsequent read commands and the current read commands are different.

[0198] In this embodiment, a command scheduling method is provided, applied to a flash memory device. The flash memory device includes flash memory chips and flash memory command queues. Each flash memory chip includes several planes, and the product of the number of flash memory chips and the number of planes contained in a flash memory chip is greater than the number of flash memory command queues. The method includes: obtaining the first read command in any flash memory command queue; issuing a flash memory operation instruction corresponding to the first read command to a first plane, and obtaining at least one command in the flash memory command queue after the first read command, wherein the first plane is the plane corresponding to the first read command; when a second plane corresponding to a certain read command in the commands is in an idle state, issuing a flash memory operation instruction for the corresponding read command to the second plane in parallel, so that at least two planes corresponding to the flash memory command queues execute read operations in parallel.

[0199] By acquiring subsequent commands in advance during the processing of the first read command in the flash command queue, and issuing the corresponding flash operation instructions to the plane in parallel when the plane corresponding to the subsequent read command is in an idle state, this application can process subsequent commands in the same flash command queue in parallel in advance when the product of the number of flash chips and the number of planes contained in a flash chip is greater than the number of flash command queues, that is, when the required number of flash command queues exceeds the hardware limit. This allows different planes sharing the same flash command queue to execute read operations in parallel, thereby improving the parallelism of flash read operations.

[0200] Please see Figure 12 , Figure 12 This is a schematic diagram of another flash memory device provided in an embodiment of this application;

[0201] like Figure 12 As shown, the flash memory device 100 includes a flash memory controller 123 and at least one flash memory medium 110. The flash memory device 100 also includes flash memory chips and flash memory command queues. Each flash memory chip includes several planes, and the product of the number of flash memory chips and the number of planes contained in a single flash memory chip is greater than the number of flash memory command queues.

[0202] The flash memory controller 123 is used to execute the command scheduling method in any of the above embodiments, for example: obtaining the first read command in any flash memory command queue; issuing a flash memory operation instruction corresponding to the first read command to a first plane, and obtaining at least one command after the first read command in the flash memory command queue, wherein the first plane is the plane corresponding to the first read command; when the second plane corresponding to a certain read command in the command is in an idle state, issuing a flash memory operation instruction of the corresponding read command to the second plane in parallel, so that at least two planes corresponding to the flash memory command queue can perform read operations in parallel.

[0203] The flash memory controller 123 includes at least one coprocessor, each coprocessor being used to schedule in parallel a plurality of flash memory command queues in at least one channel, and to process read commands in each flash memory command queue. Specifically, the coprocessor is used to execute the command scheduling method in any of the above embodiments.

[0204] Flash memory medium 110 is communicatively connected to flash memory controller 123 and is used to acquire flash memory operation instructions and, based on the flash memory operation instructions, control at least two planes corresponding to a flash memory command queue to perform read operations in parallel.

[0205] In this application embodiment, a flash memory device is provided, comprising a flash memory controller and at least one flash memory medium. By using the flash memory controller to execute the command scheduling method in any of the above embodiments, this application can pre-process subsequent commands in the same flash memory command queue in parallel when the product of the number of flash memory chips and the number of planes contained in a flash memory chip exceeds the number of flash memory command queues, i.e., when the required number of flash memory command queues exceeds hardware limitations. This allows different planes sharing the same flash memory command queue to perform read operations in parallel, thereby improving the parallelism of flash memory read operations.

[0206] Please see Figure 13 , Figure 13 This is a schematic diagram of the structure of a command scheduling system provided in an embodiment of this application;

[0207] like Figure 13 As shown, the command scheduling system 130 includes a main processor 131, a hardware module 132, and a flash memory device 100. The hardware module 132 is communicatively connected to both the main processor 131 and the flash memory device 100.

[0208] The main processor 131 is connected to the hardware module 132 and is used to issue commands to the hardware module 132. Specifically, the main processor 131 issues commands to the hardware module 132 through a hardware first-in-first-out queue. Each command includes a queue name field, which identifies the flash memory command queue corresponding to the command.

[0209] Hardware module 132, connected to main processor 131 and flash memory device 100, is used to sequentially mount commands sent by main processor 131 into different flash memory command queues. Specifically, hardware module 132 mounts each command into the corresponding flash memory command queue according to the queue name field in each command, in the order they are received.

[0210] The flash memory device 100 is connected to the hardware module 132 for parallel scheduling of flash memory command queues and processing of read commands in each flash memory command queue. Specifically, the flash memory device 100 includes at least one coprocessor for parallel scheduling of each flash memory command queue and processing of read commands in each flash memory command queue.

[0211] In this application embodiment, a command scheduling system is provided, comprising a main processor, hardware modules, and flash memory devices. This application enables the pre-processing of subsequent commands within the same flash memory command queue when the product of the number of flash memory chips and the number of planes contained in a single flash memory chip exceeds the number of flash memory command queues—that is, when the demand for flash memory command queues exceeds hardware limitations. This allows different planes sharing the same flash memory command queue to execute read operations in parallel, thereby improving the parallelism of flash memory read operations.

[0212] This application also provides a non-volatile computer storage medium storing computer-executable instructions that are executed by one or more processors, such as executing the command scheduling method in any of the above method embodiments, for example, executing the steps described above.

[0213] The apparatus or device embodiments described above are merely illustrative. The unit modules described as separate components may or may not be physically separate, and the components shown as module units may or may not be physical units; that is, they may be located in one place or distributed across multiple network module units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0214] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented using software plus a general-purpose hardware platform, or of course, using hardware. Based on this understanding, the above technical solutions, in essence or the parts that contribute to the related technology, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., including several instructions for a computer device (which may be a personal computer, server, or network device, etc.) to execute the various embodiments or some parts of the embodiments.

[0215] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of this application as described above. For the sake of brevity, they are not provided in detail; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A command scheduling method, characterized in that, The method is applied to a flash memory device, which includes flash memory chips and a flash memory command queue, and each flash memory chip includes several planes; When the product of the number of flash memory chips and the number of planes contained in a flash memory chip is greater than the number of flash command queues, The method includes: Retrieve the first read command from the first flash command queue; Send the flash memory operation instruction corresponding to the first read command to the first plane, and obtain at least one command after the first read command in the first flash memory command queue, wherein the first plane is the plane corresponding to the first read command; When the second plane corresponding to a certain read command in the command is in an idle state, the flash memory operation instruction corresponding to the Nth read command is sent to the second plane in parallel, so that at least two planes corresponding to the first flash memory command queue can perform read operations in parallel. The read operation includes data reading operation and data transfer reading operation; After the step of issuing the flash memory operation instruction corresponding to the Nth read command in parallel to the second plane, the method further includes: If the current first flash command queue is empty, or the next command after the Nth read command is an erase command or a write command, or the plane corresponding to the N+1th read command is in a busy state, determine whether the read data transfer operation corresponding to all read commands in the first flash command queue has been completed. If the read data transfer operation corresponding to all read commands in the first flash memory command queue has not been completed, then after the read waiting time for the read data operation is reached on any plane corresponding to the first flash memory command queue, a query status command is sent to that plane to confirm whether the plane has completed the read data operation. If the read waiting time is reached before the plane has completed the read data operation, continue to send query status commands to that plane until the plane has completed the read data operation; If the plane that has been waiting for the read operation to complete has finished performing the read operation, a read data transfer instruction is sent to that plane to enable it to perform the read data transfer operation, thereby completing the current read command.

2. The method according to claim 1, characterized in that, The flash memory operation instruction corresponding to the first read command issued to the first plane includes: The first read command is converted to obtain the flash memory operation instruction corresponding to the first read command, wherein the flash memory operation instruction includes a read instruction; A read instruction corresponding to the first read command is sent to the first plane so that the first plane can start executing the read operation according to the read instruction corresponding to the first read command.

3. The method according to claim 1, characterized in that, After the step of acquiring at least one command in the first flash memory command queue following the first read command, the method further includes: Determine whether each of the commands is a read command; If one of the commands is a read command, then determine whether the second plane corresponding to the read command is in an idle state; If a command is an erase command or a write command, then determine whether the read data transfer operation corresponding to all read commands in the first flash memory command queue has been completed. If all read commands in the first flash memory command queue have completed their read data transfer operations, then the erase command or write command is executed.

4. The method according to claim 3, characterized in that, When the second plane corresponding to a certain read command in the command is in an idle state, the flash memory operation command corresponding to the Nth read command is sent to the second plane in parallel, including: If the second plane corresponding to the Nth read command in the command is not currently processing a command, then the second plane is determined to be in an idle state; The Nth read command is converted to obtain the flash memory operation instruction corresponding to the Nth read command; The flash memory operation instruction corresponding to the Nth read command is sent to the second plane in parallel, so that the second plane starts to execute the read operation according to the flash memory operation instruction corresponding to the Nth read command.

5. The method according to claim 1, characterized in that, The method further includes: After a read data transfer operation is performed on a certain plane, if all other planes corresponding to the first flash command queue are in an idle state, the first read command in the current first flash command queue is retrieved again, and a flash operation instruction is sent to the corresponding plane. After a read data transfer operation is performed on a certain plane, if at least one plane corresponding to the first flash command queue is busy, then the next command in the first flash command queue is obtained. When the next command is a read command and the third plane corresponding to the next command is in an idle state, the flash memory operation instruction corresponding to the next command is sent to the third plane in parallel.

6. The method according to any one of claims 1-5, characterized in that, The number of flash command queues is at least two, and the method further includes: Based on a time-slice polling method, each of the aforementioned flash command queues is scheduled in parallel, specifically including: Process several commands in one flash command queue within one time slice, and process several commands in the next flash command queue within the next time slice; If not all commands in a flash command queue have been executed, the commands in that flash command queue will continue to be executed after polling all flash command queues.

7. A flash memory device, characterized in that, include: Flash memory controller, configured to perform the method according to any one of claims 1-6; At least one flash memory medium is communicatively connected to the flash memory controller.

8. The flash memory device of claim 7, wherein the flash memory controller includes at least one coprocessor, each coprocessor being configured to schedule in parallel a plurality of flash memory command queues in at least one channel, and to process read commands in each of the flash memory command queues.

9. A command scheduling system, characterized in that, include: The main processor connects to the hardware module and is used to issue commands to the hardware module. A hardware module, connected to the main processor and the flash memory device as described in claim 7 or 8, is used to sequentially load commands sent by the main processor into different flash memory command queues. The flash memory device as described in claim 7 or 8 includes a connected hardware module for parallel scheduling of the flash memory command queues and processing read commands in each of the flash memory command queues.

Images