Circuits for generating pseudo-random numbers and pseudo-random number generators

Abstract

The application relates to the technical field of pseudo-random number generation, and discloses a circuit for generating a pseudo-random number. The circuit for generating the pseudo-random number comprises a feedback shift register circuit, which comprises a plurality of feedback shift registers connected in sequence and is configured to shift a pseudo-random number sequence; and a multiplexing circuit, which is connected with the feedback shift register circuit and is configured to select part or all of the feedback shift registers in the feedback shift register circuit to form a feedback loop so as to output a target pseudo-random number sequence. The circuit can adjust the generation rate of the pseudo-random number, so that the generation speed of the pseudo-random sequence can be improved in a short time. The application further discloses a pseudo-random number generator.

Description

Technical Field

[0001] This application relates to the field of pseudo-random number generation technology, and for example to a circuit and a pseudo-random number generator for generating pseudo-random numbers. Background Technology

[0002] Random number generators are widely used in integrated circuits, and pseudo-random number generators (or deterministic random sequence generators) play a very important role. Whether it is generating pseudo-random sequences based on a specific seed or providing post-processing for the entropy source of a true random number generator, pseudo-random numbers need to be generated.

[0003] Related technologies typically employ linear feedback shift registers (LFSRs) to generate pseudo-random numbers. These registers have a simple circuit structure, low area overhead, and are suitable for low-cost IC circuits. However, traditional LFSRs have a slow update speed, making it difficult to improve the generation speed of pseudo-random sequences in a short period.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.

[0006] This disclosure provides a circuit and a pseudo-random number generator for generating pseudo-random numbers, which can adjust the generation rate of pseudo-random numbers to improve the generation speed of pseudo-random sequences in a short time.

[0007] In some embodiments, the circuit for generating pseudo-random numbers includes: a feedback shift register circuit, including a plurality of feedback shift registers connected in series, configured to shift and generate a pseudo-random number sequence; and a multiplexer circuit, connected to the feedback shift register circuit, configured to select some or all of the feedback shift registers in the feedback shift register circuit to form a feedback loop, so as to output a target pseudo-random number sequence.

[0008] Optionally, the multiplexing circuit includes a multiplexer, wherein: the output of the multiplexer is connected to the first feedback shift register in the feedback shift register circuit; the first input of the multiplexer is connected to the upper path of one or more feedback shift registers in the feedback shift register circuit to form an XOR upper loop; the second input of the multiplexer is connected to the lower path of one or more feedback shift registers in the feedback shift register circuit to form an XOR lower loop; the multiplexing circuit is configured to select either the XOR upper loop or the XOR lower loop as the feedback loop.

[0009] Optionally, the multiplexing circuit includes multiple multiplexers, each multiplexer including at least a head multiplexer and intermediate multiplexers, wherein: a head multiplexer is inserted before the first feedback shift register in the feedback shift register circuit, and intermediate multiplexers are inserted between two adjacent feedback shift registers at one or more preset positions in the feedback shift register circuit to form a feedback loop.

[0010] Optionally, the output of the first multiplexer is connected to the first feedback shift register in the feedback shift register circuit, and the output of the intermediate multiplexer is connected to the middle feedback shift register in the feedback shift register circuit; the first input of the first multiplexer is connected to the upper path of one or more feedback shift registers in the feedback shift register circuit located at the beginning of the series connection, forming a first XOR upper loop; the first input of the intermediate multiplexer is connected to the upper path of one or more feedback shift registers in the feedback shift register circuit located at the end of the series connection, forming a second XOR upper loop; the second input of the first multiplexer and the second input of the intermediate multiplexer are respectively connected to the lower path of one or more feedback shift registers in the feedback shift register circuit, forming a total XOR lower loop; the multiplexing circuit is configured to select the first XOR upper loop and the second XOR upper loop as feedback loops, or to select the total XOR lower loop as feedback loops.

[0011] Optionally, the input value of the first input terminal of the first multiplexer is the XOR output of the upper path of the first preset number of feedback shift registers in the feedback shift register circuit; and / or, the input value of the second input terminal of the first multiplexer is the XOR output of the lower path of the second preset number of feedback shift registers in the feedback shift register circuit; wherein, the first preset number of feedback shift registers is located in the series front path of the feedback shift register circuit.

[0012] Optionally, the intermediate multiplexer includes a first intermediate multiplexer, wherein: the input value of the first input terminal of the first intermediate multiplexer is the XOR output of the upper path of a third preset number of feedback shift registers in the feedback shift register circuit; and / or, the input value of the second input terminal of the first intermediate multiplexer is the XOR output of the lower path of a fourth preset number of feedback shift registers in the feedback shift register circuit; wherein the third preset number of feedback shift registers is located at the end of the series connection of the feedback shift register circuit.

[0013] Optionally, the intermediate multiplexer includes a plurality of second intermediate multiplexers, wherein: the input value of the first input terminal of the second intermediate multiplexer is the XOR output of the upper path of the fifth preset number of feedback shift registers in the feedback shift register circuit; and / or, the input value of the second input terminal of the second intermediate multiplexer is the XOR output of the lower path of the sixth preset number of feedback shift registers in the feedback shift register circuit; wherein the series path of the feedback shift register circuit includes a plurality of series branches connected in sequence, and the first input terminal of each second intermediate multiplexer corresponds to one series branch.

[0014] Optionally, if there is only one preset position, the multiple feedback shift registers are divided into two serial branches, and the preset position is located between the two serial branches; if there are multiple preset positions, the multiple feedback shift registers are divided into (i+1) serial branches, and the preset position is set between every two serial branches; where i is the number of preset positions.

[0015] In some embodiments, the circuit for generating pseudo-random numbers further includes: a control circuit connected to the multiplexing circuit and configured to output a control signal to cause the multiplexing circuit to select some or all of the feedback shift registers in the feedback shift register circuit to form a feedback loop.

[0016] In some embodiments, the pseudo-random number generator includes: a generator body; and circuitry for generating pseudo-random numbers as described above, mounted on the generator body.

[0017] The circuit and pseudo-random number generator provided in this disclosure can achieve the following technical effects:

[0018] By selecting some or all of the feedback shift registers in the feedback shift register circuit using a multiplexer circuit, the feedback loops formed by these registers can be flexibly switched, resulting in target pseudo-random number sequences of different lengths, periods, or characteristics at the output of the feedback shift register circuit. This allows for adjustment of the pseudo-random number generation rate by selecting different feedback loops, thereby increasing the generation speed of pseudo-random sequences in a short time.

[0019] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0020] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein:

[0021] Figure 1 This is a schematic diagram of the structure of a circuit for generating pseudo-random numbers provided in an embodiment of this disclosure;

[0022] Figure 2 This is a schematic diagram of another circuit for generating pseudo-random numbers provided in an embodiment of this disclosure;

[0023] Figure 3 This is a schematic diagram of another circuit for generating pseudo-random numbers provided in an embodiment of this disclosure;

[0024] Figure 4 This is a schematic diagram of another circuit for generating pseudo-random numbers provided in an embodiment of this disclosure;

[0025] Figure 5 This is a schematic diagram of another circuit for generating pseudo-random numbers provided in an embodiment of this disclosure;

[0026] Figure 6 This is a structural block diagram of a pseudo-random number generator provided in an embodiment of this disclosure.

[0027] Figure label:

[0028] 100. Pseudo-random number generator; 300. Generator itself;

[0029] 200. Circuits used to generate pseudo-random numbers;

[0030] 10. Feedback shift register circuit; 101. Feedback shift register;

[0031] 20. Multiplexing circuit; 201. First multiplexer; 202. Intermediate multiplexer; 2021. First intermediate multiplexer; 2022. Second intermediate multiplexer;

[0032] 30. Control circuit. Detailed Implementation

[0033] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0034] The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this disclosure are configured to distinguish similar objects and are not necessarily configured to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0035] Unless otherwise stated, the term "multiple" means two or more.

[0036] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.

[0037] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0038] The term "correspondence" can refer to an association or binding relationship. The correspondence between A and B means that there is an association or binding relationship between A and B.

[0039] It should be noted that, unless otherwise specified, the embodiments and features described in the present disclosure can be combined with each other.

[0040] Combination Figure 1 As shown, this embodiment of the disclosure provides a circuit 200 for generating pseudo-random numbers. The circuit 200 includes a feedback shift register circuit 10 and a multiplexer circuit 20. The feedback shift register circuit 10 includes a plurality of feedback shift registers 101 connected in series and configured to generate a pseudo-random number sequence. The multiplexer circuit 20 is connected to the feedback shift register circuit 10 and is configured to select some or all of the feedback shift registers 101 in the feedback shift register circuit 10 to form a feedback loop to output a target pseudo-random number sequence.

[0041] In this disclosed embodiment, the multiplexing circuit 20 selects some or all of the feedback shift registers 101 in the feedback shift register circuit 10, enabling flexible switching between these feedback loops. This allows for the generation of target pseudo-random number sequences with different lengths, periods, or characteristics at the output of the feedback shift register circuit 10. By selecting different feedback loops, the generation rate of pseudo-random numbers can be adjusted, thereby increasing the generation speed of pseudo-random sequences in a short time. Furthermore, it eliminates the need for multiple sets of registers with different lengths, achieving a high pseudo-random number generation rate within a specific time period, thus avoiding wasted area and excessive power consumption.

[0042] Furthermore, since the power consumption level is related to the length of the register group, power consumption can be reduced by selecting a portion of the feedback shift register 101.

[0043] It should be noted that the quality of pseudo-random number generation can be adjusted by selecting different feedback loops. Therefore, it is possible to improve the quality of pseudo-random sequence generation while still meeting the required pseudo-random number generation quality.

[0044] For example, the feedback shift register 101 is a linear feedback shift register (LFSR). A linear feedback shift register is a shift register that, given the output of a previous state, uses a linear function of that output as input. The XOR operation is the most common single-bit linear function: XORing certain bits of the register and using the result as input, then shifting all bits in the register as a whole.

[0045] Optionally, the multiplexing circuit 20 includes a multiplexer, wherein: the output of the multiplexer is connected to the first feedback shift register 101 in the feedback shift register circuit 10. The first input of the multiplexer is connected to the upper path of one or more feedback shift registers 101 in the feedback shift register circuit 10, forming an XOR upper loop. The second input of the multiplexer is connected to the lower path of one or more feedback shift registers 101 in the feedback shift register circuit 10, forming an XOR lower loop. The multiplexing circuit 20 is configured to select either the XOR upper loop or the XOR lower loop as the feedback loop.

[0046] For example, the lengths of the XOR upper loop and the XOR lower loop are different. This results in different periods for the feedback loops formed by the XOR upper and lower loops, thus causing different rates of pseudo-random number generation. Understandably, a shorter feedback loop generates pseudo-random numbers faster because it requires fewer computational steps to update the internal state. Longer feedback loops generate higher-quality pseudo-random number sequences because they have greater periodicity and lower latent patterns.

[0047] In this disclosed embodiment, the output of the multiplexer is connected to the first feedback shift register 101 in the feedback shift register circuit 10, so that the output of the multiplexer serves as the input of the first feedback shift register 101. The multiplexer circuit 20 selects either the upper or lower XOR loop, causing the feedback shift register circuit 10 to output the target pseudo-random number sequence corresponding to the upper XOR loop, or the pseudo-random number sequence corresponding to the lower XOR loop. Thus, by dynamically selecting the feedback loop, the quality and rate of pseudo-random number sequence generation can be adjusted, providing high flexibility and configurability in generating pseudo-random number sequences.

[0048] For example, the multiple feedback shift registers 101 are divided into two segments: one for the series-connected front path and the other for the series-connected back path. When the multiplexing circuit 20 includes a multiplexer, the output of the multiplexer is connected to the first feedback shift register 101 in the series-connected front path. The first input of the multiplexer is connected to the upper path of the series-connected front path, forming an XOR upper loop. The second input of the multiplexer is connected to the lower paths of both the series-connected front and back paths, forming an XOR lower loop. The multiplexing circuit 20 is configured to select either the XOR upper loop or the XOR lower loop as the feedback loop.

[0049] In this way, by selecting the target pseudo-random number sequence corresponding to the feedback loop formed by the output series front path through the multiplexing circuit 20, or selecting the target pseudo-random number sequence corresponding to the feedback loop formed by the output series front path and series back path, the rate and quality of pseudo-random number sequence generated by the feedback shift register circuit 10 can be adjusted, thereby improving the pseudo-random number generation rate within a specific time period while ensuring the quality of the generated pseudo-random numbers.

[0050] For example, multiple feedback shift registers 101 are divided into two segments: one is a series-connected front path, and the other is a series-connected back path. When the multiplexing circuit 20 includes a multiplexer, the output of the multiplexer is connected to the first feedback shift register 101 in the series-connected front path; the first input of the multiplexer is connected to the upper path of both the series-connected front and back paths, forming an XOR upper loop. The second input of the multiplexer is connected to the lower path of the series-connected front path, forming an XOR lower loop. The multiplexing circuit 20 is configured to select either the XOR upper loop or the XOR lower loop as the feedback loop. This allows for more flexible and diverse connection methods for the multiplexing circuit 20.

[0051] Specifically, the lengths of the first and last series paths can be the same.

[0052] Optionally, such as Figure 2As shown, the multiplexing circuit 20 includes multiple multiplexers, each of which includes at least a head multiplexer 201 and an intermediate multiplexer 202. Specifically, a head multiplexer 201 is inserted before the first feedback shift register 101 in the feedback shift register circuit 10, and intermediate multiplexers 202 are inserted between two adjacent feedback shift registers 101 at one or more preset positions in the feedback shift register circuit 10 to form a feedback loop.

[0053] It should be noted that the number of multiple feedback shift registers 101 is n, the number of multiple multiplexers is m, and the number of multiple preset positions is i. Among them, m≤n, i<m.

[0054] In this disclosed embodiment, the sequentially connected feedback shift registers 101 are segmented by inserting multiple multiplexers. By inserting a first multiplexer 201 before the first feedback shift register 101, the selection of input data for the first feedback shift register 101 can be controlled. By setting an intermediate multiplexer 202 at a preset position, the structure of the feedback loop can be changed by selecting the intermediate multiplexer 202 to generate pseudo-random number sequences with different characteristics.

[0055] Optionally, such as Figure 2 As shown, the output of the first multiplexer 201 is connected to the first feedback shift register 101 in the feedback shift register circuit 10, and the output of the intermediate multiplexer 202 is connected to the middle feedback shift register 101 in the feedback shift register circuit 10. The first input of the first multiplexer 201 is connected to the upper path of one or more feedback shift registers 101 located at the beginning of the series connection in the feedback shift register circuit 10, forming a first XOR upper loop. The first input of the intermediate multiplexer 202 is connected to the upper path of one or more feedback shift registers 101 located at the end of the series connection in the feedback shift register circuit 10, forming a second XOR upper loop. The second inputs of the first multiplexer 201 and the intermediate multiplexer 202 are respectively connected to the lower path of one or more feedback shift registers 101 in the feedback shift register circuit 10, forming a total XOR lower loop. The multiplexing circuit 20 is configured to select the first XOR upper loop and the second XOR upper loop as feedback loops, or to select the total XOR lower loop as feedback loops.

[0056] In this disclosed embodiment, by inserting an intermediate multiplexer 202 at the position of the intermediate feedback shift register 101, the multiple feedback shift registers 101 are divided into a series front path and a series back path. Thus, by selecting the first XOR upper loop and the second XOR upper loop of the feedback loop independently for the series front path and the series back path, or by selecting the total XOR lower loop as feedback, the feedback shift register circuit 10 outputs the corresponding target pseudo-random number sequence.

[0057] Optionally, such as Figure 2 As shown, the input value of the first input terminal of the first multiplexer 201 is the XOR output of the upper path of the first preset number of feedback shift registers 101 in the feedback shift register circuit 10. And / or, the input value of the second input terminal of the first multiplexer 201 is the XOR output of the lower path of the second preset number of feedback shift registers 101 in the feedback shift register circuit 10.

[0058] In this circuit, a first preset number of feedback shift registers 101 are located in the series-connected front path of the feedback shift register circuit 10. For example, the first preset number is half the number of feedback shift registers 101. This ensures that the number of feedback shift registers 101 in the series-connected front path and the series-connected back path are the same, i.e., the lengths of the series-connected front path and the series-connected back path are equal. This allows the series-connected front path to be used as an independent feedback loop when the first multiplexer 201 selects the XOR output of the upper path, thereby increasing the rate of the target pseudo-random number sequence.

[0059] For example, the second preset number is not equal to the first preset number. Specifically, the second preset number is the number of multiple feedback shift registers 101. In this way, all the feedback shift registers 101 form a feedback loop, so that when the first multiplexer 201 selects the XOR output of the next path, it will use all the feedback shift registers 101 as a total feedback loop to cycle, thereby improving the quality of the target pseudo-random number sequence.

[0060] In this disclosed embodiment, by selecting the input value at the first input terminal or the input value at the second input terminal through the head multiplexer 201, the rate and quality of generating the pseudo-random number sequence can be dynamically adjusted. This allows for the generation of corresponding pseudo-random number sequences according to usage requirements.

[0061] Optionally, such as Figure 3 As shown, the intermediate multiplexer 202 includes a first intermediate multiplexer 2021, wherein: the input value of the first input terminal of the first intermediate multiplexer 2021 is the XOR output of the upper path of a third preset number of feedback shift registers 101 in the feedback shift register circuit 10. And / or, the input value of the second input terminal of the first intermediate multiplexer 2021 is the XOR output of the lower path of a fourth preset number of feedback shift registers 101 in the feedback shift register circuit 10.

[0062] The third preset number of feedback shift registers 101 is located in the series path after the feedback shift register circuit 10. For example, the third preset number can be set according to usage requirements. The third preset number is less than the number of multiple feedback shift registers 101.

[0063] For example, the fourth preset number is not equal to the third preset number. Specifically, the fourth preset number is the number of multiple feedback shift registers 101.

[0064] In this disclosed embodiment, when the first intermediate multiplexer 2021 selects a third preset number of feedback shift registers 101 as independent feedback loops for cyclic processing, since the third preset number of feedback shift registers 101 is less than the number of multiple feedback shift registers 101, the rate of generating pseudo-random number sequences can be further improved. When the first intermediate multiplexer 2021 selects a fourth preset number of feedback shift registers 101 as the overall feedback loop for cyclic processing, the quality of generating pseudo-random number sequences can be further improved.

[0065] Optionally, such as Figure 3 As shown, the intermediate multiplexer 202 includes a plurality of second intermediate multiplexers 2022, wherein: the input value of the first input terminal of the second intermediate multiplexer 2022 is the XOR output of the upper path of the fifth preset number of feedback shift registers 101 in the feedback shift register circuit 10. And / or, the input value of the second input terminal of the second intermediate multiplexer 2022 is the XOR output of the lower path of the sixth preset number of feedback shift registers 101 in the feedback shift register circuit 10.

[0066] The series path of the feedback shift register circuit 10 includes multiple series branches connected in sequence, and the first input terminal of each second intermediate multiplexer 2022 corresponds to a series branch.

[0067] For example, the sixth preset number is not equal to the fifth preset number. Specifically, the sixth preset number is the number of the plurality of feedback shift registers 101.

[0068] In this disclosed embodiment, the number of intermediate multiplexers 202 is set to multiple, corresponding to multiple series branches of the series path. Thus, the input of the first input terminal is selected by multiple second intermediate multiplexers 2022, causing the feedback shift register circuit 10 to output the target pseudo-random number sequence corresponding to the independent feedback loops formed by the multiple series branches; the input of the second input terminal is selected by multiple second intermediate multiplexers 2022, causing the feedback shift register circuit 10 to output the target pseudo-random number sequence corresponding to the total feedback loop. In this way, the number of multiplexers is used to balance the rate and quality of the pseudo-random number sequence generated by the feedback shift register circuit 10, thereby improving the pseudo-random number generation rate while ensuring the quality of the pseudo-random number sequence generation.

[0069] Optionally, if there is only one preset position, the multiple feedback shift registers 101 are divided into two serial branches, with the preset position located between the two serial branches. If there are multiple preset positions, the multiple feedback shift registers 101 are divided into (i+1) serial branches, with the preset position set between every two serial branches; where i is the number of preset positions.

[0070] It is understandable that setting a preset position means segmenting the multiple feedback shift registers 101 and dividing them into (i+1) serial branches. For example, if the number of preset positions is 1, the multiple feedback shift registers 101 are divided into two serial branches. If the number of preset positions is 3, the multiple feedback shift registers 101 are divided into four serial branches.

[0071] For example, multiple series branches have equal lengths.

[0072] For example, the length of each serial branch is greater than 16 bits. Since the quality of the pseudo-random numbers generated by the LFSR is directly related to its length, the length of each serial branch is set to be greater than 16 bits to ensure the quality of pseudo-random sequence generation while achieving high-speed generation.

[0073] For example, the total length of the multiple feedback shift registers 101 is 128 bits (represented as LFSR0[0:128]). When there is only one preset position, the multiple feedback shift registers 101 are divided into two series branches, and the preset position is set between the two series branches.

[0074] For example, when there are multiple preset positions, the preset position can be set to 3. In this way, the multiple feedback shift registers 101 can be divided into 4 serial branches.

[0075] For example, the total length of the multiple feedback shift registers 101 is 128 bits. With three preset positions, the multiple feedback shift registers 101 are divided into four series branches, with the preset positions located between every two series branches.

[0076] For example, the primitive polynomials used in each series branch can be the same or different. If the primitive polynomials used in each series branch are different, the level of confusion can be increased.

[0077] In this disclosed embodiment, by setting an intermediate multiplexer 202 at a preset position, the multiple feedback shift registers 101 are segmented so that each series branch can form an independent feedback loop. In this way, switching is achieved by the multiplexing circuit 20, that is, the circuit can perform shift feedback according to the complete cycle of the multiple feedback shift registers 101, or it can perform shift feedback according to the independent cycle of each of the multiple series branches.

[0078] Optionally, such as Figure 4 and Figure 5 As shown, the circuit 200 for generating pseudo-random numbers also includes a control circuit 30. The control circuit 30 is connected to the multiplexer circuit 20 and is configured to output a control signal to cause the multiplexer circuit 20 to select some or all of the feedback shift registers 101 in the feedback shift register circuit 10 to form a feedback loop.

[0079] In this disclosed embodiment, the control circuit 30 can dynamically select the multiplexer 20 to select different feedback shift registers 101 to form feedback loops, thereby adjusting the pseudo-random number sequence generated by the feedback shift register circuit 10 in real time. In this way, the control circuit 30 increases the flexibility, ease of control, and dynamic adjustment capability of the circuit 200 used to generate pseudo-random numbers.

[0080] Specifically, such as Figure 2 As shown, taking a total length of 128 bits for multiple feedback shift registers 101 as an example, the circuit 200 used to generate pseudo-random numbers is further explained: the multiple feedback shift registers LFSR0[0:128] are segmented according to requirements. In this embodiment, the multiple feedback shift registers 101 are divided into two series branches, namely the pre-series branch LFSR1[0:63] and the post-series branch LFSR2[0:63], as shown below:

[0081] LFSR0[0:128] is segmented as LFSR1[0:63] + LFSR2[0:63]

[0082] A head multiplexer 201 is inserted before the first feedback shift register 101 in the series-connected front-end. The first input of the head multiplexer 201 is connected to the upper path of all the feedback shift registers 101 in the series-connected front-end, forming the first XOR upper loop; the second input of the head multiplexer 201 is connected to the lower path of multiple feedback shift registers 101, forming the total XOR lower loop. At the same time, the output of the head multiplexer 201 is connected to the first feedback shift register 101 in the series-connected front-end.

[0083] An intermediate multiplexer 202 is inserted before the first feedback shift register 101 in the series-connected path. The first input of the intermediate multiplexer 202 is connected to the upper path of all the feedback shift registers 101 in the series-connected path, forming a second XOR upper loop; the second input of the intermediate multiplexer 202 is connected in series with the last feedback shift register 101 in the series-connected path. At the same time, the output of the intermediate multiplexer 202 is connected to the first feedback shift register 101 in the series-connected path.

[0084] In this disclosed embodiment, the switching between the XOR upper loop and the total XOR lower loop is achieved through the first multiplexer 201 and the intermediate multiplexer 202. That is, the feedback shift register circuit 10 can perform shift feedback either in a complete cycle of the multiple 128-bit feedback shift registers 101, or in a cycle of two 64-bit serial branches. Specifically, when the first multiplexer 201 and the intermediate multiplexer 202 select the first XOR upper loop and the second XOR upper loop, the feedback shift register circuit 10 performs shift feedback in a cycle of two 64-bit serial branches. Figure 2 The Output1 and Output0 shown output the corresponding target pseudo-random number sequences. Because the length of this serial branch is short, the rate of generating pseudo-random numbers can be greatly improved. When the first multiplexer 201 and the intermediate multiplexer 202 select the total XOR lower loop, the feedback shift register circuit 10 performs shift feedback according to the complete cycle of multiple 128-bit feedback shift registers 101. Figure 2 The Out0 output shown corresponds to the target pseudo-random number sequence, which improves the quality of generated pseudo-random numbers.

[0085] Specifically, such as Figure 3As shown, taking a total length of 128 bits for multiple feedback shift registers 101 as an example, the circuit 200 used to generate pseudo-random numbers is further explained: the multiple feedback shift registers LFSR0[0:128] are segmented according to requirements. In this embodiment, the multiple feedback shift registers 101 are divided into four serial branches, namely the pre-serial branch LFSR1[0:31] and three serial branches in the post-serial branch. The three serial branches in the post-serial branch are respectively labeled as the first serial branch LFSR2[0:31], the second serial branch LFSR3[0:31], and the third serial branch LFSR4[0:31], as follows:

[0086] LFSR0[0:128] is segmented as LFSR1[0:63]+LFSR2[0:31]+LFSR3[0:31]+LFSR4[0:31]

[0087] A head multiplexer 201 is inserted before the first feedback shift register 101 in the series-connected front-end. The first input of the head multiplexer 201 is connected to the upper path of all the feedback shift registers 101 in the series-connected front-end, forming a third XOR upper loop; the second input of the head multiplexer 201 is connected to the lower path of multiple feedback shift registers 101, forming a total XOR lower loop. At the same time, the output of the head multiplexer 201 is connected to the first feedback shift register 101 in the series-connected front-end.

[0088] A first intermediate multiplexer 2021 is inserted before the first feedback shift register 101 in the first series branch. The first input of the first intermediate multiplexer 2021 is connected to the upper loop of all feedback shift registers 101 in the first series branch, forming a fourth XOR upper loop; the second input of the first intermediate multiplexer 2021 is connected in series with the last feedback shift register 101 in the series preceding loop. At the same time, the output of the first intermediate multiplexer 2021 is connected to the first feedback shift register 101 in the first series branch.

[0089] A second intermediate multiplexer 2022 is inserted before the first feedback shift register 101 in the second series branch. The first input of the second intermediate multiplexer 2022 is connected to the upper loop of all feedback shift registers 101 in the second series branch, forming a fifth XOR upper loop; the second input of the second intermediate multiplexer 2022 is connected in series with the last feedback shift register 101 in the first series branch. At the same time, the output of the second intermediate multiplexer 2022 is connected to the first feedback shift register 101 in the second series branch.

[0090] A second intermediate multiplexer 2022 is inserted before the first feedback shift register 101 in the third series branch. The first input of this second intermediate multiplexer 2022 is connected to the upper loop of all feedback shift registers 101 in the third series branch, forming a sixth XOR upper loop; the second input of this second intermediate multiplexer 2022 is connected in series with the last feedback shift register 101 in the second series branch. Simultaneously, the output of this second intermediate multiplexer 2022 is connected to the first feedback shift register 101 in the third series branch.

[0091] In this disclosed embodiment, the switching between the XOR upper loop and the total XOR lower loop is achieved through the first multiplexer 201, the first intermediate multiplexer 2021, one second intermediate multiplexer 2022, and another second intermediate multiplexer 2022. That is, the feedback shift register circuit 10 can perform shift feedback either in a complete cycle of the multiple 128-bit feedback shift registers 101, or in a cycle of each of the four 32-bit serial branches. Specifically, when the first multiplexer 201 and the intermediate multiplexer 202 select the third, fourth, fifth, and sixth XOR upper loops, the feedback shift register circuit 10 performs shift feedback in a cycle of each of the four 32-bit serial branches. Figure 3 R31, R63, R95, and R127, as shown, output the corresponding target pseudo-random number sequences, further improving the rate of pseudo-random number generation. When the first multiplexer 201 and the intermediate multiplexer 202 select the total XOR lower loop, the feedback shift register circuit 10 performs shift feedback according to the complete cycle of multiple 128-bit feedback shift registers 101, by... Figure 3 The R127 output shown corresponds to the target pseudo-random number sequence, which improves the quality of generated pseudo-random numbers.

[0092] Under normal circumstances, this circuit selects a longer feedback loop to generate pseudo-random number sequences. For example, it selects a feedback loop formed by multiple 128-bit feedback shift registers 101 and updates iteratively at a standard rate of 1 bit per cycle. However, during specific periods (when a large number of pseudo-random number sequences need to be generated in a short time), it switches to a shorter feedback loop. For example, it divides the multiple 128-bit feedback shift registers 101 into multiple serial branches, forming a feedback loop with the length of each serial branch, and achieves rapid updates and iterations at a high speed of 4 bits per cycle. In this way, the generation speed of pseudo-random sequences can be increased in a short time while ensuring the quality of pseudo-random number generation. In addition, this embodiment only requires the addition of multiple multiplexers, reducing additional power consumption.

[0093] It should be noted that the lengths of the multiple feedback shift registers 101 and the number of multiplexers can be set or selected according to actual usage requirements, and the disclosed embodiments of the present invention do not limit this.

[0094] Combination Figure 6 As shown, this disclosure provides a pseudo-random number generator 100, including a generator body 300 and the aforementioned circuit 200 for generating pseudo-random numbers. The circuit 200 for generating pseudo-random numbers is mounted on the generator body 300. The mounting relationship described herein is not limited to placement within the generator body 300, but also includes mounting connections with other components of the generator 100, including but not limited to physical connections, electrical connections, or signal transmission connections. Those skilled in the art will understand that the circuit 200 for generating pseudo-random numbers can be adapted to feasible generator bodies to achieve other feasible embodiments.

[0095] The foregoing description and accompanying drawings fully illustrate embodiments of this disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the terminology used in this application is configured only to describe embodiments and not to limit the claims. As used in the description of embodiments and claims, the singular forms “a,” “an,” and “the” are intended to equally include the plural forms unless the context clearly indicates otherwise. Similarly, the term “and / or” as used herein means including one or more of the associated listed items and all possible combinations thereof. Additionally, when configured in this application, the term "comprise" and its variations "comprises" and / or "comprising" refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Without further limitations, an element defined by the phrase "comprises a..." does not exclude the presence of other identical elements in the process, method, or apparatus that includes said element. In this document, each embodiment may focus on the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, the relevant parts can be referred to the description of the method section.

[0096] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this disclosure. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0097] The methods and products (including but not limited to devices and equipment) disclosed in the embodiments herein can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units may be merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the shown or discussed units may be through some interfaces, and the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected to implement this embodiment according to actual needs. Furthermore, the functional units in the embodiments of this disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0098] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions configured to implement a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than that shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different blocks may also occur in a different order than disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. Each block in a block diagram and / or flowchart, and combinations of blocks in a block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

Claims

1. A circuit for generating pseudo-random numbers, characterized in that, include: The feedback shift register circuit includes multiple feedback shift registers connected in series, configured to shift and generate a pseudo-random number sequence; A multiplexer circuit, connected to a feedback shift register circuit, is configured to select some or all of the feedback shift registers in the feedback shift register circuit to form a feedback loop in order to output a target pseudo-random number sequence. The multiplexing circuit includes a multiplexer, wherein: The output of the multiplexer is connected to the first feedback shift register in the feedback shift register circuit; The first input of the multiplexer is connected to the upper path of one or more feedback shift registers in the feedback shift register circuit to form an XOR upper loop; The second input of the multiplexer is connected to the lower path of one or more feedback shift registers in the feedback shift register circuit to form an XOR lower loop; The multiplexing circuit is configured to select either the XOR upper loop or the XOR lower loop as the feedback loop.

2. A circuit for generating pseudo-random numbers, characterized in that, include: The feedback shift register circuit includes multiple feedback shift registers connected in series, configured to shift and generate a pseudo-random number sequence; A multiplexer circuit, connected to a feedback shift register circuit, is configured to select some or all of the feedback shift registers in the feedback shift register circuit to form a feedback loop in order to output a target pseudo-random number sequence. The multiplexing circuit includes multiple multiplexers, each of which includes at least a head multiplexer and intermediate multiplexers, wherein: A head multiplexer is inserted before the first feedback shift register in the feedback shift register circuit, and intermediate multiplexers are inserted between two adjacent feedback shift registers at one or more preset positions in the feedback shift register circuit to form a feedback loop. The output of the first multiplexer is connected to the first feedback shift register in the feedback shift register circuit, and the output of the middle multiplexer is connected to the middle feedback shift register in the feedback shift register circuit. The first input terminal of the first multiplexer is connected to the upper path of one or more feedback shift registers located in the series front path in the feedback shift register circuit to form the first XOR upper loop; The first input of the intermediate multiplexer is connected to the upper path of one or more feedback shift registers located in the series path of the feedback shift register circuit to form the second XOR upper loop; The second input of the first multiplexer and the second input of the intermediate multiplexer are respectively connected to the lower path of one or more feedback shift registers in the feedback shift register circuit to form the total XOR lower loop; The multiplexing circuit is configured to select the first XOR upper loop and the second XOR upper loop as feedback loops, or to select the total XOR lower loop as feedback loops.

3. The circuit according to claim 2, characterized in that, The input value of the first input terminal of the first multiplexer is the XOR output of the upper path of the first preset number of feedback shift registers in the feedback shift register circuit; and / or, The input value of the second input terminal of the first multiplexer is the XOR output of the lower path of the second preset number of feedback shift registers in the feedback shift register circuit; Among them, the first preset number of feedback shift registers are located in the series front path of the feedback shift register circuit.

4. The circuit according to claim 2, characterized in that, The intermediate multiplexer includes a first intermediate multiplexer, wherein: The input value of the first input terminal of the first intermediate multiplexer is the XOR output of the upper path of the third preset number of feedback shift registers in the feedback shift register circuit; and / or, The input value of the second input terminal of the first intermediate multiplexer is the XOR output of the lower path of the fourth preset number of feedback shift registers in the feedback shift register circuit; Among them, the third preset number of feedback shift registers are located in the series path after the feedback shift register circuit.

5. The circuit according to claim 2, characterized in that, The intermediate multiplexer includes multiple second intermediate multiplexers, wherein: The input value of the first input terminal of the second intermediate multiplexer is the XOR output of the upper path of the fifth preset number of feedback shift registers in the feedback shift register circuit; and / or, The input value of the second input terminal of the second intermediate multiplexer is the XOR output of the lower path of the sixth preset number of feedback shift registers in the feedback shift register circuit; The series path of the feedback shift register circuit includes multiple series branches connected in sequence, and the first input terminal of each second intermediate multiplexer corresponds to a series branch.

6. The circuit according to claim 2, characterized in that, With one preset position, multiple feedback shift registers are divided into two series branches, with the preset position located between the two series branches; When there are multiple preset positions, the multiple feedback shift registers are divided into (i+1) series branches, and the preset positions are set between every two series branches; where i is the number of preset positions.

7. The circuit according to any one of claims 1 to 6, characterized in that, Also includes: The control circuit, connected to the multiplexer circuit, is configured to output a control signal to cause the multiplexer circuit to select some or all of the feedback shift registers in the feedback shift register circuit to form a feedback loop.

8. A pseudo-random number generator, characterized in that, include: Generator body; The circuit for generating pseudo-random numbers as described in any one of claims 1 to 7 is installed on the generator body.

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