Chip simulation model construction method and system

Abstract

The application provides a chip simulation model construction method and system, which comprises a chip simulation system and a peripheral expansion unit; the peripheral expansion unit comprises a plurality of simulated Root Complex controllers, each of which can be connected to one or more simulation physical device PCIe Endpoints through a simulated peripheral PCIe bus; a firmware program runs in a simulated CPU part of the original chip simulation system and can access the plurality of simulated Root Complex controllers of the peripheral expansion unit through a pre-configured simulated CPU bus address. The method takes SystemC as a basic framework, establishes a peripheral expansion unit of the chip simulation system on the basis of the original simulation system, and realizes a plurality of Root Complex engines in the peripheral expansion unit. In this way, a transaction-level simulation model of a chip supporting a plurality of Root Complex engines is built, and the simulation and testing requirements of a chip firmware program in the development process of a chip containing a plurality of Root Complex controllers are solved.

Description

Technical Field

[0001] This invention relates to the field of computer technology, specifically to a method and system for constructing a chip simulation model with a multi-root complex engine. Background Technology

[0002] In the early stages of IC and chip design, due to long design cycles and high costs per tape-out, software modeling of the system is typically performed for evaluation and simulation based on the chip design requirements. When implementing transaction-level software modeling, the industry commonly uses SystemC as a foundation to build a chip simulation environment according to the chip's business model. SystemC is essentially a C++ software library that provides software simulation encapsulation of basic components for the abstract modeling of hardware electronic systems.

[0003] Existing peripheral chip simulation design block diagrams are as follows: Figure 1 As shown, in the prior art, when designing a chip simulation model, the PCIe bus interconnect framework for designing the chip simulation system framework is as follows: Figure 1 As shown, the portion within the dashed box is a functional block diagram of the chip emulation system. The chip emulation system contains a simulated CPU unit, which can run chip firmware programs. The chip emulation system also includes a simulated Root Complex unit that connects the simulated CPU unit to other external simulated physical devices (PCIe Endpoints).

[0004] The drawbacks of existing technical solutions are that they involve complex configuration when expanding peripheral buses, are too tightly coupled with the chip emulation system, and are inconvenient for modular disassembly. Furthermore, existing solutions only provide chip emulation models supporting a single root complex, and cannot provide multiple root complexes for chip firmware debugging. Summary of the Invention

[0005] In view of this, the present invention proposes a chip simulation model construction method and system for multiple root complex engines. Based on the SystemC framework, a chip simulation system peripheral extension unit is established on the basis of the original simulation system. Multiple simulated root complex engines are implemented in the peripheral extension unit. In this combination, a transaction-level simulation model of a chip that supports multiple root complex engines is built, which solves the need for simulation and debugging of chip firmware programs in the development of chips containing multiple root complex controllers.

[0006] Based on the above objectives, in a first aspect, the present invention provides a chip simulation model construction system with a multi-root complex engine, including a chip simulation system and a peripheral expansion unit, wherein the chip simulation system has a simulated CPU unit inside, the simulated CPU unit can run chip firmware programs, and the chip simulation system also has a simulated root complex unit that connects the simulated CPU unit to other external simulated physical devices PCIe endpoints.

[0007] The peripheral expansion unit includes multiple simulated Root Complex controllers, each of which can be connected to one or more simulated physical devices PCIeEndpoints via a simulated peripheral PCIe bus.

[0008] The firmware runs on the simulated CPU part of the original chip emulation system and can access multiple simulated root complex controllers of the peripheral expansion unit through the pre-configured simulated CPU bus address.

[0009] As a further embodiment of the present invention, the peripheral expansion unit further includes a top-level configuration module, a CPU bus interface module, a root complex memory address allocation module, a root complex configuration space mapping module, and a PCIeEndpoint device registration module.

[0010] As a further aspect of the present invention, the CPU bus interface module is responsible for interfacing with the chip simulation system to complete transaction-level access interactions. The CPU bus interface module is also responsible for locating the target module based on the requested address and forwarding the corresponding request and response messages.

[0011] The top-level configuration module is responsible for the bus registration of all peripheral expansion units, Root Complex devices, to the chip simulation system, including the registration of the initiating ports of each Root Complex configuration space mapping module, the registration of the access address of the Root Complex configuration space mapping module to the target port, the registration of the initiating port of the Root Complex Memory address allocation module, the registration of the access address of the Root Complex Memory address allocation module to the target port, and the binding of PCIeEndpoint devices to Root Complex devices.

[0012] The Root Complex configuration space mapping module is responsible for receiving transaction-level configuration requests from the bus, finding the corresponding PCIe Endpoint device registered in the configuration space based on the address of the request, and forwarding the request to the PCIe Endpoint device registered in the Root Complex configuration space.

[0013] The Root Complex Memory address space mapping module is responsible for receiving transaction-level memory requests from the bus, finding the corresponding PCIe Endpoint device registered in the memory address space based on the requested address, and forwarding the request to that PCIe Endpoint device registered in the Root Complex's memory address space.

[0014] The PCIe Endpoint device registration module is responsible for binding PCIe Endpoint devices to the Root Complex. This includes a module that maps the PCIe Endpoint device's configuration space to the Root Complex's configuration space, and a module that maps the PCIe Endpoint device's memory address space to the Root Complex's memory address space.

[0015] In view of the above objectives, and in a second aspect, the present invention provides a method for constructing a chip simulation model with a multi-root complex engine. This method is executed based on the aforementioned chip simulation model construction system and includes the following steps:

[0016] Initialize the chip simulation system, create the Master interface and Slave interface, and bind one end to the chip simulation system;

[0017] Initialize the peripheral expansion unit, including creating the initiating port and the target port;

[0018] Bind the initiating port of the peripheral expansion unit to the Slave interface of the chip emulation system, and bind the target port of the peripheral expansion unit to the Master interface of the chip emulation system.

[0019] As a further aspect of the present invention, the peripheral expansion unit is a model used to simulate communication between multiple RootComplex engines and PCIe Endpoint devices.

[0020] As a further aspect of the present invention, initializing the chip simulation system includes the following steps:

[0021] The chip simulation system is initialized by calling the SystemC transaction-level access base library to create Master and Slave interfaces, and binding one end of the Master and Slave interfaces to the chip simulation system; the binding method uses the methods provided by the Master and Slave interface objects.

[0022] The peripheral expansion unit is initialized. After the peripheral expansion unit is initialized, the initiating port and the target port are created.

[0023] Bind the target port of the peripheral expansion unit to the Master port of the chip emulation system, and bind the initiating port of the peripheral expansion unit to the Slave port of the chip emulation system; after binding, mutual communication of transaction-level requests between the peripheral expansion unit and the chip emulation system is realized; the binding method uses the method provided by the top-level module of the peripheral expansion unit.

[0024] The simulation system is running.

[0025] As a further aspect of the present invention, the top-level initialization of the peripheral expansion unit includes: top-level module initialization, CPU bus interface module initialization, Root Complex configuration space mapping module initialization, Root Complex Memory address space mapping module initialization, and PCIe Endpoint device configuration information initialization; wherein:

[0026] During initialization, the top-level module creates a specified number of RootComplex configuration space mapping objects, a specified number of Root Complex Memory address space mapping objects, and a specified number of PCIe Endpoint device objects, based on the simulation requirements of the chip simulation system.

[0027] During initialization, the top-level module registers the initiation port of the Root Complex configuration space mapping object, the initiation port of the Root Complex Memory address space mapping object, and the initiation port of the PCIeEndpoint device object to the CPU bus.

[0028] During initialization, the top-level module registers the target port of the Root Complex configuration space mapping object and the configuration space address and address range size allocated to the Root Complex object to the CPU bus, and registers the target port of the Root Complex Memory address space mapping object and the address and address range size allocated to the Root Complex Memory address space mapping object to the CPU bus.

[0029] During initialization, the top-level module registers the PCIe Endpoint device object information, along with the bus number, device number, and function number of the PCIe Endpoint device object, to the Root Complex configuration space mapping object. It also registers the PCIe Endpoint device object information, along with the bus number, device number, and function number of the PCIe Endpoint device object, as well as the starting address and address range of the PCIe Endpoint device object's memory address space, to the Root Complex memory address space mapping object.

[0030] As a further aspect of the present invention, in the CPU bus interface module, when the peripheral expansion unit interface module interfaces with the chip simulation system, the target port of the peripheral expansion unit is bound to the Master port of the chip simulation system, and the initiating port of the peripheral expansion unit is bound to the Slave port of the chip simulation system. After binding, mutual communication of transaction-level requests between the peripheral expansion unit and the chip simulation system is realized.

[0031] As a further aspect of the present invention, CPU bus interface initialization includes the following steps:

[0032] Through port binding, when the chip emulation system accesses a peripheral device, the internal module of the chip emulation system initiates a request. The request reaches the external target port of the peripheral expansion unit through the bound Slave interface. The CPU bus interface looks up the device interface corresponding to the address of the request through the bus and forwards the request to the emulation device of the peripheral expansion unit. After being processed by the emulation device, the response result is transmitted back to the chip emulation system.

[0033] Through port binding, when the peripheral expansion unit initiates a request to the chip emulation system, the request is sent to the Master interface of the chip emulation system through the external initiation port of the peripheral expansion unit. The chip emulation system then passes the request to its internal processing unit. After processing, the internal processing unit of the chip emulation system transmits the response result back to the peripheral expansion unit.

[0034] As a further aspect of this invention, the working mechanism of the Root Complex configuration space mapping module is as follows: During initialization, the Root Complex configuration space mapping module creates a FIFO, a core processing thread, and trigger events. The core processing thread begins running immediately upon initialization, waiting for event triggering. The simulation of the FIFO space is implemented using the `sc_fifo` data structure provided by the SystemC library. A single entry in the FIFO includes information such as the requested address, read / write flag, data for the write request / return address for the read request, and data width. The simulation of the core processing thread is implemented using the `sc_thread` method provided by the SystemC library. The simulation of the trigger event is implemented using the `sc_event` method provided by the SystemC library.

[0035] The Root Complex configuration space mapping module is mounted on the CPU bus during initialization. When a bus request is received, the target port processes the request, parses the request content into an internal format, writes it into the internal FIFO space, and then sends an event-triggered notification to the core processing thread. The core processing thread begins processing upon receiving the triggered event.

[0036] As a further aspect of the present invention, the workflow of the PCIe Endpoint device registration module includes:

[0037] During the initialization of the PCIe Endpoint device registration module, based on the number of configured PCIe Endpoint devices and the relationship between the PCIe Endpoint devices and the Root Complex, PCIe Endpoint device configuration information is created, PCIe Endpoint device objects are created based on the configuration information, and the device objects are stored in the PCIe Endpoint device object list.

[0038] Based on the device information in the PCIe Endpoint device object list, assign bus number, device number, and function number to the PCIe Endpoint device of each Root Complex according to different Root Complexes, and configure the default BAR address and address range information of the PCIe Endpoint device;

[0039] Based on the device object information in the PCIe Endpoint device object list, obtain the corresponding Root Complex configuration space mapping object, obtain the bus number, device number, and function number of the PCIe Endpoint device, call the binding method provided by the Root Complex configuration space mapping object, and register the bus number, device number, function number of the PCIe Endpoint device, and the object information of the PCIe Endpoint device to the Root Complex configuration space mapping object.

[0040] Based on the device object information in the PCIe Endpoint device object list, obtain the corresponding Root Complex Memory address space mapping object, retrieve the bus number, device number, function number, starting address, address range size, and other information of the PCIe Endpoint device, and call the binding method provided by the Root Complex Memory address space mapping object to register the PCIe Endpoint device's bus number, device number, function number, starting address, address range size, and PCIe Endpoint device object information to the Root Complex Memory address space mapping object.

[0041] In another aspect, the present invention provides a computer device including a memory and a processor, wherein the memory stores a computer program, which, when executed by the processor, performs any of the chip simulation model construction methods of the multi-root complex engine according to the present invention.

[0042] In another aspect, the present invention provides a computer-readable storage medium storing computer program instructions that, when executed, implement any of the above-described chip simulation model construction methods for the multi-root complex engine according to the present invention.

[0043] Compared with existing technologies, the chip simulation model construction method and system proposed in this invention, which adopts a "transaction-level model based on SystemC, extending peripheral units" design, supports the simulation implementation of multiple externally extended root complexes on the basis of the chip simulation system, and has the following beneficial effects:

[0044] 1. By adopting the solution of the present invention, an engine simulation implementation of multiple root complexes can be provided for the chip simulation system, thereby supporting the firmware driver to access multiple root complexes.

[0045] 2. It allows firmware drivers to access multiple root complexes of the firmware based on simulation models before chip tape-out is complete, enabling program development and debugging. This allows chip design and firmware development to proceed simultaneously, shortening the project development cycle.

[0046] 3. The system platform built based on this simulation model can replace the functions of multiple root complexes on some hardware platforms for development and testing, saving the cost of building a new hardware testing platform for the project.

[0047] These or other aspects of this application will become more apparent from the following description of embodiments. It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the scope of this application. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0049] In the diagram:

[0050] Figure 1 This is a block diagram for simulating existing peripheral chips.

[0051] Figure 2 This is a schematic diagram of an improved chip simulation framework in a chip simulation model construction method for a multi-root complex engine according to an embodiment of the present invention.

[0052] Figure 3 This is a schematic diagram of the peripheral expansion unit system function in a chip simulation system of a chip simulation model construction method for a multi-root complex engine according to an embodiment of the present invention.

[0053] Figure 4 This is a schematic diagram illustrating the relationship between various modules in a chip simulation model construction method for a multi-root complex engine according to an embodiment of the present invention.

[0054] Figure 5 This is a schematic diagram of the chip simulation system initialization process in a chip simulation model construction method for a multi-root complex engine according to an embodiment of the present invention.

[0055] Figure 6 This is a schematic diagram of the top-level module initialization process in a chip simulation model construction method for a multi-root complex engine according to an embodiment of the present invention.

[0056] Figure 7 This is a functional block diagram of the interface module of the peripheral expansion unit and the chip simulation system in a chip simulation model construction method of a multi-root complex engine according to an embodiment of the present invention.

[0057] Figure 8 This is a schematic diagram illustrating the process of initializing the peripheral expansion unit interface module and binding the port in a chip simulation model construction method for a multi-root complex engine according to an embodiment of the present invention.

[0058] Figure 9 This is a schematic diagram illustrating the working mechanism of the RootComplex configuration space mapping module in a chip simulation model construction method for a multi-RootComplex engine according to an embodiment of the present invention.

[0059] Figure 10 This is a schematic diagram of the workflow of the RootComplex configuration space mapping module in a chip simulation model construction method for a multi-RootComplex engine according to an embodiment of the present invention.

[0060] Figure 11 This is a schematic diagram of the configuration space mapping address distribution in a chip simulation model construction method for a multi-root complex engine according to an embodiment of the present invention.

[0061] Figure 12 This is a schematic diagram illustrating the working mechanism of the RootComplex Memory address space mapping module in a chip simulation model construction method for a multi-RootComplex engine according to an embodiment of the present invention.

[0062] Figure 13 This is a schematic diagram of the workflow of the RootComplex Memory address space mapping module in a chip simulation model construction method for a multi-RootComplex engine according to an embodiment of the present invention.

[0063] Figure 14 This is a schematic diagram of the memory address space mapping address distribution in a chip simulation model construction method for a multi-root complex engine according to an embodiment of the present invention.

[0064] Figure 15 This is a flowchart illustrating the PCIeEndpoint device registration module in a chip simulation model construction method for a multi-Root Complex engine according to an embodiment of the present invention.

[0065] Figure 16 This is a schematic diagram of the address allocation of the multi-root complex peripheral expansion unit simulation system in a chip simulation model construction method for a multi-root complex engine according to an embodiment of the present invention.

[0066] Figure 17 This is an overall block diagram of the multi-root complex simulation system application in a chip simulation model construction method for a multi-root complex engine according to an embodiment of the present invention. Detailed Implementation

[0067] The present application will now be further described in conjunction with the accompanying drawings and specific embodiments. It should be noted that, without conflict, the various embodiments or technical features described below can be arbitrarily combined to form new embodiments.

[0068] To make the objectives, technical solutions, and advantages of this invention clearer, the embodiments of this invention will be further described in detail below with reference to specific examples and the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit this application.

[0069] It should be noted that all uses of "first" and "second" in the embodiments of the present invention are for the purpose of distinguishing two different entities or different parameters with the same name. Therefore, "first" and "second" are merely for convenience of expression and should not be construed as limiting the embodiments of the present invention. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, such as other steps or units inherent in a process, method, system, product, or device that includes a series of steps or units.

[0070] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0071] The flowchart shown in the attached diagram is for illustrative purposes only and does not necessarily include all content and operations / steps, nor does it necessarily have to be performed in the order described. For example, some operations / steps can be broken down, combined, or partially merged, so the actual execution order may change depending on the actual situation.

[0072] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0073] Expanding peripheral buses involves complex configurations and excessive coupling with the chip emulation system, making modular decomposition inconvenient. Furthermore, existing solutions only provide chip emulation models supporting a single root complex, failing to offer multiple root complexes for chip firmware debugging.

[0074] The purpose of this invention is to propose a method for constructing a transaction-level model of a multi-root complex controller based on SystemC. Using SystemC as the basic framework, a chip simulation system peripheral expansion unit is established on the basis of the original simulation system. Multiple simulated root complex engines are implemented in the peripheral expansion unit. In this combined way, a transaction-level simulation model of a chip that supports multiple root complex engines is built, which solves the need for simulation and debugging of chip firmware programs in the research and development of chips containing multi-root complex controllers.

[0075] See Figure 2 and Figure 3 As shown, the present invention provides a chip simulation model construction system with a multi-root complex engine, including a chip simulation system and a peripheral expansion unit. The chip simulation system has a simulated CPU unit inside, which can run chip firmware programs. The chip simulation system also has a simulated root complex unit that connects the simulated CPU unit to other external simulated physical devices PCIe endpoints.

[0076] The peripheral expansion unit includes multiple simulated Root Complex controllers, each of which can be connected to one or more simulated physical devices PCIeEndpoints via a simulated peripheral PCIe bus.

[0077] The firmware runs on the simulated CPU part of the original chip emulation system and can access multiple simulated root complex controllers of the peripheral expansion unit through the pre-configured simulated CPU bus address.

[0078] See Figure 4 As shown, the peripheral expansion unit also includes a top-level configuration module, a CPU bus interface module, a Root Complex Memory address allocation module, a Root Complex configuration space mapping module, and a PCIe Endpoint device registration module.

[0079] The CPU bus interface module is responsible for interfacing with the chip simulation system to complete transaction-level access interactions. The CPU bus interface module is also responsible for locating the target module based on the requested address and forwarding the corresponding request and response messages.

[0080] The top-level configuration module is responsible for the bus registration of all peripheral expansion units, Root Complex devices, to the chip simulation system, including the registration of the initiating ports of each Root Complex configuration space mapping module, the registration of the access address of the Root Complex configuration space mapping module to the target port, the registration of the initiating port of the Root Complex Memory address allocation module, the registration of the access address of the Root Complex Memory address allocation module to the target port, and the binding of PCIeEndpoint devices to Root Complex devices.

[0081] The Root Complex configuration space mapping module is responsible for receiving transaction-level configuration requests from the bus, finding the corresponding PCIe Endpoint device registered in the configuration space based on the address of the request, and forwarding the request to the PCIe Endpoint device registered in the Root Complex configuration space.

[0082] The Root Complex Memory address space mapping module is responsible for receiving transaction-level memory requests from the bus, finding the corresponding PCIe Endpoint device registered in the memory address space based on the requested address, and forwarding the request to that PCIe Endpoint device registered in the Root Complex's memory address space.

[0083] The PCIe Endpoint device registration module is responsible for binding PCIe Endpoint devices to the Root Complex. This includes a module that maps the PCIe Endpoint device's configuration space to the Root Complex's configuration space, and a module that maps the PCIe Endpoint device's memory address space to the Root Complex's memory address space.

[0084] This invention provides a method for constructing a chip simulation model with a multi-root complex engine. This method is based on the aforementioned chip simulation model construction system and includes the following steps:

[0085] Initialize the chip simulation system, create the Master interface and Slave interface, and bind one end to the chip simulation system;

[0086] Initialize the peripheral expansion unit, including creating the initiating port and the target port;

[0087] Bind the initiating port of the peripheral expansion unit to the Slave interface of the chip emulation system, and bind the target port of the peripheral expansion unit to the Master interface of the chip emulation system.

[0088] In this embodiment, the peripheral expansion unit is a model used to simulate communication between multiple RootComplex engines and PCIeEndpoint devices.

[0089] See Figure 5 As shown, initializing the chip simulation system includes the following steps:

[0090] The chip simulation system is initialized by calling the SystemC transaction-level access base library to create Master and Slave interfaces, and binding one end of the Master and Slave interfaces to the chip simulation system; the binding method uses the methods provided by the Master and Slave interface objects.

[0091] The peripheral expansion unit is initialized. After the peripheral expansion unit is initialized, the initiating port and the target port are created.

[0092] Bind the target port of the peripheral expansion unit to the Master port of the chip emulation system, and bind the initiating port of the peripheral expansion unit to the Slave port of the chip emulation system; after binding, mutual communication of transaction-level requests between the peripheral expansion unit and the chip emulation system is realized; the binding method uses the method provided by the top-level module of the peripheral expansion unit.

[0093] The simulation system is running.

[0094] In this embodiment, see Figure 6 As shown, the top-level initialization of the peripheral expansion unit includes: top-level module initialization, CPU bus interface module initialization, Root Complex configuration space mapping module initialization, Root Complex Memory address space mapping module initialization, and PCIe Endpoint device configuration information initialization; among which:

[0095] During initialization, the top-level module creates a specified number of RootComplex configuration space mapping objects, a specified number of Root Complex Memory address space mapping objects, and a specified number of PCIe Endpoint device objects, based on the simulation requirements of the chip simulation system.

[0096] During initialization, the top-level module registers the initiation port of the Root Complex configuration space mapping object, the initiation port of the Root Complex Memory address space mapping object, and the initiation port of the PCIeEndpoint device object to the CPU bus.

[0097] During initialization, the top-level module registers the target port of the Root Complex configuration space mapping object and the configuration space address and address range size allocated to the Root Complex object to the CPU bus, and registers the target port of the Root Complex Memory address space mapping object and the address and address range size allocated to the Root Complex Memory address space mapping object to the CPU bus.

[0098] During initialization, the top-level module registers the PCIe Endpoint device object information, along with the bus number, device number, and function number of the PCIe Endpoint device object, to the Root Complex configuration space mapping object. It also registers the PCIe Endpoint device object information, along with the bus number, device number, and function number of the PCIe Endpoint device object, as well as the starting address and address range of the PCIe Endpoint device object's memory address space, to the Root Complex memory address space mapping object.

[0099] See Figure 7 As shown, in the CPU bus interface module, when the peripheral expansion unit interface module communicates with the chip simulation system, the target port of the peripheral expansion unit is bound to the Master port of the chip simulation system, and the initiating port of the peripheral expansion unit is bound to the Slave port of the chip simulation system. After binding, the transaction-level requests between the peripheral expansion unit and the chip simulation system can be communicated with each other.

[0100] See CPU bus interface initialization procedure. Figure 5 As shown, the CPU bus interface forwarding request process is as follows: When the chip emulation system accesses the peripheral device through port binding, the chip emulation system initiates a request internally. The request reaches the external target port of the peripheral expansion unit through the bound Slave interface. The CPU bus interface searches for the device interface corresponding to the address of the request and forwards the request to the emulation device of the peripheral expansion unit. After processing by the emulation device, the response result is transmitted back to the chip emulation system.

[0101] Through port binding, when the peripheral expansion unit initiates a request to the chip emulation system, the request is sent to the Master interface of the chip emulation system through the external initiation port of the peripheral expansion unit. The chip emulation system then passes the request to its internal processing unit. After processing, the internal processing unit of the chip emulation system transmits the response result back to the peripheral expansion unit.

[0102] In this embodiment, see Figure 9 The diagram illustrates the working mechanism of the Root Complex configuration space mapping module. During initialization, the Root Complex configuration space mapping module creates a FIFO, a core processing thread, and trigger events. The core processing thread begins running immediately upon initialization, waiting for events to be triggered. The simulation of the FIFO space is implemented using the `sc_fifo` data structure provided by the SystemC base library. A single entry in the FIFO includes information such as the requested address, read / write flag, data for the write request / return address for the read request, and data width. The simulation of the core processing thread is implemented using the `sc_thread` method provided by the SystemC base library. The simulation of the trigger events is implemented using the `sc_event` method provided by the SystemC base library.

[0103] The Root Complex configuration space mapping module is mounted on the CPU bus during initialization. When a bus request is received, the target port processes the request, parses the request content into an internal format, writes it into the internal FIFO space, and then sends an event-triggered notification to the core processing thread. The core processing thread begins processing upon receiving the triggered event.

[0104] See Figure 10 The specific workflow of configuring the space mapping module for the Root Complex is as follows: During initialization, the space mapping module of the Root Complex will also register the target-side processing interface of this module to the bus so as to receive and process bus transactions.

[0105] During initialization, the Root Complex configuration space mapping module also creates a list of PCIe Endpoint devices and provides binding and unbinding methods for these devices, which are then called by the PCIe Endpoint device registration module. The binding method creates an index using the PCIe Endpoint device's bus number, device number, and function number to store the device's object information. The unbinding method uses the same index to clear the stored object information of the PCIe Endpoint device.

[0106] When the core processing thread of the Root Complex configuration space mapping module receives a bus request, it calculates the bus number, device number, and function number of the corresponding PCIe Endpoint device based on the request address information. Specifically, taking the address bit order [63:0] little-endian as an example, address bits [11:0] are used as the PCIe Endpoint device configuration space addressing range, address bits [14:12] are used as the PCIe Endpoint device function number, address bits [22:15] are used as the PCIe Endpoint device device number, and address bits [31:23] are used as the PCIe Endpoint device bus number.

[0107] The core processing thread of the Root Complex configuration space mapping module searches for PCIe Endpoint device object information based on the bus number, device number, and function number. If found, the request is forwarded to the PCIe Endpoint device object for processing. After processing, if it is a read request, the processing data is received and a response is returned to the requester.

[0108] If the PCIe Endpoint device object information cannot be found, the Root Complex configuration space mapping module organizes a response message for the requester. If it is a read request, the data content is filled with all Fs (hexadecimal), and a response is returned to the requester.

[0109] See Figure 11 As shown, Figure 11 This diagram illustrates the address distribution of the configuration space mapping in the Root Complex configuration space address mapping. Each Root Complex maps to a 256MB address space, each bus maps to a 1MB address space, each device maps to a 32KB address space, and each function maps to a 4KB address space. A 4KB address space is a minimum mapping unit, corresponding to the configuration space of a PCIe Endpoint device. Here, M and K are computer data processing units: 1MB = 1024 * 1024, 1KB = 1024.

[0110] See Figure 12 As shown, the Root Complex Memory address space mapping module describes its working mechanism. (The last sentence appears to be incomplete and possibly contains errors. It doesn't translate directly.) Figure 9 The Root Complex configuration space mapping module works in the same way.

[0111] During the initialization of the Root Complex Memory address space mapping module, a FIFO, a core processing thread, and trigger events are created. The core processing thread begins running during initialization and waits for events to be triggered. The simulation of the FIFO space is implemented using the `sc_fifo` data structure provided by the SystemC base library. A single entry in the FIFO includes information such as the requested address, read / write flag, data for the write request / return address for the read request, and data width. The simulation of the core processing thread is implemented using the `sc_thread` method provided by the SystemC base library. The simulation of the trigger events is implemented using the `sc_event` method provided by the SystemC base library.

[0112] The Root Complex Memory address space mapping module is mounted on the CPU bus during initialization. When a bus request is received, the target port processes the request, parses the request content into an internal format, writes it into the internal FIFO space, and then sends an event-triggered notification to the core processing thread. The core processing thread begins processing upon receiving the triggered event.

[0113] See Figure 13 As shown, Figure 13 This is a schematic diagram illustrating the specific workflow of the Root Complex Memory address space mapping module. During initialization, the Root Complex Memory address space mapping module also registers its target-side processing interface with the bus to facilitate receiving and processing bus transactions.

[0114] During initialization, the Root Complex Memory address space mapping module also creates a list of PCIe Endpoint devices and provides binding and unbinding methods for these devices, which are then called by the PCIe Endpoint device registration module. The binding method uses the PCIe Endpoint device's bus number, device number, function number, the starting address of the allocated memory address, and the address range as key lookup and comparison parameters, and creates an index based on the device's bus number, device number, and function number to store the PCIe Endpoint device's object information. The unbinding method uses the same index to clear the stored PCIe Endpoint device's object information.

[0115] When the core processing thread of the Root Complex Memory address space mapping module receives a bus request, it looks up the bus number, device number, and function number of the PCIe Endpoint device corresponding to the requested address based on the requested address information. Specifically, it searches the device list using the requested memory address. When the requested address falls within the address range of a device, it returns the bus number, device number, and function number of the found PCIe Endpoint device, and then uses these as an index to find the object information of the PCIe Endpoint device.

[0116] The search rules are as follows:

[0117] Addr>=Addr_Start and Addr<=Addr_Start+Addr_Range_Size–1

[0118] Where Addr is the memory address space address of the received request, Addr_Start is the starting address of the access address allocated to the memory address space of the PCIeEndpoint device, and Addr_Range_Size is the size of the accessible address range of the memory address space of the PCIeEndpoint device.

[0119] For example:

[0120] The device is configured with Addr_Start as 0x1000_0000 and Addr_Range_Size as 0x100000.

[0121] Therefore, the address range from 0x1000_0000 to 0x1000_0000+0x100000-1 is the address range corresponding to this device.

[0122] The core processing thread of the Root Complex Memory address space mapping module, based on the found PCIeEndpoint device object information, forwards the request to the PCIe Endpoint device object for processing if it determines that a PCIe Endpoint device object has been found. After processing, if it is a read request, it receives the processed data and returns a response to the requester. If it is a write request, it returns the result of the write operation to the requester.

[0123] If it is determined that no PCIe Endpoint device object information is found, the Root Complex Memory address space mapping module organizes a bus exception response message for the requester.

[0124] See Figure 14 As shown, Figure 14This diagram illustrates the address distribution for the Root Complex Memory address space. Each Root Complex maps a segment of the Memory address space. The mapped address space is determined based on the actual situation, but it cannot overlap with other address spaces on the bus. Each Root Complex allocates an address space for its bound PCIe Endpoint device. The size of the address range allocated to each PCIe Endpoint device is determined by the PCIe Endpoint device's own configuration attributes.

[0125] See Figure 15 As shown, Figure 15 Workflow diagram for the PCIe Endpoint device registration module. During initialization, the PCIe Endpoint device registration module creates PCIe Endpoint device configuration information based on the configured number of PCIe Endpoint devices and the relationship between the PCIe Endpoint devices and the Root Complex. It then creates PCIe Endpoint device objects based on the configuration information and saves the device objects in the PCIe Endpoint device object list.

[0126] Based on the device information in the PCIe Endpoint device object list, assign bus number, device number, and function number to the PCIe Endpoint device of each Root Complex according to different Root Complexes, and configure the default BAR address and address range information of the PCIe Endpoint device.

[0127] Based on the device object information in the PCIe Endpoint device object list, obtain the corresponding Root Complex configuration space mapping object, obtain the bus number, device number, and function number of the PCIe Endpoint device, call the binding method provided by the Root Complex configuration space mapping object, and register the bus number, device number, function number of the PCIe Endpoint device, and the object information of the PCIe Endpoint device to the Root Complex configuration space mapping object.

[0128] Based on the device object information in the PCIe Endpoint device object list, obtain the corresponding Root Complex Memory address space mapping object, retrieve the bus number, device number, function number, starting address, address range size, and other information of the PCIe Endpoint device, and call the binding method provided by the Root Complex Memory address space mapping object to register the PCIe Endpoint device's bus number, device number, function number, starting address, address range size, and PCIe Endpoint device object information to the Root Complex Memory address space mapping object.

[0129] See Figure 16 As shown, Figure 16 This diagram illustrates the overall address allocation for the multi-root complex peripheral expansion unit emulation system. The expansion unit emulation system provides multiple root complex emulation units, with 32 actually used. It supports multiple PCIe Endpoint emulation devices, with 256 actually used. Each PCIe Endpoint emulation device can be bound to a corresponding root complex as needed.

[0130] See Figure 17 As shown, Figure 17 This is an overall block diagram for a multi-root complex emulation system. A specific embodiment of the multi-root complex chip emulation system is built by configuring 32 root complex emulation modules and 256 simulated NVMe controller PCIe endpoint devices for firmware debugging. The firmware runs on a simulated CPU and can access the registered simulated PCIe endpoint devices and simulated NVMe controller devices through multiple RC controllers.

[0131] This invention proposes a method for constructing a chip simulation model with a multi-root complex engine. It employs a "SystemC-based transaction-level model with extended peripheral units" design, supporting the simulation implementation of multiple externally extended root complexes on top of the chip simulation system. This approach provides the chip simulation system with engine simulation implementations for multiple root complexes, thereby supporting firmware drivers' access to these complexes. It allows firmware drivers to develop and debug programs for accessing multiple root complexes based on the simulation model before chip tape-out. This enables chip design and firmware development to proceed simultaneously, shortening the project development cycle. The system platform built based on this simulation model can replace some of the functionality of multiple root complexes on a hardware platform for development and testing, saving the cost of building a new hardware testing platform.

[0132] This invention proposes a method for constructing a transaction-level model of a multi-root complex controller based on SystemC. Using SystemC as the basic framework, a chip simulation system peripheral extension unit is established on the basis of the original simulation system. Multiple root complex engines are implemented in the peripheral extension unit. In this combination, a transaction-level simulation model of a chip that supports multiple root complex engines is built, which solves the need for simulation and debugging of chip firmware programs in the research and development of chips containing multi-root complex controllers.

[0133] The simulation design adopts "a transaction-level model based on SystemC, an extended peripheral bus design, and a bus-level transaction distribution" to extend the simulation of multiple PCIe root complex peripherals on the basis of the original chip simulation system.

[0134] This invention employs a simulation design based on a SystemC transaction-level model to extend the peripheral bus. This scheme provides a method for extending the peripheral bus based on a SystemC transaction-level model. Building upon this, a simulation design based on a SystemC transaction-level model to implement multiple root complexes is used. The chip simulation system built on the SystemC transaction-level model runs a custom firmware program within the chip's executable unit. It can access multiple root complexes in the peripheral expansion unit and supports configuring multiple PCIe endpoint devices. The newly constructed simulation system can support the debugging of multiple root complex simulation devices by the custom firmware program within the chip.

[0135] This invention proposes a method for constructing a transaction-level model of a multi-root complex controller based on SystemC. Using SystemC as the basic framework, a peripheral expansion unit for the chip simulation system is established on the basis of the original simulation system. Multiple root complex engines are implemented in the peripheral expansion unit. This combination approach builds a transaction-level simulation model for a chip supporting multiple root complex engines, addressing the need for simulation and debugging of chip firmware programs during the development of chips containing multi-root complex controllers. Although the implementation described in this invention uses the design of "constructing multiple PCIe root complex simulation systems based on a SystemC transaction-level model," the above method for constructing multiple PCIe root complex simulation systems based on the SystemC transaction-level model is only for the purpose of understanding the implementation of this invention and is not intended to limit the invention. Any modifications and changes made without departing from the design and scope of this invention, especially modifications and changes to related system diagrams, mapping relationships, and related software and firmware frameworks, are within the protection scope of this invention.

[0136] A third aspect of the present invention also provides a computer device, including a memory and a processor, wherein the memory stores a computer program that, when executed by the processor, implements the method of any of the above embodiments.

[0137] The computer device includes a processor and a memory, and may also include an input system and an output system. The processor, memory, input system, and output system can be connected via a bus or other means. The input system can receive input digital or character information and generate signal inputs related to the migration of the chip simulation model construction of the multi-root complex engine. The output system may include display devices such as a screen.

[0138] Memory, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules corresponding to the chip simulation model construction method of the multi-Root Complex engine in this application embodiment. Memory may include a program storage area and a data storage area, wherein the program storage area may store the operating system and at least one application program required for a function; the data storage area may store data created using the chip simulation model construction method of the multi-Root Complex engine, etc. Furthermore, memory may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the local module via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0139] In some embodiments, the processor may be a Central Processing Unit (CPU), a controller, a microcontroller, a microprocessor, or other data processing chip. This processor is typically used to control the overall operation of a computer device. In this embodiment, the processor is used to run program code stored in memory or process data. In this embodiment, multiple processors of the computer device execute various server functions and data processing by running non-volatile software programs, instructions, and modules stored in memory, thus implementing the steps of the chip simulation model construction method for the multi-root complex engine described in the above method embodiment.

[0140] It should be understood that, where there is no conflict, all the embodiments, features and advantages described above for the chip simulation model construction method of the multi-root complex engine according to the present invention are equally applicable to the chip simulation model construction and storage medium of the multi-root complex engine according to the present invention.

[0141] Those skilled in the art will also understand that the various exemplary logic blocks, modules, circuits, and algorithm steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, the functionality of various illustrative components, blocks, modules, circuits, and steps has been generally described. Whether this functionality is implemented as software or as hardware depends on the specific application and the design constraints imposed on the system as a whole. Those skilled in the art can implement the functionality in various ways for each specific application, but such implementation decisions should not be construed as departing from the scope of the embodiments disclosed herein.

[0142] Finally, it should be noted that the computer-readable storage medium (e.g., memory) described herein can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. By way of example, and not limitation, non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM), which can act as external cache memory. By way of example, and not limitation, RAM can be obtained in various forms, such as synchronous RAM (DRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct Rambus RAM (DRRAM). The storage devices disclosed herein are intended to include, but are not limited to, these and other suitable types of memory.

[0143] The various exemplary logic blocks, modules, and circuits described herein can be implemented or performed using the following components designed to perform the functions herein: general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP, and / or any other such configuration.

[0144] The above are exemplary embodiments disclosed in this invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments of this invention as defined by the claims. The functions, steps, and / or actions of the methods according to the disclosed embodiments described herein do not need to be performed in any particular order. Furthermore, although the elements disclosed in the embodiments of this invention may be described or claimed individually, they may be understood as multiple unless explicitly limited to a singular number.

[0145] It should be understood that, as used herein, the singular form "a" is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, "and / or" refers to any and all possible combinations of one or more of the associatedly listed items. The embodiment numbers disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0146] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention (including the claims) is limited to these examples. Within the framework of the invention, technical features of the above embodiments or different embodiments can be combined, and many other variations of different aspects of the invention exist, which are not provided in the details for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the protection scope of the invention.

Claims

1. A chip simulation model building system, comprising a chip simulation system, wherein the chip simulation system includes a simulated CPU unit, and the simulated CPU unit runs chip firmware programs; The chip simulation system also includes a simulated root complex unit, which connects the simulated CPU unit to external simulated physical devices. The peripheral expansion unit includes multiple simulated root complex controllers, each of which is connected to one or more simulated physical devices via a simulated peripheral bus. The peripheral expansion unit also includes a top-level configuration module, a CPU bus interface module, a root complex storage address space mapping module, a root complex configuration space mapping module, and a simulated physical device registration module. The CPU bus interface module is responsible for interfacing with the chip simulation system to complete transaction-level access interactions. The CPU bus interface module is also responsible for finding the target module based on the request address and forwarding the corresponding request and response messages. The top-level configuration module is responsible for bus registration from the root complex controller of all peripheral expansion units to the chip simulation system, including the registration of the initiating port of each root complex configuration space mapping module, the registration of the access address of the root complex configuration space mapping module to the target port, the registration of the initiating port of the root complex storage address space mapping module, the registration of the access address of the root complex storage address space mapping module to the target port, and the binding of the simulated physical device to the root complex controller. The root complex configuration space mapping module receives a transaction-level configuration request from the bus, finds the corresponding simulated physical device registered in the configuration space based on the address of the request, and forwards the request to the simulated physical device registered in the root complex configuration space. The root complex storage address space mapping module receives transaction-level storage requests from the bus, finds the corresponding simulated physical device registered in the storage address space based on the address of the storage request, and forwards the request to the simulated physical device registered in the storage address space of the root complex. The simulation physical device registration module is responsible for binding the simulation physical device to the root complex, including registering the configuration space of the simulation physical device to the configuration space of the root complex and registering the storage address space of the simulation physical device to the storage address space of the root complex. The firmware program accesses multiple analog root complex controllers of the peripheral expansion unit through pre-configured analog CPU bus addresses.

2. A method for constructing a chip simulation model, characterized in that, This method is executed based on the chip simulation model construction system described in claim 1, and the chip simulation model construction method includes the following steps: Initialize the chip simulation system, create the master interface and slave interface, and bind one end to the chip simulation system; Initialize the peripheral expansion unit, including creating the initiating port and the target port; Bind the initiating port of the peripheral expansion unit to the slave interface of the chip emulation system, and bind the target port of the peripheral expansion unit to the master interface of the chip emulation system.

3. The chip simulation model construction method according to claim 2, characterized in that, The peripheral expansion unit is a model used to simulate communication between multiple root complex controllers and simulated physical devices.

4. The chip simulation model construction method according to claim 3, characterized in that, Initializing the chip simulation system includes the following steps: The chip simulation system is initialized by creating a master interface and a slave interface, and binding one end of the master interface and slave interface to the chip simulation system; the binding method uses the methods provided by the master interface and slave interface objects. The peripheral expansion unit is initialized. After the peripheral expansion unit is initialized, the initiating port and the target port are created. Bind the target port of the peripheral expansion unit to the main interface of the chip simulation system, and bind the initiating port of the peripheral expansion unit to the slave interface of the chip simulation system; after binding, mutual communication of transaction-level requests between the peripheral expansion unit and the chip simulation system is realized; the binding method uses the method provided by the top-level configuration module of the peripheral expansion unit. Then run the simulation system.

5. The chip simulation model construction method according to claim 4, characterized in that, Peripheral expansion unit initialization includes: top-level configuration module initialization, CPU bus interface module initialization, root complex configuration space mapping module initialization, root complex memory address space mapping module initialization, and simulation physical device configuration information initialization; among which: During initialization, the top-level configuration module creates a specified number of root complex configuration space mapping objects, a specified number of root complex memory address space mapping objects, and a specified number of simulation physical device objects, based on the simulation requirements of the chip simulation system. During initialization, the top-level configuration module registers the initiation port of the root complex configuration space mapping object and the initiation port of the root complex storage address space mapping object to the CPU bus. During initialization, the top-level configuration module registers the target port of the root complex configuration space mapping object and the configuration space address and address range size allocated to the root complex configuration space mapping object to the CPU bus, and registers the target port of the root complex storage address space mapping object and the address and address range size allocated to the root complex storage address space mapping object to the CPU bus. During initialization, the top-level configuration module registers the information of the simulated physical device object and the bus number, device number, and function number of the simulated physical device object to the root complex configuration space mapping object. It also registers the information of the simulated physical device object and the bus number, device number, and function number of the simulated physical device object, as well as the starting address and address range of the storage address space of the simulated physical device object, to the root complex storage address space mapping object.

6. The chip simulation model construction method according to claim 5, characterized in that, In the CPU bus interface module, when the peripheral expansion unit interface module interfaces with the chip simulation system, the target port of the peripheral expansion unit is bound to the main interface of the chip simulation system, and the initiating port of the peripheral expansion unit is bound to the slave interface of the chip simulation system. After binding, the peripheral expansion unit and the chip simulation system can communicate with each other for transaction-level requests.

7. The chip simulation model construction method according to claim 5, characterized in that, CPU bus interface initialization includes the following steps: Through port binding, when the chip emulation system accesses the peripheral device, the chip emulation system initiates a request internally. The request reaches the external target port of the peripheral expansion unit through the bound main interface. The CPU bus interface looks up the device interface corresponding to the address of the request through the bus and forwards the request to the emulation device of the peripheral expansion unit. After being processed by the emulation device, the response result is transmitted back to the chip emulation system. Through port binding, when the peripheral expansion unit initiates a request to the chip emulation system, the request is sent to the slave interface of the chip emulation system through the external initiation port of the peripheral expansion unit. The chip emulation system then passes the request to its internal processing unit. After processing, the internal processing unit of the chip emulation system transmits the response result back to the peripheral expansion unit.

8. The chip simulation model construction method according to claim 5, characterized in that, The working mechanism of the root complex configuration space mapping module is as follows: During initialization, the root complex configuration space mapping module creates a FIFO, a core processing thread, and trigger events. The core processing thread starts running immediately upon initialization, waiting for events to be triggered. The simulation of the FIFO space is implemented using the sc_fifo data structure provided by the SystemC base library. The content of a single entry in the FIFO includes the requested address, read / write identifier, data for the write request / return address for the read request, and data width information. The simulation of the core processing thread is implemented using the sc_thread method provided by the SystemC base library. The simulation of the trigger events is implemented using the sc_event method provided by the SystemC base library.

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