A clock tree synthesis optimization method based on H-tree

Abstract

The application provides an H-tree-based clock tree synthesis optimization method, which comprises the following steps: 1) determining a clock tree root node according to a clock tree structure, and then determining a coverage range of an H tree according to the position distribution of units connected with the root node and the distribution of basic units, so as to determine the distribution and quantity of tap points; 2) calculating a step length and a starting point and planning a direction sequence of wiring through the tap point range and quantity; 3) using a setup file to control the whole layout and wiring process, including clock tree synthesis; 4) using a customized large driving buffer for the H tree buffer and tap point to reduce delay and voltage drop; 5) deleting tap points and 0-fan-out tap points which coincide with macro positions; 6) fully utilizing design rules to remove the buffer at the T-shaped intersection of the H tree; 7) shortening the wiring distance by reversing the buffer direction; and 8) using a trapezoidal via to reduce clock delay. By using the method, the H tree clock delay can be shortened, the H tree power consumption can be reduced, and the problems of voltage drop and electromigration can be reduced.

Description

Technical Field

[0001] This invention belongs to the field of physical design technology for integrated circuit satellite navigation and positioning chips, and particularly relates to clock tree synthesis in the physical design of digital integrated circuits, specifically to a clock tree synthesis optimization method based on H-tree. Background Technology

[0002] The placement and routing phase in digital integrated circuit physical design includes layout planning, power planning, placement planning, clock tree synthesis, and routing. Clock tree synthesis (CTS) is a crucial step in integrated circuit design, primarily used to distribute clock signals across the chip to ensure synchronization and stability between different clock domains. The main goals of clock tree synthesis are to minimize clock signal delay and skew, achieve low-power design, and improve timing convergence.

[0003] Clock trees, based on their distribution characteristics within the chip, can be categorized into various structures, primarily including conventional clock trees, H-trees, X-trees, balanced trees, and clock treemeshes (comb or spine). H-trees are simple and easy to implement. Since the distance from the center point to each tap node is equal, the theoretical clock skew value is zero. Smaller clock skew means easier convergence of hold timing. H-trees are suitable for clean circuits, top-level designs without data selectors (MUX) and integrated gated clocks (ICG), or blocks with arrayed distributed macros. Current patents mostly involve modifying H-trees based on existing layouts to better suit chip design structures. On the other hand, some researchers have performed more detailed optimizations of H-trees, such as optimizing tap placement and splicing gated clocks to achieve smaller skew and timing.

[0004] Currently, H-trees still have significant room for optimization. Compared to conventional clock trees, they have a higher clock delay from the root node to the flip-flops, requiring more buffers and resulting in unnecessary power consumption. The insertion direction of the buffers affects routing, and large drives are prone to voltage drops and electromigration issues. To mitigate the impact of these problems on clock tree synthesis, an H-tree-based clock tree synthesis optimization method is urgently needed. Summary of the Invention

[0005] To address the shortcomings of the existing technologies described above, this invention provides a clock tree synthesis and optimization method based on an H-tree. This method and its specific implementation include the following steps:

[0006] Step 1: Determine the root node of the clock tree based on the structure of the target clock; then determine the coverage area of ​​the H-tree based on the positional distribution of the cells connected to the root node, thereby determining the distribution and number of tap points. The coverage area of ​​the H-tree is a rectangle with its diagonal endpoints A(x1, y1) and B(x2, y2), and the number of tap points is M rows and N columns.

[0007] Step 2: After determining the distribution range and number of tap points, calculate the step size and starting point of each tap point and plan the routing direction and sequence. The X-axis step size is l. x =(x2-x1) / M, Y-axis step size is l y =(y2-y1) / N, starting from S(x1+l) x / 2,y 1+ l y / 2), taking an application example, the present invention adopts the wiring sequence of "HVH", where "H" represents the horizontal direction and "V" represents the vertical direction.

[0008] Step 3: Use the setup.tcl file to save global variables for the entire placement and routing process and manage the entire placement and routing flow. Its purpose is to accelerate the chip back-end design cycle and improve production efficiency.

[0009] Step 4: The H-tree buffer and tap point use a custom large-drive buffer to reduce latency. Its structural features include an embedded decap to reduce peak current and thus reduce voltage drop, and the output pin is connected to a trapezoidal via to reduce timing delay.

[0010] Step 5: Delete tap points that coincide with macro cells and tap points with 0 fanout.

[0011] Step 6: Make full use of the DRV limit to remove the buffer placed at the T-junction of the H-tree.

[0012] Step 7: Shorten the wiring distance by reversing the direction of the buffer.

[0013] Step 8: Use trapezoidal vias to reduce clock latency.

[0014] Step 9: Use a more accurate POCV timing analysis model in the 22nm process.

[0015] As described above, the hybrid clock tree synthesis optimization method and specific implementation based on H-tree of the present invention have the following beneficial effects:

[0016] (1) In terms of timing, shortening the delay reduces the impact of OCV. The method of determining the range of tap points based on the fan-out point position can reduce the distance from the root node to the tap point in the H-tree, thereby reducing the delay. The use of a custom large driver for the H-tree buffer can effectively reduce the delay and speed up signal transmission. At the same time, the use of trapezoidal vias can reduce the RC parasitic parameters of the vias, thereby accelerating signal transmission. Reducing the delay helps to reduce the impact of OCV.

[0017] (2) In terms of power consumption, deleting redundant, zero-fanout tap points can reduce the number of buffers and wiring resources, optimizing T-branch reduces the number of buffers used, and flipping H-tree buffers shortens the wiring distance. The implementation of these three methods has played a certain role in power consumption optimization.

[0018] (3) Shorten the design cycle. This invention concentrates all the global variables required for layout and routing in the setup.tcl file, which facilitates subsequent modifications for projects with different characteristics, and facilitates the reading of automated script data for each stage such as layout planning, power planning, placement planning, clock tree synthesis, and routing. This makes it more suitable for pipeline operations, speeds up the design process, and shortens the design cycle.

[0019] (4) Reduce voltage drop violations. Traditional large drive signal switching will cause a large peak current, resulting in voltage drop violations. This invention uses a custom large drive with a decap physical unit embedded around it, which is equivalent to surrounding it with capacitors to reduce the peak current and thus reduce voltage drop violations.

[0020] (5) Reduce electromigration violations. Optimize the traditional via structure by using trapezoidal vias at the output of the H-tree buffer, increasing the number of vias and effectively reducing the current sharing of via resistance, thereby improving the electromigration problem. Attached Figure Description

[0021] To further illustrate the contents described in this invention, the specific embodiments of the invention will be described in more detail below with reference to the accompanying drawings. It should be understood that these drawings are merely typical examples and should not be construed as limiting the scope of the invention.

[0022] Figure 1 A flowchart of a clock tree synthesis optimization method based on H-tree.

[0023] Figure 2 A clock structure diagram commonly found in slabs.

[0024] Figure 3 Tap point location calculation diagram.

[0025] Figure 4 Setup file data flow and control.

[0026] Figure 5A top view of the large drive buffer structure.

[0027] Figure 6 The tap point is located in the application case.

[0028] Figure 7 The idea of ​​optimizing T-shaped branches.

[0029] Figure 8 T-shaped optimization scenario 2.

[0030] Figure 9 Buffer toggling optimization.

[0031] Figure 10 Trapezoidal via diagram. Detailed Implementation

[0032] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0033] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0034] This invention provides a clock tree synthesis and optimization method based on an H-tree, such as... Figure 1 As shown, the method includes:

[0035] Step S01: Examine the structure of the target clock and determine the root node of the clock tree; use ICC2 to examine the positional distribution of the cells connected to the root node to determine the distribution range and number of H-tree tap points. Since most of the basic units in this embodiment are concentrated in the upper half, a conventional H-tree structure covering the entire block is not used. Instead, an H-tree structure covering the upper half of the block's rectangle is chosen, with the two diagonal coordinates A(x1, y1) and B(x2, y2), and the number of tap points being M×N (M rows and N columns). This invention does not impose constraints on the diagonal endpoint coordinates and the number of tap points; these are mainly dynamically determined by the H-tree coverage.

[0036] In the back-end placement and routing, once the placement of the basic units is completed, the clock structure can be determined, such as... Figure 2 As shown. Due to the limitation of H-trees in directly synthesizing flip-flops by passing through gated clocks (ICGs) and data selectors (MUXs), when a data selector in the first level (L1) is the root node of the clock tree, the tap point can only be directly connected to the flip-flops, data selectors, and gated clocks in the second level. By default, EDA tools place tap points with equal height and width according to the length and width of the design block. This may result in a large number of tap points having no basic unit connection at their output, i.e., tap points fan out at 0. To solve this problem, this invention determines the distribution range of tap points based on the distribution of the second-level basic units and flip-flops (FFs). The second-level basic units of this invention are basically distributed within a rectangular area with diagonal endpoints A(x1, y1) and B(x2, y2). Therefore, M×N tap points are selected for placement in this area.

[0037] Step S02: After determining the distribution range and quantity, calculate the step size of the tap points and plan the direction and sequence of the wiring. This invention adopts the "HVH" wiring sequence. After obtaining the coverage area and determining the number of tap points, the step size can be calculated. Assuming the tap points are placed in M ​​rows and N columns, the X-axis step size is l. x =(x2-x1) / M, Y-axis step size is l y =(y2-y1) / N, starting from S(x1+l) x / 2,y 1+ l y / 2). The routing direction is generally related to the clock source location and the tap point location, where "H" represents the horizontal direction and "V" represents the vertical direction. When M=2 and N=4, the effect is as follows. Figure 3 .

[0038] Step S03: Create the setup.tcl file. The setup file stores global variables throughout the entire placement and routing process, controlling the entire floorplan, place, clock tree synthesis (CTS), and routing workflow. The file is written in TCL (Tool Command Language), hence the .tcl extension. To accelerate the design cycle and facilitate subsequent version optimizations, relevant parameters for the entire placement and routing phase are typically placed in the setup.tcl file written in TCL to improve design efficiency. The data flow is as follows: Figure 4 .

[0039] Configure parameters related to the H-tree. To build an H-tree using the ICC2 placement and routing tool, you need to set the number of rows and columns, buffer drive type, DRV repeat distance, routing direction order, clock source, routing layer of the clock tree, and prefix names of buffers and tap points. These parameters are all written in the setup.tcl file.

[0040] Step S04: Optimize the buffer. Using an H-tree increases the distance from the root node to the flip-flop, while using a large drive buffer can effectively shorten the arrival time delay between the two. However, conventional large drives can cause a significant voltage drop (IR drop). Therefore, the H-tree buffer and tap point of this invention both adopt a uniformly customized large drive buffer, the structure of which is as follows: Figure 5 Its built-in decap basic unit can reduce peak current and thus reduce voltage drop (IR Drop). The trapezoidal via connected to the output pin of the buffer also has a certain effect on reducing timing delay.

[0041] Optimize the number of tap points. Since some tap points may lie on large macros, these tap points need to be deleted. First, obtain the coordinates of the diagonal endpoints of the macro and the coordinates of each tap point, and determine if the tap point's coordinates are within the macro's range. If so, delete the tap point. Secondly, given the initial H-tree configuration, check if the tap point's fan-out is 0. If it is, delete the tap point, thus reducing the number of tap points, power consumption, and routing.

[0042] Step S05: Synthesize the tap point, i.e., place the tap point on the layout. Set the starting coordinates and step size of the tap, and set the load network ($NET) of the tap point to the network of the output pin of the high fan-out cell, such as... Figure 2 The network name of the L1 level MUX output pin. Then, the tap point is generated using the create_clock_driver instruction. The tap point uses a custom large driver buffer, and the effect is as follows. Figure 6 The prefix name is htree_tap. Figure 6 This is an application example of the present invention. In the entire design block, the upper half surrounded by the dashed line is the H-tree coverage area. Within the area, tap points are arranged in a 2×4 manner. Since one tap point overlaps with the macro, it is deleted. The upper right corner is the input and output port of the block.

[0043] Synthesize the H-tree. Configure the load network with Non-Default Routing (NDR) using twice the width and twice the spacing, and route on metal layers M6 and M5. The increased width and higher-layer routing help reduce resistance and achieve better timing; the increased width also improves electromigration resistance, while the doubled spacing helps reduce signal crosstalk. Then, synthesize the H-tree using the instruction `synthesize_multisource_global_clock_trees`. The H-tree buffer uses the same custom large driver as the tap point, and then the Zroute engine is used to complete the connections down to the pins.

[0044] Tap point assignment. Set the clock name, the pin of the driven object to the output pin of the tap, and the number of taps to M×N. The instruction synthesize_multisource_clock_taps connects the sinks to the nearest tap point.

[0045] Step S06: Optimize T-shaped branches. Conventional H-trees typically place buffers at T-shaped intersections, resulting in unnecessary power consumption. To compensate for this, it's necessary to fully utilize DRV constraints to save on buffers at intersections. The approach is as follows: Figure 7 Where Ir represents the maximum transmission distance of the buffer output signal, and X represents the distance from the buffer to the T-shaped intersection of the H-tree. The specific steps are as follows: First, obtain the pin attributes of the two buffers in the T-shaped branch. Taking one of them, buffer_L4, as an example, let the coordinates of buffer_L5 be (x5, y5), and the coordinates of buffer_L4 be (x4, y4). Let the distance from buffer_L4 to buffer_L5 be d, and the distance from the new buffer starting point to buffer_L5 be d. head (n), the maximum distance for buffer insertion is d. repeater There are three possible scenarios. When d <d head No action is taken when (n) is true; when d is true, no action is taken. head (n) <d< d head (n)+d repeater At times, such as Figure 8 Set the x-coordinate of the new buffer. pos =x5-d repeater Branch wiring allowance, i.e., tail length d tail =|x pos -x4|, the distance d from the new buffer start point of the next branch to buffer_l4. head (n-1)=(d repeater -d tail ) / 2. Determine if the tap point has been reached. If it has, then in (x pos ,ypos Insert the branch point into the buffer and proceed to the next loop. If the loop does not reach the branch point, change the position of the branch point buffer_l4 to (x pos ,y pos This is equivalent to deleting a buffer and then recursively using the function; when d > d head (n)+d repeater At that time, directly in (x pos ,y pos Insert the H-tree buffer at position ) and update x. pos =x pos -d repeater Then in (x pos ,y pos Insert the buffer. Then update d. tail =|x pos -x3| and d head (n-1)=(d repeater -d tail ) / 2. Similar to the second case, determine whether the tap point has been reached. If it has been reached, then in (x pos ,y pos Insert the buffer at the point and proceed to the next loop. If the point is not reached, change the position of the branch point buffer_l4 to (x pos ,y pos Then use the function recursively.

[0046] Conventional H-trees typically place buffers at wiring intersections. Optimizing T-branching fully utilizes the DRV limit, resulting in fewer inserted buffers.

[0047] Step S07: Shorten the wiring by flipping the buffer. For example... Figure 9 The orientation of the buffer also has a certain impact on the routing. By flipping the buffer, the routing distance can be shortened to a certain extent. The shorter the distance, the smaller the delay, which is very beneficial for building clock trees. First, obtain all H-tree buffers, then obtain the coordinates of the buffer input pins and the output pins of the preceding stage driver buffer, and finally calculate the center coordinates and their Manhattan distances. Flip the buffers and calculate their Manhattan distances again. If the distance is too large, cancel the flip. The steps to obtain the output pin of the preceding stage buffer are: first obtain the wire net connected to the input pin of the buffer, and then obtain the output pin connected to the wire. This pin is the output pin of the preceding stage buffer. Let the center coordinates of the input pin of the buffer be (x... c1 y c1 The coordinates of the output pin of the pre-stage buffer are (x...). c2 y c2 If ), then their Manhattan distance is d. man = |xc1 - x c2 |+| y c1 - y c2 |

[0048] Step S08: Add a ladder via. Ladder vias have more vias, and the metal layer connected to the via extends outwards as conductors, resulting in lower resistance and capacitance (RC) parasitic parameters. The structure is as follows: Figure 10 The steps to add a trapezoidal via are as follows: First, create a via rule named LDV, with the via layers VIA2, VIA3, VIA4, and VIA5. The number of rows in each via layer is 3, 8, 3, and 8, and the number of columns is 8, 3, 8, and 3, respectively. Second, set the routing properties to high execution and enable electromigration. Then, set the icc2 option to allow trapezoidal via insertion, configure the trapezoidal via connected to the H-tree buffer output to use the LDV rule, and finally insert the trapezoidal via.

[0049] Step S09: Use the command `clock_opt -from build_clock -to route_clock` to perform clock tree routing and enable POCV mode for timing analysis. Using the POCV timing analysis model can obtain more accurate static timing analysis data. Compared to the AOCV analysis model, AOCV timing analysis is more pessimistic and has a greater difficulty in timing convergence.

[0050] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A clock tree synthesis and optimization method based on H-tree, characterized in that, include: Step 1: Determine the root node of the clock tree based on the structure of the target clock; Then, the coverage area of ​​the H-tree is determined based on the positional distribution of the units connected to the root node and the distribution of the basic units in the plate, thereby determining the distribution and number of tap points. The coverage area of ​​the H-tree is a rectangle with its diagonal endpoints being A(x1, y1) and B(x2, y2), and the number of tap points is M rows and N columns. Step 2: After determining the distribution range and number of the tap points, calculate the step size and starting point of each tap point and plan the direction and sequence of the wiring. The X-axis step size is l. x =(x2-x1) / M, Y-axis step size is l y =(y2-y1) / N, starting from S(x1+l) x / 2,y 1+ l y / 2), the wiring direction order is HVH, where H represents the horizontal direction and V represents the vertical direction; Step 3: Use the setup.tcl file to save global variables for the entire placement and routing process and to manage the entire placement and routing flow; Step 4: The H-tree buffer and tap point use a custom large-drive buffer to reduce latency. Its structural features include decap units embedded on the left and right sides to reduce peak current and thus reduce voltage drop. The output pin is connected to a trapezoidal via close to the center, which also reduces timing delay. Step 5: Delete tap points that coincide with macrocells and tap points with 0 fanout; Step 6: Make full use of the DRV limit to remove the buffer placed at the T-junction of the H-tree; Step 7: Shorten the wiring distance by flipping the direction of the buffer; Step 8: Use trapezoidal vias for all vias on the H-tree to reduce clock latency; Step 9: Use a more accurate POCV timing analysis model in the 22nm process.

2. The clock tree synthesis and optimization method based on H-tree according to claim 1, characterized in that, Step three includes: The setup.tcl file is used to uniformly manage layout planning, power planning, placement planning, clock tree synthesis, and routing processes. It stores global variables for the entire placement and routing process. During clock tree synthesis, the setup file stores the number of rows and columns of tap points, buffer drive type, DRV repetition distance, routing direction sequence, clock source, clock tree routing layer, and prefix name information for buffers and tap points.

3. The clock tree synthesis and optimization method based on H-tree according to claim 1, characterized in that, In step six, optimizing the T-branch, the buffer at the intersection of the H-tree T-branch is deleted and the position of the next-level buffer is redefined. Let the maximum transmission distance be Ir, and the distance of the buffer closest to the intersection at this level be X. Then the distance between the next-level buffer and the intersection is (Ir-X) / 2, not 0.5×Ir.

4. The clock tree synthesis and optimization method based on H-tree according to claim 1, characterized in that, Step seven includes: first, obtaining the coordinates of the input pin of the buffer and the output pin of the preceding stage drive buffer; then, calculating the center coordinates and their Manhattan distance; flipping the buffer; recalculating their Manhattan distance; and canceling the flip if it is too large.

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