Integrated Circuit Block Simulation Method Based on Signal Flow and Graph Analysis

Abstract

This invention discloses a block-based simulation method for integrated circuits based on signal flow and graph analysis. It constructs a directed graph of the integrated circuit by using node voltages and device currents as vertices and the dependencies between them as edges. This directed graph is then divided into several strongly connected components, each containing bidirectional paths between vertices. Strongly connected components with more than a threshold of vertices are further divided based on cyclic unidirectional edges. Finally, defect block simulation is performed based on the resulting strongly connected components. This invention models the control relationship between device currents and voltage nodes in the integrated circuit using a directed graph, and then divides the directed graph into multiple strongly connected components with weak connectivity, achieving block-based defect simulation and thus improving simulation efficiency.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and more specifically, relates to an integrated circuit block simulation method based on signal flow and graph analysis. Background Technology

[0002] Large-scale integrated circuits (LSIs) have wide applications in modern society, and their reliability is crucial to the normal and safe operation of various chips. Furthermore, comprehensive defect simulation during the integrated circuit design phase is a fundamental guarantee for improving testability, which is also a basic requirement for automotive-grade chip design. For integrated circuits, each resistor and capacitor has two types of defect models, while a single MOSFET has six basic defect models. Therefore, the defect set of analog / mixed-signal integrated circuits containing tens of thousands of devices is extremely large.

[0003] In defect simulation, DC simulation is currently the most commonly used and fastest method. At the circuit level, any lumped-parameter circuit can be modeled using Kirchhoff's Current Law (KCL), Voltage Law (KVL), and branch constraint equations. The simulator uses numerical methods (such as iterative methods or matrix operations) to solve the equations to determine the voltage at each node. The solution process may require multiple iterations of Gaussian elimination to represent the circuit equations as an augmented matrix containing the circuit's admittance matrix and power vectors. Then, Gaussian elimination is used to perform row operations on the augmented matrix, transforming it into an upper triangular matrix. Finally, a back-substitution method is used, starting from the last row, to solve for the voltage at each node. The advantage of Gaussian elimination is its ability to handle complex circuit equations and allows for numerical optimization during iteration, improving computational efficiency. However, for large-scale circuit simulations, numerical analysis algorithms may face problems such as excessively large matrix sizes and computational loads. A complete defect simulation often takes months, negatively impacting practical applications and requiring further improvement. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a block simulation method for integrated circuits based on signal flow and graph analysis. The method uses a directed graph to model the control relationship between the device current and voltage nodes of the integrated circuit, and then divides the directed graph into multiple strongly connected blocks with weak connectivity to achieve block simulation of defects, thereby improving simulation efficiency.

[0005] To achieve the above-mentioned objectives, the integrated circuit block simulation method based on signal flow and graph analysis of the present invention includes the following steps:

[0006] S1: Obtain the integrated circuit netlist, then flatten it to obtain a two-dimensional list of circuit devices, including each device and the nodes connected to it;

[0007] S2: Construct a directed graph of integrated circuits by taking the voltage of each node and the device current between nodes in the two-dimensional list of circuit devices as the vertices of the graph. The edges between nodes are determined as follows: if the device current between nodes depends on the node voltage, then there is a directed edge from the node voltage to the device current; if the node voltage depends on the device current between nodes, then there is a directed edge from the device current to the node voltage.

[0008] S3: Divide the directed graph of the integrated circuit into several strongly connected components, and there are bidirectional paths between each vertex in each strongly connected component;

[0009] S4: For each strongly connected component, determine whether its number of nodes is greater than a preset threshold. If not, do not perform any operation. If it is greater, search for whether there is a cyclic one-way edge in the strongly connected component. The search method is as follows: if there is a one-way edge in the strongly connected component and there is no path between the starting point and the ending point of the one-way edge, then the one-way edge is a cyclic one-way edge. Then, disconnect all the cyclic one-way edges found in the search, and use the same method as in step S3 to further divide the strongly connected component into several strongly connected components, thereby obtaining the final strongly connected component partitioning result.

[0010] S5: Perform block defect simulation based on the strongly connected components obtained from the partitioning. The specific method is as follows:

[0011] Let K be the number of strongly connected components. Perform one flawless simulation and record the standard values ​​of all vertices. Let SCC be the number of strongly connected components k. k The set of connection points with other strongly connected components is V. k The standard value of each connection point is v. k,d d = 1, 2, ..., D k D k V represents the set of connection points k The number of vertices in the strongly connected component SCC; k Connect the set of points V k Medium-strength connected component SCC k The standard values ​​of the input vertices are used as the strongly connected component SCC. k The input for strongly connected component SCC k Simulations were performed by sequentially injecting all defects into the strongly connected component SCC. k All measuring points within the area determine whether each defect is measurable.

[0012] This invention presents an integrated circuit block simulation method based on signal flow and graph analysis. It constructs a directed graph of the integrated circuit by using node voltages and device currents in the integrated circuit as vertices and the dependencies between node voltages and device currents as edges. The directed graph of the integrated circuit is divided into several strongly connected components. There are bidirectional paths between each vertex in each strongly connected component. Then, the strongly connected components with more than a threshold number of vertices are further divided based on cyclic unidirectional edges. Finally, defect block simulation is performed based on the strongly connected components obtained from the division.

[0013] This invention uses signal flow analysis to model the control relationship between device current and voltage nodes in an integrated circuit using a directed graph. Then, it uses a graph analysis algorithm to divide the integrated circuit into multiple strongly connected blocks with weak connectivity. Based on the unidirectional signal transmission relationship in the weak connectivity graph, it achieves block simulation of defects. This greatly reduces the scale of matrix operations and allows for parallel simulation of multiple strongly connected block circuits, further shortening the simulation time. Attached Figure Description

[0014] Figure 1 These are example diagrams illustrating common circuit device modeling methods;

[0015] Figure 2 This is a modeling example of an integrated circuit;

[0016] Figure 3 yes Figure 2 The directed graph obtained by modeling the integrated circuit shown;

[0017] Figure 4 yes Figure 3 Example diagram of strongly connected components of a directed graph model shown;

[0018] Figure 5 This is an example diagram of a cyclic one-way edge;

[0019] Figure 6 This is a flowchart illustrating a specific implementation of the integrated circuit block simulation method based on signal flow and graph analysis of the present invention.

[0020] Figure 7 This is a flowchart of constructing a directed graph of an integrated circuit in this embodiment;

[0021] Figure 8 This is a flowchart of the strongly connected components obtained based on the Tarjan algorithm in this embodiment;

[0022] Figure 9 yes Figure 2 A simulation diagram of the circuit shown;

[0023] Figure 10 This is a circuit diagram of the BandGap reference circuit in this embodiment;

[0024] Figure 11 This is the directed graph of the BandGap reference circuit in this embodiment;

[0025] Figure 12 This is a schematic diagram of a strongly connected component in this embodiment;

[0026] Figure 13 This is a schematic diagram of the strongly connected component finally obtained in this embodiment. Detailed Implementation

[0027] The specific embodiments of the present invention will now be described with reference to the accompanying drawings to enable those skilled in the art to better understand the invention. It should be particularly noted that in the following description, detailed descriptions of known functions and designs that might obscure the main content of the invention will be omitted here.

[0028] To better illustrate the technical solution of the present invention, the technical principles on which the present invention is based will be briefly explained first.

[0029] For integrated circuits, the node voltage in the circuit can be defined as V, and the current between nodes (i.e., the current flowing through the device) can be defined as I, with the specific direction depending on the circuit structure. In a circuit, such voltage and current may have a bidirectional dependence or a unidirectional dependence: for example, the voltage across a node of a resistor and the current between the nodes have a bidirectional dependence, while for a MOSFET, since the gate voltage can control the current between the source and drain, but not vice versa, it has a unidirectional dependence.

[0030] This invention defines a relationship where a current I changes due to the influence of a node V, i.e., the partial derivative of I with respect to V is non-zero. This is called V→I, representing a dependency between I and V, and vice versa. In other words, any small change in V will lead to a change in I, which is represented in a directed graph as V→I. Figure 1 These are example diagrams illustrating common circuit device modeling methods. For example... Figure 1 As shown, based on the fundamental theory of circuit principles, the relationship between node voltage and inter-node current for the following common circuit components—including resistors, capacitors, inductors, MOSFETs, and transistors—can be transformed into a directed graph. Each node in the directed graph represents either inter-node current or node voltage, while the arrows represent the dependencies described above.

[0031] Figure 2 This is a modeling example of an integrated circuit. Figure 3 yes Figure 2 The directed graph obtained from the integrated circuit model shown is as follows. Figure 2 and Figure 3 As shown, voltage sources and grounding points do not need to be considered here because the simulation of defects does not target voltage sources and grounding injection defects, so they do not need to be taken into account.

[0032] During simulation, the circuit can export a netlist. The netlist file consists of two main parts: circuit component names and node numbers, rather than a direct relationship between voltage and current. Therefore, in... Figure 1 Based on this, the device name of the MOSFET is used to replace the current Ids inside the MOSFET, and the node name is used to replace the voltage value of each pin; the same applies to the cathode R and capacitor C; for transistors, such as Figure 1 The conversion method splits the BJT device into two parts, Ibe and Ice, represented by Q_b and Q_c respectively, while the voltage is still identified by the node name. Through this conversion method, the device and node connection relationships in the circuit can be directly analyzed, and the connection relationships between current and voltage can be determined, allowing for further research using graphical analysis methods.

[0033] Definition: Strongly Connected Graph (SCC)

[0034] In a directed graph G, if for every pair of vertices v i v j v i ≠v j From v i to v j and from v j to v i If all paths exist, then G is called a strongly connected graph. A maximal strongly connected subgraph in a directed graph is called a strongly connected component of the directed graph. Weak connectivity is the opposite; that is, only v exists. i to v j The path, but v does not exist. j to v i The path.

[0035] Figure 4 yes Figure 3 The diagram shows an example of strongly connected components in a directed graph model. Figure 4 As shown, Figure 3 The directed graph model shown can be divided into... Figure 4 The dashed box in the middle indicates the three strongly connected components SCC1, SCC2, and SCC3 of the strongly connected graph.

[0036] After identifying the weak connectivity relationships between strongly connected components, each strongly connected graph can be viewed as a supernode, or a condensed node. All such condensed nodes must form a directed acyclic graph (DAG). DAGs can be topologically sorted. Regarding the propagation of the impact of defects in a DAG, the following theorem clearly holds, defining SCC. k Let F be the k-th strongly connected component, and let F be its defect set. k SCC k The set of connection points with other strongly connected components is V.k (For example Figure 4 Vertex I3 and vertex V3 of SCC2.

[0037] Theorem 1: According to signal flow analysis, for Injection set F k The defect f in the directed topology graph has a subsequent SCC. k,后序 In the circuit, if in SCC k and SCC k,后序 If adding a measuring point at connection point v fails to detect the defect f, then v serves as the subsequent circuit SCC. k,后序 The input must be "normal" data, then SCC k,后序 It is impossible to detect defect f if any point in the middle is used as the measuring point.

[0038] For example, Figure 4 V1 serves as the output of SCC1 and the input of SCC2. If the defect f injected into SCC1 is unmeasurable in V1, it means that the defect f cannot be measured at any measurement point in the subsequent SCC2.

[0039] Theorem 2: According to signal flow analysis, for Since the signal flow propagates according to the direction relationship of the directed graph, the defect response of the injected defect f cannot be found in its preceding SCC in the directed topology graph. k,前序 Measured at any point in the circuit.

[0040] Based on the above analysis, it can be seen that originally, it was necessary to first perform a defect-free simulation of the entire circuit to obtain the defect-free standard values ​​at all measurement points, and then list the defects of the entire circuit as F = {f1, f2, ..., f...}. P The P defects are simulated sequentially, and the measurability of the defect is determined by comparing the output of each measurement point with its standard value. Now, by using signal flow and graph analysis methods to identify each strongly connected component, defect simulation can be performed in blocks, thereby improving the efficiency of defect simulation.

[0041] Proof of correctness: The defect coverage obtained from block simulation is the same as that obtained from direct full simulation, with the only improvement being in time efficiency. The reason for the same coverage is that for... According to Theorem 2, the defect response of a given condition cannot be determined by its preceding SCC. k,前序 It was measured; at the same time, according to Theorem 1, if this SCC k If the measuring points in the test cannot detect the defect, then SCC k,后序 It also cannot be measured. In conclusion, the accuracy of defect coverage can be guaranteed.

[0042] Furthermore, as shown in Theorem 2, defect responses cannot propagate to preorder strongly connected components; therefore, SCC is adopted. k,前序 V k,前序 The defect-free standard value is used as the SCC of each strongly connected component. k The input is correct.

[0043] The existing method involves establishing an equation for the entire circuit and solving for the voltage value for each defect. Let's assume there are N devices and T nodes, the size of the solution matrix constructed by the simulator is N×T, and the simulation time is positively correlated with the size of the solution matrix.

[0044] T all =N×T (1)

[0045] Now, after partitioning, assuming it's divided into M equally distributed strongly connected components with weak connectivity, the simulation time is now:

[0046]

[0047] Where, N m T m These represent the number of devices and nodes contained in the m-th strong connection block, respectively.

[0048] To more intuitively demonstrate the reduction in simulation time, let's assume that after partitioning, the circuit is divided into M strongly connected components with the same number of devices and nodes. Then, equation (2) will become:

[0049]

[0050] Formula (4) can then be obtained:

[0051]

[0052] It is evident that, theoretically, this can reduce the iterative solution matrix size by M times the number of strongly connected components. Furthermore, due to T... all The positive correlation means that, in reality, since the total simulation time is non-linearly related to the circuit size, this graphical analysis method can bring a time reduction of more than M times the theoretical limit.

[0053] Furthermore, the above calculations, during the summation process, are based on the time reduction obtained under the default condition of serial simulation. In fact, the method of this invention has demonstrated that it is possible to use parallel simulation to simultaneously simulate the defects of multiple strongly connected components, thus the final compression time will be shorter and the method more efficient.

[0054] As the theoretical analysis above shows, the simulation efficiency of block segmentation with weak connectivity is closely related to the number M of strongly connected components that can be segmented. That is, the larger M is, the more significant the time reduction this method can achieve. Therefore, it is desirable for a directed graph of a circuit diagram to identify a larger number of strongly connected components. In actual circuits, the number of objectively existing strongly connected components may be insufficient. Therefore, this invention also introduces an algorithm to segment and identify "Cyclic Unidirectional Edges" (CUEs) within each strongly connected component: if breaking several such edges in a strongly connected component can split the original strongly connected component into more strongly connected components, then such an edge is called a cyclic unidirectional edge. Then, by adding external switches, the breaking and connecting of "cyclic unidirectional edges" are simulated, thereby simulating circuits with more strongly connected components and further reducing simulation time. The principle of identifying cyclic unidirectional edges within a strongly connected component is given here:

[0055] For a one-way edge L i The two vertices connected are called the starting point b. i and termination point e i If there is no path with fully bidirectional edges, such that... Then the one-way edge L between these two points is called i It is a cyclic one-way edge.

[0056] Proof: Proof by contradiction. Assume there exists a path with at least one bidirectional edge. Even if the one-way edge L is disconnected... i After that, starting point b i and termination point e i They still belong to the same strongly connected component SCC, that is, disconnect L. i No more strongly connected components were generated, therefore the statement is invalid, thus proving the statement.

[0057] Figure 5 This is an example diagram of a cyclic one-way edge. For example... Figure 5 As shown, the entire SCC is a strongly connected component. For L1, there is no fully bidirectional edge path from vertex V3 to I4 that connects the two nodes; therefore, L1 is a CUE. The same applies to L2. Clearly, disconnecting either L1 or L2 can split SCC into two strongly connected components, SCC_1 and SCC_2, which have weak connectivity. Conversely, for L3, since there exists... Such a fully bilateral path, even if L3 is disconnected, cannot generate additional strongly connected components on the original basis, therefore it is not a CUE.

[0058] Based on the above theoretical analysis, this invention proposes a block simulation method for integrated circuits based on signal flow and graph analysis. Figure 6This is a flowchart illustrating a specific implementation of the integrated circuit block simulation method based on signal flow and graph analysis according to the present invention. Figure 6 As shown, the specific steps of the integrated circuit block simulation method based on signal flow and graph analysis of this invention include:

[0059] S601: Obtain the integrated circuit netlist:

[0060] Obtain the integrated circuit netlist, then flatten it to obtain a two-dimensional list of circuit devices, containing each device and the nodes it connects to. The existing circuit netlist, after flattening, is a list in the form of [circuit device name, adjacent node 1, adjacent node 2, ...], for example, a two-dimensional list set formed by [['I79.M55','8','1','0'], ['I79.M60','18','19','20'], ['I79.R248','30','31'], ['I79.C1','12','13'], ['I79.Q2','0','70','29'], ...]. The adjacent node pins of MOS and BJT devices are arranged in the order of drain, gate, source, collector, base, emitter, respectively.

[0061] S602: Constructing a directed graph for integrated circuits:

[0062] The voltage of each node in the two-dimensional list of circuit devices and the device current between nodes are used as vertices of the graph to construct a directed graph of integrated circuits. The edges between nodes are determined as follows: if the device current between nodes depends on the voltage of the node, then there is a directed edge from the node voltage to the device current; if the voltage of a node depends on the device current between nodes, then there is a directed edge from the device current to the node voltage.

[0063] Figure 7 This is a flowchart illustrating the construction of the directed graph of the integrated circuit in this embodiment. For example... Figure 7 As shown, the specific steps for constructing a directed graph of an integrated circuit in this invention include:

[0064] S701: Initialize the directed graph object of the integrated circuit:

[0065] The directed graph object of the integrated circuit is initialized using a key-value dictionary. The key is the node voltage or device current obtained from the two-dimensional list of circuit devices, and the value is the name of the node or device that is unidirectionally pointed to by the key in the directed graph. All values ​​are initialized to empty. It can be seen that the key-value dictionary format can accurately represent the connection relationship of the directed graph of the integrated circuit.

[0066] S702: Generate device objects and node objects:

[0067] Based on the two-dimensional list of circuit components, component objects (`components`) and node objects (`nodes`) are generated. Both `components` and `nodes` are in key-value dictionary format. The key-value dictionary of `components` stores the list of adjacent nodes for each component, and the key-value dictionary of `nodes` stores the list of names of adjacent components for each node. The specific directed relationships of the entire directed graph will be obtained by analyzing `components` and `nodes`.

[0068] S703: Determining directed edges based on signal flow analysis:

[0069] The edges of the directed graph of the integrated circuit are determined by analyzing nodes and components separately. The specific method is as follows:

[0070] For each node object (nodes), an edge is generated pointing from the node voltage to the corresponding device current. The corresponding device current is then added to the value list of the node voltage in the directed graph object of the integrated circuit. This is because, based on signal flow analysis, there are only two scenarios: unidirectional voltage control of current and bidirectional voltage and current control. Therefore, the node voltage can be directly made to point to the device current, i.e., voltage to current.

[0071] For device components, a case-by-case analysis is required. Since the gate voltage of a MOSFET unidirectionally controls the drain-source (DS) current, for MOSFET devices within the device components, a boundary is generated where the DS current points to the source and drain voltages. For BJTs within the device components, a boundary is generated where the transistor current points to the base and collector voltages. For other devices within the device components, a boundary is generated where the device current points to the corresponding node voltage.

[0072] S603: Divide strongly connected components:

[0073] The directed graph of the integrated circuit is divided into several strongly connected components, and there are bidirectional paths between each vertex in each strongly connected component.

[0074] In this embodiment, the Tarjan algorithm is used to partition the strongly connected components. Figure 8 This is a flowchart illustrating the process of obtaining strongly connected components based on the Tarjan algorithm in this embodiment. For example... Figure 8 As shown, the specific steps for obtaining strongly connected subgraphs based on the Tarjan algorithm in this embodiment include:

[0075] S801: Initialization:

[0076] Create an empty stack, mark the visited state of all vertices as unvisited, initialize the global variable index = 0, initialize an empty list result to record the strongly connected subgraphs, and initialize the state of all vertices as unvisited.

[0077] S802: Randomly select an unvisited vertex v.

[0078] S803: Perform depth-first search:

[0079] Mark the current vertex v as visited, then push vertex v onto the stack. Perform a depth-first search (DFS) on vertex v, setting the timestamp DFN[v] and the earliest timestamp LOW[v] of vertex v to the current index value. Increment the global variable index by 1.

[0080] For each adjacent vertex w of vertex v, if vertex w has not been visited, a depth-first search is recursively performed and the LOW value of vertex v is updated to min(LOW[v], LOW[w]). If vertex w has been visited, the LOW value of vertex v is updated to min(LOW[v], DFN[w]).

[0081] S804: Determine whether the DFN and LOW values ​​of vertex v are equal. If they are not equal, return to step S802; otherwise, proceed to step S805.

[0082] S805: Obtain strongly connected components:

[0083] If the DFN and LOW values ​​of vertex v are equal, it means that vertex v is the root node of a strongly connected component. Therefore, vertices are continuously popped from the stack until vertex v is popped, and all the popped vertices form a strongly connected component. This strongly connected component is then added to the result list.

[0084] S806: Determine whether all vertices have been visited. If yes, proceed to step S807; otherwise, return to step S802.

[0085] S807: Determine all strongly connected components:

[0086] Returning the result list yields all strongly connected components in the directed graph of the integrated circuit.

[0087] S604: Partitioning strongly connected components based on cyclic one-way edges:

[0088] For each strongly connected component, determine if its number of nodes exceeds a preset threshold. If not, no operation is performed. If it exceeds the threshold, search for a cyclic one-way edge within the strongly connected component. The search method is as follows: if a one-way edge exists in the strongly connected component and there is no path with a fully bidirectional edge between the starting and ending points of the one-way edge, then the one-way edge is a cyclic one-way edge. Then, disconnect all the cyclic one-way edges obtained from the search, and further divide the strongly connected component into several strongly connected components using the same method as in step S603, thereby obtaining the final strongly connected component partitioning result. The specific method for searching for cyclic one-way edges in this embodiment is as follows:

[0089] The `useNow` mnemonic dictionary is initialized using a key-value dictionary format. The key represents a vertex of a strongly connected component, and the value indicates whether that vertex has been evaluated; both are initially set to "no". A depth-first search function, `find_break_loop(KEY, TARGET, useNow)`, is used to search each vertex in the `useNow` mnemonic dictionary. This function returns a `judge`, where `KEY` represents the starting point of a unidirectional edge, `TARGET` represents the ending point, `useNow` is the mnemonic dictionary entry, and `judge` indicates whether the edge is identified as a cyclic unidirectional edge. The execution process of the depth-first search function is as follows: For any vertex `e` adjacent to the starting point `KEY`:

[0090] If the value of vertex e in the memory dictionary is yes, meaning that the vertex has already been evaluated, then skip that vertex.

[0091] If the value of vertex e in the memory dictionary is negative, the starting point KEY is bidirectionally connected to vertex e, and vertex e is TARGET, it means that there is at least one bidirectional path to the endpoint, indicating that the edge is not a cyclic unidirectional edge.

[0092] If the value of vertex e in the memory dictionary is negative, the starting point KEY is bidirectionally connected to vertex e. However, if vertex e is not TARGET, then continue the depth-first search to find all its neighbors. If at least one of them is positive, then the edge is not a cyclic unidirectional edge.

[0093] If the value of vertex e in the memory dictionary is negative, and the starting point KEY is unidirectionally connected to vertex e, then skip that vertex.

[0094] S605: Defect Simulation

[0095] Defect simulation is performed based on the strongly connected components obtained from the partitioning. The specific method is as follows:

[0096] Let K be the number of strongly connected components. Perform one flawless simulation and record the standard values ​​of all vertices. Let SCC be the number of strongly connected components k.k The set of connection points with other strongly connected components is V. k The standard value of each connection point is v. k,d d = 1, 2, ..., D k D k V represents the set of connection points k The number of vertices in a strongly connected component SCC. k Connect the set of points V k Medium-strength connected component SCC k The standard values ​​of the input vertices are used as the strongly connected component SCC. k The input for strongly connected component SCC k Simulations were performed by sequentially injecting all defects into the strongly connected component SCC. k All measuring points within the area determine whether each defect is measurable.

[0097] Figure 9 yes Figure 2 The simulation diagram of the circuit shown is as follows. Figure 9 As shown, since the defect simulations between each strongly connected component do not affect each other, the defect simulations of strongly connected components can be performed in parallel, thereby further improving the simulation efficiency.

[0098] Example

[0099] To better illustrate the technical effects of this invention, a specific example is used for experimental verification. In this embodiment, a bandgap reference circuit from the Benchmark circuit is used for simulation verification. A Benchmark circuit is a standardized circuit used to test and compare the performance of different electronic systems or chips. Figure 10 This is a circuit diagram of the BandGap reference circuit in this embodiment. Figure 11 This is the directed graph of the bandgap reference circuit in this embodiment. For example... Figure 11 As shown, the partial results of the graph object g.graph attribute are as follows:

[0100] '2':{'I79.M62','I79.M71','I79.M77','I89'}

[0101] '3':{'I89'}

[0102] '5':{'I79.M69','I79.M72','I79.M74'}

[0103] '6':{'I79.M61','I79.M62','I79.M65','I79.M70','I79.M71','I79.M74','I79.M76','I79.M79','I79.M80'}

[0104] …

[0105] 'I79.M85':{'13','18'}

[0106] Strongly connected components were obtained by partitioning using the Tarjan algorithm. Figure 12 This is a schematic diagram of a strongly connected component in this embodiment. For example... Figure 12 As shown, this embodiment divides the data into 4 strongly connected components. The specific splitting points are as follows: defaultdict(<class'set'> ,{'17':'XI79.net078','19':'XI79.net077','8':'XI79.net064','6':'XI79.net011'}). A bidirectional arrow relationship between a node and the SCC indicates that the node is in the strongly connected component, while a unidirectional arrow represents a unidirectional relationship in the directed graph.

[0107] Then, cyclic one-way edges are identified, and the corresponding nodes are disconnected according to the actual situation to construct more weak connectivity relationships. For the same subordinate SCC connection relationship, only one cyclic one-way edge needs to be kept and the others disconnected to generate additional weak connectivity relationships. Table 1 is a partial result table of cyclic one-way edge identification in this embodiment.

[0108] '2<->4' 'XI79.net019' 'M45.XI79' '2<->4' 'XI79.net078' 'M50.XI79' '0<->1' 'XI79.net012' 'M85.XI79' '0<->1' 'XI79.net0105' 'M58.XI79' '0<->1' 'XI79.net068' 'M86.XI79' '0<->1' 'XI79.net068' 'M63.XI79' '0<->1' 'XI79.net068' 'M87.XI79'

[0109] Table 1

[0110] In this embodiment, the data in rows 0 and 2 are retained, and the connection relationships of other data in g.graph are deleted to simulate the disconnection of the actual circuit and continue the identification process. Figure 13 This is a schematic diagram of the strongly connected component obtained in this embodiment. For example... Figure 13 As shown, this embodiment ultimately identified a total of 6 strongly connected components. Some results are shown below, and the original netlist names of the block data are output for subsequent simulation.

[0111] ['I79.M86','28','I79.Q3_c','I79.Q3_b','I79.Q1_c','I79.Q1_b','I79.R264','51' ,'I79.R260',…,'I79.R255',','I79.M71','I79.M62','I79.M77','4','3','I89','2']

[0112] ['I79.M74','I79.M90','I79.M88','24','I79.M89','23','I79.M76','I 79.M65','10','I79.M68','I79.M49','11','I79.M85',…'I79.M69','5']

[0113] ['I79.M84','17','I79.M80','I79.M27','16','I79.R11','15','I79.M45','14','I79.M59','I79.M75','19','I79.M79']

[0114] ['I79.M70','I79.M61','6']

[0115] ['I79.M51','25','I79.M81','26','I79.M82','I79.M47','9','I79.M73','I79.M50','7']

[0116] ['I79.M83','I79.M55','8']

[0117] Verification showed that the graph analysis identification results were accurate. In terms of time efficiency, the total time for graph analysis identification of the Bandgap circuit using this invention is approximately 0.0135 seconds, demonstrating excellent time efficiency. Furthermore, the algorithm based on signal flow and graph analysis used in this paper to directly simulate all defects in the Bandgap circuit takes 67.46 seconds, while the block-parallel simulation method of this invention takes only 13.88 seconds, reducing the simulation time by approximately five times. Moreover, as the circuit size increases, the simulation time will be reduced even more significantly. This will also provide considerable time reduction and guidance for defect injection simulation.

[0118] Although the illustrative specific embodiments of the present invention have been described above to enable those skilled in the art to understand the invention, it should be understood that the invention is not limited to the scope of the specific embodiments. For those skilled in the art, various changes are obvious as long as they are within the spirit and scope of the invention as defined and determined by the appended claims, and all inventions utilizing the concept of the present invention are protected.

Claims

1. A circuit segmentation method based on signal flow and graph analysis, characterized in that, Includes the following steps: S1: Obtain the integrated circuit netlist, then flatten it to obtain a two-dimensional list of circuit devices, including each device and the nodes connected to it; S2: Construct a directed graph of integrated circuits by taking the voltage of each node and the device current between nodes in the two-dimensional list of circuit devices as the vertices of the graph. The edges between nodes are determined as follows: if the device current between nodes depends on the node voltage, then there is a directed edge from the node voltage to the device current; if the node voltage depends on the device current between nodes, then there is a directed edge from the device current to the node voltage. S3: Divide the directed graph of the integrated circuit into several strongly connected components, and there are bidirectional paths between each vertex in each strongly connected component; S4: For each strongly connected component, determine whether its number of nodes is greater than a preset threshold. If not, do not perform any operation. If it is greater, search for whether there is a cyclic one-way edge in the strongly connected component. The search method is as follows: if there is a one-way edge in the strongly connected component and there is no path between the starting point and the ending point of the one-way edge, then the one-way edge is a cyclic one-way edge. Then, disconnect all the cyclic one-way edges found in the search, and use the same method as in step S3 to further divide the strongly connected component into several strongly connected components, thereby obtaining the final strongly connected component partitioning result. S5: Perform block defect simulation based on the strongly connected components obtained from the partitioning. The specific method is as follows: Let K be the number of strongly connected components. Perform one flawless simulation and record the standard values ​​of all vertices. Let SCC be the number of strongly connected components k. k The set of connection points with other strongly connected components is V. k The standard value of each connection point is v. k,d d = 1, 2, ..., D k D k V represents the set of connection points k The number of vertices in the strongly connected component SCC; k Connect the set of points V k Medium-strength connected component SCC k The standard values ​​of the input vertices are used as the strongly connected component SCC. k The input for strongly connected component SCC k Simulations were performed by sequentially injecting all defects into the strongly connected component SCC. k All measuring points within the area determine whether each defect is measurable.

2. The circuit segmentation method according to claim 1, characterized in that, The construction of the directed graph of the integrated circuit in step S2 includes the following steps: S2.1: Initialize the directed graph object of the integrated circuit in the form of a key-value dictionary. The key is the node voltage or device current obtained from the two-dimensional list of integrated circuit devices, and the value is the name of the node or device that is unidirectionally pointed to by the key in the directed graph. Initialize all values ​​to be empty. S2.2: Generate component objects (components) and node objects (nodes) from the two-dimensional list of circuit components. Both components and nodes are in key-value dictionary format. The key-value dictionary of components stores the list of adjacent nodes of each component, and the key-value dictionary of nodes stores the list of names of adjacent components of each node. S2.3: For node objects nodes, generate an edge for each node voltage pointing to the corresponding device current, and add the corresponding device current to the value list of the node voltage in the directed graph object of the integrated circuit. For MOSFET devices in the component objects, generate edges pointing the MOSFET current to the source and drain voltages; for transistors in the component objects, generate edges pointing the transistor current to the base and collector voltages; for other devices in the component objects, generate edges pointing the device current to the corresponding node voltage.

3. The circuit segmentation method according to claim 1, characterized in that, In step S3, the strongly connected components are partitioned using the Tarjan algorithm, including the following steps: S3.1: Create an empty stack, mark the access status of all vertices as unvisited, initialize the global variable index = 0, and initialize an empty list result to record strongly connected subgraphs; S3.2: Randomly select an unvisited vertex v; S3.3: Mark the current vertex v as visited, then push vertex v onto the stack, then perform a depth-first search on vertex v, set the timestamp DFN[v] and the earliest timestamp LOW[v] of vertex v to the current index value; increment the global variable index by 1; For each adjacent vertex w of vertex v, if vertex w has not been visited, a depth-first search is recursively performed and the LOW value of vertex v is updated to min(LOW[v], LOW[w]). If vertex w has been visited, the LOW value of vertex v is updated to min(LOW[v], DFN[w]). S3.4: Determine whether the DFN and LOW values ​​of vertex v are equal. If they are not equal, return to step S3.2; otherwise, proceed to step S3.

5. S3.5: Pop vertices from the stack continuously until vertex v is popped, and form a strongly connected component from all the popped vertices; add this strongly connected component to the result list; S3.6: Determine whether all vertices have been visited. If yes, proceed to step S3.7; otherwise, return to step S3.

2. S3.7: Returns the result list, which contains all strongly connected components in the directed graph of the integrated circuit.

4. The circuit segmentation method according to claim 1, characterized in that, The specific method for searching for cyclic one-way edges in step S4 is as follows: The `useNow` mnemonic dictionary is initialized using a key-value dictionary format. The key represents a vertex of a strongly connected component, and the value indicates whether that vertex has been evaluated; both are initially set to "no". A depth-first search function, `find_break_loop(KEY, TARGET, useNow)`, is used to search each vertex in the `useNow` mnemonic dictionary. This function returns a judge, where `KEY` represents the starting point of the unidirectional edge, `TARGET` represents the ending point, `useNow` is the mnemonic dictionary entry, and `judge` indicates whether the edge is identified as a cyclic unidirectional edge. The execution process of the depth-first search function is as follows: For any vertex `e` adjacent to the starting point `KEY`: If the value of vertex e in the memory dictionary is yes, meaning that the vertex has already been evaluated, then skip that vertex. If the value of vertex e in the memory dictionary is negative, the starting point KEY is bidirectionally connected to vertex e, and vertex e is TARGET, it means that there is at least one bidirectional path to the endpoint, indicating that the edge is not a cyclic unidirectional edge. If the value of vertex e in the memory dictionary is negative, the starting point KEY is bidirectionally connected to vertex e. However, if vertex e is not TARGET, then continue the depth-first search to find all its neighbors. If at least one neighbor node has a value positive, otherwise it means that the edge is not a cyclic unidirectional edge. If the value of vertex e in the memory dictionary is negative, and the starting point KEY is unidirectionally connected to vertex e, then skip that vertex.

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