Display panel and display device

Abstract

The display panel and the display device are provided. The display panel comprises a driving circuit and a signal line; the signal line comprises at least two main body sub-signal lines; the main body sub-signal line comprises a first end and a second end; the first ends of the at least two main body sub-signal lines are electrically connected, and the second ends of the at least two main body sub-signal lines are electrically connected; N main body sub-signal lines in the at least two main body sub-signal lines are directly electrically connected with the driving circuit; the N main body sub-signal lines are direct connection main body sub-signal lines; the main body sub-signal lines other than the direct connection main body sub-signal lines in the at least two main body sub-signal lines are non-direct connection main body sub-signal lines, the non-direct connection main body sub-signal lines are not directly electrically connected with the driving circuit, and the non-direct connection main body sub-signal lines are electrically connected with the driving circuit through the direct connection main body sub-signal lines; and N is a positive integer. The display panel and the display device solve the problem of signal transmission distortion caused by high resistance of the existing signal line and large parasitic capacitance on the signal line.

Description

[0001] This invention is a divisional application of the invention patent application filed on December 24, 2020, with application number 202080003631.2. Technical Field

[0002] This disclosure relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0003] In related display devices, the shift register unit in the driving circuit may include an output transistor. The source of the output transistor may be electrically connected to a clock signal line, and the drain of the output transistor may be electrically connected to the signal output terminal of the shift register unit. When the shift register unit is working, the large resistance and parasitic capacitance of the clock signal line can cause signal distortion, resulting in a long fall time for the signal provided by the shift register unit through the signal output terminal. Summary of the Invention

[0004] In one aspect, embodiments of this disclosure provide a display panel including a driving circuit disposed on a substrate and a signal line providing signals to the driving circuit;

[0005] The signal line includes at least two main sub-signal lines; each main sub-signal line includes a first end and a second end.

[0006] The first ends of the at least two main body sub-signal lines are electrically connected to each other, and the second ends of the at least two main body sub-signal lines are electrically connected to each other.

[0007] N of the at least two main body sub-signal lines are directly electrically connected to the driving circuit to provide signals to the driving circuit; the N main body sub-signal lines are direct-connected main body sub-signal lines, and the main body sub-signal lines other than the direct-connected main body sub-signal lines among the at least two main body sub-signal lines are non-direct-connected main body sub-signal lines. The non-direct-connected main body sub-signal lines are not directly electrically connected to the driving circuit, but are electrically connected to the driving circuit through the direct-connected main body sub-signal lines.

[0008] N is a positive integer, and N is less than the number of main sub-signal lines included in the signal line. Optionally, the at least two main sub-signal lines are formed in the same conductive layer; or, the at least two main sub-signal lines are formed in different conductive layers.

[0009] Optionally, the display panel further includes connecting wires, each of which is electrically connected to the driving circuit.

[0010] The connecting line and the direct-connect main body sub-signal line are formed on different conductive layers; the connecting line is electrically connected to the direct-connect main body sub-signal line through a via, and the different connecting lines formed on the same layer do not overlap.

[0011] Optionally, the signal line includes A main sub-signal lines; the signal line also includes M auxiliary sub-signal lines; the a-th main sub-signal line corresponds to the m-th auxiliary sub-signal line; A is an integer greater than 1; M is a positive integer; a is a positive integer less than or equal to A; m is a positive integer less than or equal to M.

[0012] The a-th main sub-signal line is electrically connected to the m-th auxiliary sub-signal line through at least two connection vias. The a-th main sub-signal line and the m-th auxiliary sub-signal line are formed on different conductive layers. The orthographic projection of the a-th main sub-signal line on the substrate and the orthographic projection of the m-th auxiliary sub-signal line on the substrate at least partially overlap.

[0013] Optionally, the maximum distance between the orthographic projection of one of the at least two connecting vias on the substrate and the orthographic projection of the first end of the a-th main sub-signal line on the substrate is less than a first predetermined distance;

[0014] The maximum distance between the orthographic projection of another of the at least two connecting vias on the substrate and the orthographic projection of the second end of the a-th main sub-signal line on the substrate is less than a first predetermined distance.

[0015] Optionally, the auxiliary sub-signal line includes multiple auxiliary line portions, each of which is electrically connected to a corresponding main sub-signal line via at least two vias. The orthographic projection of the auxiliary line portion on the substrate lies within the orthographic projection of the corresponding main sub-signal line on the substrate. Optionally, the auxiliary line portion includes a third end and a fourth end.

[0016] The maximum distance between the orthogonal projection of one of the at least two vias on the substrate and the orthogonal projection of the third end of the auxiliary line portion on the substrate is less than a second predetermined distance; the maximum distance between the orthogonal projection of the other of the at least two vias on the substrate and the orthogonal projection of the fourth end of the auxiliary line portion on the substrate is less than the second predetermined distance.

[0017] Optionally, a gap is provided between two adjacent auxiliary line portions of the same auxiliary sub-signal line; the display panel also includes connecting lines; the connecting lines are electrically connected to the direct-connect main body sub-signal lines through vias, and different connecting lines formed on the same layer do not overlap;

[0018] The connecting line and the auxiliary sub-signal line are formed on the same conductive layer;

[0019] The connecting wire passes through a portion of the gap and is electrically connected to the drive circuit;

[0020] The connecting line and the auxiliary sub-signal line do not overlap.

[0021] Optionally, the signal line includes a first clock signal line and a second clock signal line; the display panel includes a driving circuit, and the driving circuit, the first clock signal line, and the second clock signal line are disposed on the same side of the display panel;

[0022] The first clock signal line includes a first main body sub-signal line and a second main body sub-signal line, and the second clock signal line includes a third main body sub-signal line and a fourth main body sub-signal line;

[0023] The driving circuit includes a multi-stage shift register unit;

[0024] The first main body sub-signal line is directly electrically connected to the odd-level shift register unit, and the third main body sub-signal line is directly electrically connected to the even-level shift register unit.

[0025] Optionally, the signal lines include a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line, and the display panel includes a first driving circuit and a second driving circuit. The first driving circuit, the first clock signal line, and the second clock signal line are disposed on one side of the display panel, and the second driving circuit, the third clock signal line, and the fourth clock signal line are disposed on the other side of the display panel.

[0026] The first clock signal line includes a first main body sub-signal line and a second main body sub-signal line; the second clock signal line includes a third main body sub-signal line and a fourth main body sub-signal line; the third clock signal line includes a fifth main body sub-signal line and a sixth main body sub-signal line; and the fourth clock signal line includes a seventh main body sub-signal line and an eighth main body sub-signal line.

[0027] The first driving circuit includes a multi-stage shift register unit, and the second driving circuit includes a multi-stage shift register unit;

[0028] The first main body sub-signal line is directly electrically connected to the odd-level shift register unit in the first driving circuit; the third main body sub-signal line is directly electrically connected to the even-level shift register unit in the first driving circuit; the fifth main body sub-signal line is directly electrically connected to the odd-level shift register unit in the second driving circuit; and the seventh main body sub-signal line is directly electrically connected to the even-level shift register unit in the second driving circuit.

[0029] In a second aspect, this disclosure also provides a display device including the display panel described above. Optionally, the display device according to at least one embodiment of this disclosure further includes a driver chip; the driver chip is used to provide the signal through a signal output terminal;

[0030] The signal output terminal of the driver chip is electrically connected to the first terminal of the at least two main body sub-signal lines. Attached Figure Description

[0031] Figure 1 This is a structural diagram of at least one embodiment of the gate drive circuit;

[0032] Figure 2 This is a circuit diagram of at least one embodiment of the energy storage and output circuit in the gate drive circuit; Figure 3A This is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0033] Figure 3B Is Figure 3A In at least one embodiment of the display panel shown, the driver chip 40 provides an input clock signal C01 to the first terminal of the first clock signal line K1, a clock signal C02 output from the second terminal of K1, and a waveform diagram of the gate drive signal O0 output by the first stage shift register unit S1 included in the first driver circuit.

[0034] Figure 4 This is a layout diagram of the gate metal layer in a display panel according to at least one embodiment of the present disclosure;

[0035] Figure 5 This is a layout diagram of the source and drain metal layers in a display panel according to at least one embodiment of the present disclosure (in... Figure 5 (The middle shows that there is a hole);

[0036] Figure 6 yes Figure 5 A schematic diagram of the upper part;

[0037] Figure 7 yes Figure 5 A schematic diagram of the lower half of the diagram;

[0038] Figure 8 This is another layout diagram of the source / drain metal layer in the display panel described in at least one embodiment of this disclosure;

[0039] Figure 9 Is Figure 8 A diagram with labels based on the above;

[0040] Figure 10 Is Figure 8 A schematic diagram of the via is shown below;

[0041] Figure 11 yes Figure 10 A schematic diagram of the upper part;

[0042] Figure 12 yes Figure 10 A schematic diagram of the lower half of the diagram;

[0043] Figure 13 This is another layout diagram of the gate metal layer in the display panel described in at least one embodiment of the present disclosure;

[0044] Figure 14 This is another layout diagram of the source / drain metal layer in the display panel described in at least one embodiment of this disclosure;

[0045] Figure 15 yes Figure 14 A schematic diagram of the upper part;

[0046] Figure 16 yes Figure 15 A schematic diagram of the lower half of the diagram;

[0047] Figure 17 This is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0048] Figure 18 This is a structural diagram of a display panel according to at least one embodiment of the present disclosure;

[0049] Figure 19 This is a structural diagram of a display panel according to at least one embodiment of the present disclosure. Detailed Implementation

[0050] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure. The display panel described in the embodiments of this disclosure includes a driving circuit disposed on a substrate and signal lines providing signals to the driving circuit;

[0051] The signal line includes at least two main sub-signal lines; each main sub-signal line includes a first end and a second end.

[0052] The first ends of the at least two main body sub-signal lines are electrically connected to each other, and the second ends of the at least two main body sub-signal lines are electrically connected to each other.

[0053] N of the at least two main body sub-signal lines are directly electrically connected to the driving circuit to provide signals to the driving circuit; the N main body sub-signal lines are direct-connected main body sub-signal lines, and the main body sub-signal lines other than the direct-connected main body sub-signal lines among the at least two main body sub-signal lines are non-direct-connected main body sub-signal lines. The non-direct-connected main body sub-signal lines are not directly electrically connected to the driving circuit, but are electrically connected to the driving circuit through the direct-connected main body sub-signal lines.

[0054] N is a positive integer, and N is less than the number of main sub-signal lines included in the signal line. In this embodiment, by including at least two main sub-signal lines connected in parallel, the resistance of the signal line can be reduced; and N main sub-signal lines are directly electrically connected to the driving circuit to provide signals to the driving circuit, where N is less than the number of main sub-signal lines included in the signal line, and the N main sub-signal lines are directly connected main sub-signal lines; non-directly connected main sub-signal lines are not directly electrically connected to the driving circuit, but are electrically connected to the driving circuit through the directly connected main sub-signal lines. Therefore, the capacitance of the main sub-signal lines not directly connected to the driving circuit is negligible, and the RC delay of the main sub-signal lines not directly connected to the driving circuit is extremely small. Thus, the waveform of the signal on the main sub-signal lines not directly connected to the driving circuit is essentially undistorted.

[0055] Optionally, the signal line is an AC signal line; for example, the signal line can be a clock signal line, but is not limited thereto.

[0056] In at least one embodiment of this disclosure, the driving circuit may be a circuit that provides control signals to the pixel circuit; the control signals may be, for example, gate driving signals, light emission control signals, or reset control signals, but are not limited thereto.

[0057] In practice, the driving circuit may be located on the side of the display panel, but is not limited thereto.

[0058] When the signal line is a clock signal line, and the display panel uses the clock signal line, and the driving circuit is a gate driving circuit, the rise time and fall time of the clock signal on the clock signal line and the gate driving signal output by the gate driving circuit are significantly reduced. For example, at the far end of the clock signal line, the rise time of the clock signal can be reduced from 2.87us to 1.49us, the fall time of the clock signal can be reduced from 3.13us to 1.63us, the rise time of the gate driving signal can be reduced from 5.97us to 3.94us, and the fall time of the gate driving signal can be reduced from 5.37us to 3.64us. At the near end of the clock signal line, the rise time of the clock signal can be reduced from 1.2us to 0.58us, the fall time of the clock signal can be reduced from 1.3us to 0.63us, the rise time of the gate driving signal can be reduced from 1.81us to 1.77us, and the fall time of the gate driving signal can be reduced from 1.70us to 1.67us.

[0059] like Figure 1 As shown, at least one embodiment of the gate drive circuit may include an input circuit 11, a reset circuit 12, an energy storage and output circuit 13, and a pull-down control circuit 14.

[0060] The input circuit 11 is electrically connected to the input terminal I1 and the pull-up node P1, and is used to control the potential of the pull-up node P1 according to the input signal provided by the input terminal I1.

[0061] The reset circuit 12 is electrically connected to the reset terminal R1, the pull-up node P1 and the low voltage terminal V0 respectively, and is used to respond to the reset signal provided by the reset terminal R1.

[0062] The energy storage and output circuit 13 is electrically connected to the pull-up node P1, the pull-down node P2, the clock signal line K, and the gate drive signal output terminal O1, respectively. It is used to control the output of the gate drive signal of O1 according to the clock signal provided by the clock signal line K under the control of the potential of P1 and the potential of P2. The pull-down control circuit 14 is electrically connected to the pull-up node P1, the pull-down node P2, and the low voltage terminal V0, respectively. It is used to control the potential of P2 under the control of the potential of P1.

[0063] Among them, such as Figure 2 As shown, at least one embodiment of the energy storage and output circuit may include a capacitor C1 and an output transistor T1;

[0064] The gate of T1 is electrically connected to the pull-up node P1, the source of T1 is electrically connected to the clock signal line K, and the drain of T1 is electrically connected to the gate drive signal output terminal O1.

[0065] The first end of C1 is electrically connected to the pull-up node P1, and the second end of C2 is electrically connected to the gate drive signal output terminal O1.

[0066] exist Figure 2 In at least one embodiment shown, T1 is an n-type thin-film transistor, but is not limited thereto. Figure 2 In at least one embodiment of the energy storage and output circuit shown, when the input circuit completes its operation, C1 completes energy storage, causing the potential of P1 to increase and T1 to turn on. At this time, the potential of the clock signal provided by K is low, so O1 has no output. At the next moment, when the potential of the clock signal provided by K is high, O1 outputs a high voltage because T1 is turned on, and the potential of P1 becomes even higher due to the bootstrap effect of C1.

[0067] In at least one embodiment of this disclosure, the signal line can be a clock signal line. In at least one embodiment of this disclosure, the RC (resistance-capacitance) delay of the signal line can be reduced, and the distortion of the signal transmitted on the signal line can be improved. Therefore, the clock signal output at the far end of the clock signal line can be made distorted, thereby greatly reducing the fall time Tf of the signal output by the shift register unit that is electrically connected to the far end of the clock signal line, and improving the charging time.

[0068] When the driving circuit is a gate driving circuit and the signal output by the driving circuit is a gate driving signal, if the fall time of the gate driving signal is large, the next-stage shift register unit in the gate driving circuit will output a valid gate driving signal to control the charging of the corresponding row pixel circuit. At the same time, the previous-stage shift register unit in the gate driving circuit may also output a valid gate driving signal, which may lead to misdisplay by the display device. Therefore, it is necessary to solve the problem of the large fall time Tf of the signal output by the shift register unit.

[0069] In related technologies, for small and medium-sized display products, the method to reduce the fall time Tf of the signal output by the driver circuit is to increase the aspect ratio of T1. However, as the size of display products increases and the resolution and refresh rate also gradually improve, on the one hand, it is necessary to design the aspect ratio of T1 to be very large, reaching 10000 / 3.5 or higher. On the other hand, a large aspect ratio places a large load on the clock signal line. The load of the clock signal line includes both resistance and capacitance. The larger the display product size and the longer the trace, the greater the resistance for the same trace width. Besides the overlapping capacitance of the signal lines, a large portion of the capacitance of the clock signal line is the parasitic capacitance Cgs of T1. The larger the aspect ratio of T1, the larger Cgs, and thus the larger the capacitance of the clock signal line. Therefore, in related technologies, the RC delay of the clock signal line causes waveform distortion of the clock signal on the clock signal line. Since the driver circuit outputs a clock signal, this waveform distortion will increase the fall time Tf of the signal output by the driver circuit. Even if the aspect ratio of T1 is increased infinitely, the effect of reducing Tf is still not significant. Based on this, the present disclosure provides a display panel that can reduce the RC delay of the signal line and improve the distortion of the signal transmitted on the signal line. Therefore, the clock signal output at the far end of the clock signal line can be made distorted, thereby greatly reducing the fall time Tf of the signal output by the shift register unit that is electrically connected to the far end of the clock signal line and improving the charging time.

[0070] Optionally, the angle between the extension directions of the two main sub-signal lines can be less than a predetermined angle. In specific implementations, the angle between the extension directions of the two main sub-signal lines is less than the predetermined angle so that the two main sub-signal lines are approximately parallel, but this is not a limitation.

[0071] In at least one embodiment of this disclosure, the predetermined angle can be selected according to actual conditions. For example, the predetermined angle can be 2 degrees, but it is not limited thereto.

[0072] In actual operation, when the two main sub-signal lines are formed on the same conductive layer, the two main sub-signal lines do not need to overlap.

[0073] In at least one embodiment of this disclosure, the conductive layer may be a gate metal layer or a source / drain metal layer, but is not limited thereto.

[0074] In specific implementation, the longest distance between the first ends of any two main sub-signal lines is less than a first predetermined distance;

[0075] The longest distance between the second ends of any two main body sub-signal lines is less than a second predetermined distance. In at least one embodiment of this disclosure, the first predetermined distance and the second predetermined distance can be selected according to actual conditions, so that the distance between the first ends of any two main body sub-signal lines is relatively close, and the distance between the second ends of any two main body sub-signal lines is relatively close.

[0076] Optionally, the first ends of two main body sub-signal lines can be electrically connected through a first connecting wire, and the second ends of two main body sub-signal lines can be electrically connected through a second connecting wire. In at least one embodiment of this disclosure, the longest distance between the first ends of any two main body sub-signal lines is set to be less than a first predetermined distance, and the longest distance between the second ends of any two main body sub-signal lines is set to be less than a second predetermined distance, so that the length of the first connecting wire is shorter and the length of the second connecting wire is shorter, so as to facilitate wiring and avoid the situation where it is necessary to provide vias due to the long length of the first connecting wire and the long length of the second connecting wire, which would require overlapping with other signal lines formed on the same layer.

[0077] Optionally, the at least two main sub-signal lines are formed on the same conductive layer; or, the at least two main sub-signal lines are formed on different conductive layers.

[0078] In specific implementation, the at least two main sub-signal lines can be formed on the same conductive layer, for example, they can both be formed on the gate metal layer; or, the at least two main sub-signal lines can be formed on different conductive layers, for example, some of the main sub-signal lines can be formed on the first gate metal layer, and another part of the main sub-signal lines can be formed on the second gate metal layer.

[0079] However, this is not the limit.

[0080] Optionally, the display panel may further include connecting lines, each of which is electrically connected to the driving circuit.

[0081] The connecting line and the direct-connection main body sub-signal line can be formed on different conductive layers; the connecting line is electrically connected to the direct-connection main body sub-signal line through a via, and different connecting lines formed on the same layer do not overlap.

[0082] The connecting line can be formed on the first conductive layer, and the main body sub-signal line can be formed on the second conductive layer. An insulating layer can be provided between the first and second conductive layers. The connecting line can be electrically connected to the directly connected main body sub-signal line through a via penetrating the insulating layer. In a specific implementation, other components and lines may be provided on the second conductive layer between the directly connected main body sub-signal line and the driving circuit. Therefore, in order to avoid short circuits, the electrical connection between the directly connected main body sub-signal line and the driving circuit needs to be completed through the connecting line provided on the first conductive layer.

[0083] In at least one embodiment of this disclosure, the signal line includes A main sub-signal lines; the signal line may also include M auxiliary sub-signal lines; the a-th main sub-signal line corresponds to the m-th auxiliary sub-signal line; A is an integer greater than 1, M is a positive integer; a is a positive integer less than or equal to A, and m is a positive integer less than or equal to M;

[0084] The a-th main sub-signal line is electrically connected to the m-th auxiliary sub-signal line. The a-th main sub-signal line and the m-th auxiliary sub-signal line are formed on different conductive layers. The orthographic projection of the a-th main sub-signal line on the substrate and the orthographic projection of the m-th auxiliary sub-signal line on the substrate at least partially overlap.

[0085] In a specific implementation, the signal line may include not only A main sub-signal lines but also M auxiliary sub-signal lines, where M may be less than or equal to A. The a-th main sub-signal line corresponds to the m-th auxiliary sub-signal line. The a-th main sub-signal line is electrically connected to the m-th auxiliary sub-signal line through at least two connecting vias. The a-th main sub-signal line and the m-th auxiliary sub-signal line are formed on different conductive layers, and the orthographic projection of the a-th main sub-signal line on the substrate and the orthographic projection of the m-th auxiliary sub-signal line on the substrate are set to at least partially overlap to increase the film thickness of the signal line, thereby further reducing the resistance of the signal line.

[0086] Optionally, the maximum distance between the orthographic projection of one of the at least two connecting vias on the substrate and the orthographic projection of the first end of the a-th main sub-signal line on the substrate is less than a first predetermined distance; the maximum distance between the orthographic projection of the other connecting via on the substrate and the orthographic projection of the second end of the a-th main sub-signal line on the substrate is less than the first predetermined distance, so that the a-th main sub-signal line can form a parallel connection with the m-th auxiliary sub-signal line, further reducing the resistance of the signal line. In at least one embodiment of this disclosure, the first predetermined distance can be selected according to actual conditions, so that one of the at least two connecting vias is close to the first end of the a-th main sub-signal line, and the other connecting via is close to the second end of the a-th main sub-signal line.

[0087] In at least one embodiment of this disclosure, the orthographic projection of the m-th auxiliary sub-signal line on the substrate may be within the orthographic projection of the a-th main sub-signal line on the substrate, but is not limited thereto.

[0088] Optionally, the auxiliary sub-signal line includes multiple auxiliary line portions, which are electrically connected to the corresponding main sub-signal line through at least two vias. The orthographic projection of the auxiliary line portion on the substrate is within the orthographic projection of the corresponding main sub-signal line on the substrate, so as to better reduce the resistance of the signal line.

[0089] In a specific implementation, the auxiliary line portion may include a third end and a fourth end;

[0090] The maximum distance between the orthogonal projection of one of the at least two vias on the substrate and the orthogonal projection of the third end of the auxiliary line portion on the substrate is less than a second predetermined distance; the maximum distance between the orthogonal projection of the other of the at least two vias on the substrate and the orthogonal projection of the fourth end of the auxiliary line portion on the substrate is less than the second predetermined distance, so that the a-th main sub-signal line can form a parallel relationship with the m-th auxiliary sub-signal line, further reducing the resistance of the signal line.

[0091] In at least one embodiment of this disclosure, the third predetermined distance may be selected according to actual conditions, such that one of the at least two vias is close to the third end of the auxiliary line portion, and the other of the at least two vias is close to the fourth end of the auxiliary line portion.

[0092] In practice, the extension direction of the auxiliary line can be the same as or approximately the same as the extension direction of the corresponding main sub-signal line.

[0093] For example, when the extension direction of the auxiliary line and the extension direction of the corresponding main sub-signal line are both vertical, the first end and the third end can be the lower end, and the second end and the fourth end can be the upper end, but this is not a limitation.

[0094] The fact that the extension direction of the auxiliary line is approximately the same as the extension direction of the corresponding main sub-signal line means that the angle between the extension direction of the auxiliary line and the extension direction of the corresponding main sub-signal line is less than a predetermined angle.

[0095] In at least one embodiment of this disclosure, a gap may be provided between two adjacent auxiliary line portions of the same auxiliary sub-signal line;

[0096] The display panel also includes connecting lines; the connecting lines are electrically connected to the direct-connect main body sub-signal lines through vias, and different connecting lines formed on the same layer do not overlap.

[0097] The connecting line and the auxiliary sub-signal line are formed on the same conductive layer;

[0098] The connecting wire passes through a portion of the gap and is electrically connected to the drive circuit.

[0099] In practical implementation, since the connecting line and the auxiliary sub-signal line need not overlap to avoid signal output confusion, a gap can be provided between two adjacent auxiliary line portions of the same auxiliary sub-signal line so that the connecting line can pass through part of the gap and electrically connect to the driving circuit. Optionally, the display panel of at least one embodiment of this disclosure may include a driving circuit; the driving circuit and the signal line are both disposed on a first side of the substrate, or the driving circuit and the signal line are both disposed on a second side of the substrate.

[0100] The first side and the second side are opposite sides.

[0101] In a specific implementation, the signal line can be located on the side of the driving circuit away from the display area; or, the signal line can be located between the driving circuit and the display area.

[0102] In a specific implementation, the signal line may include a first clock signal line and a second clock signal line; the display panel includes a driving circuit, and the driving circuit, the first clock signal line and the second clock signal line are disposed on the same side of the display panel;

[0103] The first clock signal line includes a first main body sub-signal line and a second main body sub-signal line, and the second clock signal line includes a third main body sub-signal line and a fourth main body sub-signal line;

[0104] The driving circuit includes a multi-stage shift register unit;

[0105] The first end of the first main body sub-signal line and the first end of the second main body sub-signal line can be electrically connected by a wire, and the second end of the first main body sub-signal line and the second end of the second main body sub-signal line can be electrically connected by a wire. The resistance of the first clock signal line is reduced by connecting the first main body sub-signal line and the second main body sub-signal line in parallel.

[0106] The first end of the third main body sub-signal line and the first end of the fourth main body sub-signal line can be electrically connected by a wire, and the second end of the third main body sub-signal line and the second end of the fourth main body sub-signal line can be electrically connected by a wire. The resistance of the second clock signal line is reduced by connecting the third main body sub-signal line and the fourth main body sub-signal line in parallel.

[0107] The first main body sub-signal line is directly electrically connected to the odd-numbered shift register unit, and the third main body sub-signal line is directly electrically connected to the even-numbered shift register unit.

[0108] The second main body sub-signal line is not directly electrically connected to the shift register unit, and the fourth main body sub-signal line is not directly electrically connected to the shift register unit. This ensures that the parasitic capacitance on the second and fourth main body sub-signal lines is very small. Therefore, the clock signal output at the far end of the clock signal line can be kept undistorted. Consequently, the fall time Tf of the signal output by the shift register unit electrically connected to the far end of the clock signal line is greatly reduced, improving the charging time. Figure 3A As shown, the display panel described in at least one embodiment of this disclosure includes a first driving circuit, a first clock signal line K1, and a second clock signal line K2. The first driving circuit, the first clock signal line K1, and the second clock signal line K2 are all disposed on the left side of the substrate. Figure 3A In the diagram, S1 represents the first-stage shift register unit of the first driving circuit, S2 represents the second-stage shift register unit of the first driving circuit, SP-1 represents the (P-1)th stage shift register unit of the first driving circuit, and SP represents the Pth stage shift register unit of the first driving circuit; P is an integer greater than 3; the first clock signal line K1 includes a first main sub-signal line K11 and a second main sub-signal line K12; the second clock signal line includes a third main sub-signal line K21 and a fourth main sub-signal line K22;

[0109] The first end of K11 is the lower end of K11, and the second end of K11 is the upper end of K11;

[0110] The first end of K12 is the lower end of K12, and the second end of K12 is the upper end of K12;

[0111] The first end of K21 is the lower end of K21, and the second end of K21 is the upper end of K21;

[0112] The first end of K22 is the lower end of K22, and the second end of K22 is the upper end of K22; the first end of K11 is electrically connected to the first end of K12 through a wire, and the second end of K11 is electrically connected to the second end of K12 through a wire.

[0113] The first end of K11 is electrically connected to the first end of K12 via a wire, and the second end of K11 is electrically connected to the second end of K12 via a wire.

[0114] exist Figure 3A In at least one embodiment shown, K1 and K2 are disposed on the side of the first driving circuit away from the display area;

[0115] exist Figure 3A In at least one embodiment shown, the line labeled V1 is a low-voltage line, and the line labeled S0 is a start signal line. The signal lines include a first clock signal line K1 and a second clock signal line K2. Figure 3A As shown, K11 is directly electrically connected to S1 and SP-1 to provide the first clock signal for S1 and SP-1; K21 is directly electrically connected to S2 and SP to provide the second clock signal for S2 and SP.

[0116] V1 is electrically connected to S1, S2, SP-1 and SP, and is used to provide low voltage signals to S1, S2, SP-1 and SP;

[0117] S0 is electrically connected to S1 and is used to provide a start signal to S1.

[0118] exist Figure 3A In at least one of the embodiments shown, the first driving circuit is a first gate driving circuit, and the signal provided by the first driving circuit is a gate driving signal, but is not limited thereto.

[0119] Furthermore, in Figure 3A In at least one embodiment shown, the first end is the proximal end and the second end is the distal end. The proximal end can be a terminal of the signal line that is closer to the driver chip, and the distal end can be a terminal of the signal line that is farther from the driver chip.

[0120] like Figure 3A As shown, the driver chip 40 can be disposed on the lower side of the display panel. The driver chip 40 is used to provide a first clock signal for K1 and a second clock signal for K2. Figure 3AIn the diagram, P11 is the first row pixel circuit located in display area A0, P12 is the second row pixel circuit located in display area A0, P103 is the (P-1)th row pixel circuit located in display area A0, and P104 is the Pth row pixel circuit located in display area A0; S1 provides a gate drive signal for P11, S2 provides a gate drive signal for P12, SP-1 provides a gate drive signal for P103, and SP provides a gate drive signal for P104.

[0121] like Figure 3B As shown, C01 is the input clock signal provided to K1 by the driver chip 40 through the first terminal of K1, C02 is the clock signal output from the second terminal of K1, and O0 is the gate drive signal output by S1. Figure 3B It can be seen that O0 has a short descent time.

[0122] In this disclosure Figure 3A In at least one embodiment shown, each clock signal line includes two main sub-signal lines, one of which is not directly electrically connected to the drive circuit. The parasitic capacitance on the main sub-signal line is very small, so the clock signal output at the far end of the clock signal line can be made distorted. As a result, the fall time Tf of the gate drive signal output by the shift register unit electrically connected to the far end of the clock signal line is greatly reduced, thereby improving the charging time.

[0123] In this disclosure Figure 3A In at least one of the embodiments shown, the decrease in the fall time Tf of the gate drive signal output by the shift register unit is mainly due to the following two aspects:

[0124] 1. The clock signal line includes two main sub-signal lines connected in parallel, which reduces resistance. 2. One of the main sub-signal lines is not directly electrically connected to the drive circuit, nor is it electrically connected to the output transistor in the shift register unit. Therefore, the capacitance of this main sub-signal line can be basically ignored (only a small overlapping capacitance exists when it crosses other signal lines). As a result, the RC delay of the main sub-signal line that is not directly electrically connected to the drive circuit is extremely small. Even at a distance, the clock signal transmitted by the clock signal line is basically undistorted.

[0125] In practice, K11 and K12 can be formed on the same conductive layer, or K11 and K12 can be formed on different conductive layers;

[0126] K21 and K22 can be formed on the same conductive layer, or they can be formed on different conductive layers.

[0127] In a specific implementation, the display panel may include six clock signal lines, but this is not a limitation.

[0128] Figure 4 This is a layout diagram of the gate metal layer in a display panel according to at least one embodiment of the present disclosure. Figure 5 This is a first layout diagram of the source / drain metal layer in a display panel according to at least one embodiment of the present disclosure; Figure 8 This is a second layout diagram of the source / drain metal layer in a display panel according to at least one embodiment of this disclosure. For example... Figures 4-12 As shown, the display panel described in at least one embodiment of this disclosure includes a first driving circuit, a first clock signal line, a second clock signal line, a third clock signal line, a fourth clock signal line, a fifth clock signal line, and a sixth clock signal line, wherein, as... Figure 4 As shown, the first clock signal line includes a first main body sub-signal line K11 and a second main body sub-signal line K12;

[0129] The second clock signal line includes the third main body sub-signal line K21 and the fourth main body sub-signal line K22; the third clock signal line includes the fifth main body sub-signal line K31 and the sixth main body sub-signal line K32; the fourth clock signal line includes the seventh main body sub-signal line K41 and the eighth main body sub-signal line K42; the fifth clock signal line includes the ninth main body sub-signal line K51 and the tenth main body sub-signal line K52; the sixth clock signal line includes the eleventh main body sub-signal line K61 and the twelfth main body sub-signal line K62;

[0130] like Figure 4 As shown, K11, K12, K21, K22, K31, K32, K41, K42, K51, K52, K61 and K62 are all formed in the gate metal layer;

[0131] exist Figures 4-12 In the diagram, A1 is the first driving circuit area, A2 is the second driving circuit area, A3 is the third driving circuit area, A4 is the fourth driving circuit area, A5 is the fifth driving circuit area, and A6 is the sixth driving circuit area.

[0132] In the first driving circuit region A1, a shift register unit of level 6B-5 included in the first driving circuit is provided; in the second driving circuit region A2, a shift register unit of level 6B-4 included in the first driving circuit is provided; in the third driving circuit region A3, a shift register unit of level 6B-3 included in the first driving circuit is provided; in the fourth driving circuit region A4, a shift register unit of level 6B-2 included in the first driving circuit is provided; in the fifth driving circuit region A5, a shift register unit of level 6B-1 included in the first driving circuit is provided; and in the sixth driving circuit region A6, a portion of the shift register unit of level 6B included in the first driving circuit is provided; wherein, B is a positive integer;

[0133] like Figures 4-12 As shown, K11 is electrically connected to the first connection line L1 through the first via H1, and L1 is formed in the source-drain metal layer; L1 is electrically connected to the 6B-5th stage shift register cell in A1; K61 is electrically connected to the second connection line L2 through the second via H2, and L2 is formed in the source-drain metal layer; L2 is electrically connected to the 6B-4th stage shift register cell in A2;

[0134] K51 is electrically connected to the third connection line L3 through the third via H3. L3 is formed in the source and drain metal layers. L3 is electrically connected to the 6B-3 shift register cell in A3.

[0135] K41 is electrically connected to the fourth connection line L4 through the fourth via H4. L4 is formed in the source and drain metal layers. L4 is electrically connected to the 6B-2 shift register cell in A4.

[0136] K31 is electrically connected to the fifth connection line L5 through the fifth via H5. L5 is formed in the source and drain metal layers. L5 is electrically connected to the 6B-1 stage shift register cell in A5.

[0137] K21 is electrically connected to the sixth connection line L6 through the sixth via H6. L6 is formed in the source and drain metal layers. L6 is electrically connected to the sixth B-stage shift register cell in A6.

[0138] like Figure 5 and Figures 8-12 As shown, L1, L2, L3, L4, L5 and L6 do not overlap. Figure 5 The layout of the source and drain metal layers shown is similar to Figure 8 The difference in the layout of the source and drain metal layers shown is that: Figure 5 In the layout of the source and drain metal layers shown, there are no auxiliary sub-signal lines.

[0139] like Figures 8-12As shown, the first clock signal line further includes a first auxiliary sub-signal line, a second auxiliary sub-signal line, a third auxiliary sub-signal line, a fourth auxiliary sub-signal line, a fifth auxiliary sub-signal line, a sixth auxiliary sub-signal line, a seventh auxiliary sub-signal line, an eighth auxiliary sub-signal line, a ninth auxiliary sub-signal line, a tenth auxiliary sub-signal line, an eleventh auxiliary sub-signal line, and a twelfth auxiliary sub-signal line; the first auxiliary sub-signal line, the second auxiliary sub-signal line, the third auxiliary sub-signal line, the fourth auxiliary sub-signal line, the fifth auxiliary sub-signal line, the sixth auxiliary sub-signal line, the seventh auxiliary sub-signal line, the eighth auxiliary sub-signal line, the ninth auxiliary sub-signal line, the tenth auxiliary sub-signal line, the eleventh auxiliary sub-signal line, and the twelfth auxiliary sub-signal line are formed in the source / drain metal layer;

[0140] The first auxiliary sub-signal line includes a first first auxiliary line portion L011, a second first auxiliary line portion L012, a third first auxiliary line portion L013, a fourth first auxiliary line portion L014, a fifth first auxiliary line portion L015, a sixth first auxiliary line portion L016, and a seventh first auxiliary line portion L017; the second auxiliary sub-signal line includes a first second auxiliary line portion L021, a second second auxiliary line portion L022, a third second auxiliary line portion L023, a fourth second auxiliary line portion L024, a fifth second auxiliary line portion L025, a sixth second auxiliary line portion L026, and a seventh second auxiliary line portion L027; the third auxiliary sub-signal line includes a first third auxiliary line portion L031, a third second auxiliary line portion L022, a fourth second auxiliary line portion L023, a fifth second auxiliary line portion L024, a sixth second auxiliary line portion L025, a seventh second auxiliary line portion L026, and a seventh second auxiliary line portion L027. The third auxiliary line includes two third auxiliary line sections L032, a third third auxiliary line section L033, a fourth third auxiliary line section L034, a fifth third auxiliary line section L035, a sixth third auxiliary line section L036, and a seventh third auxiliary line section L037; the fourth auxiliary sub-signal line includes a first fourth auxiliary line section L041, a second fourth auxiliary line section L042, a third fourth auxiliary line section L043, a fourth fourth auxiliary line section L044, a fifth fourth auxiliary line section L045, a sixth fourth auxiliary line section L046, and a seventh fourth auxiliary line section L047; the fifth auxiliary sub-signal line includes a first fifth auxiliary line section L051, a second fifth auxiliary line section L052, a third fifth auxiliary line section L053, a fourth third auxiliary line section L054, a fifth fifth auxiliary line section L035, a sixth third auxiliary line section L036, and a seventh third auxiliary line section L037. The system includes four fifth auxiliary line sections L054 and L055, a sixth fifth auxiliary line section L056 and a seventh fifth auxiliary line section L057; the sixth auxiliary sub-signal line includes a first sixth auxiliary line section L061, a second sixth auxiliary line section L062, a third sixth auxiliary line section L063, a fourth sixth auxiliary line section L064, a fifth sixth auxiliary line section L065, a sixth sixth auxiliary line section L066 and a seventh sixth auxiliary line section L067; the seventh auxiliary sub-signal line includes a first seventh auxiliary line section L071, a second seventh auxiliary line section L072, a third seventh auxiliary line section L073, a fourth seventh auxiliary line section L074 and a fifth seventh auxiliary line section L075. The sixth and seventh auxiliary line sections L076 and L077; the eighth auxiliary sub-signal line includes the first eighth auxiliary line section L081, the second eighth auxiliary line section L082, the third eighth auxiliary line section L083, the fourth eighth auxiliary line section L084 and the fifth eighth auxiliary line section L085, the sixth eighth auxiliary line section L086 and the seventh eighth auxiliary line section L087; the ninth auxiliary sub-signal line includes the first ninth auxiliary line section L091, the second ninth auxiliary line section L092, the third ninth auxiliary line section L093, the fourth ninth auxiliary line section L094 and the fifth ninth auxiliary line section L095, the sixth ninth auxiliary line section L096 and the seventh ninth auxiliary line section L097;The tenth auxiliary sub-signal line includes a first tenth auxiliary line section L101, a second tenth auxiliary line section L102, a third tenth auxiliary line section L103, a fourth tenth auxiliary line section L104, a fifth tenth auxiliary line section L105, a sixth tenth auxiliary line section L106, and a seventh tenth auxiliary line section L107; the eleventh auxiliary sub-signal line includes a first eleventh auxiliary line section L111, a second eleventh auxiliary line section L112, a third eleventh auxiliary line section L113, a fourth eleventh auxiliary line section L114, a fifth eleventh auxiliary line section L115, a sixth eleventh auxiliary line section L116, and a seventh eleventh auxiliary line section L117;

[0141] The twelfth auxiliary sub-signal line includes a first twelfth auxiliary line section L121, a second twelfth auxiliary line section L122, a third twelfth auxiliary line section L123, a fourth twelfth auxiliary line section L124, a fifth twelfth auxiliary line section L125, a sixth twelfth auxiliary line section L126, and a seventh twelfth auxiliary line section L127;

[0142] The first first auxiliary line section L011, the second first auxiliary line section L012, the third first auxiliary line section L013, the fourth first auxiliary line section L014, the fifth first auxiliary line section L015, the sixth first auxiliary line section L016 and the seventh first auxiliary line section L017 are electrically connected to K11 through vias, so that the first auxiliary sub-signal line is electrically connected to K11;

[0143] The first second auxiliary line section L021, the second second auxiliary line section L022, the third second auxiliary line section L023, the fourth second auxiliary line section L024, the fifth second auxiliary line section L025, the sixth second auxiliary line section L026, and the seventh second auxiliary line section L027 are electrically connected to K12 through vias. The first third auxiliary line section L031, the second third auxiliary line section L032, the third third auxiliary line section L033, the fourth third auxiliary line section L034, the fifth third auxiliary line section L035, the sixth third auxiliary line section L036, and the seventh third auxiliary line section L037 are electrically connected to K21 through vias. The first fourth auxiliary line section L041, the second fourth auxiliary line section L042... The third fourth auxiliary line section L043, the fourth fourth auxiliary line section L044, the fifth fourth auxiliary line section L045, the sixth fourth auxiliary line section L046, and the seventh fourth auxiliary line section L047 are electrically connected to K22 via vias; the first fifth auxiliary line section L051, the second fifth auxiliary line section L052, the third fifth auxiliary line section L053, the fourth fifth auxiliary line section L054, the fifth fifth auxiliary line section L055, the sixth fifth auxiliary line section L056, and the seventh fifth auxiliary line section L057 are electrically connected to K31 via vias; the first sixth auxiliary line section L061, the second sixth auxiliary line section L062, the third sixth auxiliary line section L063, and the fourth sixth auxiliary line section L064 are electrically connected to K31 via vias. The fifth and sixth auxiliary line sections L065, L066, and L067 are electrically connected to K32 via vias; the first, second, third, fourth, fifth, sixth, and seventh auxiliary line sections L071, L072, L073, L074, L075, L076, and L077 are electrically connected to K41 via vias; the first, second, third, fourth, fifth, and sixth auxiliary line sections L081, L082, L083, L084, L085, and L086 are electrically connected to K41 vias. The seventh and eighth auxiliary line sections L087 are electrically connected to K42 via vias; the first ninth auxiliary line section L091, the second ninth auxiliary line section L092, the third ninth auxiliary line section L093, the fourth ninth auxiliary line section L094, the fifth ninth auxiliary line section L095, the sixth ninth auxiliary line section L096, and the seventh ninth auxiliary line section L097 are electrically connected to K51 via vias; the first tenth auxiliary line section L101, the second tenth auxiliary line section L102, the third tenth auxiliary line section L103, the fourth tenth auxiliary line section L104, the fifth tenth auxiliary line section L105, the sixth tenth auxiliary line section L106, and the seventh tenth auxiliary line section L107 are electrically connected to K52 via vias.The first eleventh auxiliary line section L111, the second eleventh auxiliary line section L112, the third eleventh auxiliary line section L113, the fourth eleventh auxiliary line section L114, the fifth eleventh auxiliary line section L115, the sixth eleventh auxiliary line section L116, and the seventh eleventh auxiliary line section L117 are electrically connected to K61 through vias.

[0144] The first twelfth auxiliary line section L121, the second twelfth auxiliary line section L122, the third twelfth auxiliary line section L123, the fourth twelfth auxiliary line section L124, the fifth twelfth auxiliary line section L125, the sixth twelfth auxiliary line section L126, and the seventh twelfth auxiliary line section L127 are electrically connected to K62 through vias.

[0145] exist Figures 5-7 , Figures 10-12 In the image, the icon with a multiplication sign inside the box represents a via. Figures 4-7 In at least one embodiment shown, each main sub-signal line is formed on a gate metal layer, and the connecting line is formed on a source-drain metal layer. An insulating layer is disposed between the gate metal layer and the source-drain metal layer, and the via is a via that penetrates the insulating layer; H1, H2, H3, H4, H5 and H6 are vias that penetrate the insulating layer.

[0146] exist Figure 4 , Figures 8-12 In at least one embodiment shown, each main sub-signal line is formed on a gate metal layer, and the connecting lines and each auxiliary sub-signal line are formed on a source-drain metal layer. An insulating layer is disposed between the gate metal layer and the source-drain metal layer, and the via is a via that penetrates the insulating layer; H1, H2, H3, H4, H5 and H6 are vias that penetrate the insulating layer.

[0147] exist Figure 4 , Figures 8-12 In at least one embodiment, the orthographic projection of the first auxiliary sub-signal line on the substrate can be within the orthographic projection of the first main sub-signal line on the substrate, the orthographic projection of the second auxiliary sub-signal line on the substrate can be within the orthographic projection of the second main sub-signal line on the substrate, the orthographic projection of the third auxiliary sub-signal line on the substrate can be within the orthographic projection of the third main sub-signal line on the substrate, the orthographic projection of the fourth auxiliary sub-signal line on the substrate can be within the orthographic projection of the fourth main sub-signal line on the substrate, and the orthographic projection of the fifth auxiliary sub-signal line on the substrate can be within the orthographic projection of the fifth main sub-signal line on the substrate, thereby increasing the film thickness of the signal line and reducing the resistance of the signal line.

[0148] like Figure 4 , Figures 8-12 In at least one embodiment shown, a gap is provided between two adjacent auxiliary line portions of the same auxiliary sub-signal line;

[0149] For example, such as Figure 9 As shown, there is a gap between L016 and L017, a gap between L026 and L027, and a gap between L036 and L037. L6 is electrically connected to the 6B-level shift register unit in A6 through the gap between L036 and L037, the gap between L026 and L027, and the gap between L016 and L017 in sequence.

[0150] exist Figure 4 , Figures 8-12 In at least one embodiment shown, each connection line and each auxiliary sub-signal line are formed on the source / drain metal layer, and the connection lines and each auxiliary sub-signal line do not overlap to avoid signal interference.

[0151] exist Figure 4 , Figures 8-12 In at least one embodiment shown, each auxiliary sub-signal line includes an auxiliary line portion that is electrically connected to the corresponding main body sub-signal line through two vias, with one via near the lower end of the auxiliary line portion and the other via near the upper end of the auxiliary line portion, so that the auxiliary sub-signal line and the corresponding main body sub-signal line can form a parallel relationship, thereby further reducing the resistance of the signal line.

[0152] Figure 11 As shown, via H7 is the seventh via, and via H8 is the eighth via; Figure 4 and Figure 11 As shown, L012 is electrically connected to K11 through H7 and H8 respectively. The orthographic projection of H7 on the substrate is close to the lower end of the orthographic projection of L012 on the substrate, and the orthographic projection of H8 on the substrate is close to the upper end of the orthographic projection of L102 on the substrate.

[0153] exist Figures 13-16In at least one embodiment shown, A1 is the first driving circuit region, A2 is the second driving circuit region, A3 is the third driving circuit region, A4 is the fourth driving circuit region, and A5 is the fifth driving circuit region. In the first driving circuit region A1, a first-stage shift register unit included in the first driving circuit is provided; in the second driving circuit region A2, a second-stage shift register unit included in the first driving circuit is provided; in the third driving circuit region A3, a third-stage shift register unit included in the first driving circuit is provided; in the fourth driving circuit region A4, a fourth-stage shift register unit included in the first driving circuit is provided; and in the fifth driving circuit region A5, a fifth-stage shift register unit included in the first driving circuit is provided.

[0154] like Figure 13 As shown, the display panel described in at least one embodiment of this disclosure includes a first driving circuit, a first clock signal line, a second clock signal line, a third clock signal line, a fourth clock signal line, a fifth clock signal line, and a sixth clock signal line, wherein, as... Figure 13 As shown, the first clock signal line includes a first main body sub-signal line K11 and a second main body sub-signal line K12;

[0155] The second clock signal line includes the third main body sub-signal line K21 and the fourth main body sub-signal line K22; the third clock signal line includes the fifth main body sub-signal line K31 and the sixth main body sub-signal line K32; the fourth clock signal line includes the seventh main body sub-signal line K41 and the eighth main body sub-signal line K42; the fifth clock signal line includes the ninth main body sub-signal line K51 and the tenth main body sub-signal line K52; the sixth clock signal line includes the eleventh main body sub-signal line K61 and the twelfth main body sub-signal line K62;

[0156] like Figure 13 As shown, K11, K12, K21, K22, K31, K32, K41, K42, K51, K52, K61 and K62 are all formed in the gate metal layer;

[0157] like Figure 14 As shown, the first auxiliary sub-signal line includes a first first auxiliary line section L011, a second first auxiliary line section L012, a third first auxiliary line section L013, a fourth first auxiliary line section L014, and a fifth first auxiliary line section L015. The first auxiliary sub-signal line is electrically connected to K11.

[0158] exist Figure 14In the diagram, H01 is the first connecting via, H02 is the second connecting via, H03 is the third connecting via, H04 is the fourth connecting via, H05 is the fifth connecting via, H06 is the sixth connecting via, H07 is the seventh connecting via, H08 is the eighth connecting via, H09 is the ninth connecting via, and H010 is the tenth connecting via.

[0159] exist Figure 13 In the diagram, the lower end of K11 is the first end of K11, and the upper end of K11 is the second end of K11; combined with... Figure 13 and Figure 14 It can be seen that the first auxiliary sub-signal line is electrically connected to K11 through H01 and H02 respectively, and the orthographic projection of H01 on the substrate is close to the lower end of the orthographic projection of K11 on the substrate, and the orthographic projection of H02 on the substrate is close to the upper end of the orthographic projection of K11 on the substrate. Figure 13 and Figure 14 It can be seen that L011 is electrically connected to K11 through H02 and H03 respectively, L012 is electrically connected to K11 through H04 and H05 respectively, L013 is electrically connected to K11 through H06 and H07, L014 is electrically connected to K11 through H08 and H09, and L015 is electrically connected to K11 through H010 and H01. The orthographic projection of H02 on the substrate is close to the upper end of the orthographic projection of L011 on the substrate, the orthographic projection of H03 on the substrate is close to the lower end of the orthographic projection of L011 on the substrate, the orthographic projection of H04 on the substrate is close to the upper end of the orthographic projection of L012 on the substrate, and the orthographic projection of H05 on the substrate is close to the upper end of the orthographic projection of L012 on the substrate. The orthographic projection is close to the lower end of the orthographic projection of L012 on the substrate. The orthographic projection of H06 on the substrate is close to the upper end of the orthographic projection of L013 on the substrate. The orthographic projection of H07 on the substrate is close to the lower end of the orthographic projection of L013 on the substrate. The orthographic projection of H08 on the substrate is close to the upper end of the orthographic projection of L014 on the substrate. The orthographic projection of H09 on the substrate is close to the lower end of the orthographic projection of L014 on the substrate. The orthographic projection of H010 on the substrate is close to the upper end of the orthographic projection of L015 on the substrate. The orthographic projection of H01 on the substrate is close to the lower end of the orthographic projection of L015 on the substrate.

[0160] exist Figures 13-16 In at least one corresponding embodiment, the orthographic projection of the first auxiliary sub-signal line on the substrate is within the orthographic projection of K11 on the substrate, the distance between the orthographic projection of H01 on the substrate and the orthographic projection of the lower end of K11 on the substrate is small, and the distance between the orthographic projection of H02 on the substrate and the orthographic projection of the upper end of K11 on the substrate is small.

[0161] Optionally, the display panel includes a first driving circuit and a second driving circuit, and the display panel includes a first signal line and a second signal line;

[0162] The first driving circuit and the first signal line are both located on the first side of the display panel, and the second driving circuit and the second signal line are both located on the second side of the display panel.

[0163] The first side and the second side are opposite sides.

[0164] In a specific implementation, the display panel may include two driving circuits and two signal lines. The first driving circuit and the first signal line may both be located on the first side of the display panel, and the second driving circuit and the second signal line may both be located on the second side of the display panel.

[0165] In at least one embodiment of this disclosure, the number of the first signal lines can be at least one, and the number of the second signal lines can be at least one.

[0166] In a specific implementation, the first signal line is located on the side of the first driving circuit away from the display area; or, the first signal line is located between the first driving circuit and the display area.

[0167] The second signal line is located on the side of the second driving circuit away from the display area; or, the second signal line is located between the second driving circuit and the display area.

[0168] In at least one embodiment of this disclosure, the display panel includes a plurality of data lines disposed on the substrate and located in the display area;

[0169] The extension direction of the main sub-signal line can be the same as or approximately the same as the extension direction of the data line.

[0170] In at least one embodiment of this disclosure, the extension direction of the main sub-signal line being substantially the same as the extension direction of the data line can mean that the angle between the extension direction of the main sub-signal line and the extension direction of the data line is less than a predetermined angle.

[0171] Optionally, the signal lines may include a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line, and the display panel may include a first driving circuit and a second driving circuit. The first driving circuit, the first clock signal line, and the second clock signal line are disposed on one side of the display panel, and the second driving circuit, the third clock signal line, and the fourth clock signal line are disposed on the other side of the display panel.

[0172] The first clock signal line includes a first main body sub-signal line and a second main body sub-signal line; the second clock signal line includes a third main body sub-signal line and a fourth main body sub-signal line; the third clock signal line includes a fifth main body sub-signal line and a sixth main body sub-signal line; and the fourth clock signal line includes a seventh main body sub-signal line and an eighth main body sub-signal line.

[0173] The first end of the first main body sub-signal line and the first end of the second main body sub-signal line can be electrically connected by a wire, and the second end of the first main body sub-signal line and the second end of the second main body sub-signal line can be electrically connected by a wire. The resistance of the first clock signal line is reduced by connecting the first main body sub-signal line and the second main body sub-signal line in parallel.

[0174] The first end of the third main body sub-signal line and the first end of the fourth main body sub-signal line can be electrically connected by a wire, and the second end of the third main body sub-signal line and the second end of the fourth main body sub-signal line can be electrically connected by a wire. The resistance of the second clock signal line is reduced by connecting the third main body sub-signal line and the fourth main body sub-signal line in parallel.

[0175] The first end of the fifth main body sub-signal line and the first end of the sixth main body sub-signal line can be electrically connected by a wire, and the second end of the fifth main body sub-signal line and the second end of the sixth main body sub-signal line can be electrically connected by a wire. By connecting the fifth main body sub-signal line and the sixth main body sub-signal line in parallel, the resistance of the third clock signal line can be reduced.

[0176] The first end of the seventh main body sub-signal line and the first end of the eighth main body sub-signal line can be electrically connected by a wire, and the second end of the seventh main body sub-signal line and the second end of the eighth main body sub-signal line can be electrically connected by a wire. The resistance of the fourth clock signal line is reduced by connecting the seventh main body sub-signal line and the eighth main body sub-signal line in parallel.

[0177] The first driving circuit includes a multi-stage shift register unit, and the second driving circuit includes a multi-stage shift register unit;

[0178] The first main body sub-signal line is directly electrically connected to the odd-numbered shift register unit in the first driving circuit, and the third main body sub-signal line is directly electrically connected to the even-numbered shift register unit in the first driving circuit.

[0179] The second main body sub-signal line is not directly electrically connected to the shift register unit, and the fourth main body sub-signal line is not directly electrically connected to the shift register unit, so that the parasitic capacitance on the second main body sub-signal line and the fourth main body sub-signal line is very small. Therefore, the clock signal output at the far end of the clock signal line can be made undistorted, thus greatly reducing the fall time Tf of the signal output by the shift register unit electrically connected to the far end of the clock signal line, and improving the charging time. The fifth main body sub-signal line is directly electrically connected to the odd-numbered shift register unit in the second driving circuit, and the seventh main body sub-signal line is directly electrically connected to the even-numbered shift register unit in the second driving circuit.

[0180] The sixth main body sub-signal line is not directly electrically connected to the shift register unit, and the eighth main body sub-signal line is not directly electrically connected to the shift register unit. This ensures that the parasitic capacitance on the sixth and eighth main body sub-signal lines is very small. Therefore, the clock signal output at the far end of the clock signal line can be kept undistorted. Consequently, the fall time Tf of the signal output by the shift register unit electrically connected to the far end of the clock signal line is greatly reduced, improving the charging time. Figure 17 As shown, the display panel includes a first driving circuit and a second driving circuit, and the display panel also includes a first clock signal line K1, a second clock signal line K2, a third clock signal line K3 and a fourth clock signal line K4;

[0181] The first clock signal line K1 and the second clock signal line K2 are located on the left side of the display panel, and the third clock signal line K3 and the fourth clock signal line K4 are located on the right side of the display panel; the first driving circuit is located on the left side of the display panel, and the second driving circuit is located on the right side of the display panel.

[0182] exist Figure 17 In the diagram, S11 represents the first-stage left-side shift register unit included in the first driving circuit, S12 represents the second-stage left-side shift register unit included in the first driving circuit, S1P-1 represents the (P-1)th stage left-side shift register unit included in the first driving circuit, and S1P represents the Pth stage left-side shift register unit included in the first driving circuit; P is an integer greater than 3.

[0183] S21 is the first-stage right-side shift register unit included in the second driving circuit, S22 is the second-stage right-side shift register unit included in the second driving circuit, S2P-1 is the P-1th-stage right-side shift register unit included in the second driving circuit, and S2P is the Pth-stage right-side shift register unit included in the second driving circuit.

[0184] exist Figure 17 In the diagram, the first row of pixel circuits located in display area A0 is labeled P11, the second row of pixel circuits located in display area A0 is labeled P103, the (P-1)th row of pixel circuits located in display area A0 is labeled P104, and the Pth row of pixel circuits located in display area A0 is labeled P104.

[0185] S11 and S21 provide gate drive signals for P11, S12 and S22 provide gate drive signals for P12, S1P-1 and S2P-1 provide gate drive signals for P103, and S1P and S2P provide gate drive signals for P104.

[0186] The first clock signal line K1 and the second clock signal line K2 are located on the side of the first driving circuit away from A0, and the third clock signal line K3 and the fourth clock signal line K4 are located on the side of the second driving circuit away from A0.

[0187] The first clock signal line K1 includes a first main sub-signal line K11 and a second main sub-signal line K12; the second clock signal line K2 includes a third main sub-signal line K21 and a fourth main sub-signal line K22; the third clock signal line K3 includes a fifth main sub-signal line K31 and a sixth main sub-signal line K32; the fourth clock signal line K4 includes a seventh main sub-signal line K41 and an eighth main sub-signal line K42.

[0188] The first end of K11 is the lower end of K11, and the second end of K11 is the upper end of K11;

[0189] The first end of K12 is the lower end of K12, and the second end of K12 is the upper end of K12;

[0190] The first end of K21 is the lower end of K21, and the second end of K21 is the upper end of K21;

[0191] The first end of K22 is the lower end of K22, and the second end of K22 is the upper end of K22; the first end of K11 is electrically connected to the first end of K12 through a wire, and the second end of K11 is electrically connected to the second end of K12 through a wire.

[0192] The first end of K11 is electrically connected to the first end of K12 via a wire, and the second end of K11 is electrically connected to the second end of K12 via a wire;

[0193] The first end of K31 is the lower end of K31, and the second end of K31 is the upper end of K31;

[0194] The first end of K32 is the lower end of K32, and the second end of K32 is the upper end of K32;

[0195] The first end of K41 is the lower end of K41, and the second end of K41 is the upper end of K41;

[0196] The first end of K42 is the lower end of K42, and the second end of K42 is the upper end of K42; the first end of K31 is electrically connected to the first end of K32 through a wire, and the second end of K31 is electrically connected to the second end of K32 through a wire.

[0197] The first end of K41 is electrically connected to the first end of K42 via a wire, and the second end of K41 is electrically connected to the second end of K42 via a wire.

[0198] exist Figure 17 In at least one embodiment shown, each driving circuit is a gate driving circuit, and the signal provided by each driving circuit is a gate driving signal, but this is not a limitation.

[0199] exist Figure 17 In at least one embodiment shown, V11 is the first low voltage line, V12 is the second low voltage line, S01 is the first start signal line, and S02 is the second start signal line.

[0200] like Figure 17 As shown, K11 is directly electrically connected to S11 and S1P-1 to provide a first clock signal for S11 and S1P-1; K21 is directly electrically connected to S12 and S1P to provide a second clock signal for S12 and S1P.

[0201] K31 is directly electrically connected to S21 and S2P-1 and is used to provide a third clock signal for S21 and S2P-1; K41 is directly electrically connected to S22 and S2P and is used to provide a fourth clock signal for S22 and S2P; the first clock signal can be the same as the third clock signal, and the second clock signal can be the same as the fourth clock signal.

[0202] V11 is electrically connected to S11, S12, S1P-1 and S1P, and is used to provide a first low voltage signal to S11, S12, S1P-1 and S1P; V12 is electrically connected to S21, S22, S2P-1 and S2P, and is used to provide a first low voltage signal to S21, S22, S2P-1 and S2P.

[0203] S01 is electrically connected to S11 and is used to provide a first start signal for S11. S02 is electrically connected to S21 and is used to provide a second start signal for S21.

[0204] Furthermore, in Figure 17 In at least one embodiment shown, the first end is the near end and the second end is the far end. The near end can be the terminal of each clock signal line that is closer to the driver chip, and the far end can be the terminal of each clock signal line that is farther from the driver chip.

[0205] like Figure 17 As shown, the driver chip 40 can be disposed on the lower side of the display panel. The driver chip 40 is used to provide a first clock signal to K1, a second clock signal to K2, a third clock signal to K3, a fourth clock signal to K4, a first start signal to S01, a second start signal to S02, a first low voltage signal to V11, and a second low voltage signal to V12. In this disclosure as... Figure 13 In at least one embodiment shown, each clock signal line includes two main sub-signal lines, one of which is not directly electrically connected to the drive circuit. This main sub-signal line has no parasitic capacitance, so the clock signal output at the far end of the clock signal line can be made distorted. As a result, the fall time Tf of the gate drive signal output by the shift register unit electrically connected to the far end of the clock signal line is greatly reduced.

[0206] Optionally, the signal line is disposed on the third side of the display panel; a driver chip that provides the signal to the signal line is attached to the third side.

[0207] The signal line is positioned between the driver chip and the display area.

[0208] In at least one embodiment of this disclosure, the driving circuit and the signal line may be disposed on the same side as the driving chip. The driving chip provides signals to the signal line, the signal line provides signals to the driving circuit, and the driving circuit provides control signals to the gate lines disposed in the display area. In this case, the signal line may be disposed on the side of the driving circuit away from the display area; or, the signal line may be disposed between the driving circuit and the display area.

[0209] In practice, in order to achieve a narrow bezel, that is, to narrow the width of the first and second sides of the display panel, the signal lines and driving circuits can also be located on the third side of the display panel.

[0210] Optionally, a driver chip that provides the signal to the signal line is attached to the third side of the display panel; the signal line and the driver circuit are disposed on the fourth side of the display panel; the third side and the fourth side are opposite sides.

[0211] In at least one embodiment of this disclosure, the driving circuit and the signal line can be disposed on a fourth side of the display panel, the fourth side being the side opposite to the third side, to achieve a narrow bezel. In this case, the signal line can be disposed on the side of the driving circuit away from the display area; or, the signal line can be disposed between the driving circuit and the display area.

[0212] In a specific implementation, the display panel further includes multiple gate lines disposed on the substrate and located in the display area;

[0213] The extension direction of the main sub-signal line is the same as or substantially the same as the extension direction of the gate line. In at least one embodiment of this disclosure, "the extension direction of the main sub-signal line is substantially the same as the extension direction of the gate line" can mean that the angle between the extension direction of the main sub-signal line and the extension direction of the gate line is less than a predetermined angle.

[0214] like Figure 18 As shown, the display panel described in at least one embodiment of this disclosure includes a driving circuit 120, a first clock signal line K1, and a second clock signal line K2;

[0215] The driver chip 40, driver circuit 120, K1 and K2 are all disposed on the lower side of the display panel; the driver circuit 120 is used to provide gate drive signals for the gate lines disposed in the display area A0; the first clock signal line K1 includes a first main body sub-signal line K11 and a second main body sub-signal line K12; the second clock signal line K2 includes a third main body sub-signal line K21 and a fourth main body sub-signal line K22;

[0216] The first end of K11 is the left end of K11, and the second end of K11 is the right end of K11;

[0217] The first end of K12 is the left end of K12, and the second end of K12 is the right end of K12;

[0218] The first end of K21 is the left end of K21, and the second end of K21 is the right end of K21;

[0219] The first end of K22 is the left end of K22, and the second end of K22 is the right end of K22; the first end of K11 is electrically connected to the first end of K12 via a wire, and the second end of K11 is electrically connected to the second end of K12 via a wire; K11 and K12 are connected in parallel to reduce the resistance of K1; the first end of K11 is electrically connected to the first end of K12 via a wire, and the second end of K11 is electrically connected to the second end of K12 via a wire; K21 and K22 are connected in parallel to reduce the resistance of K2. For example... Figure 18 As shown, K11 and K21 are directly electrically connected to the drive circuit 120, while K12 and K22 are not directly connected to the drive circuit 120. The parasitic capacitance on K12 and the parasitic capacitance on K22 are very small.

[0220] In this disclosure Figure 18 In at least one embodiment shown, each clock signal line includes two main sub-signal lines, one of which is not directly electrically connected to the drive circuit. This main sub-signal line has no parasitic capacitance, so the clock signal output at the far end of the clock signal line can be made distorted. As a result, the fall time Tf of the gate drive signal output by the shift register unit electrically connected to the far end of the clock signal line is greatly reduced.

[0221] exist Figure 18 In at least one embodiment shown, the driving circuit is a gate driving circuit, and the signal provided by the driving circuit is a gate driving signal, but is not limited thereto.

[0222] exist Figure 18 In at least one embodiment shown, when the third side is the lower side and both the driving circuit 120 and the driving chip 40 are located on the lower side of the display panel, the driving circuit can be electrically connected to the gate line located in the display area through vertical traces, but is not limited thereto.

[0223] like Figure 19 As shown, the display panel described in at least one embodiment of this disclosure includes a driving circuit 120, a first clock signal line K1, and a second clock signal line K2;

[0224] The driver chip 40 is located on the lower side of the display panel, while the driver circuits 120, K1, and K2 are all located on the upper side of the display panel.

[0225] The driving circuit 120 is used to provide gate driving signals for the gate lines disposed in the display area A0; the first clock signal line K1 includes a first main body sub-signal line K11 and a second main body sub-signal line K12; the second clock signal line K2 includes a third main body sub-signal line K21 and a fourth main body sub-signal line K22;

[0226] The first end of K11 is the left end of K11, and the second end of K11 is the right end of K11;

[0227] The first end of K12 is the left end of K12, and the second end of K12 is the right end of K12;

[0228] The first end of K21 is the left end of K21, and the second end of K21 is the right end of K21;

[0229] The first end of K22 is the left end of K22, and the second end of K22 is the right end of K22; the first end of K11 is electrically connected to the first end of K12 via a wire, and the second end of K11 is electrically connected to the second end of K12 via a wire; K11 and K12 are connected in parallel to reduce the resistance of K1; the first end of K11 is electrically connected to the first end of K12 via a wire, and the second end of K11 is electrically connected to the second end of K12 via a wire; K21 and K22 are connected in parallel to reduce the resistance of K2. For example... Figure 19 As shown, K11 and K21 are directly electrically connected to the drive circuit 40, while K12 and K22 are not directly connected to the drive circuit 120. The parasitic capacitance on K12 and K22 is very small. Figure 19 In at least one embodiment shown, the driver chip 40 is electrically connected to the left end of K11 and the left end of K12 via a first signal output line L01 to provide a first clock signal for K1, and the driver chip 40 is electrically connected to the left end of K21 and the left end of K22 via a second signal output line L02 to provide a second clock signal for K2.

[0230] In this disclosure Figure 19 In at least one embodiment shown, each clock signal line includes two main sub-signal lines, one of which is not directly electrically connected to the drive circuit. This main sub-signal line has no parasitic capacitance, so the clock signal output at the far end of the clock signal line can be made distorted. As a result, the fall time Tf of the gate drive signal output by the shift register unit electrically connected to the far end of the clock signal line is greatly reduced.

[0231] exist Figure 19 In at least one embodiment shown, the driving circuit is a gate driving circuit, and the signal provided by the driving circuit is a gate driving signal, but is not limited thereto.

[0232] exist Figure 19 In at least one embodiment shown, when the fourth side is the upper side and both the driving circuit 120 and the driving chip 40 are located on the upper side of the display panel, the driving circuit can be electrically connected to the gate line located in the display area through vertical traces, but is not limited thereto.

[0233] The display device described in this disclosure includes the display panel described above.

[0234] Optionally, the display device described in at least one embodiment of this disclosure further includes a driver chip; the driver chip provides the signal through a signal output terminal;

[0235] The signal output terminal of the driver chip is electrically connected to the first terminal of the at least two main body sub-signal lines.

[0236] The display device provided in this disclosure can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Unless otherwise defined, the technical or scientific terms used in this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar words used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Words such as "comprising" or "including" mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, but does not exclude other elements or objects. Words such as "connected," "coupled," or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0237] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0238] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0239] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A display panel, comprising a driving circuit disposed on a substrate and signal lines providing signals to the driving circuit; The signal line includes at least two main sub-signal lines; each main sub-signal line includes a first end and a second end. The first ends of the at least two main body sub-signal lines are electrically connected to each other, and the second ends of the at least two main body sub-signal lines are electrically connected to each other. The portions of the at least two master sub-signal lines, excluding the first end and the second end, are independent of each other; N of the at least two main body sub-signal lines are directly electrically connected to the driving circuit to provide signals to the driving circuit; the N main body sub-signal lines are direct-connected main body sub-signal lines, and the main body sub-signal lines other than the direct-connected main body sub-signal lines among the at least two main body sub-signal lines are non-direct-connected main body sub-signal lines. The non-direct-connected main body sub-signal lines are not directly electrically connected to the driving circuit, but are electrically connected to the driving circuit through the direct-connected main body sub-signal lines. N is a positive integer, and N is less than the number of main sub-signal lines included in the signal line; The driving circuit is a gate driving circuit; The at least two master signal lines are electrically connected to each other only at the first and second ends; Among all the signal lines included in the display panel, at least two main sub-signal lines included in the same signal line are arranged adjacent to each other; The main sub-signal line is a signal line from the first end to the second end; The signal line includes A main sub-signal lines; the signal line also includes M auxiliary sub-signal lines; the a-th main sub-signal line corresponds to the m-th auxiliary sub-signal line; A is an integer greater than 1; M is a positive integer; a is a positive integer less than or equal to A, and m is a positive integer less than or equal to M; The a-th main sub-signal line is electrically connected to the m-th auxiliary sub-signal line through at least two connection vias. The a-th main sub-signal line and the m-th auxiliary sub-signal line are formed on different conductive layers. The orthographic projection of the a-th main sub-signal line on the substrate and the orthographic projection of the m-th auxiliary sub-signal line on the substrate at least partially overlap.

2. The display panel as claimed in claim 1, wherein, The at least two main sub-signal lines are formed on the same conductive layer, and the at least two main sub-signal lines are electrically connected to each other only at the first end and the second end by a wire.

3. The display panel as claimed in claim 1, wherein, At least two of the main body sub-signal lines are formed on different conductive layers.

4. The display panel as claimed in claim 1, wherein, The display panel also includes connecting wires, each of which is electrically connected to the driving circuit. The connecting line and the direct-connect main body sub-signal line are formed on different conductive layers; the connecting line is electrically connected to the direct-connect main body sub-signal line through a via, and the different connecting lines formed on the same layer do not overlap.

5. The display panel as claimed in claim 1, wherein, The maximum distance between the orthographic projection of one of the at least two connecting vias on the substrate and the orthographic projection of the first end of the a-th main sub-signal line on the substrate is less than a first predetermined distance; The maximum distance between the orthographic projection of another of the at least two connecting vias on the substrate and the orthographic projection of the second end of the a-th main sub-signal line on the substrate is less than the first predetermined distance.

6. The display panel as claimed in claim 1, wherein, The auxiliary sub-signal line includes multiple auxiliary line portions, each of which is electrically connected to a corresponding main sub-signal line through at least two vias. The orthographic projection of the auxiliary line portion on the substrate is within the orthographic projection of the corresponding main sub-signal line on the substrate.

7. The display panel as claimed in claim 6, wherein, The auxiliary line section includes a third end and a fourth end; The maximum distance between the orthographic projection of one of the at least two vias on the substrate and the orthographic projection of the third end of the auxiliary line portion on the substrate is less than the second predetermined distance; The maximum distance between the orthographic projection of another of the at least two vias on the substrate and the orthographic projection of the fourth end of the auxiliary line portion on the substrate is less than the second predetermined distance.

8. The display panel as claimed in claim 6, wherein, A gap is provided between two adjacent auxiliary line portions of the same auxiliary sub-signal line; The display panel also includes connecting lines; the connecting lines are electrically connected to the direct-connect main body sub-signal lines through vias, and different connecting lines formed on the same layer do not overlap. The connecting wire passes through a portion of the gap and is electrically connected to the drive circuit; The connecting line and the auxiliary sub-signal line do not overlap.

9. The display panel as claimed in claim 8, wherein, The connecting line and the auxiliary sub-signal line are formed on the same conductive layer.

10. The display panel according to any one of claims 1 to 9, wherein, The signal lines include a first clock signal line and a second clock signal line; the display panel includes a driving circuit, and the driving circuit, the first clock signal line, and the second clock signal line are disposed on the same side of the display panel; The first clock signal line includes a first main body sub-signal line and a second main body sub-signal line, and the second clock signal line includes a third main body sub-signal line and a fourth main body sub-signal line; The driving circuit includes a multi-stage shift register unit; The first main body sub-signal line is directly electrically connected to the odd-level shift register unit, and the third main body sub-signal line is directly electrically connected to the even-level shift register unit.

11. The display panel according to any one of claims 1 to 9, wherein, The signal lines include a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line. The display panel includes a first driving circuit and a second driving circuit. The first driving circuit, the first clock signal line, and the second clock signal line are disposed on one side of the display panel, and the second driving circuit, the third clock signal line, and the fourth clock signal line are disposed on the other side of the display panel. The first clock signal line includes a first main body sub-signal line and a second main body sub-signal line; the second clock signal line includes a third main body sub-signal line and a fourth main body sub-signal line; the third clock signal line includes a fifth main body sub-signal line and a sixth main body sub-signal line; and the fourth clock signal line includes a seventh main body sub-signal line and an eighth main body sub-signal line. The first driving circuit includes a multi-stage shift register unit, and the second driving circuit includes a multi-stage shift register unit; The first main body sub-signal line is directly electrically connected to the odd-level shift register unit in the first driving circuit; the third main body sub-signal line is directly electrically connected to the even-level shift register unit in the first driving circuit; the fifth main body sub-signal line is directly electrically connected to the odd-level shift register unit in the second driving circuit; and the seventh main body sub-signal line is directly electrically connected to the even-level shift register unit in the second driving circuit.

12. A display device comprising a display panel as claimed in any one of claims 1 to 11.

13. The display device as claimed in claim 12, wherein, It also includes the driver chip; The driver chip is used to provide the signal through the signal output terminal; The signal output terminal of the driver chip is electrically connected to the first terminal of the at least two main body sub-signal lines.

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