A programmable memory array, programming method, and semiconductor memory

Abstract

The embodiment of the present disclosure provides a programmable storage array, a programming method and a semiconductor memory. The programmable storage array comprises a plurality of storage units, each of the storage units comprising a first transistor and a second transistor connected in series; a first end of the first transistor is connected with a bit line, a gate end of the first transistor is connected with a programming line, and a second end of the first transistor is connected with a first end of the second transistor; a gate end of the second transistor is connected with a word line, and a second end of the second transistor is connected with a first preset power supply; wherein, when programming the storage unit, the second transistor is controlled to be in a conductive state, and a voltage difference between the gate end of the first transistor and the first end of the first transistor is greater than 0; when restoring the storage unit, the second transistor is controlled to be in the conductive state, and the voltage difference between the gate of the first transistor and the first end of the first transistor is less than 0. In this way, not only the gate oxide layer is not broken down, but also multiple programming of the storage unit can be realized.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a programmable memory array, a programming method, and a semiconductor memory. Background Technology

[0002] With the continuous development of integrated circuit technology, fuse memory cells are widely used in integrated circuits for repair work. Among them, the gate oxide fuse memory cell is a typical example. Its most classic structure consists of a control gate and a fuse gate forming a fuse circuit. The programming effect is achieved by controlling whether the gate oxide of the fuse gate breaks down.

[0003] A gate oxide fuse memory cell may include a fuse transistor and a transfer transistor. When a high voltage is applied to the fuse gate of the fuse transistor, the gate oxide layer of the fuse transistor is damaged due to the voltage difference between the high-voltage fuse gate and the low-voltage bit line. Specifically, a voltage sufficient to form a conductive channel is applied to the control gate of the transfer transistor to transfer the fuse gate voltage; then, by controlling the voltage difference between the fuse gate and the bit line to break down the gate oxide layer, a programming operation is completed. Summary of the Invention

[0004] This disclosure provides a programmable memory array, a programming method, and a semiconductor memory that not only eliminates the need to break down the gate oxide layer but also enables multiple programming of memory cells.

[0005] In a first aspect, embodiments of this disclosure provide a programmable memory array, which includes a plurality of memory cells, each memory cell including a first transistor and a second transistor connected in series;

[0006] The first terminal of the first transistor is connected to the bit line, the gate terminal of the first transistor is connected to the programming line, and the second terminal of the first transistor is connected to the first terminal of the second transistor.

[0007] The gate of the second transistor is connected to the word line, and the second terminal of the second transistor is connected to the first preset power supply.

[0008] Specifically, when programming the memory cell, the second transistor is controlled to be in the on state, and the voltage difference between the gate terminal and the first terminal of the first transistor is controlled to be greater than 0.

[0009] When restoring the memory cell, the second transistor is controlled to be in the on state, and the voltage difference between the gate of the first transistor and the first terminal of the first transistor is controlled to be less than 0.

[0010] In some embodiments, the plurality of storage cells are arranged in an array, wherein:

[0011] Several memory cells are distributed along the extension direction of the bit line, and each memory cell is connected to the bit line through the first terminal of the first transistor.

[0012] Several memory cells are distributed along the extension direction of the word line, and each memory cell is connected to the word line through the gate terminal of the second transistor.

[0013] Several memory cells are distributed along the extension direction of the programming line, and each memory cell is connected to the programming line through the gate terminal of the first transistor.

[0014] The extension directions of the bit lines and word lines are perpendicular to each other, and the extension directions of the programming lines and word lines are parallel to each other.

[0015] In some embodiments, pre-charge modules are further distributed along the extension direction of the bit lines, wherein:

[0016] The precharge module is used to receive a precharge signal and precharge the bit line according to the precharge signal, so that the bit line voltage is precharged to a preset voltage.

[0017] In some embodiments, the precharge module includes a third transistor and a fourth transistor, wherein:

[0018] The first terminal of the fourth transistor is connected to the first voltage, the second terminal of the fourth transistor is connected to the bit line, and the gate terminal of the fourth transistor is used to receive the first precharge signal. When programming the memory cell, the first precharge signal turns on the fourth transistor, so that the bit line where the memory cell is located is precharged to the first voltage.

[0019] The first terminal of the third transistor is connected to the second voltage, the second terminal of the third transistor is connected to the bit line, and the gate terminal of the third transistor is used to receive the second precharge signal. When the memory cell is restored, the second precharge signal turns on the third transistor, so that the bit line where the memory cell is located is precharged to the second voltage.

[0020] The first voltage is lower than the second voltage.

[0021] In some embodiments, the first voltage ranges from -0.7 to 0V, and the second voltage ranges from 2.5 to 3V.

[0022] In some embodiments, the first voltage is -0.7V and the second voltage is 3V.

[0023] In some embodiments, the programmable memory array further includes a first power module and a second power module, wherein the first power module is connected to the programming line and the second power module is connected to the word line, wherein:

[0024] The first power supply module is used to provide control voltage for the programming line;

[0025] The second power module is used to provide word line voltage to the word lines.

[0026] In some embodiments, when programming the memory cell, the control voltage of all programming lines is controlled to be a third voltage by the first power module;

[0027] When restoring the storage unit, the control voltage of the programming line where the storage unit is located is controlled by the first power module to be the fourth voltage, and the control voltage of other programming lines is controlled to be the third voltage.

[0028] The third voltage is higher than the fourth voltage.

[0029] In some embodiments, the third voltage ranges from 2.5 to 3V, and the fourth voltage ranges from 0 to 1.5V.

[0030] In some embodiments, the third voltage is 3V and the fourth voltage is 1.5V.

[0031] In some embodiments, when a word line is selected, the word line voltage is controlled to a fifth voltage by the second power module; or, when a word line is not selected, the word line voltage is controlled to a sixth voltage by the second power module.

[0032] The fifth voltage is lower than the sixth voltage.

[0033] In some embodiments, if the fifth voltage is lower than the power supply voltage of the first preset power supply when the word line is selected, the second transistor is determined to be in the on state; or, if the sixth voltage is greater than or equal to the power supply voltage of the first preset power supply when the word line is not selected, the second transistor is determined to be in the off state.

[0034] In some embodiments, the fifth voltage is 0V and the sixth voltage is 3V.

[0035] In some embodiments, the programmable memory array further includes a readout circuit, wherein bit lines are connected to the readout circuit via different fifth transistors, wherein:

[0036] The first terminal of the fifth transistor is connected to the bit line, the second terminal of the fifth transistor is connected to the readout circuit, the gate terminal of the fifth transistor receives the column select signal, and the fifth transistor transmits the signal of the corresponding bit line to the readout circuit according to the column select signal.

[0037] In some embodiments, the readout circuit includes a readout resistor and a comparator, wherein:

[0038] The first input terminal of the comparator and the first terminal of the read resistor are both connected to the second terminal of the fifth transistor. The second terminal of the read resistor is grounded. The second input terminal of the comparator is used to receive the reference voltage. The output terminal of the comparator is used to read the data stored in the target memory cell. The target memory cell is determined by the column select signal and the word line.

[0039] In some embodiments, the first transistor is a PMOS transistor, and the second transistor is a PMOS transistor.

[0040] Secondly, embodiments of this disclosure provide a programming method applied to a programmable memory array including multiple memory cells. Each memory cell includes a first transistor and a second transistor. A first terminal of the first transistor is connected to a bit line, a gate terminal of the first transistor is connected to a programming line, a second terminal of the first transistor is connected to the first terminal of the second transistor, a gate terminal of the second transistor is connected to a word line, and a second terminal of the second transistor is connected to a first preset power supply. The method includes:

[0041] When programming the memory cell, the second transistor is controlled to be in the on state, and the voltage difference between the gate terminal and the first terminal of the first transistor is controlled to be greater than 0.

[0042] When restoring the memory cell, the second transistor is controlled to be in the on state, and the voltage difference between the gate of the first transistor and the first terminal of the first transistor is controlled to be less than 0.

[0043] In some embodiments, the method further includes:

[0044] When programming the memory cell, the control voltage of the control programming line is higher than the bit line voltage of the bit line, so that the voltage difference between the gate terminal of the first transistor and the first terminal of the first transistor is greater than 0.

[0045] When restoring a memory cell, the control voltage of the control programming line is lower than the bit line voltage of the bit line, so that the voltage difference between the gate terminal of the first transistor and the first terminal of the first transistor is less than 0.

[0046] Thirdly, embodiments of this disclosure provide a semiconductor memory including a programmable memory array as described in the first aspect.

[0047] This disclosure provides a programmable memory array, a programming method, and a semiconductor memory. The programmable memory array includes multiple memory cells, each memory cell including a first transistor and a second transistor connected in series. A first terminal of the first transistor is connected to a bit line, a gate terminal of the first transistor is connected to a programming line, and a second terminal of the first transistor is connected to a first terminal of the second transistor. The gate terminal of the second transistor is connected to a word line, and a second terminal of the second transistor is connected to a first preset power supply. When programming a memory cell, the second transistor is controlled to be in a conducting state, and the voltage difference between the gate terminal and the first terminal of the first transistor is controlled to be greater than 0. When restoring a memory cell, the second transistor is controlled to be in a conducting state, and the voltage difference between the gate terminal and the first terminal of the first transistor is controlled to be less than 0. In this way, based on the memory cell composed of the first transistor and the second transistor connected in series, when programming the memory cell, the voltage difference between the gate terminal and the first terminal of the first transistor is a positive voltage difference, which increases the channel leakage current of the first transistor, thereby enabling the data stored in the memory cell to be converted to 1; when restoring the memory cell, the voltage difference between the gate terminal and the first terminal of the first transistor is a negative voltage difference, which decreases the channel leakage current of the first transistor, thereby enabling the data stored in the memory cell to be converted to 0; thus, the memory cell can be repeatedly programmed, and since there is no need to break down the gate oxide layer, it also avoids the use of excessive voltage stress, which can improve the overshoot damage of high voltage to the memory cell, and ultimately improve the performance of the memory. Attached Figure Description

[0048] Figure 1 This is a schematic diagram of the structural composition of a gate oxide fuse memory cell;

[0049] Figure 2 A schematic diagram of the composition structure of a programmable memory array provided in this embodiment of the disclosure. Figure 1 ;

[0050] Figure 3 A schematic diagram of the composition structure of a programmable memory array provided in this embodiment of the disclosure. Figure 2 ;

[0051] Figure 4 A schematic diagram of the composition structure of a programmable memory array provided in this embodiment of the disclosure. Figure 3 ;

[0052] Figure 5 A schematic diagram illustrating the relationship between gate voltage and channel leakage current provided in an embodiment of this disclosure;

[0053] Figure 6 A schematic diagram of the composition structure of a programmable memory array provided in this embodiment of the disclosure. Figure 4 ;

[0054] Figure 7 A flowchart illustrating a programming method provided in an embodiment of this disclosure;

[0055] Figure 8 This is a schematic diagram of the composition structure of a semiconductor memory provided in an embodiment of this disclosure. Detailed Implementation

[0056] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely for explaining the relevant applications and are not intended to limit the applications. Furthermore, it should be noted that, for ease of description, only the parts relevant to the relevant applications are shown in the accompanying drawings.

[0057] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0058] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0059] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific order of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0060] It should also be noted that the high and low levels used for signals in the embodiments of this disclosure refer to the logic levels of the signals. A signal having a high level is different from having a low level. For example, a high level may correspond to a signal having a first voltage, while a low level may correspond to a signal having a second voltage. In some embodiments, the first voltage is higher than the second voltage. Furthermore, the logic level of a signal may be different from or opposite to the described logic level. For example, a signal described as having a logic "high" level may alternatively have a logic "low" level, and a signal described as having a logic "low" level may alternatively have a logic "high" level.

[0061] See Figure 1 This illustrates a schematic diagram of the structural composition of a gate oxide fuse memory cell. For example... Figure 1As shown, a gate oxide fuse memory cell may include a substrate 101 and a fuse transistor 102 and a transfer transistor 103 located above the substrate 101. A deep N-well region 104 is formed in the substrate 101, and a P-well region 105 is formed within the deep N-well region 104. A first doped region 106, a second doped region 107, and a third doped region 108 are disposed in the P-well region 105. The fuse transistor 102, also known as a programming transistor, is disposed above the substrate between the first doped region 106 and the second doped region 107; while the transfer transistor 103, also known as a selection transistor, is disposed above the substrate between the second doped region 107 and the third doped region 108.

[0062] exist Figure 1 In this configuration, the fuse gate of fuse transistor 102 is used to receive the word line voltage Wlp, and the control gate of transmission transistor 103 is used to receive the word line voltage Wlr. The first doped region 106, the second doped region 107, and the third doped region 108 can all be N+ doped regions, which can be used to form the source or drain.

[0063] Thus, as Figure 1 As shown, two separate gates (fuse gate + control gate) together form a fused path. Programming is achieved by controlling whether the gate oxide of the fuse gate breaks down. Specifically, by controlling the voltage difference between the fuse gate and the bit line to break down the gate oxide layer, a one-time programmable (OTP) operation can be completed. However, once the gate oxide fuse memory cell has completed OTP programming, the gate oxide layer of the fuse gate becomes a permanently conductive path, which cannot be subsequently reprogrammed to different states.

[0064] Based on this, embodiments of this disclosure provide a programmable memory array, which includes multiple memory cells, each including a first transistor and a second transistor connected in series. During programming of the memory cell, the voltage difference between the gate and first terminal of the first transistor is positive, increasing the channel leakage current of the first transistor, thereby enabling the data stored in the memory cell to be converted to 1. During recovery of the memory cell, the voltage difference between the gate and first terminal of the first transistor is negative, decreasing the channel leakage current of the first transistor, thereby enabling the data stored in the memory cell to be converted to 0. Thus, the memory cell can be repeatedly programmed, and since it does not require gate oxide breakdown, it avoids excessive voltage stress, mitigating overshoot damage to the memory cell from high voltage, and ultimately improving memory performance.

[0065] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0066] In one embodiment of this disclosure, see Figure 2 This illustration shows a schematic diagram of the composition structure of a programmable memory array provided in an embodiment of this disclosure. Figure 2 As shown, the programmable memory array 20 may include multiple memory cells (specifically memory cell A, memory cell B, memory cell C, and memory cell D).

[0067] Taking one of the memory cells as an example, the memory cell includes a first transistor P1 and a second transistor P2 connected in series; the first terminal of the first transistor P1 is connected to the bit line, the gate terminal of the first transistor P1 is connected to the programming line, and the second terminal of the first transistor P1 is connected to the first terminal of the second transistor P2; the gate terminal of the second transistor P2 is connected to the word line, and the second terminal of the second transistor P2 is connected to the first preset power supply.

[0068] It should be noted that during the programming of this memory cell, the second transistor P2 is controlled to be in the on state, and the voltage difference between the gate terminal and the first terminal of the first transistor P1 is controlled to be greater than 0. Thus, since the voltage difference between the gate terminal and the first terminal of the first transistor P1 is a positive voltage difference, based on the hot electron-induced breakdown (HEIP) effect of the first transistor P1, the first transistor P1 undergoes HEIP degradation under positive voltage stress, resulting in an increase in the channel leakage current of the first transistor P1. This enables the data stored in the memory cell to transition from "0" to "1".

[0069] It should also be noted that when restoring the memory cell, the second transistor P2 is controlled to be in the on state, and the voltage difference between the gate and the first terminal of the first transistor P1 is controlled to be less than 0. Thus, since the voltage difference between the gate and the first terminal of the first transistor P1 is a negative voltage difference, the first transistor P1 undergoes HEIP recovery characteristics under negative voltage stress, resulting in a reduction in the channel leakage current of the first transistor P1. This enables the data stored in the memory cell to transition from "1" to "0".

[0070] In some embodiments, the multiple storage cells may be arranged in an array, wherein:

[0071] Several memory cells are distributed along the extension direction of the bit line, and each memory cell is connected to the bit line through the first terminal of the first transistor P1.

[0072] Several memory cells are distributed along the extension direction of the word line, and each memory cell is connected to the word line through the gate terminal of the second transistor P2.

[0073] Several memory cells are distributed along the extension direction of the programming line, and each memory cell is connected to the programming line through the gate terminal of the first transistor P1.

[0074] It should be noted that, in the embodiments disclosed herein, the extension directions of the bit lines and the word lines are perpendicular to each other, and the extension directions of the programming lines and the word lines are parallel to each other.

[0075] It should also be noted that, in this embodiment of the disclosure, the number of bit lines can be at least one, the number of word lines can be at least one, and the number of programming lines can be at least one. See details... Figure 2 For four memory cells, there are two bit lines, which can be represented by BL1 and BL2; two word lines, which can be represented by WL1 and WL2; two programming lines, which can be represented by WL1' and WL2'; and the first preset power supply can be represented by VDD1.

[0076] For example, such as Figure 2 As shown, memory cells A, B, C, and D are arranged in a 2×2 array. The first terminal of the first transistor P1 in memory cell A and memory cell B is connected to bit line BL1; the first terminal of the first transistor P1 in memory cell C and memory cell D is connected to bit line BL2. The gate terminals of the first transistor P1 in memory cell A and memory cell C are connected to programming line WL1'; the gate terminals of the first transistor P1 in memory cell B and memory cell D are connected to programming line WL2'. The second terminal of the first transistor P1 in memory cell A is connected to the first terminal of its own second transistor P2; the second terminal of the first transistor P1 in memory cell B is connected to the first terminal of its own second transistor P2. The first connection is as follows: the second terminal of the first transistor P1 in memory cell C is connected to the first terminal of its own second transistor P2; the second terminal of the first transistor P1 in memory cell D is connected to the first terminal of its own second transistor P2; the gate terminals of the second transistor P2 in memory cell A and memory cell C are both connected to word line WL1; the gate terminals of the second transistor P2 in memory cell B and memory cell D are both connected to word line WL2; the second terminals of the second transistor P2 in memory cell A, memory cell B, memory cell C, and memory cell D are all connected to a first preset power supply VDD1. Here, the first preset power supply VDD1 can be 3.0V.

[0077] In some embodiments, both the first transistor and the second transistor can be P-type metal-oxide-semiconductor field-effect transistors (MOSFETs), also known as PMOSFETs or PMOS transistors. That is, the first transistor is a PMOS transistor, the second transistor is a PMOS transistor, and each memory cell consists of two PMOS transistors connected in series. Thus, based on the degradation and recovery characteristics of the PMOS transistor's HEIP (Heap In-Process) technology, multiple-time programmable (MTP) memory cells can be achieved.

[0078] It should be noted that, in the embodiments of this disclosure, the memory cell described herein, for the first transistor and the second transistor, can be composed of two PMOS transistors with thick gate oxide layers connected in series. The thickness of the thick gate oxide layer is generally greater than or equal to 30 nanometers (nm). Here, the purpose of the thick gate oxide is to prevent gate breakdown, while HEIP is the tunneling of the shallow trench isolation (STI) portion, which is unrelated to the gate oxide layer. Therefore, the fuse circuit formed by two PMOS transistors connected in series in the embodiments of this disclosure no longer needs to break down the gate oxide layer to achieve the programming effect, avoiding excessive voltage stress and effectively preventing overshoot damage to the memory cell from high voltage.

[0079] It should also be noted that, in this embodiment of the present disclosure, for the PMOS transistor, the first terminal can be the source terminal and the second terminal can be the drain terminal. In this way, based on the HEIP decay and recovery characteristics under voltage stress between the gate and source terminals of the first transistor P1, MTP programming can be performed, and overshoot damage to the memory cell caused by using excessively high voltages can be avoided.

[0080] Understandably, in Figure 2 Based on the programmable memory array 20 shown, in some embodiments, see [link to relevant documentation]. Figure 3 Pre-charge modules are also distributed along the extension direction of the bit lines, wherein:

[0081] The precharge module is used to receive a precharge signal and precharge the bit line according to the precharge signal, so that the bit line voltage is precharged to a preset voltage.

[0082] It should be noted that in this embodiment, the number of bit lines can be at least one, and correspondingly, the number of pre-charge modules is at least one. That is, pre-charge modules are distributed in the extension direction of each bit line to pre-charge the bit line where the pre-charge module is located to the corresponding preset voltage. For example, see [link to example]. Figure 3A precharge module 201 is distributed in the extension direction of bit line BL1, and a precharge module 202 is distributed in the extension direction of bit line BL2.

[0083] In some embodiments, for each precharge module, the precharge module may include a third transistor and a fourth transistor, wherein:

[0084] The first terminal of the fourth transistor is connected to the first voltage, the second terminal of the fourth transistor is connected to the bit line, and the gate terminal of the fourth transistor is used to receive the first precharge signal. When programming the memory cell, the first precharge signal turns on the fourth transistor, so that the bit line where the memory cell is located is precharged to the first voltage.

[0085] The first terminal of the third transistor is connected to the second voltage, the second terminal of the third transistor is connected to the bit line, and the gate terminal of the third transistor is used to receive the second precharge signal. When the memory cell is restored, the second precharge signal turns on the third transistor, so that the bit line where the memory cell is located is precharged to the second voltage.

[0086] In this embodiment of the disclosure, the first voltage is lower than the second voltage.

[0087] In this embodiment of the disclosure, the third transistor can be a P-type MOSFET (referred to as a PMOS transistor), and the fourth transistor can be an N-type MOSFET (referred to as an NMOS transistor).

[0088] For example, see details. Figure 3 A precharge module 201 is distributed along the extension direction of bit line BL1. This precharge module 201 may include a third transistor P31 and a fourth transistor N11. The first precharge signal can be represented by Precharge1, and the second precharge signal can be represented by CSL1. The first terminal of the fourth transistor N11 is connected to a first voltage V1, and the first terminal of the third transistor P31 is connected to a second voltage V2. The second terminals of both the third transistor P31 and the fourth transistor N11 are connected to bit line BL1. A precharge module 202 is distributed along the extension direction of bit line BL2. This precharge module 202 may include a third transistor P32 and a fourth transistor N12. The first precharge signal can be represented by Precharge2, and the second precharge signal can be represented by CSL2. The first terminal of the fourth transistor N12 is connected to the first voltage V1, and the first terminal of the third transistor P32 is connected to the second voltage V2. The second terminals of both the third transistor P32 and the fourth transistor N12 are connected to bit line BL2.

[0089] Taking memory cell A as an example, when programming memory cell A, the first precharge signal Precharge1 is set to a high level, controlling the fourth transistor N11 in the precharge module 201 to conduct, thereby precharging bit line BL1 to a low potential (i.e., the first voltage V1). When restoring memory cell A, the second precharge signal CSL1 is set to a low level, controlling the third transistor P31 in the precharge module 201 to conduct, thereby precharging bit line BL1 to a high potential (i.e., the second voltage V2). Alternatively, during the programming process of memory cell A, the second precharge signal CSL2 can also be set to a low level, controlling the third transistor P32 in the precharge module 202 to conduct, thereby precharging bit line BL2 to a high potential (i.e., the second voltage V2) to prevent other memory cells (e.g., memory cells C and D) from being programmed.

[0090] In some embodiments, the first voltage ranges from -0.7V to 0V, and the second voltage ranges from 2.5V to 3V. In one specific embodiment, the first voltage is -0.7V, and the second voltage is 3V.

[0091] In other words, taking memory cell A as an example, when programming memory cell A, the precharge module 201 controls bit line BL1 to be precharged to a low potential (e.g., -0.7V), and the precharge module 202 controls bit line BL2 to be precharged to a high potential (e.g., 3V); when restoring memory cell A, the precharge module 201 controls bit line BL1 to be precharged to a high potential (e.g., 3V), and the precharge module 202 continues to control bit line BL2 to be precharged to a high potential (e.g., 3V).

[0092] It is understandable that, Figure 3 Based on the programmable memory array 20 shown, in some embodiments, see [link to relevant documentation]. Figure 4 The programmable memory array 20 may further include a first power module 203 and a second power module 204, wherein the first power module 203 is connected to the programming line and the second power module 204 is connected to the word line, wherein:

[0093] The first power supply module 203 is used to provide control voltage for the programming line;

[0094] The second power supply module 204 is used to provide word line voltage for the word lines.

[0095] It should be noted that, in this embodiment of the disclosure, the programming lines (WL1', WL2') can be supplied with control voltage by the first power module 203; and the word lines (WL1, WL2) can be supplied with word line voltage by the second power module 204.

[0096] It should also be noted that, in the embodiments of this disclosure, when programming the memory cell, the control voltage of the programming line is controlled to be higher than the bit line voltage of the bit line, so that the voltage difference between the gate terminal of the first transistor P1 and the first terminal of the first transistor P1 is greater than 0; or, when restoring the memory cell, the control voltage of the programming line is controlled to be lower than the bit line voltage of the bit line, so that the voltage difference between the gate terminal of the first transistor P1 and the first terminal of the first transistor P1 is less than 0.

[0097] Thus, during memory cell programming, because the voltage difference between the gate and the first terminal of the first transistor P1 is greater than 0, the channel leakage current of the first transistor P1 increases due to its HEIP degradation characteristic, thereby controlling the conversion of the data stored in the memory cell from first data to second data. Alternatively, during memory cell recovery, because the voltage difference between the gate and the first terminal of the first transistor P1 is less than 0, the channel leakage current of the first transistor P1 decreases due to its HEIP recovery characteristic, thereby controlling the conversion of the data stored in the memory cell from second data to first data. Here, the first data can be 0, and the second data can be 1.

[0098] Furthermore, in some embodiments, when programming the memory cell, the control voltage of all programming lines is controlled to be a third voltage by the first power module 203;

[0099] When restoring the storage unit, the first power module 203 controls the control voltage of the programming line where the storage unit is located to the fourth voltage, and controls the control voltage of other programming lines to the third voltage.

[0100] In this embodiment of the disclosure, the third voltage is higher than the fourth voltage.

[0101] It should be noted that the programmable memory array 20 includes multiple memory cells, and the number of programming lines is at least one. For example, as shown... Figure 4 As shown, taking storage unit A as an example, when programming storage unit A, the control voltage of programming line WL1' can be controlled to the third voltage by the first power module 203, and the control voltage of other programming lines WL2' can also be controlled to the third voltage; when restoring storage unit A, the control voltage of programming line WL1' can be controlled to the fourth voltage by the first power module 203, and the control voltage of other programming lines WL2' can still be controlled to the third voltage.

[0102] In some embodiments, the third voltage ranges from 2.5 to 3V, and the fourth voltage ranges from 0 to 1.5V. In one specific embodiment, the third voltage is 3V, and the fourth voltage is 1.5V.

[0103] In other words, taking memory cell A as an example, when programming memory cell A, the control voltage of programming line WL1' can be 3V, and the control voltage of other programming lines WL2' can also be 3V; when restoring memory cell A, the control voltage of programming line WL1' can be 1.5V, and the control voltage of other programming lines WL2' remains 3V. Thus, compared to the OTP fuse circuit in related technologies, the MTP fuse circuit of this embodiment adds a control terminal to the programming line WL', which can realize the recovery of HEIP caused by the PMOS transistor under negative voltage stress, thereby enabling multiple reprogramming cycles.

[0104] Furthermore, in some embodiments, when a word line is selected, the word line voltage is controlled to a fifth voltage by the second power supply module 204; or,

[0105] When a word line is not selected, the word line voltage is controlled to the sixth voltage by the second power supply module 204.

[0106] In this embodiment of the disclosure, the fifth voltage is lower than the sixth voltage.

[0107] It should be noted that the programmable memory array 20 includes multiple memory cells, and the number of word lines is at least one. For example, as shown... Figure 4 As shown, taking memory cell A as an example, when word line WL1 is open, that is, when word line WL1 is selected, the word line voltage of word line WL1 can be controlled to the fifth voltage by the second power module 204, and the word line voltage of other unselected word lines WL2 can be controlled to the sixth voltage; when all word lines are not selected, the word line voltage of all word lines (e.g., WL1 and WL2) can be controlled to the sixth voltage by the second power module 204.

[0108] Furthermore, in some embodiments, when a word line is selected, if the fifth voltage is lower than the power supply voltage of the first preset power supply, then the second transistor is determined to be in the on state; or,

[0109] If the word line is not selected, and the sixth voltage is greater than or equal to the power supply voltage of the first preset power supply, then the second transistor is determined to be in the off state.

[0110] It should also be noted that, in the programmable memory array 20, taking word line WL1 as an example, if word line WL1 is selected, that is, when word line WL1 is turned on, the word line voltage of WL1 is lower than the power supply voltage of the first preset power supply VDD1, and the second transistor P2 in the memory cell corresponding to word line WL1 is in the on state; otherwise, if word line WL1 is not selected, that is, when word line WL1 is turned off, the word line voltage of WL1 is greater than or equal to the power supply voltage of the first preset power supply VDD1, and the second transistor P2 in the memory cell corresponding to word line WL1 is in the off state.

[0111] In some embodiments, the fifth voltage is 0V and the sixth voltage is 3V.

[0112] In other words, taking memory cell A as an example, when memory cell A is programmed, word line WL1, where memory cell A is located, is turned on, meaning the word line voltage of WL1 is 0V, controlling all second transistors P2 in all memory cells on WL1 to be in the conducting state. When memory cell A is restored, word line WL1 remains turned on, meaning the word line voltage of WL1 remains 0V, controlling all second transistors P2 in all memory cells on WL1 to be in the conducting state. For non-target memory cells, memory cell B is a non-target memory cell. Whether memory cell B is programmed or restored, word line WL2, where memory cell B is located, is turned off, meaning the word line voltage of WL2 is 3V, controlling all second transistors P2 in all memory cells on WL2 to be in the off state.

[0113] In summary, this disclosure proposes an MTP fuse circuit design based on the PMOSFET HEIP recovery mechanism, thereby realizing a novel fuse programming architecture. In this architecture, two PMOSFETs connected in series form a fuse path. Its operation consists of two parts: the first part is programming. Based on actual device testing, under voltage stress conditions of bit line BL1 = -0.7V and programming line WL1' = 3V, the first transistor P1 undergoes HEIP degradation, leading to an increase in the channel leakage current of the first transistor P1, thus achieving a transition from "0" to "1". The second part is recovery. Based on actual device testing, under voltage stress conditions of bit line BL1 = 3V and programming line WL1' = 1.5V, the first transistor P1 undergoes HEIP recovery, leading to a decrease in the channel leakage current of the first transistor P1, thus achieving a transition from "1" to "0". Therefore, this MTP fuse circuit design differs from the gate oxide fuse programming mechanism in related technologies and can support multiple reprogramming cycles. In addition, because this MTP fuse circuit does not require gate oxide layer breakdown, it also avoids excessive voltage stress and prevents overshoot damage to the memory cell from high voltage.

[0114] See Figure 5 This illustrates a schematic diagram of the relationship between gate voltage and channel leakage current provided in an embodiment of this disclosure. Figure 5 As shown, the gate voltage can be represented by Vg, with the unit being volts (V); the AC leakage current can be represented by Id, with the unit being amperes (A). Figure 5 In this example, assuming the drain voltage Vd is equal to the source voltage Vs (i.e., Vd = Vs = 3V) and the substrate voltage Vb = 0V, the curves showing the change between the initial current (Id_Fresh) and Vg can be represented by solid lines, the curves showing the change between the recovery current (Id_recover) and Vg can be represented by dashed lines, and the curves showing the change between the decay current (Id_afterstress) and Vg can be represented by dotted lines. For example, the magnitudes of the source-drain current (Ids) and the turn-off current (Ioff) in these three cases are shown in Table 1.

[0115] Table 1

[0116] Fresh -7.96E-05 -5.81E-12 After stress -9.23E-05 -1.09E-08 After recover -7.80E-05 -1.72E-11

[0117] In other words, based on the OTP fuse circuit with PMOSFET HEIP degradation mechanism, the recovery characteristics of PMOSFET HEIP under negative voltage stress (or "reverse voltage stress") can be utilized to realize the design of MTP fuse circuit based on the PMOSFET HEIP recovery mechanism. Specifically, this disclosure provides an MTP fuse memory cell circuit array design based on the PMOSFET HEIP recovery mechanism. Compared with the OTP fuse circuit, this MTP fuse circuit adds a programming line WL' control terminal, whose function is to realize the recovery of HEIP caused by the PMOSFET being subjected to reverse voltage stress, thereby enabling multiple reprogramming.

[0118] In one specific embodiment, with Figure 2 For example, when programming memory cell A, bit line BL1 = -0.7V, BL2 = 3V; programming line WL1' = 3V, WL2' = 3V; word line WL1 = 0V, WL2 = 3V; first preset power supply VDD1 = 3V; when restoring memory cell A, bit line BL1 = 3V, BL2 = 3V; programming line WL1' = 1.5V, WL2' = 3V; word line WL1 = 0V, WL2 = 3V; first preset power supply VDD1 = 3V.

[0119] This disclosure provides a programmable memory array comprising multiple memory cells, each including a first transistor and a second transistor connected in series. During programming, the voltage difference between the gate and first terminal of the first transistor is positive, increasing the channel leakage current and enabling the stored data to be converted to 1. During recovery, the voltage difference between the gate and first terminal of the first transistor is negative, decreasing the channel leakage current and enabling the stored data to be converted to 0. This allows for repeated programming of the memory cell, and because it avoids gate oxide breakdown, it prevents excessive voltage stress, mitigating overshoot damage and ultimately improving memory performance.

[0120] In another embodiment of this disclosure, see Figure 6 This illustrates a schematic diagram of the composition structure of another programmable memory array provided in an embodiment of this disclosure. Figure 6 As shown, in Figure 3 Based on the programmable memory array 20 shown, the programmable memory array 20 may further include a readout circuit 205, wherein bit lines are connected to the readout circuit 205 via different fifth transistors (e.g., N21 and N22), wherein:

[0121] The first terminal of the fifth transistor is connected to the bit line, the second terminal of the fifth transistor is connected to the readout circuit 205, the gate terminal of the fifth transistor receives the column selection signal, and the fifth transistor transmits the signal of the corresponding bit line to the readout circuit 205 according to the column selection signal.

[0122] It should be noted that in this embodiment, the number of bit lines is at least one, and correspondingly, the number of fifth transistors is at least one, that is, fifth transistors are distributed in the extension direction of each bit line; and the second terminals of these at least one fifth transistors are all connected to the readout circuit 205 so as to transmit the signal of the corresponding bit line to the readout circuit 205 according to the column select signal. For example, as... Figure 6 As shown, a fifth transistor N21 is distributed on bit line BL1. The first terminal of the fifth transistor N21 is connected to bit line BL1, and the second terminal of the fifth transistor N21 is connected to the readout circuit 205. The gate terminal of the fifth transistor N21 is used to receive the column selection signal Y0. A fifth transistor N22 is distributed on bit line BL2. The first terminal of the fifth transistor N22 is connected to bit line BL2, and the second terminal of the fifth transistor N22 is connected to the readout circuit 205. The gate terminal of the fifth transistor N22 is used to receive the column selection signal Y1. Here, if the column selection signal Y0 is set to a high level, that is, the fifth transistor N21 is turned on, then the signal of bit line BL1 will be transmitted to the readout circuit 205; if the column selection signal Y1 is set to a high level, that is, the fifth transistor N22 is turned on, then the signal of bit line BL2 will be transmitted to the readout circuit 205. In addition, it should be noted that when reading data, only one of the column selection signals is set to a high level, and no voltage is applied to bit lines BL1 and BL2 during reading.

[0123] Furthermore, for the readout circuit 205, in some embodiments, such as Figure 6 As shown, the readout circuit 205 may include a readout resistor R1 and a comparator U1, wherein:

[0124] The first input terminal of comparator U1 and the first terminal of read resistor R1 are both connected to the second terminal of the fifth transistor (e.g., N21 and N22). The second terminal of read resistor R1 is grounded. The second input terminal of comparator U1 is used to receive a reference voltage. The output terminal (OUT) of comparator U1 is used to read the data stored in the target memory cell, wherein the target memory cell is determined by the column select signal and the word line.

[0125] In this embodiment, the reference voltage can be represented by Vref, and the ground can be represented by VSS. Specifically, taking memory cell A as the target memory cell, the bit line voltage of BL2 is equal to 3V to prevent non-target cells from being programmed, that is, the first transistor P1 in memory cells C, D, and B will not be attenuated, and then the reading is performed through the bit line BL1. Here, BL1 is grounded through a read resistor R1, and the external supply of bit line voltage to BL1 is no longer provided (i.e., no longer -0.7V and 3V), and the potential at other locations remains unchanged. At this time, the first transistor P1 in memory cell A is at a large current, so the potential at the connection point of read resistor R1 and bit line BL1 is a high potential. At this time, "1" can be read through the output terminal (OUT) of comparator U1.

[0126] Understandably, in this embodiment of the disclosure, the programmable memory array 20 may include a readout circuit and a precharge module. The bit line voltage, whether 3V or -0.7V, is implemented through the precharge module. On one hand, when programming a target memory cell, the bit line containing the target memory cell can be precharged to -0.7V; on the other hand, for non-target memory cells, to prevent programming, the bit line containing the non-target memory cell can be precharged to 3V. In the same precharge module, one of the third and fourth transistors is selectively turned on, either precharging the bit line to -0.7V or precharging it to 3V.

[0127] by Figure 6 For example, when programming a target memory cell (such as memory cell A), the programming line WL1' is set to a high potential (3V), the bit line BL1 is pulled down to a low potential (-0.7V), the word line WL1 and the second precharge signal CSL2 are set to a low potential (0V), and the word line WL2 is set to a high potential (3V). To protect non-target memory cells (such as memory cell C), the bit line BL2 needs to be set to a preset voltage through the precharge module, for example, by turning on the third transistor to precharge the bit line voltage of BL2 to 3V. When the word line WL1 is turned on, the voltage difference between the gate and drain terminals of the first transistor P1 in memory cell C is small, thereby protecting memory cell C.

[0128] Additionally, when reading data, no voltage is applied to the bit lines. In this case, the target memory cell can be determined by the column select signal and the word line. For example, the target memory cell can be determined as memory cell A based on the column select signal Y0 being high and the word line WL1 being low. Then, the programming line WL1' still provides 3V. At this time, the leakage current of the first transistor P1 in memory cell A is used to determine whether the data finally read is "1" or "0".

[0129] This disclosure provides a programmable memory array that employs two thick-gate oxide PMOS transistors connected in series to form an MTP fuse cell circuit structure. By utilizing the HEIP decay characteristics of the PMOS transistors under forward voltage, the off-state leakage current of the PMOS transistors can be increased, thereby achieving the transition from "0" to "1". Conversely, by utilizing the HEIP recovery characteristics of the PMOS transistors under reverse voltage, the off-state leakage current of the PMOS transistors can be reduced, thereby achieving the transition from "1" to "0". Thus, by utilizing the HEIP decay and recovery characteristics of the PMOS transistors under forward and reverse voltages for MTP programming, overshoot damage to the memory cells caused by excessively high voltages can be avoided. Furthermore, this programmable memory array also exhibits good thermal stability, ultimately improving memory performance.

[0130] In yet another embodiment of this disclosure, see [link to relevant documentation]. Figure 7 This illustrates a flowchart of a programming method provided in an embodiment of this disclosure. Figure 7 As shown, the method may include:

[0131] S701: When programming the memory cell, control the second transistor to be in the on state and control the voltage difference between the gate terminal of the first transistor and the first terminal of the first transistor to be greater than 0.

[0132] S702: When restoring the memory cell, control the second transistor to be in the on state, and control the voltage difference between the gate of the first transistor and the first terminal of the first transistor to be less than 0.

[0133] It should be noted that, in this embodiment of the disclosure, the programming method is applied to a programmable memory array including multiple memory cells. Each memory cell may include a first transistor and a second transistor, wherein a first terminal of the first transistor is connected to a bit line, a gate terminal of the first transistor is connected to a programming line, a second terminal of the first transistor is connected to the first terminal of the second transistor, a gate terminal of the second transistor is connected to a word line, and a second terminal of the second transistor is connected to a first preset power supply.

[0134] It should also be noted that, in this embodiment of the present disclosure, the multiple memory cells can be arranged in an array. Specifically, a plurality of memory cells are distributed along the extension direction of the bit lines, and each of the memory cells is connected to the bit lines via the first terminal of the first transistor P1; a plurality of memory cells are distributed along the extension direction of the word lines, and each of the memory cells is connected to the word lines via the gate terminal of the second transistor P2; and a plurality of memory cells are distributed along the extension direction of the programming lines, and each of the memory cells is connected to the programming lines via the gate terminal of the first transistor P1.

[0135] In some embodiments, the method may further include:

[0136] When programming the memory cell, the control voltage of the control programming line is higher than the bit line voltage of the bit line, so that the voltage difference between the gate terminal of the first transistor and the first terminal of the first transistor is greater than 0.

[0137] When restoring a memory cell, the control voltage of the control programming line is lower than the bit line voltage of the bit line, so that the voltage difference between the gate terminal of the first transistor and the first terminal of the first transistor is less than 0.

[0138] It should be noted that, in this embodiment of the present disclosure, when programming the memory cell, the control voltage of the programming line is higher than the bit line voltage, so that the voltage difference between the gate terminal and the first terminal of the first transistor P1 is greater than 0. Thus, since the voltage difference between the gate terminal and the first terminal of the first transistor P1 is a positive voltage difference, the first transistor P1 experiences HEIP degradation characteristics under positive voltage stress, resulting in an increase in the channel leakage current of the first transistor P1, thereby enabling the data stored in the memory cell to transition from "0" to "1".

[0139] It should be noted that, in this embodiment of the present disclosure, when restoring the memory cell, the control voltage of the control programming line is lower than the bit line voltage, so that the voltage difference between the gate terminal and the first terminal of the first transistor is less than 0. Thus, since the voltage difference between the gate terminal and the first terminal of the first transistor P1 is a negative voltage difference, the first transistor P1 undergoes HEIP recovery characteristics under negative voltage stress, resulting in a reduction in the channel leakage current of the first transistor P1, thereby enabling the data stored in the memory cell to transition from "1" to "0".

[0140] This disclosure provides a programming method applied to the programmable memory array described in any of the foregoing embodiments. Thus, in this programmable memory array, the memory cell can be repeatedly programmed multiple times, and since there is no need to break down the gate oxide layer, excessive voltage stress is avoided, thus mitigating overshoot damage to the memory cell caused by high voltage and ultimately improving memory performance.

[0141] In another embodiment of this disclosure, see [reference needed]. Figure 8 This illustration shows a schematic diagram of the structural composition of a semiconductor memory provided in an embodiment of this disclosure. Figure 8 As shown, the semiconductor memory 80 includes at least one of the programmable memory arrays 20 described in any of the foregoing embodiments.

[0142] In some embodiments, the semiconductor memory 80 may include dynamic random access memory (DRAM). The DRAM may conform to memory specifications such as DDR, DDR2, DDR3, DDR4, and DDR5, as well as LPDDR, LPDDR2, LPDDR3, LPDDR4, and LPDDR5; no specific limitation is made here.

[0143] In this embodiment, the semiconductor memory 80 mainly involves the circuit design of the fuse memory cell. A new fuse programming principle is adopted to realize a completely new fuse programming architecture. Thus, the programmable memory array 20 includes multiple memory cells. For each memory cell, two series-connected PMOS transistors form a fuse path. Based on the HEIP decay and recovery characteristics of PMOS transistors, this not only supports multiple reprogramming cycles, but also avoids excessive voltage stress because the circuit does not require gate oxide breakdown, preventing overshoot damage to the memory cell from high voltage, thereby improving memory performance.

[0144] The above are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure.

[0145] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0146] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0147] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0148] The features disclosed in the several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

[0149] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0150] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A programmable memory array, characterized in that, include: Multiple storage cells, each storage cell including a first transistor and a second transistor connected in series; The first terminal of the first transistor is connected to the bit line, the gate terminal of the first transistor is connected to the programming line, and the second terminal of the first transistor is connected to the first terminal of the second transistor. The gate of the second transistor is connected to the word line, and the second terminal of the second transistor is connected to the first preset power supply. Specifically, when programming the memory cell, the second transistor is controlled to be in the on state, and the voltage difference between the gate terminal of the first transistor and the first terminal of the first transistor is controlled to be greater than 0. When restoring the memory cell, the second transistor is controlled to be in the on state, and the voltage difference between the gate of the first transistor and the first terminal of the first transistor is controlled to be less than 0. The plurality of storage cells are arranged in an array, wherein: A plurality of memory cells are distributed along the extension direction of the bit line, and each of the plurality of memory cells is connected to the bit line through the first terminal of the first transistor. A plurality of memory cells are distributed along the extension direction of the word line, and each of the memory cells is connected to the word line through the gate terminal of the second transistor. A plurality of memory cells are distributed along the extension direction of the programming line, and each of the memory cells is connected to the programming line through the gate terminal of the first transistor. Wherein, the extension direction of the bit line and the extension direction of the word line are perpendicular to each other, and the extension direction of the programming line is parallel to the extension direction of the word line; The programmable memory array further includes a first power module and a second power module, wherein the first power module is connected to the programming line and the second power module is connected to the word line, wherein: The first power module is used to provide control voltage to the programming line; The second power module is used to provide word line voltage to the word line; When programming the memory cell, the control voltage of all the programming lines is controlled to be a third voltage by the first power module; When restoring the storage unit, the first power module controls the control voltage of the programming line where the storage unit is located to the fourth voltage, and controls the control voltage of other programming lines to the third voltage. Wherein, the third voltage is higher than the fourth voltage; The third voltage ranges from 2.5 to 3V, and the fourth voltage ranges from 0 to 1.5V.

2. The programmable memory array according to claim 1, characterized in that, Pre-charge modules are also distributed along the extension direction of the bit line, wherein: The pre-charge module is used to receive a pre-charge signal and pre-charge the bit line according to the pre-charge signal, so that the bit line voltage of the bit line is pre-charged to a preset voltage.

3. The programmable memory array according to claim 2, characterized in that, The precharge module includes a third transistor and a fourth transistor, wherein: The first terminal of the fourth transistor is connected to the first voltage, the second terminal of the fourth transistor is connected to the bit line, and the gate terminal of the fourth transistor is used to receive the first precharge signal. When programming the memory cell, the first precharge signal turns on the fourth transistor, so that the bit line where the memory cell is located is precharged to the first voltage. The first terminal of the third transistor is connected to the second voltage, the second terminal of the third transistor is connected to the bit line, and the gate terminal of the third transistor is used to receive the second precharge signal. When the memory cell is restored, the second precharge signal turns on the third transistor, so that the bit line where the memory cell is located is precharged to the second voltage. Wherein, the first voltage is lower than the second voltage.

4. The programmable memory array according to claim 3, characterized in that, The first voltage ranges from -0.7 to 0V, and the second voltage ranges from 2.5 to 3V.

5. The programmable memory array according to claim 4, characterized in that, The first voltage is -0.7V, and the second voltage is 3V.

6. The programmable memory array according to claim 1, characterized in that, The third voltage is 3V, and the fourth voltage is 1.5V.

7. The programmable memory array according to claim 6, characterized in that, When the word line is selected, the second power module controls the word line voltage to the fifth voltage; or... When the word line is not selected, the word line voltage is controlled to the sixth voltage by the second power module; The fifth voltage is lower than the sixth voltage.

8. The programmable memory array according to claim 7, characterized in that, When the word line is selected, if the fifth voltage is lower than the power supply voltage of the first preset power supply, then it is determined that the second transistor is in the on state; or, If the sixth voltage is greater than or equal to the power supply voltage of the first preset power supply when the word line is not selected, then the second transistor is determined to be in the off state.

9. The programmable memory array according to claim 8, characterized in that, The fifth voltage is 0V, and the sixth voltage is 3V.

10. The programmable memory array according to claim 1, characterized in that, The programmable memory array further includes a readout circuit, wherein the bit lines are connected to the readout circuit via different fifth transistors, wherein: The first terminal of the fifth transistor is connected to the bit line, the second terminal of the fifth transistor is connected to the readout circuit, the gate terminal of the fifth transistor receives the column selection signal, and the fifth transistor transmits the signal corresponding to the bit line to the readout circuit according to the column selection signal.

11. The programmable memory array according to claim 10, characterized in that, The readout circuit includes a readout resistor and a comparator, wherein: The first input terminal of the comparator and the first terminal of the read resistor are both connected to the second terminal of the fifth transistor. The second terminal of the read resistor is grounded. The second input terminal of the comparator is used to receive a reference voltage. The output terminal of the comparator is used to read the data stored in the target memory cell. The target memory cell is determined by the column select signal and the word line.

12. The programmable memory array according to any one of claims 1 to 11, characterized in that, The first transistor is a PMOS transistor, and the second transistor is a PMOS transistor.

13. A programming method, characterized in that, The method is applied to a programmable memory array comprising multiple memory cells, wherein each memory cell includes a first transistor and a second transistor, and a first terminal of the first transistor is connected to a bit line, a gate terminal of the first transistor is connected to a programming line, a second terminal of the first transistor is connected to the first terminal of the second transistor, a gate terminal of the second transistor is connected to a word line, and a second terminal of the second transistor is connected to a first preset power supply; the method includes: When programming the memory cell, the second transistor is controlled to be in the on state, and the voltage difference between the gate terminal of the first transistor and the first terminal of the first transistor is controlled to be greater than 0. When restoring the memory cell, the second transistor is controlled to be in the on state, and the voltage difference between the gate of the first transistor and the first terminal of the first transistor is controlled to be less than 0. The plurality of storage cells are arranged in an array, wherein: A plurality of memory cells are distributed along the extension direction of the bit line, and each of the plurality of memory cells is connected to the bit line through the first terminal of the first transistor. A plurality of memory cells are distributed along the extension direction of the word line, and each of the memory cells is connected to the word line through the gate terminal of the second transistor. A plurality of memory cells are distributed along the extension direction of the programming line, and each of the memory cells is connected to the programming line through the gate terminal of the first transistor. Wherein, the extension direction of the bit line and the extension direction of the word line are perpendicular to each other, and the extension direction of the programming line is parallel to the extension direction of the word line; The programmable memory array further includes a first power module and a second power module, wherein the first power module is connected to the programming line and the second power module is connected to the word line, wherein: The first power module is used to provide control voltage to the programming line; The second power module is used to provide word line voltage to the word line; When programming the memory cell, the control voltage of all the programming lines is controlled to be a third voltage by the first power module; When restoring the storage unit, the first power module controls the control voltage of the programming line where the storage unit is located to the fourth voltage, and controls the control voltage of other programming lines to the third voltage. Wherein, the third voltage is higher than the fourth voltage; The third voltage ranges from 2.5 to 3V, and the fourth voltage ranges from 0 to 1.5V.

14. The method according to claim 13, characterized in that, The method further includes: When programming the memory cell, the control voltage of the programming line is controlled to be higher than the bit line voltage of the bit line, so that the voltage difference between the gate terminal of the first transistor and the first terminal of the first transistor is greater than 0. When restoring the memory cell, the control voltage of the programming line is controlled to be lower than the bit line voltage of the bit line, so that the voltage difference between the gate terminal of the first transistor and the first terminal of the first transistor is less than 0.

15. A semiconductor memory, characterized in that, The semiconductor memory includes a programmable memory array as described in any one of claims 1 to 12.

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