Memory built-in self-test method and apparatus therefor

Abstract

Embodiments of the present disclosure provide a memory built-in self-test method and apparatus thereof. The test method comprises: dividing row addresses of a memory under test into a plurality of row address sets, and dividing each of the row address sets into a plurality of row address subsets; performing, in parallel, writing of first test data for the plurality of row address sets, wherein for each of the row address sets, the writing of the first test data comprises: sequentially writing the first test data into a memory cell corresponding to each of the row address subsets; after writing the first test data into each of the row address subsets, performing a first refresh operation on the memory under test; after waiting for a preset time period, sequentially reading first output data from the memory cell corresponding to each of the row address sets; and obtaining a first test result of the memory under test according to the first test data and the first output data.

Images