Channel etching method of F-FET device and preparation method of F-FET device

Abstract

The application provides a channel etching method of an F-FET device, comprising: forming a plurality of stack structures on a substrate, and isolating the stack structures through an isolation structure; the isolation structure comprises an isolation groove and an isolation protective layer filled in the isolation groove; each stack structure comprises a first semiconductor layer and a second semiconductor layer stacked in a direction away from the substrate; taking the isolation protective layer as a mask, etching the second semiconductor in the first stack structure to form a first etching cavity and only reserve the first semiconductor layer; forming a first patterned mask layer; taking the first patterned mask layer as a mask, etching the exposed second stack structure until a surface layer of the substrate to form a slot in the second stack structure; taking the remaining first patterned mask layer as a mask, selectively etching the first semiconductor layer on both sides of the slot to form a second etching cavity, only reserving the remaining second semiconductor layer, and forming a first semiconductor channel structure on both sides of the first isolation structure in a first direction.

Description

Technical Field

[0001] This invention relates to the field of semiconductor devices, and more particularly to a channel etching method for F-FET devices and a method for fabricating F-FET devices. Background Technology

[0002] As the critical dimensions of semiconductor devices continue to shrink and device density continues to increase, the spacing between n-type field-effect transistors (nFETs) and p-type field-effect transistors (pFETs) within a standard cell will need to be even smaller. However, for FinFETs and Gate all-around transistors (GAA), the corresponding process technology limits the spacing between their nFET and pFET devices.

[0003] In this context, the forksheet-FET (F-FET) emerged, considered one of the most promising device structures following the advanced nanosheet-type FET. The forksheet can be understood as a natural extension of the GAA nanosheet device, offering additional scaling and performance beyond the 2nm technology node. In the F-FET device, the nFET and pFET are fabricated on the same substrate structure and isolated by isolation walls, resulting in a closer nFET-to-pFET spacing and further enhancing circuit compactness.

[0004] However, in F-FETs, since the channels of all pFET and nFET devices are connected to the isolation wall, the gate cannot completely wrap around the channels of all pFET and nFET devices, which may result in its electrostatic characteristics being worse than those of vertically stacked GAA nanosheet FETs.

[0005] The industry has proposed fabricating fully enclosed channel gate structures in pFET and nFET devices of the field-effect FET (F-FET) to eliminate the drawbacks of F-FET structures. However, fabricating a fully enclosed channel gate structure in a hybrid channel device requires the formation of a four-sided open channel nanolayer. Currently, there is no satisfactory solution in the field for forming a four-sided open channel nanolayer in a hybrid channel device.

[0006] Therefore, how to achieve a hollowed-out nanolayer for hybrid channels has become a key technical issue that needs to be addressed by those skilled in the art. Summary of the Invention

[0007] This invention provides a channel etching method and a fabrication method for F-FET devices to solve the problem of how to form a four-sided hollow structure in a hybrid channel.

[0008] According to a first aspect of the present invention, a method for etching the channel of an F-FET device is provided, comprising:

[0009] Provide a substrate;

[0010] A first semiconductor structure is formed on the substrate; the first semiconductor structure includes a plurality of stacked structures formed on the substrate, each stacked structure including a first semiconductor layer and a second semiconductor layer alternately stacked in a direction away from the substrate; wherein the plurality of stacked structures are arranged sequentially along a first direction of the substrate, and adjacent stacked structures are isolated by an isolation structure; the isolation structure includes an isolation trench and an isolation protective layer filled in the isolation trench, and the height of the isolation protective layer is not less than the height of the isolation trench; along the first direction, the plurality of stacked structures are sequentially divided into a first stacked structure, a second stacked structure, and other stacked structures; wherein the first sidewall of the first stacked structure is exposed, and its second sidewall is protected by the isolation protective layer; wherein the isolation structure used to isolate the first stacked structure and the second stacked structure is referred to as the first isolation structure;

[0011] Using several isolation and protective layers as masks, the second semiconductor layer or the first semiconductor layer in the first stacked structure is selectively etched to form a first etch cavity, and only the first semiconductor layer or the second semiconductor layer is retained;

[0012] A first patterned mask layer is formed; the first patterned mask layer fills the first etched cavity, wraps the first sidewall of the first stacked structure, and covers the surfaces of the plurality of stacked structures and the plurality of isolation protective layers; only the top of a portion of the second stacked structure is exposed;

[0013] Using the first patterned mask layer as a mask, the exposed second stacked structure is etched down to the surface of the substrate to form a trench in the second stacked structure, the trench dividing the second stacked structure into a first part and a second part along the first direction;

[0014] Using the remaining first patterned mask layer as a mask, the first semiconductor layer or the second semiconductor layer on both sides of the slot is selectively etched to form a second etch cavity, and only the remaining second semiconductor layer or the first semiconductor layer is retained to form a first semiconductor channel structure and a second semiconductor channel structure on both sides of the first isolation structure along the first direction, respectively.

[0015] Optionally, a first semiconductor structure is formed on the substrate, specifically including:

[0016] The plurality of stacked structures are formed on the substrate; wherein the plurality of stacked structures are arranged sequentially along the first direction of the substrate, and the isolation groove is formed between adjacent stacked structures;

[0017] The isolation groove is filled with protective material, and the protective material is deposited on the surface of the plurality of stacked structures;

[0018] The protective material on the surface of the plurality of stacked structures is etched away, along with the protective material covering the first sidewall of the first stacked structure, to expose the first sidewall of the first stacked structure, thereby forming the isolation protective layer in the isolation groove.

[0019] Optionally, forming several of the aforementioned isolation and protective layers specifically includes:

[0020] A first protective material is deposited on the surface and sidewalls of the plurality of stacked structures;

[0021] A second protective material is formed on the surface of the first protective material and fills the plurality of said isolation grooves;

[0022] The first protective material and the second protective material on the surfaces of the plurality of stacked structures and the first sidewall of the first stacked structure are etched away to form the isolation protective layer in the isolation groove.

[0023] Optionally, forming the first patterned mask layer specifically includes:

[0024] In the first etched cavity, the first sidewall of the first stacked structure, and the surface of the plurality of stacked structures and the isolation protective layer, a first mask layer is deposited;

[0025] A patterned photoresist is formed on the surface of the first mask layer; the patterned photoresist covers the surface of the first mask layer and exposes only a portion of the first mask layer at the top of the second stacked structure;

[0026] Using the patterned photoresist as a mask, the first mask layer is etched up to the surface of the second stacked structure to form the first patterned mask layer.

[0027] Optionally, the first semiconductor layer is an N-type semiconductor layer and the second semiconductor layer is a P-type semiconductor layer.

[0028] Optionally, the first semiconductor layer is silicon; the second semiconductor layer is germanium-silicon.

[0029] Optionally, the second protective material is silicon nitride, and the first protective material is silicon oxide.

[0030] According to a second aspect of the present invention, a method for fabricating an F-FET device is provided, comprising the channel etching method for the F-FET device as described in any one of the first aspects of the present invention.

[0031] According to a third aspect of the present invention, an F-FET device is provided, which is fabricated using the F-FET device fabrication method described in the second aspect of the present invention.

[0032] According to a fourth aspect of the present invention, a method for fabricating an electronic device is provided, comprising the method for fabricating an F-FET device as described in the second aspect of the present invention.

[0033] According to a fifth aspect of the present invention, an electronic device is provided, comprising the F-FET device described in the third aspect of the present invention.

[0034] The F-FET device channel etching method provided by the present invention involves forming a plurality of stacked structures and an isolation protective layer on a substrate, using the isolation protective layer between the plurality of stacked structures as a mask, etching the edge to expose the sidewalls of a first stacked structure, thereby releasing a first semiconductor layer or a second semiconductor layer to form a first semiconductor channel structure; further forming a first patterned mask layer, using the first patterned mask layer as a mask to etch a second stacked structure to form a trench in the second stacked structure to divide the second stacked component into a first part and a second part; thereby selectively etching the second semiconductor layer or the first semiconductor layer on both sides of the trench to form a second semiconductor channel structure; wherein the first semiconductor channel structure and the second semiconductor channel structure form a set of hybrid channel structures. As can be seen, the technical solution provided by this invention ingeniously designs an etching method for the channel in a hybrid channel device, forming a channel structure with four sides open in the hybrid channel device, solving the problem of difficulty in forming a channel structure with four sides open in the prior art; and, since a channel structure with four sides open is formed in the channel device, the gate material layer formed subsequently can completely surround the channel structure, making it possible to form a gate structure that completely surrounds the channel in the F-FET device, thus significantly improving the performance of the F-FET device. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1This is a schematic flowchart of a channel etching method for an F-FET device according to an embodiment of the present invention;

[0037] Figure 2 This is a schematic diagram of the device structure at different process stages fabricated according to the channel etching method of the F-FET device provided in an embodiment of the present invention. Figure 1 ;

[0038] Figure 3 This is a schematic diagram of the device structure at different process stages fabricated according to the channel etching method of the F-FET device provided in an embodiment of the present invention. Figure 2 ;

[0039] Figure 4 This is a schematic diagram of the device structure at different process stages fabricated according to the channel etching method of the F-FET device provided in an embodiment of the present invention. Figure 3 ;

[0040] Figure 5 This is a schematic diagram of the device structure at different process stages fabricated according to the channel etching method of the F-FET device provided in an embodiment of the present invention. Figure 4 ;

[0041] Figure 6 This is a schematic diagram of the device structure at different process stages fabricated according to the channel etching method of the F-FET device provided in an embodiment of the present invention. Figure 5 ;

[0042] Figure 7 This is a schematic diagram of the device structure at different process stages fabricated according to the channel etching method of the F-FET device provided in an embodiment of the present invention. Figure 6 ;

[0043] Figure 8 This is a schematic diagram of the device structure at different process stages fabricated according to the channel etching method of the F-FET device provided in an embodiment of the present invention. Figure 7 ;

[0044] Figure 9 This is a schematic diagram of the device structure at different process stages fabricated according to the channel etching method of the F-FET device provided in an embodiment of the present invention. Figure 8 ;

[0045] Figure 10 This is a schematic diagram of the device structure at different process stages fabricated according to the channel etching method of the F-FET device provided in an embodiment of the present invention. Figure 9 ;

[0046] Figure 11 This is a schematic diagram of the device structure at different process stages fabricated according to the channel etching method of the F-FET device provided in an embodiment of the present invention. Figure 10 ;

[0047] Figure 12 This is a schematic diagram of the device structure at different process stages fabricated according to the channel etching method of the F-FET device provided in an embodiment of the present invention. Figure 10 one;

[0048] Figure 13 This is a schematic diagram of the device structure at different process stages fabricated according to the channel etching method of the F-FET device provided in an embodiment of the present invention. Figure 10 two;

[0049] Figure 14 This is a schematic diagram of the device structure at different process stages fabricated according to the channel etching method of the F-FET device provided in an embodiment of the present invention. Figure 10 three;

[0050] Explanation of reference numerals in the attached figures:

[0051] 101-Substrate;

[0052] 102 - First semiconductor layer;

[0053] 1021 - First semiconductor material layer;

[0054] 103 - Second semiconductor layer;

[0055] 1031 - Second semiconductor material layer;

[0056] 104 - Patterned photolithography layer;

[0057] 1041 - Graphical anti-reflective layer;

[0058] 1042 - Patterned photoresist layer;

[0059] 105 - Isolation groove;

[0060] 106 - First protective material;

[0061] 107 - Second protective material;

[0062] 108 - First etched cavity;

[0063] 109 - First mask layer;

[0064] 110 - Patterned photoresist;

[0065] 111 - A graphical anti-reflective material layer;

[0066] 112 - First patterned mask layer;

[0067] 113 - Second etched cavity;

[0068] 114 - First stacked structure;

[0069] 115 - Second stacked structure;

[0070] 116 - Second patterned mask layer;

[0071] 117 Third etched cavity;

[0072] 118 - First hybrid channel structure;

[0073] 119 - Second hybrid channel structure. Detailed Implementation

[0074] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0075] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0076] In existing F-FET devices, because the channels of all pFET and nFET devices are connected to the isolation wall, the gate cannot completely surround the channels of all pFET and nFET devices, resulting in potentially worse electrostatic characteristics than vertically stacked GAA nanosheet FETs. Currently, there is no feasible solution to fabricate a fully enclosed channel gate structure in F-FET pFET and nFET devices due to the performance limitations of hybrid channel structures. To improve device performance, it is necessary to etch a four-sided perforated channel nanolayer to fabricate a fully enclosed channel gate structure. However, during the fabrication of the perforated nanolayer of the hybrid channel, the etching of the hybrid channels can interfere with each other. This can lead to damage to the n-channel nanolayer during the etching of the p-channel nanolayer, or vice versa, making the etching of the hybrid channel difficult to achieve.

[0077] In view of this, the inventors of this application propose a channel etching method for F-FET devices to effectively form a four-sided hollowed-out hybrid channel structure in a hybrid channel device, so that the gate material layer formed subsequently can completely surround the channel structure, thereby making it possible to form a gate structure that completely surrounds the channel in an F-FET device, thus significantly improving the performance of the F-FET device.

[0078] It should be noted that the corresponding method of the present invention is not only applicable to F-FET devices, but also applicable to other devices with similar requirements to F-FET devices according to the corresponding needs.

[0079] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0080] Please refer to Figures 1-14 According to an embodiment of the present invention, a method for etching the channel of an F-FET device is provided, comprising:

[0081] S11: Provide a substrate 101;

[0082] S12: A first semiconductor structure is formed on the substrate 101; the first semiconductor structure includes a plurality of stacked structures formed on the substrate 101, each stacked structure including a first semiconductor layer 102 and a second semiconductor layer 103 alternately stacked in a direction away from the substrate 101; wherein the plurality of stacked structures are arranged sequentially along a first direction of the substrate 101, and adjacent stacked structures are isolated by an isolation structure; the isolation structure includes an isolation trench 105 and an isolation protective layer filled in the isolation trench 105, and the height of the isolation protective layer is not less than the height of the isolation trench 105; along the first direction, the plurality of stacked structures are sequentially divided into a first stacked structure 114, a second stacked structure 115 and other stacked structures; wherein the first sidewall of the first stacked structure 114 is exposed, and its second sidewall is protected by the isolation protective layer; wherein the isolation structure used to isolate the first stacked structure 114 and the second stacked structure 115 is referred to as the first isolation structure. In one embodiment, the first semiconductor layer 102 is an N-type semiconductor layer, and the second semiconductor layer 103 is a P-type semiconductor layer; in a specific example, the first semiconductor layer 102 is silicon; the second semiconductor layer 103 is germanium-silicon; and the first semiconductor layer 102 is an N-type semiconductor channel.

[0083] The first stacked structure 114 and the second stacked structure 115, as well as the first isolation groove 105 formed between them, are not substantially different from other stacked structures and isolation grooves 105. They are only named for convenience of description in this application. See the description of the specific process below.

[0084] In one embodiment, please refer to Figures 2-6 In step S12, a first semiconductor structure is formed on the substrate 101, which may include steps S121-S123, as follows:

[0085] S121: The plurality of stacked structures are formed on the substrate 101; wherein the plurality of stacked structures are arranged sequentially along the first direction of the substrate 101, and the isolation trench 105 is formed between adjacent stacked structures; wherein step S121 may further include, for example, the following S1211-S1213:

[0086] S1211: An alternately stacked first semiconductor material layer 1021 and second semiconductor material layer 1031 are epitaxially formed on the substrate 101; as shown in... Figure 2 As shown;

[0087] S1212: A patterned photolithography layer 104 is formed on the surface of the alternately stacked structure; the patterned photolithography layer 104 includes a patterned anti-reflective layer 1041 and a patterned photoresist layer 1042; such as Figure 3 As shown;

[0088] S1213: Using the patterned photolithography layer as a mask, etch the alternately stacked first semiconductor material layer 1021 and second semiconductor material layer 1031 until the surface of the substrate 101 or the surface of the substrate 101, to form a first semiconductor structure on the substrate 101.

[0089] S1214: Remove the patterned photolithography layer, such as Figure 4 As shown.

[0090] S122: Fill the isolation groove 105 with protective material and deposit the protective material on the surface of the plurality of stacked structures;

[0091] S123: Etch away the protective material on the surface of the plurality of stacked structures and the protective material covering the first sidewall of the first stacked structure 114 to expose the first sidewall of the first stacked structure 114 to form the isolation protective layer in the isolation groove 105.

[0092] In one embodiment, forming a plurality of the isolation and protective layers specifically includes:

[0093] A first protective material 106 is deposited on the surface and sidewalls of the plurality of stacked structures, such as Figure 5 As shown;

[0094] A second protective material 107 is formed; the second protective material 107 is formed on the surface of the first protective material 106 and fills the plurality of isolation grooves 105. In one embodiment, the second protective material 107 is silicon nitride, and the first protective material 106 is silicon oxide.

[0095] In this embodiment, a double-layer structure is formed by first depositing a first protective material 106 and then depositing a second protective material 107. The double-layer structure can avoid the problem of pinhole defects formed by direct atomic layer filling.

[0096] The first protective material 106 and the second protective material 107 on the surfaces of the plurality of stacked structures and the first sidewalls of the first stacked structure 114 are etched away to form the isolation protective layer in the isolation groove 105, such as Figure 6 As shown.

[0097] S13: Using the aforementioned isolation and protective layers as a mask, selectively etch the second semiconductor layer 103 or the first semiconductor layer 102 in the first stacked structure 114 to form a first etching cavity 108, retaining only the first semiconductor layer 102 or the second semiconductor layer 103; Figure 7 As shown; wherein, the isolation protective layer has a high etch selectivity relative to the first semiconductor layer 102, so as to etch away the first semiconductor layer 102 in the first stacked structure 114 while retaining the second semiconductor layer 103; or the isolation protective layer has a high etch selectivity relative to the second semiconductor layer 103, so as to etch away the second semiconductor layer 103 in the first stacked structure 114 to expose the first semiconductor layer 102;

[0098] Please continue to refer to the following: Figure 7 and combined Figure 6 Since the first sidewall of the first stacked structure 114 is exposed after the isolation protection layer is formed, and the other sidewall is protected by the isolation protection layer in the first isolation trench 105, the sidewall of the stacked structure on the substrate 101 opposite to the first stacked structure 114 is also exposed, and its other sidewall is protected by the isolation protection layer; therefore, when the first stacked structure 114 is selectively etched using the isolation protection layer as a mask, the second semiconductor layer 103 or the first semiconductor layer 102 in the stacked structure opposite to the first stacked structure 114 formed at the edge of the substrate 101 is also etched away, while the first semiconductor layer 102 or the second semiconductor layer 103 is retained.

[0099] S14: Form a first patterned mask layer 112; the first patterned mask layer fills the first etched cavity 108, wraps the first sidewall of the first stacked structure 114, and covers the surfaces of the plurality of stacked structures and the plurality of isolation protective layers; only the top of the second stacked structure 115 is exposed.

[0100] In one embodiment, please refer to Figure 8-10 Step S14, forming the first patterned mask layer 112, specifically includes steps S141-S143, as follows:

[0101] S141: A first mask layer 109 is deposited on the first etched cavity 108, the first sidewall of the first stacked structure 114, the surface of the plurality of stacked structures and the isolation protective layer.

[0102] S142: A patterned photoresist 110 is formed on the surface of the first mask layer 109; the patterned photoresist 110 covers the surface of the first mask layer 109, and only exposes a portion of the top of the first mask layer 109 of the second stacked structure 115; wherein, in a specific example, a patterned anti-reflective material layer 111 is also formed between the patterned photoresist 110 and the first mask layer 109; such as Figure 8 As shown;

[0103] S143: Using the patterned photoresist 110 as a mask, etch the first mask layer 109 up to the surface of the second stacked structure 115 to form the first patterned mask layer 112, such as... Figure 9 As shown.

[0104] In one embodiment, after the first patterned mask layer 112 is formed in S143, the patterned photoresist 110 is just removed.

[0105] In another embodiment, after the first patterned mask layer 112 is formed in S143, the patterned photoresist 110 is removed.

[0106] S15: Using the first patterned mask layer as a mask, etch the exposed second stacked structure 115 down to the surface of the substrate 101 to form trenches in the second stacked structure 115, the trenches dividing the second stacked structure 115 into a first part and a second part along the first direction; Figure 10 As shown; this step divides the second stacked structure 115 into a first part and a second part, exposing one side wall of the first part and one side wall of the second part; while the other side wall of the first part and the other side wall of the second part are protected by an isolation protective layer.

[0107] S16: Using the remaining first patterned mask layer 112 as a mask, selectively etch the first semiconductor layer 102 or the second semiconductor layer 103 on both sides of the trench to form a second etch cavity 113, and retain only the remaining second semiconductor layer 103 or the first semiconductor layer 102 to form a first semiconductor channel structure and a second semiconductor channel structure on both sides of the first isolation structure along the first direction, respectively. Figure 11 As shown.

[0108] When the first semiconductor layer 102 in the first stacked structure 114 is etched away in step S13, the second semiconductor layer 103 in the first portion and the second portion of the second stacked structure 115 is etched away in step S16, and vice versa. Thus, the remaining first semiconductor layer 102 in the first stacked structure 114 and the remaining second semiconductor layer 103 in the first portion of the second stacked structure 115 form a first semiconductor channel structure; or the remaining second semiconductor layer 103 in the first stacked structure 114 and the remaining first semiconductor layer 102 in the first portion of the second stacked structure 115 form a second semiconductor channel structure, thereby forming the first hybrid channel structure 118.

[0109] The number of the first stacking structure 114, the second stacking structure 115, and other stacking structures is not limited. In one embodiment, the number of the first stacking structure 114 and the second stacking structure 115 is one.

[0110] In another embodiment, the number of the first stacking structure 114, the second stacking structure 115, and other stacking structures can also be several. When the number of the first stacking structure 114, the second stacking structure 115, and other stacking structures is greater than 1, several of the first stacking structures 114 are arranged along a second direction, which is perpendicular to the first direction (the second direction refers to the direction perpendicular to the plane of the paper). Several of the second stacking structures 115 are arranged along the second direction; several of the other stacking structures are also arranged along the second direction.

[0111] In one embodiment, the number of the first stacking structure 114, the second stacking structure 115, and other stacking structures may be the same or different.

[0112] In the actual etching process, the first stacked structure 114, the second stacked structure 115, and other stacked structures are sequentially etched along the first direction. Therefore, after forming the isolation protective layer, the stacked structure with exposed sidewalls along the first direction is named the first stacked structure 114, and the exposed sidewalls are called the first sidewalls. Of course, one sidewall of the edge stacked structures in other stacked structures will also be exposed simultaneously. For ease of description, the stacked structure adjacent to the first stacked structure 114 is referred to as the second stacked structure 115; the isolation trench 105 between the first stacked structure 114 and the second stacked structure 115 is referred to as the first isolation trench 105. When the substrate 101 also includes several other stacked structures, all of which need to be etched, the other stacked structures are subsequently etched along the first direction to form other hybrid channel structures. Specifically, this includes:

[0113] S17: Please refer to Figures 12-14 The etching process involves etching the other stacked structures closest to the second stacked structure 115. Specifically, this includes forming a second patterned mask layer 116, using the second patterned mask layer as a mask to etch the exposed other stacked structures closest to the second stacked structure 115 down to the surface of the substrate 101, to form trenches in the other stacked structures, the trenches dividing the other stacked structures into a first part and a second part along the first direction; using the remaining second patterned mask layer 116 as a mask to selectively etch the first semiconductor layer 102 or the second semiconductor layer 103 on both sides of the trenches, to form a third etching cavity 117.

[0114] Therefore, the remaining second semiconductor layer 103 or first semiconductor layer 102 in the second portion of the second stacked structure 115, together with the remaining first semiconductor layer 102 or second semiconductor layer 103 in the first portion of other stacked structures adjacent to the second stacked structure 115, form a second hybrid channel structure 119, such as... Figure 14 As shown. For specific process details, please refer to steps S14-S16, which will not be elaborated here.

[0115] Repeat the above steps to sequentially etch the remaining stacked structures along the first direction, wherein the semiconductor layers in the second portion of the other stacked structures adjacent to the second stacked structure 115 constitute the channel structure of the subsequent device. Similarly, several mixed channel structures can be formed on the substrate 101 along the first direction; of course, in one specific example, the last group of channel structures may be identical channels, such as the isolation trench 105 where both sides may have a first semiconductor layer 102 or both sides may have a second semiconductor layer 103, which can be discarded or reserved for other uses as needed.

[0116] Finally, the remaining patterned mask layer formed above needs to be removed, such as... Figure 14 As shown.

[0117] In another embodiment, when the second stacked structure 115 is etched and the first hybrid channel structure 118 is fabricated, the first hybrid channel structure 118 can be cut off. Subsequently, a mask material is deposited on the remaining semiconductor structure, such as... Figure 8 As shown; at this time, the remaining first group or first stacked structure along the first direction is designated as the first stacked structure 114, the nearest other stacked structures are designated as the second stacked structure 115, and the isolation groove 105 between them is designated as the new first isolation groove 105; then steps S14-S16 are repeated to form the second hybrid channel structure 119. By repeating the above steps, several hybrid channel structures can be formed. After each group of hybrid channel structures is fabricated and cut, the remaining mask layer can be removed respectively.

[0118] In summary, the channel etching method for F-FET devices proposed in this application can effectively form a four-sided hollowed-out hybrid channel structure in hybrid channel devices, so that the gate material layer formed subsequently can completely surround the channel structure, thereby making it possible to form a gate structure that completely surrounds the channel in F-FET devices, thus significantly improving the performance of F-FET devices.

[0119] Furthermore, in the first hybrid channel structure, the germanium-silicon channel in the P-channel region, compared to the silicon nanochannel, can provide more channel stress because germanium has a larger lattice factor than silicon, and the germanium-silicon channel has a greater carrier mobility. Therefore, changing the P-channel from Si to SiGe further increases the performance of the F-FET.

[0120] Secondly, according to an embodiment of the present invention, a method for fabricating an F-FET device is also provided, including the channel etching method for the F-FET device described in any of the foregoing embodiments of the present invention.

[0121] According to one embodiment of the present invention, an F-FET device is also provided, which is fabricated using the F-FET device fabrication method described in the foregoing embodiments of the present invention.

[0122] In addition, according to one embodiment of the present invention, a method for fabricating an electronic device is provided, including the method for fabricating an F-FET device as described in the foregoing embodiments of the present invention.

[0123] According to one embodiment of the present invention, an electronic device is also provided, including the F-FET device described in the foregoing embodiments of the present invention.

[0124] It should be noted that in the fabrication process of the F-FET device of the present invention, there are other device structures that are not specifically described or illustrated. The present invention focuses on the fabrication process of the channel region structure of the hybrid channel. Other structures and processes can be referred to common knowledge in the field. Combined with the description of the present invention, the complete fabrication of the F-FET device can be achieved.

[0125] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for etching the channel of an F-FET device, characterized in that, include: Provide a substrate; A first semiconductor structure is formed on the substrate; the first semiconductor structure includes a plurality of stacked structures formed on the substrate, each stacked structure including a first semiconductor layer and a second semiconductor layer alternately stacked in a direction away from the substrate; The plurality of stacked structures are arranged sequentially along a first direction of the substrate, and adjacent stacked structures are isolated by an isolation structure; the isolation structure includes an isolation groove and an isolation protective layer filled in the isolation groove, and the height of the isolation protective layer is not less than the height of the isolation groove; Along the first direction, the plurality of stacked structures are sequentially divided into a first stacked structure, a second stacked structure, and other stacked structures; wherein, the first sidewall of the first stacked structure is exposed, and its second sidewall is protected by the isolation protective layer; wherein, the isolation structure used to isolate the first stacked structure and the second stacked structure is referred to as the first isolation structure; Using several isolation and protective layers as masks, the second semiconductor layer or the first semiconductor layer in the first stacked structure is selectively etched to form a first etch cavity, and only the first semiconductor layer or the second semiconductor layer is retained; A first patterned mask layer is formed; the first patterned mask layer fills the first etched cavity, wraps the first sidewall of the first stacked structure, and covers the surfaces of the plurality of stacked structures and the plurality of isolation protective layers; only the top of a portion of the second stacked structure is exposed; Using the first patterned mask layer as a mask, the exposed second stacked structure is etched down to the surface of the substrate to form a slot in the second stacked structure, the slot dividing the second stacked structure into a first part and a second part along the first direction; Using the remaining first patterned mask layer as a mask, the first semiconductor layer or the second semiconductor layer on both sides of the slot is selectively etched to form a second etch cavity, and only the remaining second semiconductor layer or the first semiconductor layer is retained to form a first semiconductor channel structure and a second semiconductor channel structure on both sides of the first isolation structure along the first direction, respectively.

2. The channel etching method for an F-FET device according to claim 1, characterized in that, A first semiconductor structure is formed on the substrate, specifically including: The plurality of stacked structures are formed on the substrate; wherein the plurality of stacked structures are arranged sequentially along the first direction of the substrate, and the isolation groove is formed between adjacent stacked structures; The isolation groove is filled with protective material, and the protective material is deposited on the surface of the plurality of stacked structures; The protective material on the surface of the plurality of stacked structures is etched away, along with the protective material covering the first sidewall of the first stacked structure, to expose the first sidewall of the first stacked structure, thereby forming the isolation protective layer in the isolation groove.

3. The channel etching method for an F-FET device according to claim 2, characterized in that, Forming several of the aforementioned isolation and protective layers specifically includes: A first protective material is deposited on the surface and sidewalls of the plurality of stacked structures; A second protective material is formed on the surface of the first protective material and fills the plurality of said isolation grooves; The first and second protective materials on the surfaces of the plurality of stacked structures and the first sidewall of the first stacked structure are etched away to form the isolation protective layer in the isolation groove.

4. The channel etching method for an F-FET device according to claim 3, characterized in that, The formation of the first patterned mask layer specifically includes: In the first etched cavity, the first sidewall of the first stacked structure, and the surface of the plurality of stacked structures and the isolation protective layer, a first mask layer is deposited; A patterned photoresist is formed on the surface of the first mask layer; the patterned photoresist covers the surface of the first mask layer and exposes only a portion of the first mask layer at the top of the second stacked structure; Using the patterned photoresist as a mask, the first mask layer is etched up to the surface of the second stacked structure to form the first patterned mask layer.

5. The channel etching method for an F-FET device according to claim 4, characterized in that, The first semiconductor layer is an N-type semiconductor layer, and the second semiconductor layer is a P-type semiconductor layer.

6. The channel etching method for an F-FET device according to claim 5, characterized in that, The first semiconductor layer is silicon; the second semiconductor layer is germanium-silicon.

7. The channel etching method for an F-FET device according to claim 6, characterized in that, The second protective material is silicon nitride, and the first protective material is silicon oxide.

8. A method for fabricating an F-FET device, characterized in that, The method includes the channel etching method for the F-FET device according to any one of claims 1-7.

9. An F-FET device, characterized in that, It is prepared using the method for preparing the F-FET device according to claim 8.

10. A method for manufacturing an electronic device, characterized in that, The method for fabricating the F-FET device as described in claim 8.

11. An electronic device, characterized in that, Includes the F-FET device as described in claim 9.

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