Channel etching method of GAA device and preparation method of GAA device

Abstract

The application provides a channel etching method of a GAA device, which comprises the following steps: forming a plurality of fin structures on a substrate; forming a first patterned mask layer and a first protection structure; taking the first patterned mask layer as a mask to etch the first protection structure at the top end and the sidewall of the stack structure of the first fin structure; taking the remaining first protection structure as a mask to selectively etch the second semiconductor layer in the first fin structure to form a first channel structure; forming a second patterned mask layer and a first protection layer; the remaining first protection structure and the first protection layer form a second protection structure; taking the second patterned mask layer as a mask to etch the second protection structure at the top end and the sidewall of the stack structure in the second fin structure; and taking the remaining second protection structure as a mask to selectively etch the first semiconductor layer therein to form a second channel structure. The technical scheme provided by the application realizes the process purpose of mixed channel preparation on the same substrate.

Description

Technical Field

[0001] This invention relates to the field of semiconductor devices, and more particularly to a channel etching method for GAA devices and a method for fabricating GAA devices. Background Technology

[0002] As semiconductor device sizes continue to shrink, Gate-All-Around (GAA) transistors, with their smaller channel lengths, further reduce device size and exhibit superior performance.

[0003] However, as the critical dimensions of semiconductor devices continue to shrink and device density continues to increase, the spacing between n-type field-effect transistors (nFETs) and p-type field-effect transistors (pFETs) within a standard cell will need to be even smaller. To address this issue, the current approach is to fabricate two different types of GAA transistors on the same substrate and introduce an isolation wall structure between the two transistors, thereby forming a hybrid-channel GAA transistor on the same substrate, which allows for a further reduction in the spacing between the two transistors.

[0004] For hybrid channel transistors, in pFET devices, compared to silicon nanochannels, germanium-silicon channels can provide more channel stress because germanium has a higher lattice factor than silicon. Furthermore, germanium-silicon channels have greater carrier mobility. Therefore, changing the pFET channel from silicon to germanium-silicon and presenting it in the form of germanium-silicon nanosheets can greatly increase the performance of GAA devices.

[0005] However, there are significant technological challenges in fabricating both P-type and N-type channels on the same substrate.

[0006] Therefore, how to effectively etch channels in GAA devices to form hybrid channels on the same substrate has become a technical problem that the industry urgently needs to solve. Summary of the Invention

[0007] This invention provides a channel etching method and a fabrication method for GAA devices to solve the problem of how to fabricate hybrid channels on the same substrate.

[0008] According to a first aspect of the present invention, a method for etching the channel of a GAA device is provided, comprising:

[0009] Provide a substrate;

[0010] A plurality of fin structures are formed on the substrate; wherein the plurality of fin structures are arranged on the substrate along a first direction; wherein each fin structure includes a stacked structure, the stacked structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked along the first direction; the first direction is parallel to the surface of the substrate; the plurality of fin structures include first fin structures and second fin structures, the first fin structures and the second fin structures being arranged alternately along the first direction;

[0011] A first patterned mask layer and a first protective structure are formed; the first protective structure is formed in the gap between adjacent fin structures and covers the surface of the plurality of fin structures; the first patterned mask layer covers the surface of the first protective structure and exposes only the top of the first fin structure and a portion of the first protective structure on both sides of the first fin structure along a first direction; wherein, the gap between the fin structures forms an isolation trench;

[0012] Using the first patterned mask layer as a mask, the first protective structure of the top and sidewalls of the stacked structure in the first fin structure is etched.

[0013] Using the remaining first protective structure as a mask, the second semiconductor layer or the first semiconductor layer in the first fin structure is selectively etched, while retaining the first semiconductor layer or the second semiconductor layer, to form a first channel structure or a second channel structure; wherein, after etching the first protective structure and the second semiconductor layer or the first semiconductor layer, a first etch cavity is formed;

[0014] A second patterned mask layer and a first protective layer are formed; the first protective layer fills the first etched cavity and covers the surface of the remaining first protective structure; the remaining first protective structure and the first protective layer form a second protective structure; the second patterned mask layer covers the surface of the second protective structure and exposes only the top of the second fin structure and the portions of the second protective structure on both sides of the second fin structure along the first direction.

[0015] Using the second patterned mask layer as a mask, the second protective structure on the top and sidewalls of the second fin structure is etched to expose the top and sidewalls of the stacked structure in the second fin structure;

[0016] Using the remaining second protective structure as a mask, the first semiconductor layer or the second semiconductor layer in the second fin structure is selectively etched, while the second semiconductor layer or the first semiconductor layer is retained, to form a second channel structure or a first channel structure.

[0017] Optionally, forming the first patterned mask layer and the first protective structure specifically includes:

[0018] The first protective structure is formed; the first protective structure fills the isolation trench and covers the surface of the plurality of fin structures;

[0019] The first patterned mask layer is formed.

[0020] Optionally, forming the second patterned mask layer and the first protective layer specifically includes:

[0021] The first protective layer is formed; the remaining first protective structure and the first protective layer form the second protective structure;

[0022] The second patterned mask layer is formed.

[0023] Optionally, forming the first protective structure specifically includes:

[0024] A first transition protective layer is formed; the first transition protective layer wraps around the surface and sidewalls of the plurality of fin structures;

[0025] A first etch protection layer is formed; the first etch protection layer covers the surface of the first transition protection layer and fills the isolation trench; the first protection structure includes the first transition protection layer and the first etch protection layer;

[0026] The first patterned mask layer is formed on the surface of the first etched protective layer.

[0027] Optionally, when etching the first protective structure on the top and sidewalls of the first fin structure using the first patterned mask layer as a mask, the process specifically includes:

[0028] Using the first patterned mask layer as a mask, the first etch protection layer on the top and sidewalls of the first fin structure is etched to expose the first transition protection layer on the surface and sidewall surfaces of the stacked structure.

[0029] Using the remaining first etched protective layer as a mask, the exposed first transition protective layer is etched to expose the stacked structure in the first fin structure. Optionally, using the second patterned mask layer as a mask, etching the second protective structure at the top and sidewalls of the second fin structure specifically includes:

[0030] Using the second patterned mask layer as a mask, the first etch protection layer and the first protective layer on the top and sidewalls of the second fin structure are etched to expose the first transition protective layer covering the surface and sidewalls of the stacked structure in the second fin structure.

[0031] Using the remaining first etched protective layer and the remaining first protective layer as a mask, the exposed first transition protective layer is etched to expose the stacked structure in the second fin structure.

[0032] Optionally, the material of the first etched protective layer and / or the first protective layer is a metal oxide or a nitride.

[0033] Optionally, the first channel structure is an N-channel and the second channel structure is a P-channel; the material of the second semiconductor layer is germanium-silicon and the material of the first semiconductor layer is silicon.

[0034] According to a second aspect of the present invention, a method for fabricating a GAA device is provided, comprising the channel etching method for the GAA device described in any one of the first aspects of the present invention.

[0035] According to a third aspect of the present invention, a GAA device is provided, which is prepared using the GAA device preparation method described in the second aspect of the present invention.

[0036] According to a fourth aspect of the present invention, a method for manufacturing an electronic device is provided, including the method for manufacturing a GAA device as described in the second aspect of the present invention.

[0037] According to a fifth aspect of the present invention, an electronic device is provided, comprising the GAA device described in the third aspect of the present invention.

[0038] This invention provides a channel etching method for GAA devices. During the etching of the first fin structure, a first protective structure is formed to protect the second fin structure, thereby forming either a first channel structure or a second channel structure. Conversely, during the etching of the second fin structure, a second protective structure is formed to protect the first fin structure, thereby forming either a second channel structure or a first channel structure. This achieves the goal of fabricating hybrid channels on the same substrate. Therefore, the technical solution provided by this invention solves the problem of difficulties in hybrid channel etching processes.

[0039] Furthermore, when the first channel structure is an N-channel and the second channel structure is a P-channel; the material of the second semiconductor layer is germanium-silicon and the material of the first semiconductor layer is silicon, since the second semiconductor layer of germanium-silicon material constitutes a P-channel, the stress of the P-channel and the carrier mobility of the GAA device are also improved. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a schematic flowchart of a channel etching method for a GAA device according to an embodiment of the present invention;

[0042] Figure 2 This is a schematic diagram of the device structure at different process stages fabricated according to the channel etching method of GAA devices provided in an embodiment of the present invention. Figure 1 ;

[0043] Figure 3 This is a schematic diagram of the device structure at different process stages fabricated according to the channel etching method of GAA devices provided in an embodiment of the present invention. Figure 2 ;

[0044] Figure 4 This is a schematic diagram of the device structure at different process stages fabricated according to the channel etching method of GAA devices provided in an embodiment of the present invention. Figure 3 ;

[0045] Figure 5 This is a schematic diagram of the device structure at different process stages fabricated according to the channel etching method of GAA devices provided in an embodiment of the present invention. Figure 4 ;

[0046] Figure 6 This is a schematic diagram of the device structure at different process stages fabricated according to the channel etching method of GAA devices provided in an embodiment of the present invention. Figure 5 ;

[0047] Figure 7 This is a schematic diagram of the device structure at different process stages fabricated according to the channel etching method of GAA devices provided in an embodiment of the present invention. Figure 6 ;

[0048] Figure 8 This is a schematic diagram of the device structure at different process stages fabricated according to the channel etching method of GAA devices provided in an embodiment of the present invention. Figure 7 ;

[0049] Figure 9 This is a schematic diagram of the device structure at different process stages fabricated according to the channel etching method of GAA devices provided in an embodiment of the present invention. Figure 8 ;

[0050] Figure 10This is a schematic diagram of the device structure at different process stages fabricated according to the channel etching method of GAA devices provided in an embodiment of the present invention. Figure 9 ;

[0051] Figure 11 This is a schematic diagram of the device structure at different process stages fabricated according to the channel etching method of GAA devices provided in an embodiment of the present invention. Figure 10 ;

[0052] Figure 12 This is a schematic diagram of the device structure at different process stages fabricated according to the channel etching method of GAA devices provided in an embodiment of the present invention. Figure 10 one;

[0053] Figure 13 This is a schematic diagram of the device structure at different process stages fabricated according to the channel etching method of GAA devices provided in an embodiment of the present invention. Figure 10 two;

[0054] Figure 14 This is a schematic diagram of the device structure at different process stages fabricated according to the channel etching method of GAA devices provided in an embodiment of the present invention. Figure 10 three;

[0055] Figure 15 This is a schematic diagram of the device structure at different process stages fabricated according to the channel etching method of GAA devices provided in an embodiment of the present invention. Figure 10 Four;

[0056] Figure 16 This is a schematic diagram of the device structure at different process stages fabricated according to the channel etching method of GAA devices provided in an embodiment of the present invention. Figure 10 five;

[0057] Explanation of reference numerals in the attached figures:

[0058] 101-Substrate;

[0059] 102 - First semiconductor layer;

[0060] 1021 - First semiconductor epitaxial layer;

[0061] 103 - Second semiconductor layer;

[0062] 1031 - Second semiconductor epitaxial layer;

[0063] 104 - Patterned photoresist;

[0064] 105 - Isolation trench;

[0065] 106-fin structure;

[0066] 1061 - First fin structure;

[0067] 1062 - Second fin structure;

[0068] 107 - First transition protective layer;

[0069] 108 - First etching protective layer;

[0070] 109 - First patterned mask layer;

[0071] 110 - First etched cavity;

[0072] 111 - Second patterned mask layer;

[0073] 112 - Second etching protective layer. Detailed Implementation

[0074] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0075] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0076] In hybrid-channel semiconductor devices, specifically in the P-channel, the germanium-silicon channel offers greater channel stress compared to the silicon nanochannel due to the higher lattice coefficient of germanium. Furthermore, the germanium-silicon channel exhibits higher carrier mobility. Therefore, changing the channel of a pFET from Si to a SiGe nanolayer can enhance the performance of the GAA device. During P-channel fabrication, germanium-silicon is typically retained while silicon is etched away. However, fabricating both p-type and N-type channels on the same substrate is inherently very challenging. Specifically, during P-channel fabrication, the germanium-silicon must be retained while silicon is etched away. Therefore, etching the silicon in the P-type channel can damage the silicon nanolayer in the N-type channel region, or vice versa, making the etching process for hybrid channels particularly difficult.

[0077] In view of this, the inventors of this application provide a method for etching the channel of a GAA device, which realizes the fabrication of a hybrid channel.

[0078] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0079] Please refer to Figures 1-16 According to an embodiment of the present invention, a channel etching method for a GAA device is provided, such as... Figure 1 As shown, it includes:

[0080] S11: Provide a substrate 101;

[0081] S12: A plurality of fin structures 106 are formed on the substrate 101; wherein the plurality of fin structures 106 are arranged on the substrate 101 along a first direction; wherein each fin structure 106 includes a stacked structure, the stacked structure including a plurality of first semiconductor layers 102 and a plurality of second semiconductor layers 103 alternately stacked along the first direction; the first direction is parallel to the surface of the substrate 101; the plurality of fin structures 106 include a first fin structure 1061 and a second fin structure 1062, the first fin structure 1061 and the second fin structure 1062 being alternately arranged along the first direction; wherein, the fin structure refers to a multiple nanosheet or a multiple nanobridge.

[0082] Please refer to the following: Figures 2-4 Step S12, which involves forming a plurality of fin structures 106 on the substrate 101, specifically includes the following steps S121-S123:

[0083] S121: A plurality of first semiconductor epitaxial layers 1021 and a plurality of second semiconductor epitaxial layers 1031 are formed on the substrate 101; wherein the first semiconductor epitaxial layers 1021 and the second semiconductor epitaxial layers 1031 are alternately stacked in a direction away from the substrate 101; as shown in the figure. Figure 2 As shown; the material of the second semiconductor epitaxial layer is germanium silicon, and the material of the first semiconductor epitaxial layer is silicon.

[0084] S122: A patterned photoresist 104 is formed on the surface of the epitaxial layer, such as... Figure 3 As shown; that is, a patterned photoresist 104 is formed on the surface of the stacked component consisting of the first semiconductor epitaxial layer 1021 and the second semiconductor epitaxial layer 1031.

[0085] In one specific example, the surface of the stacked component facing away from the substrate 101 is composed of a first semiconductor material layer, and the patterned photoresist 104 is formed on the surface of the first semiconductor material layer. In another specific example, the surface of the stacked component facing away from the substrate 101 is composed of a second semiconductor material layer, and the patterned photoresist 104 is formed on the surface of the second semiconductor material layer. The patterned photoresist 104 serves as a mask layer during the etching of the epitaxial layer. Of course, those skilled in the art should understand that the patterned photoresist 104 can be replaced by other mask layers, and any implementation of the mask layer is within the scope of protection of this invention, which is not limited thereto.

[0086] S123: Using the patterned photoresist 104 as a mask, etch the plurality of first semiconductor material layers and the plurality of second semiconductor material layers down to the surface of the substrate 101 to form the plurality of fin structures 106 and the plurality of isolation trenches 105 on the substrate 101. The isolation trenches 105 are trenches formed after etching the plurality of first semiconductor material layers, the plurality of second semiconductor material layers, and the substrate 101; such as Figure 4 As shown.

[0087] S13: Form a first patterned mask layer 109 and a first protective structure; the first protective structure is formed in the gap (isolation trench 105) between adjacent fin structures 106 and covers the surface of the plurality of fin structures 106; the first patterned mask layer 109 covers the surface of the first protective structure and exposes only the top of the first fin structure 1061 and the portion of the first protective structure on both sides of the first fin structure 1061 along a first direction; wherein the gap between the fin structures 106 forms an isolation trench 105; such that after the first protective structure is formed in the isolation trench 105, the adjacent fin structures 106 are isolated by the isolation structure.

[0088] The isolation structure includes an isolation trench 105 and a first protective structure formed in the isolation trench 105.

[0089] In one example of the present invention, before forming the first patterned mask layer 109 and the first protective structure in step S13, the method further includes: removing the patterned photoresist 104.

[0090] In one embodiment, please refer to Figures 5-7 In step S13, forming the first patterned mask layer 109 and the first protective structure specifically includes the following steps S131-S132:

[0091] S131: Form the first protective structure; the first protective structure fills the isolation trench 105 and covers the surface of the plurality of fin structures 106.

[0092] In a preferred embodiment, forming the first protective structure in step S131 specifically includes the following steps S1311-S1312:

[0093] S1311: Forming a first transition protective layer 107; the first transition protective layer 107 wraps around the surface and sidewalls of the plurality of fin structures 106; as shown in the figure Figure 5 As shown;

[0094] S1312: Form the first etch protective layer 108, such as Figure 6 As shown; the first etch protection layer 108 covers the surface of the first transition protection layer 107 and fills the isolation trench 105; the first protection structure includes the first transition protection layer 107 and the first etch protection layer 108; in this embodiment, by first depositing a first transition protection layer 107 and then depositing the first etch protection layer 108, the double-layer structure can avoid the problem of forming pinhole defects by directly filling atomic layers.

[0095] The first patterned mask layer 109 is formed on the surface of the first etch protection layer 108.

[0096] In other embodiments, the first protective structure includes only the first etched protective layer 108 that fills the isolation trench 105 and covers the surface of the fin structure 106.

[0097] S132: Form the first patterned mask layer 109, such as Figure 7 As shown.

[0098] S14: Using the first patterned mask layer 109 as a mask, etch the first protective structure of the top and sidewalls of the stacked structure in the first fin structure 1061.

[0099] In specific examples, when etching the first protective structure, HF gas, HF gas, and NH3 etching can be used; alternatively, FC-based C can be used. x F y Etching of free radicals such as NF3, SF6, XeF2, O2, N2, H2, Ar, and He.

[0100] In one embodiment, please refer to Figures 8-9 When the first protective structure includes the first transition protective layer 107 and the first etch protective layer 108, step S14, using the first patterned mask layer as a mask, specifically includes the following steps S141-S142 when etching the first protective structure of the top and sidewalls of the first fin structure 1061:

[0101] S141: Using the first patterned mask layer 109 as a mask, etch the first etch protection layer 108 on the top and sidewalls of the first fin structure 1061 to expose the first transition protection layer 107 on the surface and sidewall surfaces of its stacked structure; Figure 8 As shown.

[0102] S142: Using the remaining first etch protection layer 108 as a mask, etch the exposed first transition protection layer 107 to expose the stacked structure in the first fin structure 1061; as Figure 9 As shown.

[0103] In another embodiment, when the first protective structure only includes the first etched protective layer 108, step S14, using the first patterned mask layer as a mask, specifically includes etching the first protective structure at the top and sidewalls of the first fin structure 1061, and includes:

[0104] Using the first patterned mask layer 109 as a mask, the first etch protection layer 108 on the top and sidewalls of the first fin structure 1061 is etched to expose the stacked structure in the first fin structure 1061.

[0105] In one embodiment, after etching the first etch protection layer 108 on the top and sidewalls of the first fin structure 1061, when a first patterned mask layer 109 of relatively large thickness is provided, the exposed first transition protection layer 107 is etched using the remaining first patterned mask layer 109 and the remaining first etch protection layer 108 as masks.

[0106] In another embodiment, when a first patterned mask layer 109 with a relatively small thickness is provided, the first patterned mask layer 109 is removed at the same time as the remaining first etch protection layer 108 is formed after step S141. At this time, the first transition protection layer 107 is etched using the remaining first etch protection layer 108 as a mask.

[0107] S15: Using the remaining first protective structure as a mask, selectively etch the second semiconductor layer 103 or the first semiconductor layer 102 in the first fin structure 1061, while retaining the first semiconductor layer 102 or the second semiconductor layer 103, to form a first channel structure or a second channel structure; wherein, after etching the first protective structure and the second semiconductor layer 103 or the first semiconductor layer 102, a first etching cavity 110 is formed; as Figure 10 As shown; in one embodiment, when the first channel structure is an N-channel and the second channel structure is a P-channel, the material of the second semiconductor layer is germanium-silicon and the material of the first semiconductor layer is silicon.

[0108] In one embodiment, in step S15, the second semiconductor layer 103 is selectively etched in the first fin structure 1061, while the first semiconductor layer 102 is retained. The first protective structure has a high etching selectivity relative to the second semiconductor layer 103, such that the second semiconductor layer 103 is removed while the first semiconductor layer 102 is retained.

[0109] In another embodiment, in step S15, the first semiconductor layer 102 of the first fin structure 1061 is selectively etched, while the second semiconductor layer 103 is retained. The first protective structure has a high etching selectivity relative to the first semiconductor layer 102, such that the first semiconductor layer 102 is removed and the second semiconductor layer 103 is retained.

[0110] S16: A second patterned mask layer 111 and a first protective layer are formed; the first protective layer fills the first etch cavity 110 and covers the surface of the remaining first protective structure; the remaining first protective structure and the first protective layer form a second protective structure; the second patterned mask layer 111 covers the surface of the second protective structure and exposes only the top of the second fin structure 1062 and the portions of the second protective structure on both sides of the second fin structure 1062 along the first direction; the material of the first etch protective layer 108 and / or the first protective layer is a metal oxide or a nitride. Specifically, the metal oxide or nitride can be ALD oxide (interlayer dielectric oxide), Flowable Nitride, spin-on-carbon, oxynitride, carbon hydrogen oxygen compound, and other metal oxides or nitrides. The material of the first transition protective layer 107 is silicon nitride. Of course, the material of the first transition protective layer 107 can also be other materials. This invention is not limited to this. Any implementation of the material of the first transition protective layer 107 is within the protection scope of this invention.

[0111] In one embodiment, please refer to Figures 11-12 In step S16, a second patterned mask layer and a first protective layer are formed, specifically including the following steps S161-S162:

[0112] S161: Form the first protective layer; wherein the remaining first protective structure and the first protective layer form the second protective structure; as shown Figure 11 As shown;

[0113] In one embodiment, when the first protective structure includes a first transition protective layer 107 and a first etch protective layer 108, the first protective layer fills the first etch cavity 110 and covers the surface of the remaining first etch protective layer 108; the remaining first etch protective layer 108, the first protective layer, and the first transition protective layer 107 form the second protective structure; the remaining first etch protective layer 108 and the first protective layer constitute the second etch protective layer 112.

[0114] In another embodiment, when the first protective structure includes only the first etch protection layer 108, the remaining first etch protection layer 108 and the first protective layer form the second protective structure; the remaining first etch protection layer 108 and the first protective layer constitute the second etch protection layer 112.

[0115] S162: Form the second patterned mask layer 111; the second patterned mask layer 111 is formed on the surface of the first protective layer, such as... Figure 12 As shown.

[0116] S17: Using the second patterned mask layer 111 as a mask, etch the second protective structure on the top and sidewalls of the second fin structure 1062 to expose the top and sidewalls of the stacked structure in the second fin structure 1062.

[0117] In one embodiment, in step S17, when the first protective structure includes the first etched protective layer 108 and the first transition protective layer 107, the second protective structure includes: the second etched protective layer 112 and the first transition protective layer 107; therefore, using the second patterned mask layer 111 as a mask, etching the second protective structure of the top and sidewalls of the second fin structure 1062 specifically includes the following steps S171-S172:

[0118] S171: Using the second patterned mask layer 111 as a mask, etch the remaining first etch protection layer 108 and the first protective layer (i.e., the second etch protection layer 112) on the top and sidewalls of the second fin structure 1062 to expose the first transition protective layer 107 covering the surface and sidewalls of the stacked structure in the second fin structure 1062; Figure 13 As shown.

[0119] S172: Using the remaining first etchable protective layer 108 and the remaining first protective layer as a mask, etch the exposed first transition protective layer 107 to expose the stacked structure in the second fin structure 1062; as Figure 14 As shown.

[0120] In one embodiment, when the first protective structure includes only the first etch protection layer 108, the second protective structure includes: the remaining first transition protection layer 107, the remaining first etch protection layer 108, and the first protective layer (second etch protection layer 112). Therefore, in step S17, using the second patterned mask layer 111 as a mask, etching the top and sidewalls of the second fin structure 1062 to form the second protective structure specifically includes:

[0121] Using the second patterned mask layer 111 as a mask, the remaining second etch protection layer 112 on the top and sidewalls of the second fin structure 1062 is etched to expose the stacked structure in the second fin structure 1062.

[0122] S18: Using the remaining second protective structure as a mask, selectively etch the first semiconductor layer 102 or the second semiconductor layer 103 in the second fin structure 1062, and retain the second semiconductor layer 103 or the first semiconductor layer 102 to form a second channel structure or a first channel structure, such as... Figure 15 As shown.

[0123] In one embodiment, when the first channel structure is formed in step S15, step S18 includes: using the remaining second protective structure as a mask, selectively etching the first semiconductor layer 102 in the second fin structure 1062, and retaining the second semiconductor layer 103, to form the second channel structure.

[0124] In another embodiment, when the second channel structure is formed in step S15, step S18 includes: using the remaining second protective structure as a mask, selectively etching the second semiconductor layer 103 in the second fin structure 1062, and retaining the first semiconductor layer 102, to form the first channel structure.

[0125] In one embodiment, the remaining second protective structure includes the remaining first etch protection layer 108, the remaining first protective layer, and the first transition protection layer 107.

[0126] In another embodiment, the remaining second protective structure includes the remaining first etched protective layer 108 and the remaining first protective layer.

[0127] In one specific embodiment, the first semiconductor layer 102 is silicon, and the second semiconductor layer 103 is germanium-silicon. Thus, after step S15, a first channel structure is formed, wherein the first channel structure includes first semiconductor layers 102 stacked at intervals along a direction away from the substrate 101, and the material of the first semiconductor layers 102 is silicon; after step S18, a second channel structure is formed, wherein the second channel structure includes second semiconductor layers 103 stacked at intervals, and the material of the second semiconductor layers 103 is germanium-silicon; therefore, steps S15 and S18 respectively form an N-type channel structure and a P-type channel structure; or steps S15 and S18 respectively form a P-type channel structure and an N-type channel structure; thus, the fabrication of two channel types in the semiconductor device is realized.

[0128] After forming the first channel structure and the second channel structure, the process also includes: removing the remaining second protective structure, such as... Figure 16 As shown (only one set of hybrid channel structures is shown).

[0129] The etching gas used to remove the remaining second protective structure was: fluorine-based gas, C x Fy SF6, C x F y F z The process involves combinations of inert gases such as X1F2+H2, O2, N2+Ar, and He. Other process conditions are similar to those used in SiGe etching and will not be elaborated upon here.

[0130] According to one embodiment of the present invention, a method for fabricating a GAA device is also provided, including the channel etching method for the GAA device described in any of the foregoing embodiments of the present invention.

[0131] The present invention provides a channel etching method in a GAA device. In the fabrication process of a P-type channel or an N-type channel, a first protective structure and a second protective structure are cleverly designed and utilized to protect the first fin structure 1061 and the second fin structure 1062 respectively. This successfully avoids the problem that the first channel is damaged by subsequent channel etching due to mutual interference during the fabrication process of different channels.

[0132] Furthermore, by designing a first protective structure, the present invention utilizes a two-step process to deposit two protective materials: a first etch protection layer 108 and a first transition protection layer 107, so that the surface of the first etch protection layer 108 deposited based on the first transition protection layer 107 will not have defects such as wafer hole pins.

[0133] Secondly, according to an embodiment of the present invention, a GAA device is also provided, which is prepared using the GAA device preparation method described in the foregoing embodiments of the present invention.

[0134] In addition, according to one embodiment of the present invention, a method for manufacturing an electronic device is also provided, including the method for manufacturing a GAA device as described in the foregoing embodiments of the present invention.

[0135] According to one embodiment of the present invention, an electronic device is also provided, including the GAA device described in the foregoing embodiments of the present invention.

[0136] It should be noted that in the fabrication process of the GAA device of the present invention, there are other device structures that are not specifically described or illustrated. The present invention focuses on the fabrication process of the channel region structure of the hybrid channel. Other structures and processes can be referred to common knowledge in the field. Combined with the description of the present invention, the complete fabrication of the GAA device can be achieved.

[0137] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for etching the channel of a GAA device, characterized in that, include: Provide a substrate; A plurality of fin structures are formed on the substrate; wherein the plurality of fin structures are arranged on the substrate along a first direction; wherein each fin structure includes a stacked structure, the stacked structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked along the first direction; the first direction is parallel to the surface of the substrate; the plurality of fin structures include first fin structures and second fin structures, the first fin structures and the second fin structures being arranged alternately along the first direction; A first patterned mask layer and a first protective structure are formed; the first protective structure is formed in the gap between adjacent fin structures and covers the surface of the plurality of fin structures; the first patterned mask layer covers the surface of the first protective structure and exposes only the top of the first fin structure and a portion of the first protective structure on both sides of the first fin structure along a first direction; wherein, the gap between the fin structures forms an isolation trench; Using the first patterned mask layer as a mask, the first protective structure of the top and sidewalls of the stacked structure in the first fin structure is etched. Using the remaining first protective structure as a mask, the second semiconductor layer or the first semiconductor layer in the first fin structure is selectively etched, while retaining the first semiconductor layer or the second semiconductor layer, to form a first channel structure or a second channel structure; wherein, after etching the first protective structure and the second semiconductor layer or the first semiconductor layer, a first etch cavity is formed; A second patterned mask layer and a first protective layer are formed; the first protective layer fills the first etched cavity and covers the surface of the remaining first protective structure; the remaining first protective structure and the first protective layer form a second protective structure; the second patterned mask layer covers the surface of the second protective structure and exposes only the top of the second fin structure and the portions of the second protective structure on both sides of the second fin structure along the first direction. Using the second patterned mask layer as a mask, the second protective structure on the top and sidewalls of the second fin structure is etched to expose the top and sidewalls of the stacked structure in the second fin structure; Using the remaining second protective structure as a mask, the first semiconductor layer or the second semiconductor layer in the second fin structure is selectively etched, while the second semiconductor layer or the first semiconductor layer is retained, to form a second channel structure or a first channel structure.

2. The channel etching method for the GAA device according to claim 1, characterized in that, The formation of the first patterned mask layer and the first protective structure specifically includes: The first protective structure is formed; the first protective structure fills the isolation trench and covers the surface of the plurality of fin structures; The first patterned mask layer is formed.

3. The channel etching method for the GAA device according to claim 2, characterized in that, The formation of the second patterned mask layer and the first protective layer specifically includes: The first protective layer is formed; the remaining first protective structure and the first protective layer form the second protective structure; The second patterned mask layer is formed.

4. The channel etching method for the GAA device according to claim 3, characterized in that, The formation of the first protective structure specifically includes: A first transition protective layer is formed; the first transition protective layer wraps around the surface and sidewalls of the plurality of fin structures; A first etch protection layer is formed; the first etch protection layer covers the surface of the first transition protection layer and fills the isolation trench; the first protection structure includes the first transition protection layer and the first etch protection layer; The first patterned mask layer is formed on the surface of the first etched protective layer.

5. The channel etching method for a GAA device according to claim 4, characterized in that, When etching the first protective structure on the top and sidewalls of the first fin structure using the first patterned mask layer as a mask, the process specifically includes: Using the first patterned mask layer as a mask, the first etch protection layer on the top and sidewalls of the first fin structure is etched to expose the first transition protection layer on the surface and sidewall surfaces of the stacked structure. Using the remaining first etched protective layer as a mask, the exposed first transition protective layer is etched to expose the stacked structure in the first fin structure.

6. The channel etching method for a GAA device according to claim 5, characterized in that, Using the second patterned mask layer as a mask, etching the second protective structure on the top and sidewalls of the second fin structure specifically includes: Using the second patterned mask layer as a mask, the first etch protection layer and the first protective layer on the top and sidewalls of the second fin structure are etched to expose the first transition protective layer covering the surface and sidewalls of the stacked structure in the second fin structure. Using the remaining first etched protective layer and the remaining first protective layer as a mask, the exposed first transition protective layer is etched to expose the stacked structure in the second fin structure.

7. The channel etching method for a GAA device according to claim 6, characterized in that, The material of the first etch protective layer and / or the first protective layer is: metal oxide or nitride; the material of the first transition protective layer is silicon nitride.

8. The channel etching method for a GAA device according to claim 1, characterized in that, The first channel structure is an N-channel, and the second channel structure is a P-channel; the material of the second semiconductor layer is germanium-silicon, and the material of the first semiconductor layer is silicon.

9. A method for fabricating a GAA device, characterized in that, The method includes the channel etching method for the GAA device according to any one of claims 1-8.

10. A GAA device, characterized in that, It is prepared using the fabrication method of the GAA device according to claim 9.

11. A method for manufacturing an electronic device, characterized in that, The method for fabricating the GAA device as described in claim 9.

12. An electronic device, characterized in that, Includes the GAA device as described in claim 10.

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