Method for repairing a line
Patent Information
- Application Number
- CN202311817452.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-26
- Publication Date
- 2026-10-30
- Estimated Expiration
- 2043-12-26
AI Technical Summary
[0002]对于半导体芯片的设计,在线路设计阶段,在线路设计出来之后,大部分都会存在某些缺陷,其中,通常会存在一些设计阶段无法发现的缺陷,这种缺陷一般只有等流片出来之后,通过测试才能发现
[0017]本申请实施例,可以在线路复杂,封装后修补所在位置焊线非常密集情形下,连线电阻可以达到1Ω以内,连线长度最高可达8mm,解决了降低运营成本,解决了点胶等其他无法完成的技术问题。
Smart Images

Figure CN117766416B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more specifically, to a method for repairing circuits. Background Technology
[0002] In semiconductor chip design, during the circuit design phase, most circuits will contain some defects after they are completed. Among these, some defects are often undetectable during the design phase and can only be discovered through testing after the chip is fabricated. After discovering these defects, designers typically use circuit repair methods to improve the design. The general practice for circuit repair is to cut short-circuited conductive lines or connect previously disconnected (open-circuit) conductive lines. These operations are usually performed using a focused ion beam (FIB) scanner.
[0003] When two connection points are close together, tungsten metal wires can meet performance requirements. However, when the two connection points are far apart, the tungsten metal wire used as the connection will be longer, resulting in a higher resistance. For example, when the length of the deposited tungsten metal wire is 1000µm, the connection resistance (R) can reach as high as 10kΩ. During the testing phase, such a high resistance may be mistaken for an open circuit. Furthermore, it cannot carry a current exceeding 0.1A. This is undoubtedly unacceptable for chips manufactured using advanced processes with high speed requirements.
[0004] Furthermore, it typically takes half an hour to deposit a tungsten metal wire that is 0.3 μm thick, 1 μm wide, and 100 μm long using FIB. If the two pads mentioned above are 1000 μm apart, then FIB deposition will take 5 hours. Since FIB is charged based on usage time, the cost will be higher.
[0005] Therefore, there is an urgent need for a better method for line repair. Summary of the Invention
[0006] The purpose of this application is to provide a line repair method to reduce the cost of line repair.
[0007] In a first aspect, this application provides a circuit repair method, the method comprising: determining a circuit connection diagram of a packaged chip, the circuit connection diagram indicating the positional relationship of pads and the connection relationship of pads connected by wires; determining a circuit to be modified, the circuit to be modified including pads that need to be connected and / or pads that need to be disconnected; determining a modification scheme based on the circuit connection diagram and the circuit to be modified, the modification scheme including one or more sets of positions, each set of positions including two positions to be connected, or two positions to be deleted; based on the modification scheme, using a pressure bonding process to connect every two positions to be connected; or to delete the connection between every two positions to be deleted.
[0008] In some alternative implementations, the modification also includes a metallic material used at the connection point.
[0009] In some optional implementations, based on the modified scheme, a pressure bonding process is used to connect every two positions to be connected, including: opening the packaged chip and removing the molding compound from each position to be connected; when the current position to be connected uses aluminum, using a focused ion beam to etch the passivation layer on the surface of the current position to expose the conductive metal; when the current position to be connected uses copper, using a focused ion beam to extend a tungsten pad, making the copper and the tungsten pad conductive, wherein the length * width * thickness of the tungsten pad is greater than 60um * 60um * 2um; wherein the current position to be connected is a relatively flat area that will not interfere with other circuits; and using a pressure bonding process to connect the tungsten pad and the conductive metal, or the conductive metal to the conductive metal, of every two positions to be connected.
[0010] In some optional implementations, deleting the connection between every two positions of the connection to be deleted includes: using tweezers to pull out the connection to be deleted.
[0011] In some alternative implementations, the method is applicable to a circuit repair system, which includes an ultrasonic wire bonding assembly, a focused ion beam assembly, a vision assembly, a fixture, and a data processing and control assembly. Based on the modified scheme, a pressure welding process is used to connect every two locations to be connected; or to delete the connection between every two locations to be deleted, including: when the current location to be connected uses aluminum, the data processing and control assembly controls the focused ion beam assembly to use a focused ion beam at the current location to be connected to etch the passivation layer of the surface, exposing the conductive metal; when the current location to be connected uses copper, the data processing and control assembly controls the focused ion beam assembly... A focused ion beam is used to connect a long tungsten pad to a copper metal conductor. The current connection point is a relatively flat area that will not interfere with other circuits. The data processing and control component controls the ultrasonic wire bonding assembly to use a pressure bonding process to connect the tungsten pad to the conductive metal or the conductive metal to the conductive metal at each pair of connection points. The data processing and control component controls the fixture to delete the connection between each pair of connection points to be deleted. The vision component acquires an image of the packaged chip and sends the image to the data processing and control component, which performs position matching based on the image of the packaged chip and the modification scheme.
[0012] In some optional implementations, the circuit repair system further includes a display component for displaying a control interface based on instructions from the data processing and control component. The control interface includes an image of the packaged chip and the modification scheme displayed in association with the image of the packaged chip.
[0013] In some optional implementations, the method further includes: determining the location to be modified based on the modification scheme, opening the packaged chip to expose the location to be modified, and acquiring an image of the exposed area; identifying the image of the exposed area to obtain an actual circuit diagram of the exposed area; matching the actual circuit diagram with the modification scheme to determine a first location to be connected and a second location to be connected; the line connecting the first location and the second location intersects with a target line in the actual circuit diagram; determining a first height of the target line; and based on the first height of the target line, determining a second height of the line connecting the first location and the second location, wherein the second height is higher than the first height, so that the first location and the second location can be connected based on the second height.
[0014] In some alternative implementations, the first height is determined based on the process used in the packaged chip.
[0015] In some alternative implementations, the first height is the maximum value of the process used in the packaged chip.
[0016] In some optional implementations, the maximum value of the second height is 700um, and the modification scheme is optimized when the first height is greater than or equal to 700um.
[0017] In this embodiment, even with complex circuitry and densely packed solder lines at the repair location after packaging, the wiring resistance can be reduced to less than 1Ω, and the wiring length can reach up to 8mm. This solves the problems of reducing operating costs and resolving other technical issues that cannot be addressed, such as dispensing. Attached Figure Description
[0018] To more clearly illustrate the technical solutions of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0019] Figure 1 This is a schematic flowchart of a line repair method provided in an embodiment of this application;
[0020] Figure 2 A schematic diagram of a packaged chip circuit is provided for an embodiment of this application;
[0021] Figure 3 This is a schematic diagram of another line repair method provided in an embodiment of this application;
[0022] Figure 4 This is a schematic diagram of another packaged chip circuit provided in an embodiment of this application. Detailed Implementation
[0023] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.
[0024] Figure 1 This is a schematic flowchart of a line repair method provided in an embodiment of this application. Figure 1 As shown, the method may include the following steps:
[0025] S110, determine the circuit connection diagram of the packaged chip. This circuit connection diagram can be used to indicate the positional relationship of the pads and the connection relationship of the pads through the wires.
[0026] The circuit diagram for this packaged chip can be provided by the chip designer.
[0027] The wiring diagram may include the positions of pads and pins, as well as the connection relationships between pads and pins; or it may include the positions of the redistribution layer (RDL) and the connections between the RDL and pads.
[0028] For example, such as Figure 2 As shown, a packaged chip may include multiple pads 201 and multiple pins 202. There are some connections between the pads 201 and pins 202, which are usually connected by wires.
[0029] By modifying the wiring connected to the pad, the circuitry of the packaged chip can be repaired. This wiring can be a metal wire, such as a gold wire.
[0030] S120, Determine the line to be modified, which includes pads that need to be connected and / or pads that need to be disconnected;
[0031] For chip designers, after designing a chip, they can package it and test the packaged chip. During testing, if anomalies such as short circuits, leakage, or functional failures are found, non-destructive and destructive analysis, including IV testing, X-ray, capping, and hotspot localization, can be used to narrow down the anomalies. Based on this narrowed anomaly analysis, a schematic design can be developed for circuit modification. The modified packaged chip can then be tested again to verify the design's correctness. Circuit modifications can include removing connections and re-establishing connections.
[0032] S130, Based on the line connection diagram and the line to be modified, determine the modification plan. The modification plan includes one or more sets of positions, each set of positions including two positions to be connected, or two positions to be deleted.
[0033] When determining a modification plan based on the route connection diagram and the route to be modified, certain constraints can be followed. These constraints can be predefined in the system. During the design of the modification plan, the designed plan can be evaluated based on these constraints to determine whether it meets the requirements. If it does not meet the requirements, a prompt can be given to allow for revision.
[0034] The constraints here may include: maximum line length, maximum line height, maximum line diameter, etc.
[0035] It can also determine whether there are alternative and lower-cost solutions for modifying the route based on the route connection diagram, and if so, it needs to be reminded.
[0036] S140, based on the modified scheme, uses pressure welding process to connect every two positions to be connected; or deletes the connection between every two positions to be deleted.
[0037] In this modified design, the connection points use metal materials. Therefore, in step S140 above, based on the modified design, a pressure welding process is used to connect every two connection points. This can be achieved through the following steps:
[0038] Step 1) Open the packaged chip and remove the plastic encapsulation material from each connection point;
[0039] Step 2): When the current connection location uses copper metal, a focused ion beam long tungsten pad is used to make the copper metal and the tungsten pad conductive. The length * width * thickness of the tungsten pad is greater than 60um * 60um * 2um. The current connection location is a relatively flat area that will not interfere with other circuits. In some embodiments, the connection location in the modified scheme can be determined as the initial location. Based on the image of the packaged chip, a relatively flat area near the initial location that will not interfere with other circuits can be selected as the optimized location. A focused ion beam long tungsten pad can be used at the optimized location to make the copper metal and the tungsten pad conductive.
[0040] Step 3): When aluminum is used at the current connection point, a focused ion beam is used to etch the passivation layer on the surface at the current connection point to expose the conductive metal.
[0041] Step 4) Use pressure welding to connect each pair of pads to conductive metal, or conductive metal to conductive metal, at the positions to be connected.
[0042] In another embodiment, tweezers can be used to pull out the wire that needs to be removed.
[0043] In this embodiment, even with complex circuitry and densely packed solder lines at the repair location after packaging, the wiring resistance can be reduced to less than 1Ω, and the wiring length can reach up to 8mm. This solves the problems of reducing operating costs and resolving other technical issues that cannot be addressed, such as dispensing.
[0044] In some embodiments, the method can be applied to a circuit repair system, which includes an ultrasonic wire bonding assembly, a focused ion beam assembly, a vision assembly, a fixture, and a data processing and control assembly. Based on this, the above-described S140 can be implemented through the following steps:
[0045] Step A): When aluminum is used at the current connection point, the data processing and control component controls the focused ion beam component to use a focused ion beam at the current connection point to etch the passivation layer on the surface and expose the conductive metal.
[0046] Step B), when the current location to be connected uses copper metal, the data processing and control component controls the focused ion beam component to use a focused ion beam long tungsten pad, so that the copper metal and the tungsten pad are connected. The current location to be connected is a relatively flat place that will not interfere with other circuits.
[0047] Step C), the data processing and control component controls the ultrasonic wire bonding assembly to use a pressure welding process to connect the tungsten pad and conductive metal, or conductive metal to conductive metal, at every two positions to be connected.
[0048] Step D): The data processing and control component controls the fixture to delete the connection between every two positions of the connection to be deleted;
[0049] Step E): The vision component acquires an image of the packaged chip and sends the image of the packaged chip to the data processing and control component, which performs position matching based on the image of the packaged chip and the modification scheme.
[0050] The data processing and control components can be electronic devices with processors, such as personal computers, servers, or network devices.
[0051] This data processing and control component can communicate with the ultrasonic wire bonding component, focused ion beam component, vision component, and fixture, and can transmit data and signals between them to achieve data reporting and equipment control.
[0052] This data processing and control component can send information such as the welding position and welding parameters to the ultrasonic wire bonding assembly, so that the ultrasonic wire bonding assembly can perform welding at the welding position based on the welding parameters. These welding parameters may include parameters of the gold wire, etc.
[0053] The data processing and control component can send the deposition location or etching location and power parameters to the focused ion beam assembly, so that the focused ion beam assembly can perform pad deposition at the deposition location or etch at the etching location using the corresponding power parameters.
[0054] The data processing and control component can send control commands to the fixture so that the fixture can perform corresponding actions, such as movement and gripping.
[0055] The data processing and control component can be connected to the ultrasonic wire bonding component, the focused ion beam component, the vision component, and the fixture via a CAN bus.
[0056] In some embodiments, the circuit repair system further includes a display component for displaying a control interface based on instructions from the data processing and control component. The control interface includes an image of the packaged chip and a modification scheme displayed in association with the image of the packaged chip.
[0057] When displayed, this modification scheme may include some positions and connections that can be highlighted on the image of the packaged chip.
[0058] In some embodiments, assistance may also be provided in determining the modification scheme. For example... Figure 3 As shown, this can be achieved through the following steps:
[0059] S310 determines the location that needs to be modified based on the modification plan, opens the packaged chip to expose the location that needs to be modified, and obtains an image of the exposed area.
[0060] like Figure 4 As shown, the packaged chip can be decapsulated, and the molding compound on each connection point can be removed to obtain the following... Figure 4 The image shown includes the exposed area of the packaged chip. The lines and corresponding pads in the image represent actual locations.
[0061] S320 identifies the image of the exposed area to obtain the actual circuit diagram of the exposed area.
[0062] Semantic recognition can be performed on the exposed area of the image to obtain the various lines, and the endpoints of the lines can be identified as pads. This semantic recognition can be based on a pre-trained semantic recognition model, which can be a neural network-based model. This model can be trained using training samples, which may include image samples and corresponding line markings.
[0063] The actual circuit diagram can be a diagram that only includes the connection, and the endpoint of the connection on the chip is defined as a pad.
[0064] S330, Match the actual route map with the modified plan to determine the first position to be connected and the second position to be connected; the line connecting the first position and the second position intersects with the target line in the actual route map.
[0065] The scale of the actual circuit diagram and the modified plan may differ. Therefore, it's advisable to first register the actual circuit diagram and the modified plan based on the positions of each pad, unifying them to the same scale. Then, determine if the added lines intersect with the actual lines on the projection plane. During registration, first determine the positions of the pads or pins in the actual circuit diagram, selecting some relatively dispersed pads or pins as key locations. Also, determine the proportional relationship between the distances between key locations in the actual circuit diagram and the distances between key locations in the modified plan, and then unify the actual circuit diagram and the modified plan to the same scale based on this proportional relationship.
[0066] In some embodiments, since both the modified scheme and the actual circuit diagram may target only a portion of the packaged chip's circuitry, not all of it, determining the key locations is crucial during matching. In practice, multiple sets of key locations can be identified, each with a defined proportional relationship. The value with the highest repetition rate among these proportional relationships can then be determined. Based on this highest repetition rate proportional relationship, the actual circuit diagram and the modified scheme are unified under the same scale.
[0067] In some embodiments, since the actual circuit diagram is obtained by taking a photograph, it may be distorted, resulting in different proportions at different locations.
[0068] As an example, the actual route map can be divided into multiple grids, each corresponding to a set of key locations. A scale relationship can be determined for each set of key locations. When unifying the actual route map and the modified plan at the same scale, the areas corresponding to different grids are scaled using their respective scale relationships. Furthermore, since the actual route map exists as a whole, if the scale relationship between adjacent grids differs significantly, the scaling may appear abrupt. To increase smoothness, a gradual or interpolation method can be used for smooth scaling. For example, when scaling the image within the current grid area, the nearest neighboring grid to the pixel to be scaled can be determined, and the pixel is scaled based on the average of the scale relationships of that neighboring grid and the current grid.
[0069] As another example, for scaling the current pixel, the three nearest key positions to the current pixel to be scaled can be determined, and the pixel can be scaled based on the average of the proportional relationships corresponding to the three nearest key positions.
[0070] Identify the first and second positions corresponding to the intersecting lines, and the target lines that intersect with the lines connecting the first and second positions. These target lines are actual lines that are not to be deleted in the modification scheme.
[0071] S340, determine the first altitude of the target line.
[0072] For intersecting connections, the first approach is to stagger them by varying their heights. Therefore, it's necessary to determine the initial height of the target connections. Since the initial height of the target connections is difficult to determine in the image, a default value can be used. For example, this initial height can be determined based on the manufacturing process used in the packaged chip; it can be the maximum value of the process used in the packaged chip.
[0073] S350, based on the first height of the target line, determine the second height of the line connecting the first position and the second position, the second height being higher than the first height; so as to connect the first position and the second position based on the second height.
[0074] The maximum value of this second height can be 700um.
[0075] Specifically, when the first height is greater than or equal to 700um, the modified scheme is optimized to change the route and bypass the target connection.
[0076] The diameter of the modified line can be determined according to the size of the chip pad window, such as 0.5mil, 2.0mil, 5mil or 25mil, etc. The height and angle of the modified line can be freely adjusted, up to 700um, and can cross multiple line obstructions.
[0077] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.
[0078] Furthermore, the units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0079] Furthermore, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.
[0080] It should be noted that if the function is implemented as a software module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0081] In this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any such actual relationship or order between these entities or operations.
[0082] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.
Claims
1. A method for repairing circuits, characterized in that, The method includes: Determine the circuit connection diagram of the packaged chip, which is used to indicate the positional relationship of the pads and the connection relationship of the pads through the wires; Identify the lines to be modified, including pads that need to be connected and / or pads that need to be disconnected; Based on the circuit connection diagram and the circuit to be modified, a modification scheme is determined. The modification scheme includes one or more sets of positions, each set of positions including two positions to be connected or two positions to be deleted. The modification scheme also includes the metal material used for the positions to be connected. Based on the aforementioned modification scheme, the connection between every two positions of the connection to be deleted will be deleted; Alternatively, the packaged chip can be opened to remove the plastic encapsulation material from each connection point; When aluminum is used at the current connection point, a focused ion beam is used to etch the passivation layer on the surface to expose the conductive metal. When the current connection location is made of copper, a tungsten pad is grown using a focused ion beam to make the copper and the tungsten pad conductive. The length × width × thickness of the tungsten pad is greater than 60 μm × 60 μm × 2 μm. The current connection location is a relatively flat area that will not interfere with other circuits. A pressure welding process is used to connect the tungsten pads and conductive metal, or conductive metal to conductive metal, at every two locations to be connected.
2. The method according to claim 1, characterized in that, The step of deleting the connection between every two positions of the line to be deleted includes: Use tweezers to disconnect the wires that need to be removed.
3. The method according to claim 1, characterized in that, The method is applicable to a circuit repair system, which includes an ultrasonic wire bonding assembly, a focused ion beam assembly, a vision assembly, a fixture, and a data processing and control assembly. Based on the modified scheme, a pressure welding process is used to connect every two positions to be connected. Alternatively, delete the lines between any two lines to be deleted, including: When the current connection location uses aluminum metal, the data processing and control component controls the focused ion beam component to use a focused ion beam at the current connection location to etch the passivation layer on the surface and expose the conductive metal. When the current location to be connected is made of copper, the data processing and control component controls the focused ion beam component to grow a tungsten pad using a focused ion beam, so that the copper and the tungsten pad are connected. The current location to be connected is a relatively flat place that will not interfere with other circuits. The data processing and control component controls the ultrasonic wire bonding component to use a pressure welding process to connect the tungsten pad and conductive metal, or conductive metal to conductive metal, at every two positions to be connected. The data processing and control component controls the fixture to delete the connection between every two positions of the connection to be deleted; The vision component is used to acquire an image of the packaged chip and send the image of the packaged chip to the data processing and control component, which performs position matching based on the image of the packaged chip and the modification scheme.
4. The method according to claim 3, characterized in that, The circuit repair system also includes a display component, which displays a control interface based on the instructions of the data processing and control component. The control interface includes an image of the packaged chip and the modification scheme displayed in association with the image of the packaged chip.
5. The method according to claim 4, characterized in that, Also includes: Based on the modification scheme, the location that needs to be modified is determined, and the packaged chip is opened to expose the location that needs to be modified, and an image of the exposed area is obtained; The image of the exposed area is identified to obtain the actual circuit diagram of the exposed area; The actual route map is matched with the modified plan to determine the first position to be connected and the second position to be connected; the line connecting the first position and the second position intersects with the target line in the actual route map; Determine the first height of the line connecting the targets; Based on the first height of the target line, a second height of the line connecting the first position and the second position is determined, wherein the second height is higher than the first height; so that the first position and the second position can be connected based on the second height.
6. The method according to claim 5, characterized in that, The first height is determined based on the process used in the packaged chip.
7. The method according to claim 6, characterized in that, The first height is the maximum value of the process used in the packaged chip.
8. The method according to claim 5, characterized in that, The maximum value of the second height is 700um. When the first height is greater than or equal to 700um, the modification scheme is optimized.
Citation Information
Patent Citations
Tweezers used for circuit board wiring
CN108544387A
Apparatus and methods for making simultaneous electrical connections
US5288007A
System and method for circuit repair
US6205239B1