A trench diode avalanche shaping device and method of making the same

Abstract

The present application relates to a kind of trench diode avalanche shaping device and its preparation method, N+ type substrate layer has bevelled side wall, the side wall of N-type epitaxial layer is located on the extension line of bevelled side wall;Trench region is set below the upper surface of N-type epitaxial layer, several trenches are spaced apart in the trench region;P+ type ion implantation region extends from the upper surface of N-type epitaxial layer to the inside, including: trench implantation region and the arc surface injection area located on the both sides of trench implantation region;Trench implantation region is located below the trench region, and there is bump in the one-to-one correspondence with the trench in the trench implantation region.The present application sets up trench implantation region in P+ type ion implantation region and combines with the arc surface injection area on both sides, then combines bevelled terminal feature, arc surface injection area and bevelled terminal form equivalent positive bevel structure, and the electric field concentration is relieved.Several bumps carry out voltage division and inhibit the electric field concentration effect at metallurgical junction inflection point position, introduce electric field concentration into body, and use multi-point electric field concentration " quasi-uniform " trigger device.

Description

Technical Field

[0001] This invention belongs to the field of pulse power system technology, specifically relating to a trench diode avalanche shaping device and its fabrication method. Background Technology

[0002] A diode avalanche shaper (DAS) is a semiconductor device that utilizes the delayed breakdown effect to achieve its special function. In the reverse cutoff state, when a rapidly rising reverse pulse signal is applied to the device, its breakdown voltage exceeds the usual static breakdown voltage, i.e., the delayed breakdown effect. Upon reaching the maximum breakdown voltage, the portion of the electric field exceeding the critical breakdown electric field induces strong impact ionization, generating a large number of electron-hole pairs, also known as plasma. When this plasma fills the entire device, the device rapidly conducts; this process is called delayed avalanche. Based on delayed avalanche, the diode avalanche shaper successfully solves a problem faced by commonly used devices in traditional pulse power generators, such as thyristors, insulated-gate bipolar transistors, and MOS field-effect transistors: how to achieve rapid conduction speed while maintaining high breakdown voltage. Therefore, diode avalanche shapers have broad application prospects in pulse power systems.

[0003] For SiC-based DAS devices, the high hardness and stable chemical properties of SiC material preclude the application of wet etching. Furthermore, the positive trapezoidal etching morphology formed by dry etching exhibits a negative angled termination characteristic at the P+ / N- metallurgical junction of P+ / N- / N+ type SiC-based DAS devices based on N-type substrates. This means that the heavily doped P+ type region at the top loses more charge than the lightly doped N- type epitaxial region below. The depletion region expands less in the P-type region and contracts at the surface of the N-type region, resulting in a higher electric field at the termination surface than in the bulk, ultimately leading to unstable surface breakdown. This unreliable negative angled edge effect will severely restrict the widespread application of SiC-based DAS devices.

[0004] By adjusting the ion implantation mask morphology to create a "U-shaped" parallel planar junction in the P+ region, the angle between the P+ region and the etched sidewalls is effectively reduced to a positive oblique angle, thus mitigating electric field concentration at the surface. However, due to the unavoidable curvature of the P+ region, electric field concentration easily occurs at the junction inflection point. Reducing the junction curvature and the concentration gradient at the P+ / N- metallurgical junction can alleviate the electric field concentration effect to some extent, but achieving an optimal balance is difficult. Therefore, a diode avalanche shaping device capable of mitigating the electric field concentration effect is needed. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a diode avalanche shaper with a trenched U-junction coupled at an angled terminal. The technical problem to be solved by this invention is achieved through the following technical solution:

[0006] This invention provides a trench diode avalanche shaping device, comprising:

[0007] An N+ type substrate layer having a first upper surface, a second upper surface, and beveled sidewalls;

[0008] The second upper surface is located above the first upper surface, and the first upper surface is symmetrically distributed on both sides of the second upper surface;

[0009] The angled sidewall is located between the first upper surface and the second upper surface, and the acute angle between the angled sidewall and the first upper surface is θ1;

[0010] An N-type epitaxial layer is disposed on the second upper surface, wherein the sidewall of the N-type epitaxial layer is located on the extension line of the beveled sidewall;

[0011] A trench region is provided below the upper surface of the N-type epitaxial layer, and a plurality of trenches are provided at intervals within the trench region;

[0012] The P+ type ion implantation region extends from the upper surface of the N- type epitaxial layer to the interior and includes: a trench implantation region and arc-shaped implantation regions located on both sides of the trench implantation region;

[0013] The groove injection area is located below the groove area, and a number of protrusions are provided in the groove injection area corresponding one-to-one with the number of grooves.

[0014] The lower edge of the arc-shaped injection area is arc-shaped;

[0015] The first electrode is disposed on the lower surface of the N+ type substrate layer and is in ohmic contact with the N+ type substrate layer;

[0016] The second electrode is disposed on the upper surface of the N-type epitaxial layer and is in ohmic contact with the P+ type ion implantation region.

[0017] In one embodiment of the present invention, the oblique sidewall and the first upper surface form an acute angle θ1, where 70°≤θ1<90°.

[0018] In one embodiment of the present invention, the tangent at the position where the end of the arc injection region away from the trench injection region intersects with the upper surface of the N-type epitaxial layer forms an acute angle θ2 between it and the sidewall of the N-type epitaxial layer on the same side, where 5°≤θ1≤50°.

[0019] In one embodiment of the present invention, the horizontal distance between the intersection of the trench injection region, the arc injection region and the N-type epitaxial layer and the intersection of the arc injection region and the upper surface of the N-type epitaxial layer on the same side is m.

[0020] In one embodiment of the present invention, the horizontal distance x between the end of the arc injection region away from the trench injection region and the upper surface of the N-type epitaxial layer and the edge of the upper surface of the N-type epitaxial layer ranges from -m to +mμm.

[0021] In one embodiment of the present invention, the trench is an inverted trapezoidal structure, the top of the trench is located above its bottom, and the width w of the top of the trench is greater than the width of its bottom.

[0022] The width w of the top of the trench ranges from 0.5 to 2 μm;

[0023] The acute angle θ3 between the side of the groove and its bottom is 65°≤θ3<90°;

[0024] The vertical distance h from the top to the bottom of the trench ranges from 0.5 to 1.5 μm.

[0025] In one embodiment of the present invention, the two adjacent sides of two adjacent trenches intersect the upper surface of the N-type epitaxial layer, and the horizontal distance between the two intersecting positions is the spacing s between the two adjacent trenches, wherein the spacing s ranges from 0.5 to 5 μm.

[0026] In one embodiment of the present invention, the horizontal distance q between the side of the groove near the arc injection area and the arc injection area on the same side is in the range of s to 2s.

[0027] In one embodiment of the present invention, the doping concentration distribution in the P+ type ion implantation region exhibits a Gaussian distribution from top to bottom.

[0028] This invention also provides a method for fabricating a trench diode avalanche shaping device, used to fabricate the above-mentioned trench diode avalanche shaping device, the fabrication method comprising the following steps:

[0029] Step 1: Select an N+ type substrate layer and epitaxially grow an N- type epitaxial layer on the N+ type substrate layer;

[0030] Step 2: Deposit a first SiO2 layer on the N-type epitaxial layer, and form a first photoresist etching mask on the upper surface of the first SiO2 layer;

[0031] Step 3: After etching the first SiO2 layer, remove the first photoresist etching mask to form the first SiO2 etching mask;

[0032] Step 4: Dry etching is used to form several trenches to obtain the trench region;

[0033] Step 5: Remove the first SiO2 etching mask, deposit a second SiO2 layer on the upper surface of the N-type epitaxial layer, and form a second photoresist etching mask on the upper surface of the second SiO2 layer;

[0034] Step 6: Wet etching is used to etch the second SiO2 layer to form a first ion implantation mask with a trapezoidal morphology with beveled angles;

[0035] Step 7: Remove the second photoresist etching mask, perform P-type ion implantation and annealing on the first ion implantation mask to form a P+ type ion implantation region. The P+ type ion implantation region includes a trench implantation region and arc-shaped implantation regions located on both sides of the trench implantation region.

[0036] Step 8: Remove the first ion implantation mask, deposit a third SiO2 layer on the upper surface of the N-type epitaxial layer, and form a third photoresist etching mask on the upper surface of the third SiO2 layer;

[0037] Step 9: Etch the third SiO2 layer to make its two sides steep, forming a second SiO2 etching mask;

[0038] Step 10: Remove the third photoresist etching mask, dry etch the N-type epitaxial layer, and penetrate into the N+ type substrate layer to form beveled sidewalls;

[0039] Step 11: Remove the second SiO2 etching mask, and after cleaning, form the first electrode and the second electrode by sputtering below the N+ type substrate and above the P+ type ion implantation region, respectively, to obtain a trench diode avalanche shaping device.

[0040] The first electrode is an ohmic contact negative electrode, and the second electrode is an ohmic contact positive electrode.

[0041] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0042] The trench diode avalanche shaping device of the present invention combines the trench implantation region within the P+ type ion implantation region with the arc-shaped implantation regions on both sides, and further incorporates the beveled terminal feature (sidewalls with negative bevels on both sides). During device operation, the arc-shaped implantation region and the beveled terminal form an equivalent positive bevel structure, alleviating electric field concentration. Several trenches are etched on the upper surface of the N-type epitaxial layer to form a trench region, correspondingly forming several bumps within the P+ type ion implantation region. The voltage division through these bumps further suppresses the electric field concentration effect in the arc-shaped implantation region, especially at the metallurgical junction inflection point, introducing the electric field concentration into the bulk, further alleviating the electric field concentration effect and solving the problem of device damage caused by surface electric field concentration.

[0043] This invention not only alleviates electric field concentration at inflection points by introducing trenches, but also achieves a "quasi-uniform" distribution of several electric field concentration points within the device by reasonably setting the parameters of the trenches and the distribution of several trenches throughout the trench area after artificially introducing several trenches. By using multi-point electric field concentration to trigger the device, the thermal concentration effect of the device is alleviated; it also enables the device to conduct faster, thereby achieving a shorter turn-on time.

[0044] The method for fabricating the trench diode avalanche shaping device of the present invention involves etching several trenches in the N-type epitaxial layer before implanting to form a P+ type ion implantation region. This allows for deeper ion implantation in areas with trenches during ion implantation, forming a trench implantation region. The bumps can concentrate the electric field from the metallurgical junction inflection point of the P+ type ion implantation region into the bulk, thereby preventing electric field concentration on the surface and effectively mitigating the electric field concentration effect.

[0045] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0046] Figure 1 This is a schematic diagram of the structure of a trench diode avalanche shaping device provided in an embodiment of the present invention;

[0047] Figure 2 This is a schematic diagram of another trench diode avalanche shaping device provided in an embodiment of the present invention;

[0048] Figure 3 This is a diagram illustrating the fabrication steps of a trench diode avalanche shaping device provided in an embodiment of the present invention.

[0049] Icons: 10 - N+ type substrate; 11 - First upper surface; 12 - Second upper surface; 13 - Angled sidewall; 20 - N-type epitaxial layer; 30 - Trench region; 31 - Trench; 40 - P+ type ion implantation region; 41 - Trench implantation region; 42 - Arc implantation region; 421 - Metallurgical junction inflection point; 50 - First electrode; 60 - Second electrode; Detailed Implementation

[0050] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a trench diode avalanche shaping device and its preparation method based on the present invention.

[0051] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and specific understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.

[0052] Example 1

[0053] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of a trench diode avalanche shaping device provided in an embodiment of the present invention.

[0054] like Figure 1 As shown, a trench diode avalanche shaping device of the present invention includes: an N+ type substrate layer 10, an N- type epitaxial layer 20, a trench region 30, a P+ type ion implantation region 40, a first electrode 50, and a second electrode 60, wherein...

[0055] N+ type substrate 10 has a first upper surface 11, a second upper surface 12, and a beveled sidewall 13; the second upper surface 12 is located above the first upper surface 11, and the first upper surface 11 is symmetrically distributed on both sides of the second upper surface 12; the beveled sidewall 13 is located between the first upper surface 11 and the second upper surface 12, and the acute angle between the beveled sidewall 13 and the first upper surface 11 is θ1;

[0056] An N-type epitaxial layer 20 is disposed on the second upper surface 12, and the sidewall of the N-type epitaxial layer 20 is located on the extension line of the oblique sidewall 13;

[0057] The trench region 30 is disposed below the upper surface of the N-type epitaxial layer 20, and a plurality of trenches 31 are disposed at intervals within the trench region 30;

[0058] The P+ type ion implantation region 40 extends from the upper surface of the N- type epitaxial layer 20 to the interior and includes: a trench implantation region 41 and arc-shaped implantation regions 42 located on both sides of the trench implantation region 41; the trench implantation region 41 is located below the trench region 30, and a number of protrusions are provided in the trench implantation region 41 corresponding to a number of trenches 31.

[0059] The first electrode 50 is disposed on the lower surface of the N+ type substrate 10 and is in ohmic contact with the N+ type substrate 10;

[0060] The second electrode 60 is disposed on the upper surface of the N-type epitaxial layer 20 and is in ohmic contact with the P+ type ion implantation region 40.

[0061] In an optional embodiment, the N+ type substrate layer 10 is a SiC substrate.

[0062] In one optional embodiment, an acute angle θ1 is formed between the angled sidewall 13 and the first upper surface 11, where θ1 ranges from 70° to 90°. When θ1 = 90°, the area between the trapezoidal first upper surface 11 and the second upper surface 12 transforms into a rectangular shape. However, considering that the etching process of the device cannot form an absolute 90°, and assuming that the length and height of the upper base of the trapezoid remain constant, as θ1 increases, the length of the lower base of the trapezoid decreases, and the area of ​​the N-type epitaxial layer 20, which is located on the extension line of the angled sidewall 13 and also has a trapezoidal shape, becomes smaller. The depletion region forms at the pn junction between the P+ type ion implantation region 40 and the N- type epitaxial layer 20, and extends to both sides. According to the principle of charge conservation, when the area of ​​the N- type epitaxial layer 20 (N-region) decreases, the depletion region must expand wider to achieve charge conservation. Since the voltage of the pn junction is mainly borne by the depletion region, under the same voltage, the wider the depletion region, the smaller the electric field strength per unit area. Therefore, the device performance is optimal when θ1 = 90°. However, due to the limitations of the device etching process, it is preferable that the value of θ1 is within the range of 80-90° without affecting the device performance. Furthermore, even if the value of θ1 is within the range of 70-80°, the device performance will decrease slightly, but it is still within an acceptable range. However, if the angle of θ1 is lower than 70°, the electric field concentration of the device becomes more obvious. Therefore, the value of θ1 should be within the range of 70°-90°.

[0063] In an optional embodiment, the tangent at the point where the end of the arc injection region 42 away from the trench injection region 41 intersects the upper surface of the N-type epitaxial layer 20 forms an acute angle θ2 with the sidewall of the N-type epitaxial layer 20 on the same side, and the value of θ2 is in the range of 5°≤θ1≤50°.

[0064] In an optional embodiment, the horizontal distance between the intersection point of the trench injection region 41, the arc injection region 42 and the N-type epitaxial layer 20 (hereinafter referred to as the metallurgical junction inflection point 421) and the intersection point of the arc injection region 42 on the same side with the upper surface of the N-type epitaxial layer 20 is m.

[0065] It is worth noting that the value of θ2 is determined by m and the trapezoidal hypotenuse of the N-type epitaxial layer 20. When the value of θ1 is fixed, the value of m affects the curvature of the arc-shaped implantation region 42 at the inflection point 421 under the metallurgical junction. The arc-shaped implantation region 42 can be regarded as the bottom of a circle with a large radius. As m increases, the radius of this circle also increases, and the curvature at the inflection point 421 under the metallurgical junction becomes smaller, so the electric field concentration is not obvious. The intersection of this circle and the upper surface of the N-type epitaxial layer 20 is the side edge of the P+ type ion implantation region 40. The acute angle between the tangent at this position and the sidewall of the N-type epitaxial layer 20 on the same side is θ2. In other words, the larger m is, the larger the radius of the circle, and the larger θ2 is. At the same time, the curvature at the inflection point 421 of the metallurgical junction is smaller, and the electric field concentration is smaller. Conversely, if m is smaller, the radius of the circle is smaller, and the θ2 is smaller. At the same time, the curvature at the inflection point 421 of the metallurgical junction is larger, and the electric field concentration is greater. Although theoretically, the larger θ2 is, the better, considering process factors, θ2 cannot be made very large, because this would also require m to be as long as possible. Therefore, preferably, the value of θ2 is in the range of 40° to 50°. When the value of θ2 is less than 40°, the electric field concentration becomes more and more obvious, until it is less than 5°, when the electric field concentration is no longer acceptable.

[0066] Furthermore, there is no optimal value for m, because m is determined based on the optimal value of θ2 combined with the depth of the P+ type ion implantation region 40 formed by ion implantation. Taking a depth of 1.2 μm for the P+ type ion implantation region 40 and θ2 = 50° as an example, m = 7 μm is chosen in this case.

[0067] In an optional embodiment, the horizontal distance x between the intersection of the end of the arc injection region 42 away from the trench injection region 41 and the upper surface of the N-type epitaxial layer 20 and the edge of the upper surface of the N-type epitaxial layer 20 ranges from -m to +mμm.

[0068] In an optional embodiment, the trench 31 is an inverted trapezoidal structure, and the two adjacent sides of two adjacent trenches 31 intersect the upper surface of the N-type epitaxial layer 20 respectively; the top of the trench 31 is located above its bottom, and the width w of the top of the trench 31 is greater than the width of its bottom; the width w of the top of the trench 31 ranges from 0.5 to 2 μm; for a single trench 31, its parameters w, h and θ3, i.e., width, height and angle, are three parameters that affect each other. When h = 1 μm and θ3 = 80°, when w changes, the upper and lower bases of the inverted trapezoid will change accordingly. Specifically, when w decreases, the inverted trapezoid is compressed laterally, meaning the lower base of the inverted trapezoid decreases until it forms an inverted triangle (in reality, it will not actually form an inverted triangle). This makes the electric field concentration at the bottom corner of the bottom of the trench 31 more obvious, and even results in a strong local electric field concentration due to the superposition of the two bottom corners. Furthermore, the excessively small width w increases the manufacturing difficulty during device fabrication. Similarly, when w increases, the inverted trapezoid is stretched laterally, and the electric field concentration at the two bottom corners becomes too dispersed, which is not conducive to achieving uniformity. Therefore, the width w of the trench top is in the range of 0.5 to 2 μm.

[0069] In an optional implementation, similar to the value of w, when w and θ3 are fixed, as the height h of the inverted trapezoid increases, the inverted trapezoid will be stretched longitudinally, and the two base corners will gradually approach each other until the inverted trapezoid is called an inverted triangle, and the local electric field concentration will be more obvious; when the height h of the inverted trapezoid decreases, the inverted trapezoid will be flattened longitudinally, and the electric field concentration at the two base corners will be too dispersed, which is not conducive to the realization of uniformity. Therefore, the value range of the vertical distance h from the top of the trench 31 to its bottom is 0.5 to 1.5 μm.

[0070] In an alternative implementation, similar to the values ​​of w and h, w and h are fixed, and as θ3 increases, the inverted trapezoid approaches a rectangle, making the curvature at the two base corners larger and the electric field concentration effect more pronounced. Conversely, when θ3 decreases, the curvature decreases, and the electric field concentration slows down. However, an excessively small angle will cause the two base corners of the inverted trapezoid to gradually approach each other until they resemble an inverted triangle. Therefore, the acute angle θ3 between the side of the trench and its bottom is 65° ≤ θ3 < 90°.

[0071] Since the parameters w, h, and θ3 of a single trench are mutually influential, preferably, the value range of w is 1.6 to 1.7 μm, the value range of h is 0.7 to 0.9 μm, and the value range of θ3 is 80° to 85°, thus achieving multi-point and uniform electric field concentration.

[0072] In an optional implementation, the horizontal distance between two intersecting positions is the spacing s between two adjacent grooves 31, and the spacing s ranges from 0.5 to 5 μm.

[0073] In an optional embodiment, the horizontal distance q between the side edge of the trench 31 near the side edge of the arc injection region 42 and the metallurgical junction inflection point 421 on the same side ranges from s to 2s. When the horizontal distance q is too close, the electric fields at the bottom corner of the metallurgical junction inflection point 421 and the bottom corner of the trench 31 are prone to mutual interference or even superposition, forming a larger local electric field concentration; however, when the distance is too large, the electric field concentration at the edge of the device is no longer uniform, which is not conducive to achieving the goal of multiple current paths and uniform heat generation. Therefore, this distance q is controlled to be 1 to 2 spacings s.

[0074] In an optional implementation, the doping concentration distribution within the P+ type ion implantation region 40 exhibits a Gaussian distribution from top to bottom.

[0075] It is worth noting that by setting trenches 31, a "quasi-uniform" distribution of several electric field concentration points within the device is achieved. "Quasi-uniform" means that without trenches 31, the pn junction between the P+ type ion implantation region 40 and the N- type epitaxial layer 20 would be a straight line with a uniform electric field distribution. With the introduction of trenches 31, the bumps created by the trenches cause electric field concentration. This concentration can be used to alleviate the electric field intensity at the inflection point 421 under the metallurgical junction. Furthermore, with many trenches 31, by properly configuring the trench parameters, the degree of electric field concentration in each trench 31 can be made approximately uniform. Therefore, each trench 31 plays a role during device triggering, although it is not a straight line, hence the term "quasi-uniform." Using a "quasi-uniform" electric field distribution to trigger the device helps alleviate the thermal concentration effect.

[0076] The trench diode avalanche shaping device provided in this invention combines the trench implantation region within the P+ type ion implantation region with the arc-shaped implantation regions on both sides, and further incorporates the beveled terminal feature (sidewalls with negative bevels on both sides). During device operation, the arc-shaped implantation region and the beveled terminal form an equivalent positive bevel structure, alleviating electric field concentration. Several trenches are etched on the upper surface of the N-type epitaxial layer to form a trench region, correspondingly forming several bumps within the P+ type ion implantation region. The voltage division through these bumps further suppresses the electric field concentration effect in the arc-shaped implantation region, especially at the metallurgical junction inflection point, introducing the electric field concentration into the bulk, further alleviating the electric field concentration effect and solving the problem of device damage caused by surface electric field concentration.

[0077] The trench diode avalanche shaping device provided in this invention not only alleviates the electric field concentration at the inflection point by introducing trenches, but also achieves a "quasi-uniform" distribution of several electric field concentration points within the device by reasonably setting the parameters of the trenches and the distribution of several trenches throughout the trench area after artificially introducing several trenches. By using multi-point electric field concentration to trigger the device, the thermal concentration effect of the device is alleviated, and the device can be turned on more quickly, thereby achieving a shorter turn-on time.

[0078] Example 2

[0079] Please see Figure 2 , Figure 2 This is a schematic diagram of another trench diode avalanche shaping device provided in an embodiment of the present invention.

[0080] like Figure 2 As shown, after sequentially fabricating the N+ type substrate layer 10, the N- type epitaxial layer 20, the trench region 30, and the P+ type ion implantation region 40, beveled sidewalls are etched from top to bottom. The difference between this embodiment of the trench diode avalanche shaping device and the first embodiment is that in the first embodiment, the etching location is outside the P+ type ion implantation region 40, while in this embodiment, the etching location is inside the P+ type ion implantation region 40, i.e., the side edge of the P+ type ion implantation region 40 is etched away. When the etching location is outside the P+ type ion implantation region 40, the horizontal distance x between the side edge of the arc-shaped implantation region 42 and the upper surface edge of the N- type epitaxial layer 20 is positive; when the etching location is inside the P+ type ion implantation region 40, the value of x is negative, and the range of x is limited to -m to +mμm. If x is positive and its value is greater than m, the larger x is, the larger the area of ​​the N-type epitaxial layer 20 becomes. According to the charge balance principle, the depletion region expands more narrowly within the N-type epitaxial layer 20, and the electric field concentration becomes more pronounced under the same breakdown voltage. When x is negative and its value is less than m, the etching location will be very close to the trench location, and it will destroy the inflection point 421 of the small curvature metallurgical junction used to alleviate the edge electric field concentration, resulting in significant electric field concentration on the surface of the device on both sides of the bevel, thereby affecting the reliability of the device.

[0081] In one optional embodiment, the optimal spacing s of the trenches 31 is 1.5–5 μm. When the spacing of the trenches 31 is too small, the electric field concentration at the bottom corners of adjacent trenches 31 will cause interference, causing the electric field concentration of the later trench 31 to shield the electric field concentration of the earlier trench 31. This results in a phenomenon where the electric field concentration of the trenches 31 at both ends is severe and becomes less obvious closer to the middle, which is detrimental to the uniformity of the device. When s is too large, the trenches 31 are approximately independent of each other, and the electric field concentration at the bottom corners of each trench 31 is almost the same. However, the excessively large spacing reduces the number of trenches 31 that the device can accommodate, resulting in fewer current paths during device operation and hindering heat dissipation.

[0082] Example 3

[0083] In this embodiment, the method for fabricating the trench diode avalanche shaping device of the present invention includes the following steps:

[0084] Step 1: Select an N+ type substrate and epitaxially grow an N- type epitaxial layer on the N+ type substrate;

[0085] Step 2: Deposit a first SiO2 layer on the N-type epitaxial layer, and form a first photoresist etching mask on the upper surface of the first SiO2 layer;

[0086] Step 3: After etching the first SiO2 layer, remove the first photoresist etching mask to form the first SiO2 etching mask;

[0087] Step 4: Dry etching of the N-type epitaxial layer is used to form several trenches, thus obtaining the trench region;

[0088] Step 5: Remove the first SiO2 etching mask, deposit a second SiO2 layer on the upper surface of the N-type epitaxial layer, and form a second photoresist etching mask on the upper surface of the second SiO2 layer;

[0089] Step 6: Wet etching of the second SiO2 layer to form a first ion implantation mask with a trapezoidal morphology with beveled angles;

[0090] Step 7: Remove the second photoresist etching mask, perform P-ion implantation on the first ion implantation mask and anneal it to form a P+ type ion implantation region. The P+ type ion implantation region includes a trench implantation region and an arc implantation region located on both sides of the trench implantation region.

[0091] Step 8: Remove the first ion implantation mask, deposit a third SiO2 layer on the upper surface of the N-type epitaxial layer, and form a third photoresist etching mask on the upper surface of the third SiO2 layer;

[0092] Step 9: Etch the third SiO2 layer to make its two sides steep, forming the second SiO2 etching mask;

[0093] Step 10: Remove the third photoresist etching mask, dry etch the N-type epitaxial layer, and penetrate into the N+ type substrate layer to form beveled sidewalls;

[0094] Step 11: Remove the second SiO2 etching mask, and after cleaning, form the first electrode and the second electrode by sputtering below the N+ type substrate and above the P+ type ion implantation region, respectively, to obtain a trench diode avalanche shaping device.

[0095] The first electrode is an ohmic contact negative electrode, and the second electrode is an ohmic contact positive electrode.

[0096] The method for fabricating a trench diode avalanche shaping device provided in this embodiment of the invention involves etching several trenches in the N-type epitaxial layer before forming the P+ type ion implantation region. This allows for deeper ion implantation in areas with trenches during ion implantation, forming a trench implantation region. The bumps can concentrate the electric field from the metallurgical junction inflection point of the P+ type ion implantation region into the bulk, thereby preventing electric field concentration on the surface and effectively mitigating the electric field concentration effect.

[0097] Example 4

[0098] Please see Figure 3 , Figure 3 middle, Figure 3 a to Figure 3 v is a diagram illustrating the fabrication steps of a trench diode avalanche shaping device provided in an embodiment of the present invention.

[0099] like Figure 3 As shown in Figure a, an N+ type semiconductor is selected, and standard RCA cleaning is performed on the N+ type semiconductor to form an N+ type substrate layer 10. The thickness of the N+ type substrate layer 10 is 350 μm, and the doping concentration is 1 × 10⁻⁶. 18 ~1×10 20 cm -3 .

[0100] like Figure 3 As shown in Figure b, an N-type epitaxial layer 20 is epitaxially grown on an N+ type substrate layer 10. The N+ type substrate layer 10 and the N-type epitaxial layer 20 have the same doping type, but the N-type epitaxial layer 20 is lightly doped, and the N+ type substrate layer 10 has a higher ion doping concentration than the N-type epitaxial layer 20. Specifically, the thickness of the N-type epitaxial layer 20 is 4–6 μm, and the doping concentration is 1 × 10⁻⁶ μm. 14 cm -3 ~1×10 17 cm -3 .

[0101] like Figure 3As shown in Figure c, a first SiO2 layer is deposited on the N-type epitaxial layer 20; specifically, the first SiO2 layer is deposited on the N-type epitaxial layer 20 by plasma enhanced chemical vapor deposition (PECVD), and the thickness of the first SiO2 layer is 1 to 3 μm.

[0102] like Figure 3 As shown in d, a first photoresist (PR) etching mask is formed on the surface of the first SiO2 layer; specifically, photoresist is coated on the surface of the first SiO2 layer, and after exposure, development, post-baking and UV curing, a first photoresist etching mask is formed on the surface and both sides of the first SiO2 layer.

[0103] like Figure 3 As shown in e, the first SiO2 layer is etched according to the first photoresist etching mask; specifically, the first SiO2 layer is etched by ICP or RIE plasma dry etching, so that the two sides of the etched area of ​​the first SiO2 layer are steep and aligned with the two sides etched by the first photoresist.

[0104] like Figure 3 As shown in f, the first photoresist etching mask on the etched first SiO2 layer is removed to form the first SiO2 etching mask;

[0105] like Figure 3 As shown in g, the N-type epitaxial layer 20 is etched using a dry method according to the first SiO2 etching mask; specifically, the N-type epitaxial layer 20 is etched using ICP or RIE plasma dry method to form several trenches and trench regions 30 with steep sidewalls and an angle of 70° to 90° with the horizontal direction.

[0106] like Figure 3 As shown in h, the first SiO2 etching mask is removed; specifically, the first SiO2 etching mask is wet-etched over the entire device using a buffered oxide etchant (BOE).

[0107] like Figure 3 As shown in i, a second SiO2 layer is deposited on the surface of the N-type epitaxial layer 20 with etched trenches;

[0108] like Figure 3 As shown in j, a second photoresist etching mask is formed on the surface of the second SiO2 layer; specifically, photoresist is coated on the surface of the second SiO2 layer, and after exposure, development, post-baking and UV curing, a second photoresist etching mask is formed on the surface and both sides of the second SiO2 layer.

[0109] like Figure 3As shown in k, the second SiO2 layer is etched to form a first ion implantation mask with a trapezoidal morphology with an oblique angle; specifically, the second SiO2 layer is wet-etched above the entire device using a buffered oxide etchant (BOE) to form a first ion implantation mask with a trapezoidal morphology with an oblique angle.

[0110] like Figure 3 As shown in l, the second photoresist etching mask is removed;

[0111] like Figure 3 m and Figure 3 As shown in n, ion implantation is performed above a first ion implantation mask with an angled trapezoidal morphology, followed by rapid annealing at 1700°C for 10 minutes. Specifically, ions with a different doping type than those in the N-type epitaxial layer 20 are implanted. Subsequently, a P+ type ion implantation region 40 with a trench implantation region 41 and an arc-shaped implantation region 42 is formed on the upper surface of the N-type epitaxial layer 20. The arc-shaped implantation region 42 is symmetrically arranged on both sides of the trench implantation region 41, with an arc-shaped lower edge. The trench implantation region 41 has bumps corresponding to the trenches. The doping concentration distribution in the P+ type ion implantation region 40 is Gaussian from top to bottom, that is, from the upper surface of the P+ type ion implantation region 40 to the N-type epitaxial layer 20 below.

[0112] like Figure 3 As shown in o, the first ion implantation mask is removed;

[0113] like Figure 3 As shown in p, a third SiO2 layer is deposited on the upper surface of the N-type epitaxial layer 20 with trenches;

[0114] like Figure 3 As shown in q, a third photoresist etching mask is formed on the upper surface of the third SiO2 layer; specifically, photoresist is coated on the upper surface of the third SiO2 layer, and after exposure, development, post-baking and UV curing, the photoresist forms a third photoresist etching mask, which is located above the P+ type ion implantation region 40.

[0115] In an optional implementation, if the edge of the third photoresist etching mask is located in the vertical direction above the P+ type ion implantation region 40, then the horizontal distance between the two sides of the third photoresist etching mask and the side edge of the arc implantation region 42 on the same side is less than m, where m is the horizontal distance between the metallurgical junction inflection point 421 and the side edge of the arc implantation region 42 on the same side. The length of m is controlled by the morphology of the first ion implantation mask, which acts as a barrier layer. When the thickness of the barrier layer remains constant, the longer its inclined side, the longer m becomes.

[0116] like Figure 3As shown in r, the third SiO2 layer is etched according to the third photoresist etching mask, so that the two sides of the third SiO2 layer are steep, forming the second SiO2 etching mask; specifically, the third SiO2 layer is etched by ICP or RIE plasma dry etching, so that the two sides of the third SiO2 layer are steep and aligned with the two sides of the third photoresist etching mask.

[0117] like Figure 3 As shown in Figure s, the third photoresist etching mask is removed;

[0118] like Figure 3 As shown in t, the N-type epitaxial layer 20 is etched to penetrate into the N+ type substrate layer 10 according to the second SiO2 etching mask, so that the first upper surface of the substrate layer 10 and the N-type epitaxial layer 20 both form beveled terminal structures. The etching depth H is the projection length of the beveled sidewall and its extension in the vertical direction. To ensure the effect, the etching must penetrate into the interior of the N+ type substrate layer 10.

[0119] In an alternative implementation, overetching is defined as the etching start point being located within the range above the P+ type ion implantation region 40 in the vertical direction.

[0120] In another alternative embodiment, an etching start point that extends vertically beyond the P+ type ion implantation region 40, or whose edge coincides with the edge of the P+ type ion implantation region 40, is considered non-over-etching.

[0121] like Figure 3 As shown in u, the second SiO2 etching mask is removed, and standard RCA cleaning is performed.

[0122] like Figure 3 As shown in Figure v, a first electrode is formed by sputtering metal below the N+ type substrate layer 20, and a second electrode is formed by sputtering metal above the P+ type ion implantation region 40. The first electrode is an ohmic contact negative electrode, and the second electrode is an ohmic contact positive electrode. The width of the second electrode does not exceed the range above the P+ type ion implantation region 40 in the vertical direction.

[0123] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or device comprising said element. Terms such as "connected" or "linked" are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect. The orientations or positional relationships indicated by terms such as "upper," "lower," "left," and "right" are based on the orientations or positional relationships shown in the accompanying drawings and are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the invention.

[0124] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A trench diode avalanche shaping device, characterized in that, include: An N+ type substrate layer (10) having a first upper surface (11), a second upper surface (12), and a beveled sidewall (13); The second upper surface (12) is located above the first upper surface (11), and the first upper surface (11) is symmetrically distributed on both sides of the second upper surface (12); The oblique sidewall (13) is located between the first upper surface (11) and the second upper surface (12), and the acute angle between the oblique sidewall (13) and the first upper surface (11) is θ1; An N-type epitaxial layer (20) is disposed on the second upper surface (12), and the sidewall of the N-type epitaxial layer (20) is located on the extension line of the oblique sidewall (13); A trench region (30) is disposed below the upper surface of the N-type epitaxial layer (20), and a plurality of trenches (31) are disposed at intervals in the trench region (30); The P+ type ion implantation region (40) extends from the upper surface of the N- type epitaxial layer (20) into the interior and includes: a trench implantation region (41) and arc-shaped implantation regions (42) located on both sides of the trench implantation region (41); The groove injection area (41) is located below the groove area (30), and a number of protrusions are provided in the groove injection area (41) corresponding to the number of grooves (31). The lower edge of the arc injection area (42) is arc-shaped; The first electrode (50) is disposed on the lower surface of the N+ type substrate layer (10) and is in ohmic contact with the N+ type substrate layer (10); The second electrode (60) is disposed on the upper surface of the N-type epitaxial layer (20) and is in ohmic contact with the P+ type ion implantation region (40).

2. The trench diode avalanche shaping device according to claim 1, characterized in that, The oblique sidewall (13) and the first upper surface (11) form an acute angle θ1, where 70°≤θ1<90°.

3. The trench diode avalanche shaping device according to claim 1, characterized in that, The tangent at the point where the end of the arc injection area (42) away from the trench injection area (41) intersects the upper surface of the N-type epitaxial layer (20) forms an acute angle θ2 between it and the sidewall of the N-type epitaxial layer (20) on the same side, where 5°≤θ1≤50°.

4. The trench diode avalanche shaping device according to claim 1, characterized in that, The horizontal distance between the intersection of the trench injection area (41), the arc injection area (42) and the N-type epitaxial layer (20), and the intersection of the arc injection area (42) and the upper surface of the N-type epitaxial layer (20) on the same side, is m.

5. The trench diode avalanche shaping device according to claim 4, characterized in that, The horizontal distance x between the intersection of the end of the arc injection region (42) away from the trench injection region (41) and the upper surface of the N-type epitaxial layer (20) and the edge of the upper surface of the N-type epitaxial layer (20) ranges from -m to +mμm.

6. The trench diode avalanche shaping device according to claim 4, characterized in that, The groove (31) has an inverted trapezoidal structure, with the top of the groove (31) located above its bottom, and the width w of the top of the groove (31) is greater than the width of its bottom. The width w of the top of the groove (31) ranges from 0.5 to 2 μm; The side of the groove (31) forms an acute angle θ3 with its bottom, 65°≤θ3<90°; The vertical distance h from the top to the bottom of the groove (31) is in the range of 0.5 to 1.5 μm.

7. The trench diode avalanche shaping device according to claim 6, characterized in that, The two adjacent sides of two adjacent trenches (31) intersect the upper surface of the N-type epitaxial layer (20) respectively. The horizontal distance between the two intersecting positions is the spacing s between the two adjacent trenches (31), and the value of the spacing s ranges from 0.5 to 5 μm.

8. The trench diode avalanche shaping device according to claim 7, characterized in that, The horizontal distance q between the side of the groove (31) near the arc injection area (42) and the arc injection area (42) on the same side ranges from s to 2s.

9. The trench diode avalanche shaping device according to claim 1, characterized in that, The doping concentration distribution in the P+ type ion implantation region (40) exhibits a Gaussian distribution from top to bottom.

10. A method for fabricating a trench diode avalanche shaping device, characterized in that, The method for fabricating the trench diode avalanche shaping device according to any one of claims 1 to 9 includes the following steps: Step 1: Select an N+ type substrate layer and epitaxially grow an N- type epitaxial layer on the N+ type substrate layer; Step 2: Deposit a first SiO2 layer on the N-type epitaxial layer, and form a first photoresist etching mask on the upper surface of the first SiO2 layer; Step 3: After etching the first SiO2 layer, remove the first photoresist etching mask to form the first SiO2 etching mask; Step 4: Dry etching is used to form several trenches, resulting in the trench region; Step 5: Remove the first SiO2 etching mask, deposit a second SiO2 layer on the upper surface of the N-type epitaxial layer, and form a second photoresist etching mask on the upper surface of the second SiO2 layer; Step 6: Wet etching is used to etch the second SiO2 layer to form a first ion implantation mask with a trapezoidal morphology with beveled angles; Step 7: Remove the second photoresist etching mask, perform P-type ion implantation and annealing on the first ion implantation mask to form a P+ type ion implantation region. The P+ type ion implantation region includes a trench implantation region and arc-shaped implantation regions located on both sides of the trench implantation region. Step 8: Remove the first ion implantation mask, deposit a third SiO2 layer on the upper surface of the N-type epitaxial layer, and form a third photoresist etching mask on the upper surface of the third SiO2 layer; Step 9: Etch the third SiO2 layer to make its two sides steep, forming a second SiO2 etching mask; Step 10: Remove the third photoresist etching mask, dry etch the N-type epitaxial layer, and penetrate into the N+ type substrate layer to form beveled sidewalls; Step 11: Remove the second SiO2 etching mask, and after cleaning, form the first electrode and the second electrode by sputtering below the N+ type substrate and above the P+ type ion implantation region, respectively, to obtain a trench diode avalanche shaping device. The first electrode is an ohmic contact negative electrode, and the second electrode is an ohmic contact positive electrode.

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