A preparation method of a micro-LED chip array based on maskless secondary epitaxy

Abstract

The application discloses a preparation method of a micro-LED chip array based on maskless secondary epitaxy. The method comprises the following steps: performing dry etching on a GaN template to form a stress relaxation patterned GaN template, and then performing selective secondary epitaxy of a multi-quantum well structure and the like on the stress relaxation patterned GaN template. The method effectively avoids dry etching on the multi-quantum well region, thereby avoiding sidewall etching damage of the multi-quantum well. The stress relaxation patterned GaN template effectively relaxes the stress suffered by n-type doped GaN. The pre-stress layer grown on the stress relaxation patterned GaN template partially relaxes the compressive stress suffered and expands the in-plane lattice constant, thereby reducing the energy required for indium incorporation and increasing the incorporation of indium in the multi-quantum well. In the process of preparing the stress relaxation patterned GaN template, etching is performed so that only the top surface of the GaN micropillar array is a c-plane, serving as a growth surface. The selective secondary epitaxy growth does not require an additional mask, thereby reducing the complexity of the micro-LED preparation process.

Description

Technical Field

[0001] This invention relates to the field of semiconductor devices, and more specifically to a method for fabricating a micro-LED chip array based on maskless secondary epitaxy. Background Technology

[0002] Large-size blue light-emitting diodes (LEDs) based on group III nitride semiconductors play a crucial role in solid-state lighting due to their high efficiency and stability. When applications shift to the display field, ultra-small, full-color micro-LED devices become essential, especially for augmented reality (AR) and virtual reality (VR) applications. Compared to liquid crystal displays (LCDs), organic light-emitting diodes (OLEDs) offer significant advantages in display applications, particularly in brightness, contrast ratio, response speed, and stability.

[0003] As devices continue to miniaturize, micro-LEDs suffer from a gradual decrease in efficiency as size decreases. Studies have shown that the impact of defect recombination on micro-LEDs becomes more severe with smaller dimensions. These defects likely originate primarily from sidewall dangling bonds and damage caused by dry etching. Although the damage from dry etching is only at a nanometer-scale depth on the micro-LED sidewall surface, severe non-radiative recombination occurs in the sidewall region due to carrier diffusion and the high recombination rate of sidewall surface states. Currently, sidewall repair methods commonly used to address etching damage to the micro-LED chip sidewalls include atomic-layer deposition (ALD) of silicon dioxide layers and KOH solution etching (Opt. Express 26, 21324 (2018), Appl. Phys. Express 12, 097004 (2019)). However, these sidewall repair methods cannot completely eliminate etching damage, and micro-LEDs still experience a sharp drop in efficiency as size decreases. Furthermore, in top-down micro-LED processes, sidewall damage caused by dry etching cannot be avoided.

[0004] On the other hand, due to the excessive lattice mismatch between indium nitride (InN) and gallium nitride (GaN), high-indium (In) composition, long-wavelength micro-LEDs also face the problem of low efficiency. This efficiency decrease with increasing wavelength mainly stems from the high defect density caused by low-temperature growth and the strong polarization electric field caused by the compressive strain of InGaN. The strong polarization electric field in the quantum well causes electrons and holes to be spatially separated, which severely reduces the radiative recombination efficiency of long-wavelength LEDs. On the other hand, the indium incorporation efficiency is related to the strain energy required for In-N bond bonding. When there is strong compressive strain in the quantum well, indium incorporation becomes more difficult due to the need for higher strain energy (J. Cryst. Growth 312, 735–749 (2010)). Therefore, alleviating the compressive strain in InGaN helps to improve the radiative recombination efficiency in the quantum well and increase the indium incorporation efficiency.

[0005] Eliminating sidewall etching damage in micro-LEDs and addressing the compressive strain problem in InGaN are crucial for achieving high-efficiency long-wavelength LEDs. Currently, the mainstream fabrication process for long-wavelength micro-LEDs is top-down etching. In the past, a few have used bottom-up methods to fabricate LEDs, mainly in the field of molecular beam epitaxy (MBE) for nanopillar LEDs, and a small number of studies have involved metal-organic chemical vapor deposition (MOCVD). Nanopillar LEDs obtained through top-down secondary epitaxy can effectively relax the compressive stress on InGaN, which helps to incorporate indium into the quantum well. Nanopillar LED structures fabricated through secondary epitaxy have been shown to effectively improve the luminous efficiency of long-wavelength LEDs (Photon. Res. 10, 2809 (2022), Appl. Phys. Lett. 122, 151103 (2023)). However, MBE (Metal-Based Epitaxy) is difficult to apply to the large-scale mass production of micro-LEDs due to its low yield and high cost. Furthermore, the secondary epitaxy method for nanopillar LEDs requires nanoscale patterned masks, which is incompatible with existing micro-LED processes. In recent years, some studies have employed MOCVD (Metal-Based Chemical Epitaxy) to perform secondary epitaxy of micro-LEDs on patterned silicon dioxide masks. This method effectively avoids etching damage and exhibits significant stress relaxation effects. However, the fabrication process for silicon dioxide masks is complex and costly (ACS Photonics 2020, 7, 411 (2020), ACS Photonics 9, 2073 (2022)). Therefore, a maskless secondary epitaxy scheme based on MOCVD is needed to reduce cost and process complexity, thereby improving the luminous efficiency of long-wavelength micro-LEDs. Summary of the Invention

[0006] To address the problems existing in the prior art, this invention proposes a method for fabricating micro-LED chip arrays based on maskless secondary epitaxy. This invention differs from the current industry method of fabricating micro-LED chips by top-down etching. Instead, it first patterns the GaN template and then completes the fabrication of the micro-LED chip array through maskless secondary epitaxy.

[0007] The present invention provides a method for fabricating a micro-LED chip array based on maskless secondary epitaxy, comprising the following steps:

[0008] 1) Provide a substrate and place it into a metal-organic chemical vapor deposition (MOCVD) reaction chamber. Using the MOCVD method, grow an unintentionally doped GaN layer and an n-type doped GaN layer sequentially from bottom to top on the substrate to obtain a planar GaN template.

[0009] 2) After growth is complete, the planar GaN template is removed from the MOCVD reaction chamber and cleaned.

[0010] 3) The planar GaN template is dry etched using photolithography or nanoimprinting to etch the n-type doped GaN layer to form a GaN micropillar array. The GaN micropillars are frustum-shaped with tilted sidewalls. The bottoms of adjacent GaN micropillars are connected to each other to obtain a stress-relaxed patterned GaN template.

[0011] The bottom of the GaN micropillar array in the stress-relaxed patterned GaN template is interconnected and there is no c-plane for growth. The sidewalls of the GaN micropillar array are curved and there are no complete planar crystal planes or c-planes for growth. Only the top surface of the GaN micropillar array is a c-plane and serves as the growth surface.

[0012] Stress-relaxed patterned GaN templates effectively relax the stress on n-type doped GaN layers after patterning.

[0013] 4) The stress-relaxed patterned GaN template is cleaned and returned to the MOCVD reaction chamber;

[0014] 5) On a GaN micropillar array with a stress-relaxed patterned GaN template, an n-type doped GaN thin layer is epitaxially grown in a secondary manner. The n-type doped GaN thin layer and the GaN micropillar array together constitute the n-type doped GaN layer after secondary growth. On the n-type doped GaN layer after secondary growth, a prestress layer, a multi-quantum well layer, and a p-type doped GaN layer are selected and grown sequentially from bottom to top in a secondary epitaxial manner. The n-type doped GaN thin layer, prestress layer, multi-quantum well layer, and p-type doped GaN layer are grown only on the top surface of the GaN micropillar array, which serves as the growth surface, and are all patterned. The grown n-type doped GaN layer, prestressed layer, multi-quantum well layer, and p-type doped GaN layer form a micro-LED epitaxial wafer array. The pattern of the micro-LED epitaxial wafer array is consistent with the pattern of the stress-relaxed patterned GaN template, thus obtaining the micro-LED epitaxial wafer. The patterned multi-quantum well layer is not etched by dry etching, thereby avoiding sidewall etching damage of the multi-quantum well. The prestressed layer grown on the stress-relaxed patterned GaN template experiences partial relaxation of the compressive stress, and the in-plane lattice constant is expanded, thereby reducing the energy required for indium incorporation and effectively increasing the incorporation of indium in the multi-quantum well.

[0015] 6) Place the micro-LED epitaxial wafers that have undergone secondary epitaxy in an alkaline solution to perform sidewall etching on the micro-LED epitaxial wafer array. The sidewalls of the micro-LED epitaxial wafer array are etched into the predetermined shape to obtain the micro-LED epitaxial wafers.

[0016] LED chip array.

[0017] In step 1), the substrate is sapphire (Al2O3), silicon substrate (Si), or silicon carbide (SiC); the thickness of the n-type doped GaN layer is between 1.0 μm and 8 μm.

[0018] In step 2), the cleaning process involves acid washing followed by organic cleaning. Acid washing uses a sulfuric acid (H₂SO₄) to hydrogen peroxide (H₂O₂) volume ratio of 3:1 to 10:1, and is performed in a water bath at 80–100°C for 3–15 minutes. Organic cleaning involves ultrasonic cleaning at room temperature in acetone, anhydrous ethanol, and water, each for 3–15 minutes.

[0019] In step 3), a stress-relaxed patterned GaN template is obtained using photolithography or nanoimprinting, including the following steps:

[0020] a) Using photoresist:

[0021] i. Photoresist is uniformly spin-coated onto the surface of the n-type doped GaN layer of a planar GaN template. A periodic pattern of a micron-scale pattern array is formed on the photoresist using photolithography to obtain a patterned photoresist.

[0022] ii. A dry etching method is used, with patterned photoresist as a mask, to etch the GaN template, etching the n-type doped GaN layer to form a GaN micropillar array. During etching, some photoresist is removed, leaving residual photoresist on the growth surface. The GaN micropillars are frustum-shaped with tilted sidewalls, and the bottoms of two adjacent GaN micropillars are connected to each other, thus obtaining a stress-relaxed patterned GaN template.

[0023] b) Using nano-imprint adhesive:

[0024] i. A nanoimprint adhesive is uniformly spin-coated onto the surface of an n-type doped GaN layer in a planar GaN template. A periodic pattern of a micron-scale pattern array is formed on the nanoimprint adhesive using the nanoimprint method to obtain a patterned nanoimprint adhesive.

[0025] ii. A dry etching method is used, with patterned nanoimprint stencil as a mask, to etch the GaN template, etching the n-type doped GaN layer to form a GaN micropillar array. During etching, some nanoimprint stencil is removed, leaving residual nanoimprint stencil on the growth surface. The GaN micropillars are frustum-shaped with tilted sidewalls, and the bottoms of two adjacent GaN micropillars are connected to each other, thus obtaining a stress-relaxed patterned GaN template.

[0026] In step a)i), the period of the micron-scale pattern array is between 1.5 μm and 50 μm, and the diameter of the micron-scale pattern is between 1 μm and 30 μm; in step a)ii), the etching depth is between 500 nm and 5 μm.

[0027] In step b)i), the period of the micron-scale patterned array is between 1 μm and 20 μm, and the diameter of the micron-scale pattern is between 500 nm and 10 μm; in step b)ii), the etching depth is between 300 nm and 5 μm.

[0028] In step 4), the cleaning process employs a combination of acid washing and organic cleaning. Acid washing removes residual photoresist or nanoimprint adhesive from the growth surface, while organic cleaning removes organic contaminants from the surface. Acid washing uses a sulfuric acid (H₂SO₄) to hydrogen peroxide (H₂O₂) volume ratio of 3:1 to 10:1, and is performed in a water bath at 80–100°C for 3–15 minutes. Organic cleaning involves sequential ultrasonic cleaning at room temperature in acetone, anhydrous ethanol, and water, each for 3–15 minutes.

[0029] In step 5), the thickness of the n-type doped GaN layer is between 1.0 μm and 8 μm, and the concentration of n-type doping is 1 × 10⁻⁶. 18 cm -3 ~5×10 20 cm -3 Between; the prestressed layer uses In x Ga 1-x N / GaN superlattice or In x Ga 1-x The structure consists of an N-layer monolayer, where x represents the indium content in the prestressed layer, ranging from 1% to 20%; the multi-quantum-well layer is a periodic In layer. y Ga 1-y In N / GaN, y represents the indium composition in the multiple quantum well layer, ranging from 10% to 50%; the thickness of the p-type doped GaN layer ranges from 50 nm to 300 nm, and the p-type doping concentration is 1 × 10⁻⁶. 18 cm -3 ~5×10 20 cm -3 between.

[0030] In step 6), the shape is set to a cylinder, a frustum, an inverted frustum, a trapezoid, or an inverted trapezoid.

[0031] Advantages of this invention:

[0032] (1) In the traditional top-down fabrication process of micro-LED chips, dry etching of the LED quantum well region cannot be avoided; the present invention forms a stress-relaxed patterned GaN template by dry etching of GaN template, and then selects a region for secondary epitaxial multiple quantum wells and other structures on the stress-relaxed patterned GaN template, which effectively avoids dry etching of the multiple quantum well region and thus avoids sidewall etching damage of the multiple quantum well.

[0033] (2) Stress-relaxed patterned GaN template After patterning the n-type doped GaN layer, the stress on the n-type doped GaN is effectively relaxed; the prestress layer grown on the stress-relaxed patterned GaN template is partially relaxed under the compressive stress, and the in-plane lattice constant is expanded, thereby reducing the energy required for indium (In) incorporation and effectively increasing the incorporation of indium in multiple quantum wells.

[0034] (3) In the selected area secondary epitaxy process, no additional mask is required to achieve the selected area secondary epitaxy; in the process of preparing the stress-relaxed patterned GaN template, the bottom of the GaN micro pillar array of the stress-relaxed patterned GaN template is interconnected due to etching, and there is no c-plane for growth. The sidewalls of the GaN micro pillar array are curved, and there is no complete planar crystal plane or c-plane for growth. Only the top surface of the GaN micro pillar array is a c-plane, which serves as the growth surface; based on this patterned GaN template selected area secondary epitaxy method, no additional mask is required, which reduces the complexity of the micro-LED fabrication process. Attached Figure Description

[0035] Figure 1 This is a flowchart of the fabrication method of micro-LED chip array based on maskless secondary epitaxy according to the present invention;

[0036] Figure 2 A cross-sectional view of a planar GaN template is obtained for an embodiment of the fabrication method of a micro-LED chip array based on maskless secondary epitaxy according to the present invention;

[0037] Figure 3 A cross-sectional view of a stress-relaxed patterned GaN template is obtained for an embodiment of the fabrication method of a micro-LED chip array based on maskless secondary epitaxy according to the present invention.

[0038] Figure 4 A cross-sectional view of a micro-LED epitaxial wafer array is obtained for an embodiment of the fabrication method of micro-LED chip array based on maskless secondary epitaxy according to the present invention;

[0039] Figure 5 A cross-sectional view of a micro-LED chip array is obtained for an embodiment of the fabrication method of micro-LED chip array based on maskless secondary epitaxy according to the present invention;

[0040] Figure 6 The image shows the results obtained from an embodiment of the fabrication method of micro-LED chip array based on maskless secondary epitaxy according to the present invention, wherein (a) is a scanning electron microscope (SEM) image and (b) is the corresponding cathodoluminescence (CL) image;

[0041] Figure 7 The image shows the photoluminescence (PL) spectrum under a 405 nm laser in an embodiment of the fabrication method of micro-LED chip array based on maskless secondary epitaxy according to the present invention. Detailed Implementation

[0042] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0043] The fabrication method of micro-LED chip array based on maskless secondary epitaxy in this embodiment is as follows: Figure 1 As shown, it includes the following steps:

[0044] 1) A sapphire substrate 101 with a thickness of 430 micrometers is provided. The substrate is placed in an MOCVD reaction chamber, and the temperature is raised to 1000°C in an H2 atmosphere using MOCVD. After 10 minutes of purging, the temperature is lowered to 540°C, and TMGa, NH3, and H2 are introduced to grow a nucleation layer on the substrate. The temperature is then raised to 1040°C, and an unintentionally doped GaN layer 102 with a thickness of 2 micrometers is grown on the nucleation layer. The temperature is then raised to 1060°C to grow an n-type doped GaN layer 103 with a thickness of 3 micrometers and an n-type doping concentration of 2 × 10⁻⁶. 19 cm -3 This yields a planar GaN template, such as... Figure 2 As shown;

[0045] 2) After growth is complete, the planar GaN template is removed from the MOCVD reaction chamber and treated with sulfuric acid (H2SO4): hydrogen peroxide (H2O2).

[0046] The volume ratio was 5:1. The mixture was cleaned for 10 minutes in a 100°C water bath, and then ultrasonically cleaned for 5 minutes each in acetone, anhydrous ethanol, and water at room temperature.

[0047] 3) Using nanoimprinting:

[0048] i. A nanoimprint adhesive with a thickness of 1.0 μm is uniformly spin-coated onto the surface of an n-type doped GaN layer on a planar GaN template. A periodic pattern of a micron-scale pattern array is formed on the nanoimprint adhesive using a nanoimprinting method, resulting in a patterned nanoimprint adhesive. The height of the nanoimprint adhesive pillars is 1.8 μm, the residual adhesive thickness at the gaps between the nanoimprint adhesive pillars is 150 nm, the pattern is cylindrical, the period is 3.0 μm, the diameter is 2.1 μm, and the height is 1.8 μm.

[0049] ii. A planar GaN template with patterned nanoimprinted resist on its surface is placed in the chamber of an inductively coupled plasma (ICP) etching machine to etch the GaN template. First, the residual resist with a thickness of 150 nm at the gaps between the imprinted patterns is etched in an oxygen atmosphere. After the residual resist is etched, using patterned resist pillars as masks, the n-type doped GaN layer is subjected to ICP etching in an atmosphere of boron trichloride, chlorine, and argon (BCl3, Cl2, Ar). The etched portion of the n-type doped GaN layer, such as... Figure 3 As shown, Figure 3 In the diagram, 113 is the un-etched n-type doped GaN layer with a thickness of 1.3 micrometers, and 114 is the GaN micropillar array retained after etching with a thickness of 1.7 micrometers. There are residual nanoimprinted adhesives on the growth surface. The height of the nanoimprinted adhesive pillars is reduced by 800 nanometers, and the remaining height of the nanoimprinted adhesive pillars is 1 micrometer. That is, the etching selectivity ratio of nanoimprinted adhesives to n-type doped GaN layers is approximately 0.47:1, forming a GaN micropillar array. The GaN micropillars are frustum-shaped with tilted sidewalls. The bottoms of two adjacent GaN micropillars are connected to each other, meaning there are no or few residual c-plane GaNs at the bottom, thus obtaining a stress-relaxed patterned GaN template.

[0050] The bottom of the GaN micropillar array in the stress-relaxed patterned GaN template is interconnected and there is no c-plane for growth. The sidewalls of the GaN micropillar array are curved and there are no complete flat crystal planes or c-planes for growth. Only the top surface of the GaN micropillar array is a c-plane and serves as the growth surface.

[0051] Stress-relaxed patterned GaN templates effectively relax the stress on n-type doped GaN layers after patterning.

[0052] 4) The stress-relaxed patterned GaN template is first cleaned with sulfuric acid (H2SO4): hydrogen peroxide (H2O2) in a volume ratio of 5:1 in a 100°C water bath for 10 minutes to remove residual nanoimprint adhesive on the growth surface. Then, it is ultrasonically cleaned for 5 minutes each in acetone, anhydrous ethanol and water at room temperature to remove organic contaminants on the surface and then returned to the MOCVD reaction chamber.

[0053] 5) On a stress-relaxed patterned GaN template, the temperature is raised to 1060℃ in an atmosphere of H2 and NH3. TMGa, NH3, and H2 are introduced, and a 0.3 μm thick n-type doped GaN thin layer is selectively grown on the growth surface of the GaN micropillar array 114. The n-type doping concentration is 2 × 10⁻⁶. 19 cm -3The n-type doped GaN thin layer grown by secondary epitaxy and the GaN micron pillar array together constitute the n-type doped GaN layer 124 after secondary growth, and the thickness of the n-type doped GaN layer 124 after secondary growth is 2.0 micrometers. The gas atmosphere is switched to N2 and NH3, and the temperature is lowered to 950°C. TEGa, TMI, NH3, SiH4 and N2 are introduced to grow a prestressed layer 125 with a thickness of 120 nanometers. A multi-quantum well layer 126 with a thickness of 90 nanometers is then grown, in which TMI is introduced. A 2.5 nm thick InGaN quantum well layer was grown using EGa, TMIn, NH3, and N2 at a growth temperature of 710 °C. Then, a 12.5 nm thick GaN barrier layer was grown using TEGa, NH3, and N2 at a growth temperature of 850 °C. Subsequently, the gas atmosphere was switched to H2 and NH3, and the temperature was raised to 950 °C. Then, TMGa, NH3, Cp2Mg, and H2 were introduced to grow a 90 nm thick p-type doped GaN layer (127) with a p-type doping concentration of 1 × 10⁻⁶. 19 cm -3 ,like Figure 4 As shown, the prestressed layer 125 is In x Ga 1-x The N / GaN superlattice has an indium composition of approximately 5% and a period number of 24; the multi-quantum well layer 126 is made of In. y Ga 1-y The N / GaN quantum wells have 6 periods and an indium composition of approximately 28%. The n-type doped GaN thin layer, prestress layer, multi-quantum well layer, and p-type doped GaN layer, grown epitaxially in a secondary manner, are all patterned and grown only on the top surface of the GaN micropillar array serving as the growth plane. The n-type doped GaN layer 124, prestress layer 125, multi-quantum well layer 126, and p-type doped GaN layer 127, after secondary growth, form a micro-LED epitaxial wafer array. The pattern of the micro-LED epitaxial wafer array is consistent with the pattern of the stress-relaxed patterned GaN template, resulting in a micro-LED epitaxial wafer. The patterned multi-quantum well layer was not etched using dry etching, thus avoiding sidewall etching damage to the multi-quantum wells. The prestress layer grown on the stress-relaxed patterned GaN template experiences partial relaxation of compressive stress, resulting in an expansion of the in-plane lattice constant. This reduces the energy required for indium incorporation, effectively increasing indium incorporation into the multi-quantum wells.

[0054] 6) The micro-LED epitaxial wafers that have undergone selective area secondary epitaxy are immersed in a KOH aqueous solution for wet etching. The KOH aqueous solution is prepared by dissolving 10g of KOH solid in 300mL of water. The etching conditions are 70℃ water bath heating for 10min. The sidewalls of the micro-LED epitaxial wafer array are etched at a much higher rate in the KOH aqueous solution than the top c-plane GaN. Therefore, the micro-LED chip array is etched into a cylindrical shape with steep sidewalls after etching. The array period is 3.0 μm, the diameter is 2.0 μm, and the height is 2.3 μm. Figure 5 As shown, Figure 5 In the diagram, 134 is an n-type doped GaN layer grown after etching, with a thickness of 2.0 micrometers; 135 is a prestressed layer after etching, with a thickness of 120 nanometers; 136 is a multi-quantum well layer after etching, with an indium content of approximately 28% and a thickness of 90 nanometers; and 137 is a p-type doped GaN layer after etching, with a thickness of 90 nanometers, thus obtaining a micro-LED chip array.

[0055] Figure 6 The images shown are SEM images and corresponding CL images of the micro-LED chip array in this embodiment. The SEM images show that a close-packed micro-LED chip array with a period of 3 micrometers and a diameter of approximately 2 micrometers was obtained through secondary epitaxy. This chip array achieves a pixel per inch (PPI) of 8466. The CL images show that the light emission of the micro-LED chip array originates from the plateau region of the pattern, specifically the top c-plane region retained by the stress-relaxed patterned GaN template. The gaps in the pattern do not participate in light emission, indicating that selective epitaxy of the micro-LED chips was achieved without a mask. Furthermore, the vast majority of the micro-LED chips effectively emit light, exhibiting good brightness uniformity.

[0056] Figure 7 This is the PL spectrum of the micro-LED chip under 405nm laser light in this embodiment, where sample A corresponds to the micro-LED chip with InGaN stress-free release, and sample B corresponds to the micro-LED chip with InGaN lamination stress relaxed by patterned secondary epitaxy. Figure 7 In the figure, the dashed line represents the PL spectrum of sample A, and the solid line represents the PL spectrum of sample B. As can be seen from the figure, the peak PL wavelength of sample A is 485 nm, while that of sample B is 540 nm. The stress relaxation effect brought about by patterned secondary epitaxy causes a 55 nm redshift in the emission wavelength of the quantum well, indicating that the strain relaxation of InGaN effectively improves the indium incorporation in the quantum well.

[0057] In the above micro-LED chip fabrication process, a periodic micron-sized patterned GaN array was prepared by etching a GaN template. Then, a quantum well was grown on top of the pattern using a maskless secondary epitaxy method, thus successfully fabricating the micro-LED chip array. This fabrication process avoids ICP etching of the quantum well region, preventing etching damage to the quantum well area of ​​the micro-LED chip. Furthermore, after patterning, the residual compressive stress on the GaN template is significantly relaxed. Based on this, the compressive stress of the secondary epitaxial InGaN structure is also significantly relaxed, thereby increasing indium incorporation in the quantum well and redshifting the quantum well emission wavelength. Therefore, this micro-LED chip fabrication process has advantages such as maskless secondary epitaxy, elimination of etching damage, and relaxation of InGaN compressive stress.

[0058] Finally, it should be noted that the purpose of disclosing the embodiments is to help further understand the present invention. However, those skilled in the art will understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the claims.

Claims

1. A method for fabricating a micro-LED chip array based on maskless secondary epitaxy, characterized in that, The preparation method includes the following steps: 1) Provide a substrate and place it into a metal-organic chemical vapor deposition (MOCVD) reaction chamber. Using the MOCVD method, grow an unintentionally doped GaN layer and an n-type doped GaN layer sequentially from bottom to top on the substrate to obtain a planar GaN template. 2) After growth is complete, the planar GaN template is removed from the MOCVD reaction chamber and cleaned. 3) The planar GaN template is dry etched using photolithography or nanoimprinting to etch the n-type doped GaN layer to form a GaN micropillar array. The GaN micropillars are frustum-shaped with tilted sidewalls. The bottoms of adjacent GaN micropillars are connected to each other to obtain a stress-relaxed patterned GaN template. The bottom of the GaN micropillar array in the stress-relaxed patterned GaN template is interconnected and there is no c-plane for growth. The sidewalls of the GaN micropillar array are curved and there are no complete planar crystal planes or c-planes for growth. Only the top surface of the GaN micropillar array is a c-plane and serves as the growth surface. Stress-relaxed patterned GaN templates effectively relax the stress on n-type doped GaN layers after patterning. 4) The stress-relaxed patterned GaN template is cleaned and returned to the MOCVD reaction chamber; 5) On a GaN micropillar array with a stress-relaxed patterned GaN template, an n-type doped GaN thin layer is epitaxially grown in a secondary manner. The n-type doped GaN thin layer and the GaN micropillar array together constitute the n-type doped GaN layer after secondary growth. On the n-type doped GaN layer after secondary growth, a prestress layer, a multi-quantum well layer, and a p-type doped GaN layer are selected and grown sequentially from bottom to top in a secondary epitaxial manner. The n-type doped GaN thin layer, prestress layer, multi-quantum well layer, and p-type doped GaN layer are grown only on the top surface of the GaN micropillar array, which serves as the growth surface, and are all patterned. The grown n-type doped GaN layer, prestressed layer, multi-quantum well layer, and p-type doped GaN layer form a micro-LED epitaxial wafer array. The pattern of the micro-LED epitaxial wafer array is consistent with the pattern of the stress-relaxed patterned GaN template, thus obtaining the micro-LED epitaxial wafer. The patterned multi-quantum well layer is not etched by dry etching, thereby avoiding sidewall etching damage of the multi-quantum well. The prestressed layer grown on the stress-relaxed patterned GaN template experiences partial relaxation of the compressive stress, and the in-plane lattice constant is expanded, thereby reducing the energy required for indium incorporation and effectively increasing the incorporation of indium in the multi-quantum well. 6) Place the micro-LED epitaxial wafer that has completed the secondary epitaxy of the selected area into an alkaline solution and perform sidewall etching on the micro-LED epitaxial wafer array to etch the sidewalls of the micro-LED epitaxial wafer array into the set shape to obtain a micro-LED chip array.

2. The preparation method according to claim 1, characterized in that, In step 1), the substrate is a sapphire substrate, a silicon substrate, or a silicon carbide substrate.

3. The preparation method according to claim 1, characterized in that, In step 2), the cleaning process involves acid washing followed by organic cleaning.

4. The preparation method according to claim 1, characterized in that, In step 3), a stress-relaxed patterned GaN template is obtained using photolithography or nanoimprinting, including the following steps: a) Using photoresist: i. Photoresist is uniformly spin-coated onto the surface of the n-type doped GaN layer of a planar GaN template. A periodic pattern of a micron-scale pattern array is formed on the photoresist using photolithography to obtain a patterned photoresist. ii. A dry etching method is used, with patterned photoresist as a mask, to etch the GaN template, etching the n-type doped GaN layer to form a GaN micropillar array. During etching, some photoresist is removed, leaving residual photoresist on the growth surface. The GaN micropillars are frustum-shaped with tilted sidewalls, and the bottoms of two adjacent GaN micropillars are connected to each other, thus obtaining a stress-relaxed patterned GaN template. b) Using nano-imprint adhesive: i. A nanoimprint adhesive is uniformly spin-coated onto the surface of an n-type doped GaN layer in a planar GaN template. A periodic pattern of a micron-scale pattern array is formed on the nanoimprint adhesive using the nanoimprint method to obtain a patterned nanoimprint adhesive. ii. A dry etching method is used, with patterned nanoimprint stencil as a mask, to etch the GaN template, etching the n-type doped GaN layer to form a GaN micropillar array. During etching, some nanoimprint stencil is removed, leaving residual nanoimprint stencil on the growth surface. The GaN micropillars are frustum-shaped with tilted sidewalls, and the bottoms of two adjacent GaN micropillars are connected to each other, thus obtaining a stress-relaxed patterned GaN template.

5. The preparation method according to claim 4, characterized in that, In step a)i), the period of the micron-scale pattern array is between 1.5 μm and 50 μm, and the diameter of the micron-scale pattern is between 1 μm and 30 μm; in step a)ii), the etching depth is between 500 nm and 5 μm.

6. The preparation method according to claim 4, characterized in that, In step 5), in step b)i), the period of the micron-scale pattern array is between 1 μm and 20 μm, and the diameter of the micron-scale pattern is between 500 nm and 10 μm; in step b)ii), the etching depth is between 300 nm and 5 μm.

7. The preparation method according to claim 4, characterized in that, In step 4), the cleaning process involves acid washing followed by organic cleaning. Acid washing is used to remove residual photoresist or nanoimprint adhesive on the growth surface, while organic cleaning is used to remove organic contaminants from the surface.

8. The preparation method according to claim 1, characterized in that, In step 5), the prestressed layer uses In x Ga 1-x N / GaN superlattice or In x Ga 1-x N is a single-layer structure, and x is the indium component in the prestressed layer, ranging from 1% to 20%.

9. The preparation method according to claim 1, characterized in that, In step 5), the multiple quantum well layer is a periodic In... y Ga 1-y N / GaN, where y is the indium composition in the multi-quantum well layer, ranging from 10% to 50%.

10. The preparation method according to claim 1, characterized in that, In step 6), the shape is set to a cylinder, a frustum, an inverted frustum, a trapezoid, or an inverted trapezoid.

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