A control circuit for a low-light energy harvesting chip
By designing a simple and efficient current sampling circuit and zero-crossing detection, the problems of large size and insufficient inductor current saturation protection in traditional multi-input energy harvesting chip circuits are solved, achieving circuit miniaturization and improved safety.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ZHEJIANG JUZI INTELLIGENT TECH
- Filing Date
- 2023-12-22
- Publication Date
- 2026-07-31
AI Technical Summary
Traditional multi-input energy harvesting chip circuits are large in size, difficult to integrate, and have high requirements for inductor values. They also lack protection measures when the inductor current is saturated, resulting in high circuit design difficulty and low safety.
The circuit employs a main circuit, input/output sampling circuit, MPPT circuit, control circuit, and current sampling circuit. It utilizes NMOS and SenseFET transistors for current sampling and combines Schmitt triggers for input/output sampling. The design creates a simple and efficient current sampling circuit that detects the inductor current crossing zero and ends charging when the inductor current is about to saturate, thus protecting the circuit.
It achieves miniaturized integration of the circuit, improves inductor utilization, reduces design difficulty and losses, enhances detection accuracy and circuit safety, expands the power supply range, and prevents damage caused by inductor continuing to charge after current saturation.
Smart Images
Figure CN117767735B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of electronic circuit technology, and more specifically, to a control circuit for a low-light energy harvesting chip. Background Technology
[0002] With the rapid advancement of Wireless Sensor Network (WSN) technology, sensor nodes are also evolving towards miniaturization, low power consumption, and low cost. The drawbacks of traditional battery-based power supply methods are becoming increasingly apparent, mainly in terms of large battery size, difficulty in replacement, and high cost. Therefore, there is an urgent need for new power supply methods; and the maturity of chip design and environmental micro-energy harvesting technology provides a solution to this problem.
[0003] Common micro-energy sources in the environment include light energy, heat energy, vibration energy, and radio frequency energy. Among these, light energy is widely considered a good micro-energy source due to its high stability and wide applicability. Since the output power of a light transducer is strictly limited by light intensity, multiple transducers need to be connected to an energy harvesting chip simultaneously under low-light conditions to increase output power and ensure the stable operation of the WSN system.
[0004] Traditional multi-input energy harvesting chips employ a multi-channel, multi-inductor, multi-capacitor structure. While each input channel boasts high efficiency, the large inductor values result in a bulky circuit that is difficult to integrate, hindering miniaturization. Subsequent researchers proposed a single-inductor circuit topology, which achieves the functionality of a multi-inductor topology and effectively improves inductor utilization. However, this topology places high demands on inductor values and lacks measures to address inductor current saturation. Summary of the Invention
[0005] In view of the shortcomings of the existing technology, the purpose of this invention is to provide a weak light energy harvesting chip control circuit that solves the above-mentioned technical problems.
[0006] To achieve the above objectives, the present invention provides the following technical solution: A low-light energy harvesting chip control circuit includes a main circuit, an input / output sampling circuit, an MPPT circuit, a control circuit, and a current sampling circuit. The input / output sampling circuit is connected to the main circuit, MPPT circuit, and control circuit; the MPPT circuit is also connected to the control circuit, which is the core of the energy harvesting circuit and connects to other circuits.
[0007] Furthermore, the main circuit includes a photovoltaic cell equivalent circuit, an input capacitor, a switching transistor, an inductor, an output capacitor, and a load. The input capacitor is connected in parallel with the photovoltaic cell equivalent circuit and is used to filter out AC harmonics and stabilize the input voltage. The switching transistor controls the charging and discharging process of the inductor, and the output capacitor is used to store energy and supply it to the load. The equivalent circuit of a photovoltaic cell includes an equivalent current source, a diode, a series resistor, and a parallel resistor. The equivalent current source, diode, and parallel resistor are connected in parallel with each other, and the series resistor is connected to the main circuit. The switching transistors include NMOS transistors MV, ML1, ML2, and MC. The upper plate of the input capacitor is connected to the drain of NMOS transistor MV, the source of NMOS transistor MV is connected to the drain of NMOS transistor ML2, and the source of NMOS transistor ML2 is grounded. The inductor is connected to the drain of NMOS transistors ML2 and ML1. The source of NMOS transistor ML1 is grounded. The drain of NMOS transistor MC is connected to the drain of ML1. The source of MC is connected to one end of the output capacitor. The other end of the output capacitor is grounded. The load is connected in parallel with the output capacitor.
[0008] Furthermore, the input / output sampling circuit includes resistors Ro1, Ro2, Ri1, Ri2, amplifiers Uo1 and Ui1, inverters No1, Ni1, and Ni2. One end of resistor Ri1 is connected to the output of the input sampling circuit. Resistor Ro1 is connected to the non-inverting input of amplifier Uo1. The inverting input of amplifier Uo1 is connected to the reference voltage. The two ends of resistor Ro2 are connected to the non-inverting input and the output of amplifier Uo1. The output of amplifier Uo1 is connected to the input of inverter No1. One end of resistor Ri1 is connected to the input terminal of the sampling circuit, and the other end is connected to the non-inverting terminal of amplifier Ui1. The inverting terminal of amplifier Ui1 is connected to the MPPT circuit. The two ends of resistor Ri2 are connected to the non-inverting terminal and the output terminal of amplifier Ui1. The output terminal of amplifier Ui1 is connected to the input terminal of inverter Ni1. Inverters Ni2 are connected in series with Ni1.
[0009] Furthermore, the MPPT circuit includes NMOS transistor Mm1, capacitors Cm1 and Cm2, resistors Rd1 and Rd2, amplifier Um, inverters Nm1 and Nm2, and a two-input AND gate Am1. The upper plate of capacitor Cm1 is connected to the input terminal of the main circuit, and the upper plate of capacitor Cm1 is connected to resistor Rd1 and the non-inverting terminal of amplifier Um. The lower plate of capacitor Cm1 is grounded. One end of resistor Rd2 is grounded, and the other end of resistor Rd2 is connected to Rd1 and the drain terminal of NMOS transistor Mm1. The upper plate of capacitor Cm2 is connected to the source terminal of Mm1 and the inverting terminal of amplifier Um. The lower plate of capacitor Cm2 is grounded. The output of amplifier Um is connected to the input terminal of inverter Nm1 and then to the input terminal of two-input AND gate Am1. One side of the external clock signal Pulse1 is connected to the gate of NMOS transistor Mm1, and the other input terminal of two-input AND gate Am1 is connected to the output terminal of inverter Nm1.
[0010] Furthermore, the current sampling circuit includes a zero-crossing detection circuit and a current saturation prediction circuit; The zero-crossing detection circuit includes SenseFET transistors MSeT1 and MSeT2, resistors RL1, Rp1, Rp2, Rp3, Rp4, and Rp5, amplifiers Up1 and Up2, inverters N1 and N2, capacitors Cp1 and Cp2, and a two-input OR gate Oi. The saturation current prediction circuit includes amplifier Up3, amplifier Up4, inverter N3, inverter N4, inverter N5, and inverter N6; In the main circuit, the connections between the inductor and the drain terminals of NMOS transistors ML2 and ML1 are terminals A and B, respectively. The drain of SenseFET MSeT1 is connected to terminal B. The source of SenseFET MSeT1 is connected to resistor RL1, the non-inverting input of amplifier Up1, and the non-inverting input of amplifier Up4. The other end of resistor RL1 is grounded. The drain of SenseFET MSeT2 is connected to terminal A. The source of SenseFET MSeT2 is connected to resistor RL2 and the non-inverting input of amplifier Up3. The other end of resistor RL2 is grounded. The output of amplifier Up4 is connected to the input of inverter N5. Inverters N5 and N6 are connected in series. The output of amplifier Up3 is connected to the input of inverter N3. Inverters N3 and N4 are connected in series. The outputs of inverters N4 and N6 are connected to the input of two-input OR gate Oi. The output of two-input OR gate Oi outputs a current zero-crossing detection signal QI. Resistor RL1 is connected to the non-inverting input of amplifier Up1. The inverting input of amplifier Up1 is connected to the output terminal. Resistor Rp1 is connected to resistor Rp2 and the inverting input of amplifier Up2. One end of resistor Rp3 is connected to the output terminal of Up1. The other end of resistor Rp3 is connected to resistor Rp4 and the upper plate of capacitor Cp1. The other end of Rp4 is connected to the lower plates of capacitors Cp1 and Cp2 and grounded. Resistor Rp5 is connected to the upper plates of capacitors Cp1 and Cp2 and is connected to the non-inverting input of amplifier Up2. The output terminal of amplifier Up2 is connected to two inverters N1 and N2 connected in series.
[0011] Furthermore, the control circuit includes an input / output status judgment circuit, an SV1 signal control circuit, an SL1 signal control circuit, an SL2 signal control circuit, an SC signal control circuit, and a zero-current control circuit. The input / output decision circuit includes D flip-flops Dtr-Vin and D flip-flops Dtr-Out, inverters Nd1, Nd2, Nd3, Ndo1, Ndo3, and Ndo3. The CLK terminals of both D flip-flops Dtr-Vin and D flip-flops Dtr-Out are connected to the external clock signal Pulse2. The D terminals of both D flip-flops Dtr-Vin and D flip-flops Dtr-Out are grounded. The outputs H1 and Hout of the input / output sampling circuit are connected to the SET terminals of D flip-flops Dtr-Vin and D flip-flops Dtr-Out via inverters Nd1 and Ndo2, respectively. The output of D flip-flop Dtr-Vin is output as Q1 via inverters Nd2 and Nd3 in series, and the output of D flip-flop Dtr-Out is output as Qout via inverters Ndo2 and Ndo3 in series.
[0012] Furthermore, the SV1 signal control circuit includes a D flip-flop Dtr-mppt, inverters Nmp1, Nmp2, Nmp3, NV, two-input AND gates A1, A2, A3, and A4. The CLK terminal of the D flip-flop Dtr-mppt is connected to an external clock signal, and the D input terminal of the D flip-flop Dtr-mppt is grounded. The output terminal of the MPPT circuit is connected to the SET terminal of the D flip-flop Dtr-mppt via an inverter Nmp1. The output terminal of the D flip-flop Dtr-mppt is connected to inverters Nmp2 and Nmp3 in series and outputs Qmp. The Q1 and Qout signals are the inputs of the two-input AND gate A1. Qmp and the output of the two-input AND gate A1 are used as the inputs of the two-input AND gate A2. The output of the two-input AND gate A2 and the QSL1 signal are used as the inputs of the two-input AND gate A3. The output of the two-input AND gate A3 and the De signal are used as the two inputs of the two-input AND gate A4 via an inverter NV. The two-input AND gate A4 outputs the SV1 signal.
[0013] Furthermore, the SL1 signal control circuit includes a D flip-flop Dtr-SL1, an inverter Ndl1, an inverter Ndl2, an inverter Ndl5, an inverter Ndl4, a capacitor Ce1, a resistor Re1, a two-input AND gate ATl1, a two-input AND gate ATl2, a two-input AND gate Ad1, and a two-input OR gate OT1. The CLK terminal of the D flip-flop Dtr-SL1 is connected to an external clock signal. The D input terminal of the D flip-flop Dtr-SL1 is grounded. The output of the current saturation prediction circuit is connected to the SET terminal of the D flip-flop Dtr-SL1 via an inverter Ndl1. The output of the D flip-flop Dtr-SL1 is connected to the input terminal of the two-input AND gate Ad1. The Qi signal is connected to resistor Re1 via an inverter Ndl2. Resistor Re1 is connected to the upper plate of capacitor Ce1. The lower plate of capacitor Ce1 is grounded. The upper plate of capacitor Ce1 is connected to the series inverter... The inverter Ndl3 is connected, and the output of the inverter Ndl3 is connected to the input of the two-input AND gate Adl. The input of the inverter Ndl4 is connected to the output of the two-input AND gate Adl. The inverter Ndl4 outputs the QSL1 signal. The Q1 and Qout signals are used as the inputs of the two-input AND gate ATl1. The output of the two-input AND gate ATl1 and the QSL1 signal are used as the inputs of the two-input AND gate ATl2. The output of the two-input AND gate ATl2 and the De signal are used as the inputs of the two-input OR gate OT1 and output the SL1 signal.
[0014] Furthermore, the SL2 signal control circuit includes a D flip-flop Dtr-SL2, inverters Nd21, Nd22, Nd23, Nd24, Nd25, and Nd26, a two-input AND gate Ad, a two-input OR gate OT2, a resistor Re2, and a capacitor Ce2. The QI signal enters through the input of inverter Nd21. The output of inverter Nd21 is connected to one end of resistor Re2. The other end of resistor Re2 is connected to the input of inverter Nd22 and the upper plate of capacitor Ce2. The lower plate of capacitor Ce2 is grounded. The output of inverter Nd22 serves as the input of AND gate Ad. The QST1 signal is connected to the other input of two-input AND gate Ad after inverter Nd23. The output of two-input AND gate Ad is DTR2. The CLK terminal of D flip-flop Dtr-SL2 is connected to the external clock signal. The D input terminal of D flip-flop Dtr-SL2 is grounded. The DTR2 signal is connected to the SET terminal of D flip-flop Dtr-SL2 through inverter Nd24. The output of flip-flop Dtr-SL2 is connected to inverters Nd25 and Nd26 in series and outputs the QSL2 signal. The Qout and QSL2 signals are the inputs of AND gate AT21. The De signal and the output of two-input AND gate AT21 serve as the inputs of two-input OR gate OT2. Two-input OR gate OT2 outputs the SL2 signal.
[0015] Furthermore, the SC signal control circuit includes two-input AND gates Ac1 and Ac2, capacitor Ce3, resistor Re3, inverter Nd27, and inverter Nd28. The QSL2 and Qout signals are used as inputs to AND gate Ac1. The QI signal is input through inverter Nd27. The output of inverter Nd27 is connected to resistor Re3. The other end of resistor Re3 is connected to the upper plate of capacitor Ce3. The lower plate of capacitor Ce3 is grounded. The upper plate of capacitor Ce3 is connected to the input of inverter Nd28. The output of inverter Nd28 and the output of two-input AND gate Ac1 are connected to the input of two-input AND gate Ac2 and output the SC signal.
[0016] Furthermore, the reset control circuit includes inverters Nd1, Nd2, Nd3, and Nd4, resistor Rde, and a two-input OR gate Od. Signal DTR2 enters through the input terminal of inverter Nd1. The output terminal of inverter Nd1 is connected to the input terminals of inverters Nd2 and Nd3. The output terminal of inverter Nd2 is connected to one end of resistor Rde. The other end of resistor Rde is connected to the upper plate of capacitor Cde and the input terminal of inverter Nd4. The lower plate of capacitor Cde is grounded. The output terminals of inverters Nd3 and Nd4 are connected to the input terminals of two-input OR gate Od. The output terminal of two-input OR gate Od outputs the De signal.
[0017] By adopting the above technical solution, the beneficial effects of the present invention are as follows: 1. To address the shortcomings of existing technologies, taking one input terminal of a multi-input energy harvesting circuit as an example, a simple and efficient current sampling circuit is provided. This circuit maximizes the use of inductors, reduces design complexity, decreases circuit size, facilitates chip-level integration, and ends charging when the inductor current is about to saturate, thus protecting the circuit.
[0018] 2. Zero-crossing detection of the inductor current employs resistive sampling based on a Sennheiser transistor, increasing detection sensitivity and reducing the impact of sampling on the main circuit and losses in the detection circuit. After the charging phase ends, a delayed pulse generation circuit is used to ground the inductor terminals, clearing any remaining current and preventing it from affecting the next charging phase. A Schmitt trigger is used for sampling at the input, working in conjunction with the control circuit to adaptively adjust the inductor charging time, reducing switching losses, improving efficiency, and providing a wider dynamic range.
[0019] 3. The input / output sampling circuit of this invention uses a Schmitt trigger to sample the input and output terminals. Based on the Schmitt trigger signal level, the input and output terminal states are transmitted to the control circuit. Using a Schmitt trigger for sampling can eliminate the need for a compensation circuit, reduce noise, and obtain a wider power supply range. 4. In the existing technology, voltage sampling at one end of the inductor connected to the power supply capacitor is often subject to large errors due to the influence of parasitic parameters of circuit components, which greatly reduces the sensitivity of detection. Moreover, the interface between the sampling circuit and the main circuit can interfere with the operation of the circuit. The current sampling circuit of the present invention is based on the SENSEFT tube detection of the resistance sampling method. It utilizes the width-to-length ratio of the SENSEFT tube and the MOS tube under test to reduce the detection current, reduce losses, and increase the electromagnetic compatibility of the main circuit with the sampling circuit, making the detection more accurate and sensitive. 5. Existing technologies lack protection against inductor current saturation and design larger inductors based on limited maximum charging time and voltage, resulting in inductors that cannot be fully utilized and occupy more space. The saturation current prediction circuit provided by this invention can end the charging phase when the current is about to reach the inductor's saturation current, thus allowing the inductor to reach its maximum utilization state, reducing the required inductance value in the design, and thereby reducing the inductor size. As the required inductance value decreases, its parasitic parameters will also decrease, reducing losses; by predicting the saturation current to end the charging phase, it prevents the inductor from continuing to charge after the current has saturated, which could burn out the circuit and increase circuit safety. Attached Figure Description
[0020] Figure 1 This is the main circuit for a multi-input weak light energy harvesting circuit; Figure 2 This is a block diagram of an energy harvesting system using a single input in a multi-input system as an example. Figure 3 a and Figure 3b The schematic diagram and input / output waveform diagrams of the sampling circuit at the input and output terminals are provided. Figure 4 a , Figure 4b and Figure 4c The present invention includes the MPPT circuit schematic, operating state diagram, and output waveform diagram. Figure 5 a and Figure 5b The schematic diagram and output waveform diagram of the current sampling circuit of the present invention are shown below; Figure 6 a , Figure 6b , Figure 6c , Figure 6d and Figure 6e The control circuit of this invention includes an input / output state judgment circuit, an MPPT circuit state judgment circuit, an SL1 signal control circuit, an SL2 and SC signal control circuit, and a current clearing control circuit. Figures 7a and 7b show the circuit diagrams for the inductor charging stage and the waveform diagrams for the charging transition stage. Figures 7c and 7d show the circuit diagrams for the inductor discharging stage and the waveform diagrams for the discharging transition stage. Figures 7e and 7f show the circuit diagrams for the inductor clearing stage and the waveform diagrams for the inductor clearing stage. Detailed Implementation
[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0022] See Figure 1 This is a multi-input weak light energy harvesting main circuit. Each energy input terminal is stabilized by a storage capacitor and stores energy. Then, it is connected to the power stage circuit through the NMOS transistor of its respective branch. Each time, one energy input is selected as the input terminal to charge the inductor L. After the inductor L discharges, the energy is transferred to the storage capacitor CL to supply power to the load.
[0023] See Figure 2 This is a block diagram of an energy harvesting system based on one input out of multiple inputs, as described in this invention. Since the selection of the input terminal does not affect the energy extraction by the control inductor, only one input terminal is used as an example to highlight the inductor charging and discharging control circuit provided by this invention. In the photovoltaic equivalent circuit:
[0024] I o The saturation current in the VD direction of the diode is V. t The thermal voltage of a photovoltaic cell. a These are the ideal parameters for a diode. Capacitor C1 is connected in parallel with a photovoltaic equivalent circuit to filter AC harmonics and stabilize the input voltage. It is connected to the power stage circuit through NMOS transistor MV1. The power stage circuit consists of NMOS transistors, NMOS transistors, and an intermediate inductor. The power stage circuit controls the charging and discharging process of the inductor through transistors ML1 and ML2. NMOS transistor MC is used to isolate the output terminal. The large capacitor CL at the output terminal is used to store energy and supply it to the load.
[0025] The input / output sampling circuit compares the input voltage with a reference voltage using a Schmitt trigger, dynamically calibrating the input and output, and outputting a signal to the control circuit to determine the input and output states. The MPPT circuit controls the on / off state of switch MV1 during inductor charging, achieving maximum power energy extraction. The current sampling circuit monitors the charging and discharging process, outputting a current status signal to the control circuit. The control circuit is the core component, collecting output signals from other circuits, performing logic operations, and controlling the on / off state of each switch to transfer the input energy to the output power supply capacitor.
[0026] See attached figure 3 aThis is a circuit diagram of a non-inverting Schmitt trigger provided by the present invention, which is a Schmitt trigger designed based on a proportional amplifier. Assume the high level output of the sampling circuit amplifier Uo1 at the output terminal is V. H The output low level is V L According to Kirchhoff's current law and the amplifier's "virtual short, virtual open" principle, it can be concluded that when V O 1=V H At that time, there were:
[0027] When V O 1=V L At that time, there were:
[0028] Since the amplifier's lowest output is 0, when V O 1=V L At that time, there were:
[0029] Similarly, for the input sampling circuit, when Vs1=V H Sometimes, there are:
[0030] When Vs1=0, we have:
[0031] Among them, selecting a suitable amplifier makes V H satisfy:
[0032] Furthermore, due to:
[0033] have:
[0034] Finally, based on the input and output sampling circuits, the relationship between the input and output of the sampling circuit is determined, as shown in the attached figure. Figure 3b As shown.
[0035] See Figure 4 a The power stage circuit input port is connected to the non-inverting input of amplifier Um. The switching on and off of MOSFET Mm1 is controlled by the drive signal Pulse1. Rd1 and Rd2 are relatively large. Capacitor Cm1 is used for filtering and voltage regulation, while Cm2 is relatively small and used to store the voltage magnitude. The open-circuit voltage V of the photovoltaic cell... OC The output voltage V corresponding to its maximum output power point Max The present invention is based on an approximately linear relationship to track the maximum output power point of photovoltaic cells. αThe voltage scaling factor represents the relationship between photovoltaic power and voltage scaling factor. The proportionality constant related to battery characteristics is empirically considered to be typically 0.7. The MPPT circuit adjusts the input voltage of the power stage circuit by changing the duty cycle of the MV1 transistor, ensuring Vin = 0.7V. OC Extract energy at maximum power.
[0036] See Figure 4b The operating status of the MPPT circuit is shown in the attached figure. Figure 4b As shown, when Mm1 is on, MV1 is off, Vin is the open-circuit voltage of the energy input terminal, Cm1 is used for filtering, Rd1:Rd2=3:7, and Cm2 is used to maintain 0.7V when Mm1 is on. OC The comparison voltage, Cm2, generally needs to be appropriately selected. If it's too small, the voltage cannot be maintained while Mm1 is off; if it's too large, Vmppt will follow 0.7VOC too slowly. When Mm1 is off, Vin is now compared to the voltage maintained by capacitor Cm2 in the previous state, which is 0.7V. OC In contrast, if Vin > 0.7V OC To reduce the input voltage, amplifier Um outputs a high level, inverter Nm1 outputs a low level, and AND gate Am1 outputs a low signal Smp. At this point, disconnect MV1 and reduce the input voltage Vin. If Vin < 0.7V... OC When inverter Nm1 outputs a high level and Smp outputs a high level, MV1 is closed, increasing the voltage at the power stage circuit interface.
[0037] See appendix Figure 4c During the rise of Vin, V Rd2 With a value of 0.7Vin, Vmppt approaches V during the high level of Pulse1. Rd2 Then, the two coincide; when Pulse1 is low, compare Vin with 0.7V. OC The size relationship between the two is used to control the on / off state of the MV1 transistor.
[0038] See Figure 5 a The current sampling section employs resistance sampling using a current mirror structure for SenseFET transistors, by connecting MSeT1 and MSeT2 to the drain and gate of ML1 and ML2 transistors, respectively. Since the MOSFETs operate in saturation when turned on, according to the saturation Sachs equation:
[0039] I DS Where is the drain-source current of the MOSFET, μ is the carrier mobility, and C is the source-drain current. OX The gate oxide capacitance per unit area is W / L, which is the channel width-to-length ratio, and V is V. GS V is the gate-source voltage. thIf MOSFETs made of the same material and using the same manufacturing process are selected for the turn-on voltage, then their current ratio after conduction is:
[0040] The aspect ratio of MSeT1 and MSeT2 transistors needs to be appropriately selected. Too large an aspect ratio will result in insufficient current, inaccurate resistor sampling, and insensitive detection; too small an aspect ratio will lead to excessive losses in the detection circuit. Through resistor sampling, the voltage information is obtained at the non-inverting inputs of amplifiers Up3 and Up4. This information then passes through an inverter and a two-input OR gate. Current flows through the inductor, and the OR gate OI outputs a high-level Qi signal. The current saturation detection circuit first uses a voltage follower to track the voltage Udet to prevent subsequent circuits from interfering with the sampling of Udet. The follower outputs a voltage Ufo1, making...
[0041] But R P1 It should not be too small to prevent the voltage from concentrating entirely on R. P2 R P3 Used to prevent subsequent R P5 C P2 The circuit oscillates after Ufo1 drops to 0, causing R to... P4 >>R P3 Prevent R P3 A higher voltage distribution affects detection, C p1 Used to filter out high-order harmonics, R P5 and C P2 Construct a delay circuit to make the voltage U POS Later U PAS A stable state has been reached.
[0042] See appendix Figure 5b When the inductor current approaches saturation, U appears PAS POS To U PAS >U POS At the transitional moment, amplifier U P2 The output will flip, outputting a high-level Qpeak signal. Upon receiving this signal, the control circuit will disconnect MV1 and ML1 transistors and turn on ML2 transistor. This ends the inductor charging phase and begins the inductor discharging phase. Due to the threshold voltage at the amplifier input, the actual transition time will be slightly delayed. See Figure 6 a This is an input / output status judgment circuit. When H1 and Hout are low, it means that the input power is insufficient and the output does not need to be charged. The output terminals of the D flip-flops Dtr-Vin and Dtr-Out are low. When H1 and Hout are high, it means that the input power is sufficient and the output needs power. The priority of setting the SET terminal of the D flip-flop to 1 is greater than setting the D input terminal to 0. The output terminals of the flip-flops Dtr-Vin and Dtr-Out are high, Q1 and Qout.
[0043] See Figure 6b The MPPT circuit state judgment circuit, during the period when the QSL1 signal is high, when the MPPT circuit output signal Smp is low, it means the input terminal is disconnected, the trigger Dtr-mppt outputs a low-level Qmp signal, the SV1 signal is low, and the MV1 transistor is off; when the MPPT circuit outputs a high-level Smp signal, Dtr-mppt outputs a high-level Qmp signal, when SV1 is high, and the MV1 transistor is turned on.
[0044] See Figure 6c When the saturation current prediction circuit outputs a high-level Qpeak signal, ML1 needs to be disconnected. After passing through inverter Ndl1, the Qpeak signal sets the output of D flip-flop Dtr-SL1 to a high level. When the circuit is never powered on, the QI signal is low, Dtr-SL1 outputs a low level, AND gate Ad1 outputs a low level, and inverter Ndl4 outputs a high-level signal QSL1, with ML1 waiting to be turned on. When the circuit is powered on and charging is complete, there is no current in the circuit, and the QI signal is low. Since the amplifier has the same input, it will maintain the Qpeak signal at a high level, and D flip-flop Dtr-SL1 outputs a high level. The low-level QI signal and the high-level Dtr-SL1 output signal, after passing through AND gate Ad1 and inverter Ndl4, output a high-level QSL1, with ML1 waiting to be turned on. When the input is powered but the output requires power, the ML1 transistor is turned on and power is supplied when the QSL1 signal is high. After this, current flows through the circuit. Due to U... POS Lagging behind U PAS Qpeak immediately becomes low, Dtr-SL1 outputs low, AND gate Adl outputs low, and after passing through inverter Ndl4, the QSL1 signal becomes high; After a period of delay, QI becomes high. At this time, since the Dtr-SL1 outputs low, the AND gate Ad1 outputs low, the inverter Ndl4 outputs high, and the QSL1 signal remains high; when the inductor current is about to reach saturation, the saturation current prediction signal Qpeak is high, both inputs of the AND gate Ad1 are high, the inverter Ndl4 outputs low, and the QSL1 signal becomes low. Or when the input voltage is not sufficient to continue supplying energy, the Q1 signal becomes low, the ATl1 outputs low, and the ML1 transistor is about to turn off. When the ML2 transistor conducts and the inductor discharges, the QI signal is high. However, during the inductor discharge phase, U PAS is always less than U POS , the Qpeak signal is high, the AND gate Ad1 outputs high, and after passing through the inverter, the QSL1 signal is low. During the discharge phase, the MV1 and ML1 transistors cannot conduct; during the current zeroing phase, the zeroing circuit generates a short-duration DE high-level signal. During this period, the SL1 signal becomes high and conducts the MLL1 transistor.
[0045] Referring to 6d, when the ML1 transistor turns off, the circuit is disconnected everywhere, and the QI signal becomes low. After a time controlled by Re2 and Ce2, the upper plate voltage of the capacitor Ce2 delays, and the inverter Nd22 receives the change in the QI signal level. Then the output of the inverter Nd22 remains high; the QST1 signal is low, and after passing through the inverter Nd23, it outputs high. The AND gate Ad will output a high-level DTR2 signal; after passing through the D flip-flop Dtr-SL2, it outputs a high-level QSL2 signal, the ML2 conducts, and the MC also conducts simultaneously, and current flows through the circuit. The QI signal changes from low to high. Before the upper plate voltage of the capacitor Ce2 increases to the threshold voltage of the inverter Nd22, the QI signal becomes high. After that, the upper plate voltage of the Ce2 starts to decrease, and during this period, the inverter Nd22 always outputs high; When the inductor discharge is complete, the QI low-level signal passes through the delay inverter Nd22, and the DTR2 signal is still high, so the QSL2 signal is still high. However, since Re3Ce3 << Re2Ce2, the inverter Nd28 receives the QI low-level signal much earlier than Nd22. Therefore, the MC transistor disconnects first, and the ML2 disconnects later; the purpose of setting Re3Ce3 << Re2Ce2 is that Re2Ce2 is relatively large, which can ensure that after ML1 is turned off, ML2 conducts smoothly; Re2Ce2 is relatively small to prevent current backflow in the circuit after the discharge phase ends and the current becomes 0. When there is no current in the circuit, the QI signal is 0, and the Ad outputs low. When the inductor is in the charging state, the QST1 signal is high, the inverter Nd23 outputs low, and the Ad outputs a level. In both phases, the ML2 transistor and the MC transistor cannot conduct.
[0046] Referring to 6e, the inductor discharge phase ends only when the DPTR2 signal drops from high to low. At this time, the OR gate Od outputs a high-level pulse, the pulse width of which is controlled by Rde and Cde. During this period, the ML1 and ML2 transistors are driven to close, grounding the inductor and clearing the remaining current to zero. At this time, the current is already below the minimum current detection value, so there is no need to worry about the QI signal being greater than 0 during the clearing phase, causing other circuits to operate.
[0047] See Figure 7 a When the power supply capacitor needs to be charged and the input terminal is powered, transistors ML1 and MV1 are closed, while transistors ML2 and MC are open, and the circuit enters the inductor charging stage. During the charging stage, the energy at the input terminal is converted into electrical energy and stored in the inductor L.
[0048] See Figure 7b When the inductor is charging, the SL1 signal changes from low to high. The SV1 signal alternates between high and low levels during the high-level period of SL1 to extract energy with maximum power. When the SL1 signal is high, the SL2 and SC signals need to be set to low.
[0049] See Figure 7c When ML1 is turned off, MC turns on first, followed by ML2. The circuit enters the inductor discharge stage, at which time the energy in inductor L is released to the power supply capacitor CL, and the output voltage increases.
[0050] See Figure 7d When the inductor charging phase ends, the SL1 and SV signals go low, and then the SL2 and SC signals go high. When the inductor L finishes discharging, the SC signal goes low first, the MC transistor turns off first, and the inductor discharge phase ends.
[0051] See Figure 7e When the inductor discharge phase ends, the current clearing control circuit will turn on transistors ML1 and ML2 to release the remaining current in inductor L to the ground.
[0052] See Figure 7f When the DTR2 signal goes low, the reset control circuit will generate a high-level signal De for a short period of time, the SL1 signal will go high, and the SL2 signal will remain high. After the De signal goes low, the remaining current will be released, and the SL1 and SL2 signals will go low. During this period, the SC and SV signals will be low.
[0053] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any ordinary changes and substitutions made by those skilled in the art within the scope of the technical solution of the present invention should be included within the protection scope of the present invention.
Claims
1. A control circuit for a low light energy harvesting chip, comprising: include The main circuit includes a photovoltaic cell equivalent circuit, an input capacitor, a switching transistor, an inductor, an output capacitor, and a load. The input capacitor is connected in parallel with the photovoltaic cell equivalent circuit and is used to filter AC harmonics and stabilize the input voltage. The switching transistor controls the charging and discharging process of the inductor, and the output capacitor is used to store energy and supply it to the load. The input / output sampling circuit is used to compare the input voltage with the reference voltage, perform dynamic calibration of the input and output, and output a signal to the control circuit to determine the state of the input and output terminals. The MPPT circuit is used to control the on / off state of switch MV1 during inductor charging, thereby extracting energy at maximum power. The current sampling circuit is used to monitor the charging and discharging process and outputs a current status signal to the control circuit. The control circuit is used to collect output signals from other circuits, perform logic operations, control the on / off state of each switch, and complete the transfer of electrical energy from the input terminal to the output power supply capacitor. The input / output sampling circuit is connected to the main circuit and the MPPT circuit; the control circuit is connected to the main circuit, the input / output sampling circuit, the MPPT circuit and the current sampling circuit.
2. The control circuit of a low light energy harvesting chip according to claim 1, wherein, The photovoltaic cell equivalent circuit includes an equivalent current source, a diode, a series resistor, and a parallel resistor. The equivalent current source, diode, and parallel resistor are connected in parallel with each other, and the series resistor is connected to the main circuit. The switching transistors include NMOS transistors MV, ML1, ML2, and MC. The upper plate of the input capacitor is connected to the drain of NMOS transistor MV, the source of NMOS transistor MV is connected to the drain of NMOS transistor ML2, and the source of NMOS transistor ML2 is grounded. The inductor is connected to the drain of NMOS transistor ML2 and the drain of NMOS transistor ML1. The source of NMOS transistor ML1 is grounded. The drain of NMOS transistor MC is connected to the drain of ML1. The source of NMOS transistor MC is connected to one end of the output capacitor. The other end of the output capacitor is grounded. The load is connected in parallel with the output capacitor.
3. The control circuit of a low light energy harvesting chip according to claim 2, wherein, The input / output sampling circuit includes resistors Ro1, Ro2, Ri1, Ri2, amplifiers Uo1 and Ui1, inverters No1, Ni1, and Ni2. One end of resistor Ri1 is connected to the output of the input sampling circuit, resistor Ro1 is connected to the non-inverting input of amplifier Uo1, the inverting input of amplifier Uo1 is connected to the reference voltage, the two ends of resistor Ro2 are connected to the non-inverting input and the output of amplifier Uo1, and the output of amplifier Uo1 is connected to the input of inverter No1. One end of resistor Ri1 is connected to the input terminal of the sampling circuit, and the other end is connected to the non-inverting terminal of amplifier Ui1. The inverting terminal of amplifier Ui1 is connected to the MPPT circuit. The two ends of resistor Ri2 are connected to the non-inverting terminal and the output terminal of amplifier Ui1. The output terminal of amplifier Ui1 is connected to the input terminal of inverter Ni1. Inverters Ni2 and Ni1 are connected in series.
4. The control circuit of a low light energy harvesting chip according to claim 3, wherein, The MPPT circuit includes an NMOS transistor Mm1, capacitors Cm1 and Cm2, resistors Rd1 and Rd2, an amplifier Um, inverters Nm1 and Nm2, and a two-input AND gate Am1. The upper plate of capacitor Cm1 is connected to the input terminal of the main circuit, and the upper plate of capacitor Cm1 is connected to resistor Rd1 and the non-inverting terminal of amplifier Um. The lower plate of capacitor Cm1 is grounded. One end of resistor Rd2 is grounded, and the other end of resistor Rd2 is connected to Rd1 and the drain terminal of NMOS transistor Mm1. The upper plate of capacitor Cm2 is connected to the source terminal of Mm1 and the inverting terminal of amplifier Um. The lower plate of capacitor Cm2 is grounded. The output of amplifier Um is connected to the input terminal of inverter Nm1 and then to the input terminal of two-input AND gate Am1. One side of the external clock signal Pulse1 is connected to the gate of NMOS transistor Mm1, and the other input terminal of two-input AND gate Am1 is connected to the output terminal of inverter Nm1.
5. The control circuit of a low light energy harvesting chip according to claim 4, wherein, The current sampling circuit includes a zero-crossing detection circuit and a current saturation prediction circuit; The zero-crossing detection circuit includes SenseFET transistors MSeT1 and MSeT2, resistors RL1, Rp1, Rp2, Rp3, Rp4, and Rp5, amplifiers Up1 and Up2, inverters N1 and N2, capacitors Cp1 and Cp2, and a two-input OR gate Oi. The saturation current prediction circuit includes amplifier Up3, amplifier Up4, inverter N3, inverter N4, inverter N5, and inverter N6. The connections between the inductor and the drain terminals of NMOS transistors ML2 and ML1 in the main circuit are terminals A and B, respectively. The drain terminal of the SenseFET transistor MSeT1 is connected to terminal B. The source terminal of the SenseFET transistor MSeT1 is connected to resistor RL1, the non-inverting input of amplifier Up1, and the non-inverting input of amplifier Up4. The other end of resistor RL1 is grounded. The drain terminal of the SenseFET transistor MSeT2 is connected to terminal A, and the source terminal of the SenseFET transistor MSeT2 is connected to resistor RL2 and the non-inverting input of amplifier Up3. The other end of resistor RL2 is grounded. The output of amplifier Up4 is connected to the input of inverter N5. Inverters N5 and N6 are connected in series. The output of amplifier Up3 is connected to the input of inverter N3. Inverters N3 and N4 are connected in series. The outputs of inverters N4 and N6 are connected to the input of two-input OR gate Oi. The output of two-input OR gate Oi outputs a current zero-crossing detection signal QI. The resistor RL1 is connected to the non-inverting input of amplifier Up1, and the inverting input of amplifier Up1 is connected to the output terminal. Resistor Rp1 is connected to resistor Rp2 and the inverting input of amplifier Up2. One end of resistor Rp3 is connected to the output terminal of Up1, and the other end of resistor Rp3 is connected to resistor Rp4 and the upper plate of capacitor Cp1. The other end of Rp4 is connected to the lower plates of capacitors Cp1 and Cp2 and grounded. Resistor Rp5 is connected to the upper plates of capacitors Cp1 and Cp2 and is connected to the non-inverting input of amplifier Up2. The output terminal of amplifier Up2 is connected to two inverters N1 and N2 connected in series.
6. The control circuit of a low light energy harvesting chip according to claim 5, wherein, The control circuit includes an input / output status judgment circuit, an SV1 signal control circuit, an SL1 signal control circuit, an SL2 signal control circuit, an SC signal control circuit, and a zero-current control circuit. The input / output determination circuit includes D flip-flops Dtr-Vin and D flip-flops Dtr-Out, inverters Nd1, Nd2, Nd3, Ndo1, Ndo3, and Ndo3. The CLK terminals of both the D flip-flop Dtr-Vin and D flip-flop Dtr-Out are connected to the external clock signal Pulse2. The D terminals of both the D flip-flop Dtr-Vin and D flip-flop Dtr-Out are grounded. The outputs H1 and Hout of the input-output sampling circuit are connected to the SET terminals of the D flip-flop Dtr-Vin and D flip-flop Dtr-Out via inverters Nd1 and Ndo2, respectively. The output of the D flip-flop Dtr-Vin is output as Q1 via inverters Nd2 and Nd3 in series. The output of the D flip-flop Dtr-Out is output as Qout via inverters Ndo2 and Ndo3 in series. The SV1 signal control circuit includes a D flip-flop Dtr-mppt, inverters Nmp1, Nmp2, Nmp3, NV, two-input AND gates A1, A2, A3, and A4. The CLK terminal of the D flip-flop Dtr-mppt is connected to an external clock signal, the D input terminal of the D flip-flop Dtr-mppt is grounded, the output terminal of the MPPT circuit is connected to the SET terminal of the D flip-flop Dtr-mppt via an inverter Nmp1, the output terminal of the D flip-flop Dtr-mppt is connected to inverters Nmp2 and Nmp3 in series and outputs Qmp, and the Q1 and Qout signals are the inputs of the two-input AND gate A1. The SL1 signal control circuit includes a D flip-flop Dtr-SL1, an inverter Ndl1, an inverter Ndl2, an inverter Ndl5, an inverter Ndl4, a capacitor Ce1, a resistor Re1, a two-input AND gate ATl1, a two-input AND gate ATl2, a two-input AND gate Ad1, and a two-input OR gate OT1. The CLK terminal of the D flip-flop Dtr-SL1 is connected to an external clock signal, and the D input terminal of the D flip-flop Dtr-SL1 is grounded. The output terminal of the current saturation prediction circuit is connected to the SET terminal of the D flip-flop Dtr-SL1 after passing through an inverter Ndl1. The output of the flip-flop Dtr-SL1 is connected to the input terminal of the two-input AND gate Ad1. The Q1 signal is connected to a resistor Re1 after passing through an inverter Ndl2. The resistor Re1 is connected to the upper plate of the capacitor Ce1, and the lower plate of the capacitor Ce1 is grounded. The upper plate of the capacitor Ce1 is connected to an inverter Ndl3 connected in series. The output terminal of the inverter Ndl3 is connected to the input terminal of the two-input AND gate Ad1. The input terminal of the inverter Ndl4 is connected to the output terminal of the two-input AND gate Ad1. The inverter Ndl4 outputs the QSL1 signal. The Q1 and Qout signals are used as the inputs of the two-input AND gate ATl1. The output of the two-input AND gate ATl1 and the QSL1 signal are used as the inputs of the two-input AND gate ATl2. The SL2 signal control circuit includes a D flip-flop Dtr-SL2, inverters Nd21, Nd22, Nd23, Nd24, Nd25, and Nd26, a two-input AND gate Ad, a two-input OR gate OT2, a resistor Re2, and a capacitor Ce2. The Qi signal enters through the input of inverter Nd21. The output of inverter Nd21 is connected to one end of resistor Re2. The other end of resistor Re2 is connected to the input of inverter Nd22 and the upper plate of capacitor Ce2. The lower plate of capacitor Ce2 is grounded. The output of inverter Nd22 serves as the input of AND gate Ad. The output of the two-input AND gate Ad is DTR2. The CLK terminal of D flip-flop Dtr-SL2 is connected to an external clock signal. The D input terminal of D flip-flop Dtr-SL2 is grounded. The DTR2 signal is connected to the SET terminal of D flip-flop Dtr-SL2 via inverter Nd24. The output of flip-flop Dtr-SL2 is connected to inverters Nd25 and Nd26 in series and outputs the QSL2 signal. The Qout and QSL2 signals are the inputs of AND gate AT21. The SC signal control circuit includes two-input AND gates Ac1 and Ac2, capacitor Ce3, resistor Re3, inverter Nd27, and inverter Nd28. The QSL2 and Qout signals are used as inputs to AND gate Ac1. The QI signal is input through inverter Nd27. The output of inverter Nd27 is connected to resistor Re3. The other end of resistor Re3 is connected to the upper plate of capacitor Ce3. The lower plate of capacitor Ce3 is grounded. The upper plate of capacitor Ce3 is connected to the input of inverter Nd28. The output of inverter Nd28 and the output of two-input AND gate Ac1 are connected to the input of two-input AND gate Ac2 and output the SC signal. The reset control circuit includes inverters Nd1, Nd2, Nd3, and Nd4, a resistor Rde, and a two-input OR gate Od. Signal DTR2 enters through the input terminal of inverter Nd1. The output terminal of inverter Nd1 is connected to the input terminals of inverters Nd2 and Nd3. The output terminal of inverter Nd2 is connected to one end of resistor Rde. The other end of resistor Rde is connected to the upper plate of capacitor Cde and the input terminal of inverter Nd4. The lower plate of capacitor Cde is grounded. The output terminals of inverters Nd3 and Nd4 are connected to the input terminals of two-input OR gate Od. The output terminal of two-input OR gate Od outputs the De signal.
7. The control circuit of a low light energy harvesting chip according to claim 6, wherein, The output of Qmp and the two-input AND gate A1 are used as the input of the two-input AND gate A2. The output of the two-input AND gate A2 and the QSL1 signal are used as the input of the two-input AND gate A3. The output of the two-input AND gate A3 and the De signal are used as the two inputs of the two-input AND gate A4 via the inverter NV. The two-input AND gate A4 outputs the SV1 signal.
8. The control circuit for a low-light energy harvesting chip according to claim 6, characterized in that, The output of the two-input AND gate AT12 and the De signal are used as the input of the two-input OR gate OT1 and the output signal SL1 is used as the output. The QST1 signal is connected to the other input terminal of the two-input Ad after passing through the inverter Nd23.
9. The control circuit of a low light energy harvesting chip according to claim 6, wherein, The De signal and the output of the two-input AND gate AT21 are used as the inputs of the two-input OR gate OT2, and the two-input OR gate OT2 outputs the SL2 signal.
10. The control circuit of a low light energy harvesting chip according to claim 6, wherein, The QSL2 and Qout signals are input to the AND gate Ac1, and the QI signal is input through the inverter Nd24.