A method for preventing latch-up of a switching power supply chip

Abstract

The application discloses a method for preventing latching of a switching power supply chip, which is applied to an ultra-low standby power consumption primary PWM chip with an optical coupling circuit. When it is detected that a power supply system works in a normal wake-up mode and a working frequency is higher than or equal to a preset value, power supply of the PWM power supply chip enters a first mode, the power supply is provided by an auxiliary winding of a transformer and has a function of being internally forced to be kept in a constant voltage range. When it is detected that the power supply system enters a sleep mode, a power supply voltage has a rising edge waveform and the working frequency is lower than the preset value, the power supply of the PWM power supply chip enters a second mode, and the power supply is completely provided by the auxiliary winding. When the primary PWM chip cannot obtain a wake-up signal provided by a secondary chip in the sleep mode, the power supply voltage of the PWM chip is automatically discharged to an under-voltage off voltage, and then recharging is started, so that the chip is prevented from being in the sleep mode all the time, and a charger is prevented from being unable to resume charging after being connected with a mobile phone.

Description

Technical Field

[0001] This invention belongs to the field of design and application of switching power supply chips, and specifically relates to a method for preventing latch-up in switching power supply chips. Background Technology

[0002] The charger's control chip includes a primary PWM IC and a secondary Protocol IC. For example... Figure 1 As shown. Ultra-low standby power chargers typically have a standby power consumption of less than 5mW, requiring both primary and secondary chips to enter sleep mode to reduce power consumption. When the charger is disconnected from the phone, the secondary chip detects the disconnection signal first and then sends a sleep signal to the primary chip. Upon receiving the sleep signal, the primary chip reduces its operating current and shuts down the drive. Then, the secondary chip shuts off the optocoupler's current, enters sleep mode, and provides voltage pulses to the primary chip through the transformer windings. The primary chip, based on the received voltage pulse signal, issues fixed-width drive pulses to maintain the power supply required in sleep mode.

[0003] System loss analysis revealed that in standby mode, besides the chip's own power consumption, the switching losses of the power devices on the primary side also account for a significant portion. Since switching losses are directly proportional to frequency, the switching frequency needs to be reduced sufficiently to effectively decrease system losses. However, reducing the switching frequency too much can lead to insufficient VCC power supply, meaning the energy provided by a single pulse is insufficient to sustain the chip's power consumption, causing the VCC voltage to drop below UVLO.

[0004] To prevent the primary-side power supply chip from triggering undervoltage lockout (UVLO) of the chip's VCC under light load and dynamic load conditions, thus causing the chip to restart, a VCC hold function is designed. The hold voltage is typically slightly higher than the UVLO voltage (the difference is approximately 1V). When the VCC voltage drops to the VCC hold voltage threshold, the rectified DC voltage from the AC input passes through resistor R1 to the HV terminal. Then, the HV terminal charges the VCC capacitor internally through a current source, ensuring that the VCC voltage remains at a level not lower than the VCC_hold hold voltage.

[0005] A diagram illustrating the VCC hold function charging is shown below. Figure 2 As shown. In VCC hold mode, there is no need to generate a GATE drive pulse. The HV terminal can continuously charge the VCC capacitor with a constant small current, keeping the chip in the working state. This method of maintaining the VCC voltage without pulse generation is beneficial for maintaining a constant output voltage. Figure 2 In the middle, GATE represents the drive pulse of the PWM chip, V STVCC is the startup voltage, VCC_hold is the holding voltage, and VCC_uvlo is the undervoltage lockout voltage. CHG_HV This is the charging current at the HV terminal.

[0006] After the primary-side chip fully enters sleep mode, it detects the voltage signal received on the transformer auxiliary winding via the chip's DEM pin and sends a drive pulse of the same frequency to the primary switching transistor, providing the power supply with sustaining energy in sleep mode. However, this also brings disadvantages: for example, if the secondary output capacitor loses power due to an abnormality, the secondary-side chip will stop working. In this case, when the charger is connected to a phone, it cannot recognize the phone connection and cannot provide a wake-up signal to the primary-side chip. The primary-side chip will also not receive the signal to exit sleep mode, and due to the VCC hold function, it will remain in sleep mode. Figure 4 As shown in the diagram, C1 represents VFB voltage; C2 represents the PWM driver; C3 represents the output capacitor voltage; and C4 represents the primary-side VCC capacitor voltage. The PWM power chip cannot restart unless VCC drops below UVLO voltage, and it enters a latch-up state, unable to charge the phone. Even after powering off and on again, it cannot resume operation quickly. This is because the PWM chip's quiescent current is very small in sleep mode, and the VCC capacitor voltage cannot discharge quickly below UVLO. Often, it takes several minutes or more after powering off before it can restart. Summary of the Invention

[0007] This invention proposes a method to prevent latch-up in switching power supply chips, aiming to solve the latch-up problem that easily occurs when ultra-low standby power chargers enter sleep mode. When the voltage of the output capacitor abnormally drops during sleep mode, the secondary-side chip cannot continue to operate and cannot notify and wake up the primary-side chip. Alternatively, an abnormality at the output terminal may cause the primary-side PWM chip to mistakenly enter sleep mode. In this case, due to the VCC hold function, the PWM chip will remain in sleep mode and cannot restart. In this state, the charger cannot provide normal charging after connecting a mobile phone. This invention can solve the latch-up problem that causes the power supply PWM chip to fail to start.

[0008] The specific technical solution for achieving the objective of this invention is as follows:

[0009] A method for preventing latch-up in a switching power supply chip, applied to an ultra-low standby power primary PWM chip with optocoupler circuitry, specifically includes:

[0010] When the power system is detected to be operating in normal wake-up mode and the operating frequency is higher than or equal to the preset value, the PWM power chip enters the first mode. Its power supply is provided by the transformer auxiliary winding, and it has the function of internally maintaining a constant voltage range. When the power system is detected to be entering sleep mode, the supply voltage has a rising edge waveform, and the operating frequency is lower than the preset value, the PWM power chip enters the second mode. Its power supply is entirely provided by the auxiliary winding, and it does not have the function of internally maintaining a constant voltage range. When the output voltage drops too low or the secondary-side chip does not provide the voltage pulse to maintain drive in sleep mode, the VCC of the primary-side chip can drop below the undervoltage shutdown voltage, and a restart can begin. Among these:

[0011] Entering the second mode specifically includes:

[0012] The secondary control chip enters sleep mode based on the rising edge waveform of the VCC voltage after the primary chip enters sleep mode.

[0013] The switching frequency of the primary-side PWM chip is used as condition two to determine whether the secondary-side control chip enters sleep mode.

[0014] Its power supply is entirely provided by the auxiliary winding, and it does not have the function of forcibly maintaining a constant voltage range, specifically including:

[0015] The PWM chip's function of maintaining the VCC power supply voltage provided by the high-voltage HV terminal is disabled. It can only supply energy to VCC through the transformer winding when a drive pulse is present, and the VCC voltage can rise. Without a drive pulse, the VCC voltage will drop to UVLO, i.e., the undervoltage lockout voltage, as the chip itself is consumed.

[0016] The condition for determining whether the secondary-side control chip enters sleep mode is based on the existence of a rising edge waveform of the VCC voltage after the primary-side chip enters sleep mode. Specifically, this includes:

[0017] After receiving the sleep signal from the secondary side, the primary PWM chip first enters the sleep transition state. During the sleep transition state, the power supply of the PWM chip enters the VCC voltage holding mode. When the PWM chip receives the voltage pulse signal transmitted by the secondary side through the auxiliary winding, the VCC voltage will rise from the VCC holding voltage by one voltage step. The appearance of this voltage step is one of the conditions for determining that the secondary side chip has entered the sleep mode.

[0018] This invention avoids issues with ultra-low standby power chargers when output abnormalities occur, such as a short circuit preventing the primary-side chip from receiving a wake-up signal, or other abnormal conditions on the secondary side causing the primary-side PWM chip to mistakenly enter a sleep state without the secondary-side chip's awareness, resulting in the PWM chip failing to receive a wake-up signal. These situations ultimately lead to the primary-side chip remaining in a sleep state with persistent VCC hold-up, preventing chip restart, output voltage recovery, and normal phone charging. Even with the AC power off, a relatively long VCC discharge time is required before the next startup. This invention solves these problems, ensuring no charging failure when the charger is disconnected and reconnected to the phone, guaranteeing a normal charging experience for the user. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of an existing switching power supply chip system application.

[0020] Figure 2 A schematic diagram illustrating the VCC hold-up function of an existing power chip for charging.

[0021] Figure 3 This is a waveform diagram of the VCC voltage of the power supply chip of the present invention during sleep transition;

[0022] Figure 4 The waveform diagram shows the latch-up problem that occurs when the output capacitor of an existing power chip is short-circuited.

[0023] Figure 5 This is a circuit flowchart illustrating the anti-latch-up circuit of the switching power supply chip of the present invention.

[0024] Figure 6 The waveform diagram shows how the system can restart normally after the power chip of the present invention is short-circuited in the output capacitor;

[0025] Figure 7 This is a flowchart illustrating the power supply process for the PWM chip of the present invention. Detailed Implementation

[0026] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0027] Example

[0028] See the detailed circuit flowchart for implementation. Figure 5The external power supply VCC terminal of the chip is connected to the inverting input of comparator U1, while the two non-inverting inputs of U1 are connected to voltage references of 9V and 10V. This limits the voltage passing through comparator U1 to between 9V and 10V. The inverting output of U1 is connected to one input of logic AND gate U3. The signal detection DEM terminal of the auxiliary winding is connected to the signal detection and pulse generation module. The pulse output of this module is connected to switch S2, which is connected to capacitor C3. The internal power supply VDD charges capacitor C3 through current source Is2, and capacitor C3 is connected to the inverting input of U2. REF_H and V REF_L Two voltage references are connected to the two non-inverting inputs of comparator U2, and comparator U2 limits the voltage value passing through it to V. REF_H and V REF_L Between them, the inverting output of U2 is connected to another input of the AND gate U3. The third input of U3 is connected to the output of the sleep mode module, and the output of U3 is connected to the gate of NMOS switch S1. The high voltage HV terminal of the chip charges VCC through constant current source Is1 via NMOS switch S3. The gate of S3 is connected to the drain of NMOS switch S1 and the output of the VCC hold control module.

[0029] This embodiment includes the following specific steps, please refer to... Figure 7 PWM chip power supply flowchart:

[0030] Step 1: After the charger is disconnected from the phone, the Protocol chip on the secondary side notifies the PWM chip on the primary side to enter sleep mode.

[0031] The secondary-side protocol IC detects changes in the USB port signal and sends a sleep signal to the FB feedback pin of the primary-side PWM chip via an optocoupler. Upon receiving the sleep signal, the primary-side PWM IC enters sleep mode, reducing its quiescent current and shutting down most of its functional modules. During this phase, VCC remains in normal operating mode. The secondary-side chip also enters sleep mode after a certain delay following the primary-side chip's entry into sleep mode.

[0032] Step 2: After the primary-side PWM chip enters sleep mode, exit VCC hold mode after confirming that the secondary-side chip has also entered sleep mode.

[0033] After the primary-side chip enters sleep mode, to maintain the output voltage, the secondary-side chip provides a sleep-state voltage pulse signal to the primary-side chip through the transformer winding. The primary-side PWM IC can maintain the output by responding to the voltage pulse signal detected on the auxiliary winding by issuing a corresponding gate drive pulse. After entering sleep mode, the switching frequency exhibits a pattern of initially high and then low based on the output voltage feedback. When the switching frequency is high, the auxiliary winding provides more energy to VCC, and the VCC voltage will show a significant rise, such as... Figure 3 As shown in the figure, C1: VFB voltage; C2: secondary side Vds voltage; C3: output capacitor voltage; C4: primary side VCC capacitor voltage; this rise process is one of the criteria for the secondary side chip to enter sleep mode, which is used to confirm that the secondary side chip has taken over the drive signal of the primary side chip and can provide the primary side chip with a voltage higher than the VCC holding threshold.

[0034] Since the switching frequency required to maintain the power supply's own power consumption in sleep mode is much lower than 1kHz, the switching frequency subsequently begins to decrease. When the primary-side chip detects that the switching frequency of the pulse signal provided by the secondary side is lower than the set fs1 (optional 1kHz) in sleep mode, this serves as the second criterion for determining that the secondary-side chip has entered sleep mode. When both criteria are met, the PWM chip can exit VCC hold mode. Specifically, as follows... Figure 5 As shown, in sleep mode, the DEM terminal receives a voltage signal transmitted from the secondary-side chip through the transformer winding. This signal is then processed by a signal detection and pulse generation circuit to generate a voltage pulse with a fixed pulse width (typically 3µs). This pulse is then used to control the charging and discharging cycle of capacitor C3 via switch S2, thus affecting the amplitude of the charging voltage across the capacitor. The charging of C3 is provided by the chip's internal power supply VDD via the Is2 current source. When the voltage across capacitor C3 exceeds the reference voltage V... REF_H At this time, the U2 inverting comparator outputs a high level. Simultaneously, the other two inputs of the U3 AND gate are also high, so U3 outputs a high level, switch S1 is turned on, switch S3 is turned off, and the HV terminal connected to the DC input voltage cannot charge the VCC capacitor through the constant current source Is1, causing the VCC holding function to fail.

[0035] Even if the output capacitor short-circuits in this situation, because the VCC hold-up function is lost, the VCC voltage can quickly drop below the UVLO voltage. Once the short circuit is cleared, the primary-side PWM chip can automatically restart and resume operation. For example... Figure 6 As shown in the figure, C1: VFB voltage; C2: PWM drive; C3: output capacitor voltage; C4: primary side VCC capacitor voltage;

[0036] Step 3: After the charger is connected to the phone, the secondary chip wakes up the primary chip, and the VCC hold function is reactivated.

[0037] When the charger is reconnected to the phone, the secondary-side chip first exits sleep mode. The secondary-side Protocol chip then wakes the primary-side PWM chip by sending a current pulse with a frequency higher than the set value fs2 (optional 5kHz) through the transformer winding. The primary-side chip obtains a high-frequency voltage signal through frequency detection at the DEM terminal. Because the frequency increases, the charging time of capacitor C3 is shortened, and the capacitor voltage drops below V. REF_L Afterwards, the output of the U2 inverting comparator goes low, the output of the U3 AND gate is also set low, switch S1 is turned off, and switch S3 is turned on. The HV terminal connected to the DC input voltage can charge the VCC capacitor through the constant current source Is1, and the VCC holding function begins to recover. At this time, the PWM chip can rely on the VCC holding function to prevent a deep drop in VCC voltage caused by light load and dynamic load conditions.

Claims

1. A method for preventing latch-up of a switching power supply chip, characterized in that, It is applied in ultra-low standby power primary PWM power supply chips with optocoupler circuits, specifically including: When the power system is detected to be operating in normal wake-up mode and the operating frequency is higher than or equal to the preset value, the primary PWM power chip enters the first mode. Its power supply is provided by the transformer auxiliary winding, and it has the function of internally maintaining a constant voltage range. When the power system is detected to be entering sleep mode, the VCC voltage of the primary PWM power chip has a rising edge waveform, and the switching frequency of the primary PWM power chip is lower than the preset value, the power supply of the primary PWM power chip enters the second mode. Its power supply is entirely provided by the auxiliary winding, and it does not have the function of forcibly maintaining a constant voltage range. When the output voltage drops too low or the secondary control chip does not provide the voltage pulse to maintain drive in sleep mode, the VCC voltage of the primary PWM power chip can drop below the undervoltage shutdown voltage, and a restart begins. Wherein: Entering the second mode specifically includes: The secondary control chip enters sleep mode based on the rising edge waveform of the VCC voltage of the primary PWM power chip after the primary PWM power chip enters sleep mode. The switching frequency of the primary PWM power supply chip is used as condition two to determine whether the secondary control chip enters sleep mode. Its power supply is entirely provided by the auxiliary winding, and it does not have the function of forcibly maintaining a constant voltage range, specifically including: The primary PWM power chip's VCC voltage holding function, provided by the high-voltage HV terminal, fails. It can only supply energy to the VCC terminal through the transformer winding when a drive pulse is present, allowing the VCC voltage to rise. Without a drive pulse, the VCC voltage will continue to drop to UVLO, the undervoltage lockout voltage, as the chip itself consumes power.

2. The method for preventing latch-up of a switching power supply chip according to claim 1, characterized in that, The condition for determining whether the secondary control chip enters sleep mode is based on the existence of a rising edge waveform of the VCC voltage of the primary PWM power supply chip after the primary PWM power supply chip enters sleep mode. Specifically, this includes: After receiving the sleep signal from the secondary, the primary PWM power chip first enters the sleep transition state. During the sleep transition state, the power supply of the primary PWM power chip enters the VCC voltage holding mode. When the primary PWM power chip receives the voltage pulse signal transmitted by the secondary through the auxiliary winding, the VCC voltage will rise from the VCC holding voltage by one voltage step. The appearance of this voltage step is one of the conditions for determining that the secondary control chip has entered the sleep mode.

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