A dead-time-free three-level topology circuit and a three-phase dead-time-free three-level topology circuit
By designing a dead-zone-free three-level topology circuit, and utilizing a combination of capacitors and switching transistors, bridge arm shoot-through and inductor current surges are avoided. This solves the problems of bridge arm shoot-through and dead-zone harmonics in the three-level topology, thereby improving circuit safety and power quality.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HEFEI UNIV OF TECH
- Filing Date
- 2023-12-15
- Publication Date
- 2026-06-26
AI Technical Summary
In a three-level topology, the delayed turn-off of the power switch leads to a shoot-through of the bridge arm, causing a momentary short circuit on the DC side. Furthermore, the dead time introduces low-order harmonics, reducing the quality of the circuit's output power.
A dead-zone-free three-level topology circuit is adopted. By combining capacitors and switching transistors, the characteristic that the inductor current cannot change abruptly is used to avoid bridge arm shoot-through. Diode freewheeling is used to avoid inductor current change abruptly. The control signal design ensures the proper conduction and turn-off of the switching transistors.
This achieves zero shoot-through risk in the bridge arm, avoids low-order harmonics introduced by dead zones, improves circuit safety and reliability, and maintains power quality without increasing the number of external diodes.
Smart Images

Figure CN117767780B_ABST