Apparatus and method for channel coding / decoding in a communication or broadcasting system

Abstract

A method and apparatus for channel encoding, decoding in a communication or broadcasting system are provided. The method for channel encoding includes identifying a block size based on input bits, performing an encoding process for encoding the input bits based on a parity check matrix corresponding to the block size, and transmitting the encoded input bits. The parity check matrix is identified based on a base matrix. The base matrix includes a sub-matrix composed of a plurality of rows and columns. Column indices corresponding to non-zero elements included in two or more consecutive rows in the sub-matrix include different values for the two or more consecutive rows. The parity check matrix is identified based on the values 1 in the base matrix being replaced by a matrix that is not a zero matrix. The number of rows in the sub-matrix is less than the number of rows in the base matrix, and the number of columns in the sub-matrix is less than the number of columns in the base matrix.

Description

[0001] This application is a divisional application of the invention patent application filed on March 30, 2018, with application number 201880023086.6 and entitled "Apparatus and method for channel coding / decoding in a communication or broadcasting system". Technical Field

[0002] This disclosure relates to an apparatus and method for channel coding / decoding in a communication or broadcasting system. More specifically, this disclosure relates to an apparatus and method for low-density parity check (LDPC) coding / decoding capable of supporting various input lengths and coding rates. Background Technology

[0003] To meet the growing demand for wireless data services since the deployment of fourth-generation (4G) communication systems, efforts have been made to develop improved fifth-generation (5G) or pre-5G communication systems. Therefore, 5G or pre-5G communication systems are also referred to as "beyond 4G networks" or "post-Long Term Evolution (LTE) systems."

[0004] 5G communication systems are being considered for implementation in higher-frequency millimeter-wave (mmWave) bands (e.g., the 60 GHz band) to achieve higher data rates. To reduce radio wave propagation loss and increase transmission distance, beamforming, massive MIMO (Multiple-Input And Multiple-Output), full-dimensional MIMO (FD-MIMO), array antennas, analog beamforming, and massive MIMO technologies are being discussed in 5G communication systems.

[0005] In addition, in 5G communication systems, system network improvements are being developed based on advanced small cells, radio access networks (RAN), ultra-dense networks, device-to-device (D2D) communication, wireless backhaul, mobile networks, cooperative communication, coordinated multi-points (CoMP), and receiver interference cancellation.

[0006] In 5G systems, Hybrid FSK and QAM modulation (FQAM) and Sliding Window Superposition Coding (SWSC) as Advanced Coding Modulation (ACM), and Filter Bank Multi Carrier (FBMC), Non-Orthogonal Multiple Access (NOMA), and Sparse Code Multiple Access (SCMA) as advanced access technologies have been developed. In communication or broadcasting systems, link performance can be significantly degraded due to various types of channel noise, fading phenomena, and inter-symbol interference (ISI). Therefore, to implement high-speed digital communication or broadcasting systems requiring high data throughput and reliability (such as next-generation mobile communications, digital broadcasting, and portable internet), it is necessary to develop technologies capable of overcoming noise, fading, and ISI. Recently, as part of research on overcoming noise, research on error-correcting codes has been actively pursued as a method to enhance communication reliability by effectively recovering information distortion.

[0007] The above information is presented as background information only to aid in understanding this disclosure. No determination or assertion is made as to whether any of the above content is applicable to prior art with respect to this disclosure. Summary of the Invention

[0008] Technical issues

[0009] This disclosure addresses at least the aforementioned problems and / or disadvantages, and provides at least the advantages described below. Therefore, one aspect of this disclosure is intended to provide an apparatus and method for low-density parity-check (LDPC) encoding / decoding capable of supporting various input lengths and encoding rates.

[0010] Another aspect of this disclosure provides a method for designing an elementary matrix for parity checking matrices of LDPC codes that support very high decoder throughput.

[0011] Another aspect of this disclosure is to provide a method for designing a parity check matrix based on an elementary matrix of the designed parity check matrix.

[0012] Another aspect of this disclosure is to provide an apparatus and method for supporting LDPC encoding / decoding of various codeword lengths from a parity check matrix of a design.

[0013] Problem Solution

[0014] According to one aspect of this disclosure, a method for channel coding in a communication system is provided, the method being performed by means including a transceiver and at least one processor coupled to the transceiver, the method comprising: identifying a block size based on input bits by the at least one processor; performing an encoding process by the at least one processor for encoding the input bits based on a parity check matrix corresponding to the block size; and transmitting the encoded input bits by the transceiver, wherein the parity check matrix is ​​identified based on a base matrix, wherein the base matrix includes a submatrix consisting of a plurality of rows and columns, wherein column indices corresponding to non-zero elements included in two or more consecutive rows in the submatrix include different values ​​for the two or more consecutive rows, wherein the parity check matrix is ​​identified based on the value 1 in the base matrix being replaced by a matrix that is not a zero matrix, and wherein the number of rows in the submatrix is ​​less than the number of rows in the base matrix, and the number of columns in the submatrix is ​​less than the number of columns in the base matrix.

[0015] According to another aspect of this disclosure, a method for channel decoding in a communication system is provided, the method being performed by means including a transceiver and at least one processor coupled to the transceiver, the method comprising: receiving a signal corresponding to input bits via the transceiver; identifying a block size based on the input bits via the at least one processor; and performing a decoding process via the at least one processor for encoding the signal based on a parity check matrix corresponding to the block size, wherein the parity check matrix is ​​identified based on a base matrix, wherein the base matrix includes a submatrix consisting of a plurality of rows and columns, wherein column indices corresponding to non-zero elements included in two or more consecutive rows in the submatrix include different values ​​for the two or more consecutive rows, wherein the parity check matrix is ​​identified based on the value 1 in the base matrix being replaced by a matrix that is not a zero matrix, and wherein the number of rows in the submatrix is ​​less than the number of rows in the base matrix, and the number of columns in the submatrix is ​​less than the number of columns in the base matrix.

[0016] According to another aspect of this disclosure, an apparatus for channel coding in a communication system is provided, the apparatus comprising: a transceiver; and at least one processor coupled to the transceiver and configured to: identify a block size based on input bits; perform an encoding process for encoding the input bits based on a parity check matrix corresponding to the block size; and control the transceiver to transmit the encoded input bits, wherein the parity check matrix is ​​identified based on a base matrix, wherein the base matrix comprises a submatrix consisting of a plurality of rows and columns, wherein column indices corresponding to non-zero elements included in two or more consecutive rows in the submatrix include different values ​​for the two or more consecutive rows, wherein the parity check matrix is ​​identified based on the value 1 in the base matrix being replaced by a matrix that is not a zero matrix, and wherein the number of rows in the submatrix is ​​less than the number of rows in the base matrix, and the number of columns in the submatrix is ​​less than the number of columns in the base matrix.

[0017] According to another aspect of this disclosure, an apparatus for channel decoding in a communication system is provided, the apparatus comprising: a transceiver; and at least one processor coupled to the transceiver and configured to: control the transceiver to receive a signal corresponding to input bits, identify a block size based on the input bits, and perform a decoding process for encoding the signal based on a parity check matrix corresponding to the block size, wherein the parity check matrix is ​​identified based on a base matrix, wherein the base matrix comprises a submatrix consisting of a plurality of rows and columns, wherein column indices corresponding to non-zero elements included in two or more consecutive rows in the submatrix include different values ​​for the two or more consecutive rows, wherein the parity check matrix is ​​identified based on the value 1 in the base matrix being replaced by a matrix that is not a zero matrix, and wherein the number of rows in the submatrix is ​​less than the number of rows in the base matrix, and the number of columns in the submatrix is ​​less than the number of columns in the base matrix.

[0018] According to another aspect of this disclosure, a method for channel coding in a communication or broadcasting system is provided. The method includes: determining a block size Z; and performing coding based on the block size and a parity check matrix corresponding to the block size, wherein the parity check matrix is ​​determined based on a base matrix and a plurality of cyclic permutation matrices, and wherein a portion of the column index indicating the position of a non-zero element in each row of the base matrix includes an index according to the mathematical expression 22 below.

[0019] According to another aspect of this disclosure, a method for channel decoding in a communication or broadcasting system is provided. The method includes: determining a block size Z; and performing decoding based on the block size and a parity check matrix corresponding to the block size, wherein the parity check matrix is ​​determined based on a base matrix and a plurality of cyclic permutation matrices, and wherein a portion of the column index indicating the position of a non-zero element in each row of the base matrix includes an index according to the following mathematical expression 22.

[0020] According to another aspect of this disclosure, an apparatus for channel coding in a communication or broadcasting system is provided. The apparatus includes: a transceiver; and at least one processor, wherein the at least one processor is configured to determine a block size Z and perform coding based on the block size and a parity check matrix corresponding to the block size, wherein the parity check matrix is ​​determined based on a base matrix and a plurality of cyclic permutation matrices, and wherein a portion of the column index indicating the position of a non-zero element in each row of the base matrix includes an index according to the following mathematical expression 22.

[0021] According to another aspect of this disclosure, an apparatus for channel decoding in a communication or broadcasting system is provided. The apparatus includes: a transceiver; and at least one processor, wherein the at least one processor is configured to determine a block size Z and perform decoding based on the block size and a parity check matrix corresponding to the block size, wherein the parity check matrix is ​​determined based on a base matrix and a plurality of cyclic permutation matrices, and a portion of the column index indicating the position of a non-zero element in each row of the base matrix includes an index according to the following mathematical expression 38.

[0022] According to another aspect of this disclosure, a method for generating LDPC codes in a communication or broadcasting system is provided. The method includes a weight distribution of an elementary matrix satisfying a balance condition.

[0023] According to another aspect of this disclosure, a method for generating LDPC codes in a communication or broadcasting system is provided. The method includes a weight distribution of an elementary matrix satisfying a partial window orthogonality condition.

[0024] According to another aspect of this disclosure, a method for channel decoding in a communication or broadcasting system is provided. The method includes: determining the block size of a parity check matrix; and reading out a sequence used to generate a parity check matrix in which the weight distribution is strongly balanced. The method further includes transforming the sequence by applying operations to the sequence.

[0025] Beneficial effects of the invention

[0026] According to one aspect of this disclosure, LDPC codes can be supported for variable length and variable rate.

[0027] Other aspects, advantages, and distinctive features of this disclosure will become apparent to those skilled in the art from the following detailed description of various embodiments disclosed in conjunction with the accompanying drawings. Attached Figure Description

[0028] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0029] Figure 1 This is a diagram illustrating the structure of a systematic low-density parity-check (LDPC) codeword according to an embodiment of the present disclosure;

[0030] Figure 2 This is a diagram illustrating a graphical representation method of LDPC codes according to embodiments of the present disclosure;

[0031] Figure 3 This is a diagram illustrating the structure of the parity check matrix of an LDPC code according to an embodiment of the present disclosure;

[0032] Figure 4A , Figure 4B and Figure 4C This is a diagram illustrating the index matrix according to various embodiments of the present disclosure;

[0033] Figure 5 This is a diagram of an elementary matrix according to an embodiment of the present disclosure;

[0034] Figure 6 It is based on embodiments of this disclosure for those having Figure 5 A diagram illustrating the scheduling of LDPC decoding of the parity check matrix of the elementary matrix using two block parallel processors;

[0035] Figure 7 This is a diagram of an elementary matrix according to an embodiment of the present disclosure;

[0036] Figure 8 It is based on embodiments of this disclosure for those having Figure 7 A diagram illustrating the scheduling of LDPC decoding of the elementary matrix parity check matrix using two block parallel processors;

[0037] Figure 9A , Figure 9B and Figure 9C This is a diagram illustrating the index matrix according to various embodiments of the present disclosure;

[0038] Figure 10 This is a block diagram illustrating the configuration of a transmitting / receiving device according to an embodiment of the present disclosure;

[0039] Figure 11AThis is a diagram illustrating the structure of a decoding device according to an embodiment of the present disclosure;

[0040] Figure 11B This is a diagram illustrating the structure of an encoding device according to an embodiment of the present disclosure;

[0041] Figure 12 This is a diagram illustrating the structure of a transport block according to an embodiment of the present disclosure;

[0042] Figure 13A , Figure 13B , Figure 13C , Figure 13D , Figure 13E , Figure 13F , Figure 13G , Figure 13H and Figure 13I These are illustrations of other elementary matrices according to various embodiments of this disclosure;

[0043] Figure 14A , Figure 14B , Figure 14C , Figure 14D , Figure 14E , Figure 14F , Figure 14G , Figure 14H and Figure 14I This is a diagram illustrating other index matrices according to various embodiments of the present disclosure;

[0044] Figure 15A , Figure 15B and Figure 15C These are illustrations of other elementary matrices according to various embodiments of this disclosure;

[0045] Figure 16A , Figure 16B , Figure 16C , Figure 16D and Figure 16E These are illustrations of other elementary matrices according to various embodiments of this disclosure;

[0046] Figure 17A , Figure 17B , Figure 17C , Figure 17D and Figure 17E These are illustrations of other elementary matrices according to various embodiments of this disclosure;

[0047] Figure 18A , Figure 18B , Figure 18C , Figure 18D and Figure 18E These are illustrations of other elementary matrices according to various embodiments of this disclosure;

[0048] Figure 19A , Figure 19B , Figure 19C , Figure 19D and Figure 19E This is a diagram illustrating other index matrices according to various embodiments of the present disclosure;

[0049] Figure 20A , Figure 20B , Figure 20C , Figure 20D and Figure 20E This is a diagram illustrating other index matrices according to various embodiments of the present disclosure;

[0050] Figure 21A , Figure 21B , Figure 21C , Figure 21D , Figure 21E , Figure 21F , Figure 21G , Figure 21H , Figure 21I and Figure 21J These are illustrations of other elementary matrices according to various embodiments of this disclosure;

[0051] Figure 22A , Figure 22B , Figure 22C and Figure 22D This is a diagram illustrating other index matrices according to various embodiments of the present disclosure;

[0052] Figure 23A , Figure 23B , Figure 23C and Figure 23D This is a diagram illustrating other index matrices according to various embodiments of the present disclosure; and

[0053] Figure 24A , Figure 24B , Figure 24C and Figure 24D These are illustrations of other elementary matrices according to various embodiments of the present disclosure.

[0054] Throughout the accompanying drawings, similar reference numerals will be understood to refer to similar parts, components, and structures. Detailed Implementation

[0055] The following description, provided with reference to the accompanying drawings, is intended to aid in a full understanding of the various embodiments of the present disclosure as defined by the claims and their equivalents. It includes various specific details to aid understanding, but these will be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the various embodiments described herein without departing from the scope and spirit of the present disclosure. Additionally, descriptions of well-known functions and structures may be omitted for clarity and brevity.

[0056] The terms and words used in the following description and claims are not limited to their literal meaning, but are used by the inventors only to enable a clear and consistent understanding of this disclosure. Therefore, it will be apparent to those skilled in the art that the following description providing various embodiments of this disclosure is for illustrative purposes only and is not intended to limit the purpose of this disclosure as defined by the appended claims and their equivalents.

[0057] It should be understood that the singular forms “a” and “the” include plural indicators unless the context clearly specifies otherwise. Thus, for example, a reference to “component surface” includes a reference to one or more such surfaces.

[0058] The term “substantially” means that the characteristic, parameter, or value does not need to be precisely achieved, but rather deviations or variations (including, for example, tolerances, measurement errors, measurement accuracy limitations, and other factors known to those skilled in the art) may occur in a quantity that does not preclude the effect that the characteristic is intended to provide.

[0059] Low-density parity-check (LDPC) codes, first introduced by Gallager in the 1960s, were largely forgotten due to their complexity, which was difficult to implement with the technology available at the time. However, in 1993, due to the performance of turbo codes proposed by Berrou, Glavieux, and Thitimajshima, which showed near-Shannon channel capacity, much research was conducted on graph-based and iterative decoding-based channel coding, leveraging extensive analysis of the performance and characteristics of turbo codes. Taking advantage of this, LDPC codes were re-examined in the latter half of the 1990s, and it became clear that LDPC codes also possess near-Shannon channel capacity performance by applying iterative decoding based on a sum-product algorithm to the Tanner graph corresponding to the LDPC codes.

[0060] Typically, LDPC codes are defined as parity check matrices and can be represented using a bipartite graph commonly known as a Tanner graph.

[0061] Figure 1 This is a diagram illustrating the structure of a systematic LDPC codeword according to an embodiment of the present disclosure.

[0062] In the following text, see references Figure 1 This will describe the systematic LDPC codewords.

[0063] refer to Figure 1 LDPC code reception is handled by K ldpc Bit or K ldpc The information word 102, consisting of N symbols, is taken as input and generated as a result. ldpc Bit or Nldpc The codeword consists of K symbols. For ease of explanation, the input is assumed to include K symbols. ldpc The information word 102 is generated from N bits. ldpc The codeword is 100, composed of bits. For example, if it is composed of K... ldpc Information word composed of input bits If 102 is LDPC encoded, then the codeword is generated. 100. For example, an information word and a codeword are bit strings composed of multiple bits, and the information word bits and codeword bits represent the individual bits that make up the information word and codeword. If the codeword includes an information word, such as:

[0064] It is then called systematic code. Here, It has 104 parity bits, and the number of parity bits is N. parity It can be expressed as N parity =N ldpc -K ldpc .

[0065] LDPC code is a linear block code and includes the process of determining codewords that satisfy the conditions expressed in the following mathematical expression 1.

[0066] [Mathematical Expression 1]

[0067]

[0068] Here, C is

[0069] In mathematical expression 1, H represents the parity check matrix, C represents the codeword, and c i Represents the i-th bit, and N ldpc This indicates the length of the LDPC codeword. Here, h i This represents the i-th column of the parity check matrix H.

[0070] Parity check matrix H is composed of N ldpc The parity check matrix is ​​composed of columns, where the number of columns equals the number of bits in the LDPC codeword. Since mathematical expression 1 implies that the i-th column h of the parity check matrix... i With the i-th codeword bit c i The sum of the products of the i-th column h is 0, therefore the i-th column h i With the i-th codeword bit c i Related.

[0071] Figure 2 This is a diagram illustrating a graphical representation method of LDPC codes according to an embodiment of the present disclosure.

[0072] refer to Figure 2 This will describe the graphical representation method of LDPC codes.

[0073] Figure 2 An example of the parity check matrix H1 of an LDPC code consisting of 4 rows and 8 columns is shown, along with a Tanner plot illustrating H1. References Figure 2 Since the parity check matrix H1 has 8 columns, it generates codewords of length 8. The code generated by H1 means LDPC code, and each column corresponds to 8 bits of the encoding.

[0074] refer to Figure 2 The Tanner graph of the LDPC code, which performs encoding and decoding based on the parity check matrix H1, consists of eight variable nodes x1(202), x2(204), x3(206), x4(208), x5(210), x6(212), x7(214), and x8(216), and four parity check nodes 218, 220, 222, and 224. Here, the i-th column and j-th row of the parity check matrix H1 of the LDPC code correspond to the variable node xi and the j-th parity check node, respectively. Furthermore, the value 1 at the intersection of the j-th column and j-th row of the parity check matrix H1 of the LDPC code, i.e., a non-zero value, indicates the existence of an edge in the Tanner graph connecting the variable node xi and the j-th parity check node, such as... Figure 2 As shown.

[0075] In the Tanner graph of an LDPC code, the degree of the variable node and the parity node represents the number of edges connecting each node, and this number is equal to the number of non-zero entries in the column or row corresponding to the corresponding node in the parity check matrix of the LDPC code. For example, Figure 2 The degrees of variable nodes x1(202), x2(204), x3(206), x4(208), x5(210), x6(212), x7(214), and x8(216) change to 4, 3, 3, 3, 2, 2, 2, and 2 respectively, and the degrees of check nodes 218, 220, 222, and 224 change to 6, 5, 5, and 5 respectively. Furthermore, in relation to... Figure 2 The corresponding variable node Figure 2 In each column of the parity check matrix H1, the number of non-zero elements corresponds to the degrees 4, 3, 3, 3, 2, 2, 2, and 2 mentioned above, and is consistent with... Figure 2 The corresponding verification node Figure 2 In each row of the parity check matrix H1, the number of non-zero elements is consistent with the degrees 6, 5, 5 and 5 mentioned above.

[0076] It can be based on Figure 2An iterative decoding algorithm based on the sum-product algorithm on a bipartite graph is used to decode LDPC codes. Here, the sum-product algorithm is a message-passing algorithm, and such a message-passing algorithm is one in which messages are exchanged through edges on the bipartite graph and messages are computed from input nodes to variable nodes or check nodes, and output messages are updated.

[0077] Here, the value of the i-th coded bit can be determined based on the message of the i-th variable node. For the i-th coded bit value, both hard and soft decision are possible. Therefore, the performance of ci as the i-th bit of the LDPC codeword corresponds to the performance of the i-th variable node in the Tanner graph, and this can be determined based on the position and number of 1s in the i-th column of the parity check matrix. In other words, the N of the codeword... ldpc The performance of a codeword bit can be dominated by the position and number of 1s in the parity check matrix, meaning that the performance of LDPC codes is greatly affected by the parity check matrix. Therefore, in order to design LDPC codes with superior performance, a method for designing a good parity check matrix is ​​needed.

[0078] To implement parity check matrices used in communication or broadcasting systems, quasi-cyclic LDPC (QC-LDPC) codes, which typically use quasi-cyclic parity check matrices, are widely used.

[0079] The QC-LDPC code is characterized by having a parity check matrix consisting of a zero matrix in the form of a square matrix, or a cyclic permutation matrix. In this case, the permutation matrix indicates that all elements of the square matrix are either 0 or 1, and each row or column contains only one 1. Furthermore, a cyclic permutation matrix means a matrix in which the elements of the identity matrix are cyclically shifted to the right.

[0080] The QC-LDPC code will be described below.

[0081] As defined in mathematical expression 2, P = (P) is a variable of size L × L. i，j Here, P i，j This means the element in the i-th row and j-th column of matrix P (where 0 ≤ i and j < L).

[0082] [Mathematical Expression 2]

[0083]

[0084] For the permutation matrix P defined above, P i (0≤i<L) is a cyclic permutation matrix, which is of the form that the elements of an identity matrix of size L×L are cyclically shifted up to i times in the right direction.

[0085] The parity check matrix H of the simplest QC-LDPC code can be expressed in the form of the following mathematical expression 3.

[0086] [Mathematical Expression 3]

[0087]

[0088] If P -1 Defined as a zero matrix of size L×L, then each exponent a of the cyclic permutation matrix or zero matrix in mathematical expression 3 is... i，j It has one of the values ​​{-1, 0, 1, 2, ..., L-1}. Furthermore, since the parity check matrix H in mathematical expression 3 has n column blocks and m row blocks, it has a size of mL × mL.

[0089] If the parity check matrix in mathematical expression 3 has full rank, it is clear that the size of the information word bits of the QC-LDPC code corresponding to the parity check matrix becomes (nm)L. For convenience, the (nm) column blocks corresponding to the information word bits are called column blocks, and the m column blocks corresponding to the remaining parity bits are called parity column blocks.

[0090] Typically, the binary matrix of size m×n obtained by replacing each cyclic permutation matrix and the zero matrix with 1 and 0 respectively in the parity matrix of mathematical expression 3 is called the parent matrix or base matrix M(H), and the integer matrix of size m×n obtained by choosing the exponent of each cyclic permutation matrix and the zero matrix is ​​called the exponent matrix E(H) of the parity matrix.

[0091] [Mathematical Expression 4]

[0092]

[0093] As a result, an integer included in the exponent matrix corresponds to a cyclic permutation matrix in the parity check matrix, and therefore, for convenience, the exponent matrix can be expressed as a sequence of integers (this sequence can also be referred to as an LDPC sequence or a sequence of LDPC codes to distinguish it from other sequences). Typically, the parity check matrix can be expressed not only as an exponent matrix but also as a sequence having the same algebraic properties. In embodiments of this disclosure, for convenience, the parity check matrix is ​​expressed as an exponent matrix or sequence indicating the positions of 1s present in the parity check matrix. However, there are various sequence notation methods capable of distinguishing between the positions of 1s and 0s included in the parity check matrix, and therefore the parity check matrix is ​​not limited to the method expressed in the description but can be expressed in various sequence forms that represent the same algebraic effect.

[0094] Furthermore, according to the features of the implementation, the transceiver on the device can perform LDPC encoding and decoding by directly generating a parity check matrix, or it can perform LDPC encoding and decoding using an exponential matrix or sequence that has the same effect as a parity check matrix algebraically. Therefore, although encoding / decoding using a parity check matrix has been described in the embodiments of this disclosure for convenience, it should be considered that various methods capable of achieving the same effect as a parity check matrix can be used to implement encoding / decoding.

[0095] For reference, the same effect in algebra means that two or more different expressions can be interpreted as logically or mathematically identical or interchangeable.

[0096] In the embodiments of this disclosure, for convenience, a cyclic permutation matrix is ​​described as corresponding to a block; however, this disclosure can also be applied to situations where several cyclic permutation matrices are included in a block. For example, if two cyclic permutation matrices... If the sum is included in a position in the i-th row block and the j-th column block, then the exponential matrix can be expressed as mathematical expression 6. In the matrix as in mathematical expression 6, it can be known that two integers correspond to the i-th row and j-th column corresponding to the row block and column block containing the sum of multiple cyclic permutation matrices.

[0097] [Mathematical Expression 5]

[0098]

[0099] [Mathematical Expression 6]

[0100]

[0101] As in the embodiments described above, a typical QC-LDPC code is characterized by multiple cyclic permutation matrices corresponding to a row block and a column block of a parity check matrix. In this disclosure, for convenience, only the case where one cyclic permutation matrix corresponds to one block will be described, but the subject matter of this disclosure is not limited thereto. For reference, a matrix of size L×L in which multiple cyclic permutation matrices repeat in a row block and a column block is called a cyclic matrix or a cycle.

[0102] On the other hand, the parent matrix or basis matrix and exponent matrix of the parity check matrix in mathematical expressions 5 and 6 mean the binary matrix obtained by replacing each cyclic permutation matrix and zero matrix with 1 and 0 respectively in a manner similar to the definition used in mathematical expression 3, and simply replacing the sum of multiple cyclic permutation matrices (i.e., cyclic matrices) included in a block with 1.

[0103] Since the performance of LDPC codes is determined based on the parity check matrix, it is necessary to design a parity check matrix for LDPC codes with superior performance. Furthermore, for various services in the system, LDPC encoding or decoding methods that support flexible input lengths and encoding rates are essential. When designing LDPC codes, not only encoding performance and flexibility but also decoding efficiency become important factors. Generally, it is well known that QC-LDPC codes have structures favorable for parallel decoding, and parallel decoding is suitable for reducing latency caused by decoding by increasing decoding throughput. Parallel decoding of QC-LDPC codes can further maximize decoding efficiency based on the basis matrix of the parity check matrix. In embodiments of this disclosure, a basis matrix structure that maximizes decoding efficiency is proposed, and furthermore, a method for designing the basis matrix is ​​presented.

[0104] Figure 3 This is a diagram illustrating the structure of the parity check matrix of an LDPC code according to an embodiment of the present disclosure.

[0105] refer to Figure 3 The description will be as follows Figure 3 The structure of the parity check matrix is ​​shown. Figure 3 In the matrix, portions of matrices A and D correspond to K information word bits, and the remaining portions of matrices B and D correspond to G first parity bits. Matrices C and E correspond to (NKG) second parity bits. Typically, based on... Figure 3 In an LDPC encoding / decoding system with a parity check matrix structure, C can be configured as a zero matrix, and E can be restricted to an identity matrix or a lower triangular matrix. In embodiments of this disclosure, various multi-rate or high-flexibility techniques, such as Incremental Redundancy (IR) HARQ, are employed. For ease of explanation, the following description only addresses the case where E is an identity matrix; however, the subject matter of this disclosure is not limited to the case where E is an identity matrix.

[0106] Figures 4A to 4C This is a diagram of an index matrix according to various embodiments of the present disclosure.

[0107] refer to Figures 4A to 4C The following will describe Figure 4A The exponential matrix. For reference, Figure 4B and Figure 4C It is shown Figure 4A Enlarged view of each part of the exponential matrix. Figure 4A Each part corresponds to a matrix in which matrices corresponding to the reference numerals described in each part are combined. Therefore, it can be achieved through... Figure 4B and Figure 4C To configure by combining parts such as Figure 4AThe image shows an exponential matrix.

[0108] Figure 4A The basis matrix of the exponential matrix is ​​as follows Figure 5 As shown. In Figure 4A In the exponential matrix, an empty sub-block represents a zero matrix of size Z x Z, and the element 0 represents the identity matrix. Furthermore, in Figure 5 In the basis matrix, an empty block means that the element is 0.

[0109] Figure 5 This is a diagram of an elementary matrix according to an embodiment of the present disclosure.

[0110] refer to Figure 5 , Figure 4A The position of the circular matrix in each row block, i.e. Figure 5 The position of 1 in each row can be generalized based on column blocks, as exemplified below (the first row is taken as the zeroth row). ...

[0112] Row-6(Row-6):{0,1,13,16,23,38}

[0113] Line-7:{1,2,4,10,11,13,17,21,27,32,39}

[0114] Line -8:{0,8,15,19,24,30,35,40}

[0115] Line -9:{0,1,5,9,14,20,22,25,41}

[0116] Line-10:{0,1,3,29,33,37,42}

[0117] Line-11:{1,6,12,14,20,23,26,43} ...

[0119] Typically, when an LDPC decoder uses a single block-parallel processor to perform the decoding of LDPC codes, the decoding is performed sequentially in units of blocks corresponding to the aforementioned positions in each row block. When using two or more block-parallel processors, each processor performs sequential decoding in units of blocks appropriately partitioned from each row block. In this case, the blocks partitioned from each row block should be determined according to the hardware implementation characteristics and rules specific to all row blocks. For example, one could consider an LDPC decoder processing cyclic permutation matrices such as those included in each row block, by partitioning them into cyclic permutation matrices corresponding to even-numbered column blocks and cyclic permutation matrices corresponding to odd-numbered column blocks. Figure 6 The diagram shows the scheduling via two block parallel processors.

[0120] Figure 6 It is based on embodiments of this disclosure for those having Figure 5 A diagram illustrating the scheduling of LDPC decoding of the elementary matrix parity check matrix using two block parallel processors.

[0121] Figure 6 An example of the scheduling enumeration positions of blocks corresponding to a cyclic permutation matrix processed by the respective processors in process order is shown. For example, processor 0 processes line -6 in the order of block 0, block 16, and block 38, and then processes line -7 in the order of block 2, block 4, block 10, block 32, and block 39.

[0122] refer to Figure 6 According to the established rules, the first processor processes only cyclic permutation matrices located in even-numbered column blocks, and the second processor processes only cyclic permutation matrices located in odd-numbered column blocks. Here, it is assumed that column blocks with a degree of 1 do not follow the above rules, and in order to minimize the idle time of each processor, the appropriate processor may selectively process the corresponding column blocks.

[0123] Even if an LDPC decoder designed using the above rules with two block parallel processors can properly arrange the blocks corresponding to column blocks of degree 1, the idle time of a particular processor may still become longer, such as... Figure 6 The case of row -10. Because of the inefficiency of such processing, the overall processing time is ultimately increased, thus reducing the hourly decoding throughput, which can lead to decoding latency as a result. In other words, in the normal scenario of performing decoding using two or more block-parallel processors, each processor needs to divide the blocks included in its respective row block (i.e., the cyclic permutation matrix) into a set as large as the number of processors according to appropriate rules, so as to properly allocate the blocks to be processed by each processor.

[0124] However, after designing the base matrix of the parity check matrix of the LDPC code without considering the use of two or more block parallel processors, it is often difficult to divide it into as many blocks as the number of processors using the appropriate rules described above. Specifically, this is much more difficult when it is unknown whether the LDPC decoder uses two, three, or four block parallel processors.

[0125] This disclosure proposes a method for designing a basis matrix that maximizes decoding efficiency based on the use of two or more block parallel processors by restricting the position of the cyclic permutation matrix in the exponent matrix (i.e., by restricting the position of element 1 in the basis matrix based on the use of multiple block parallel processors).

[0126] First, if we assume that the basis matrix to be designed is... Figure 3Given the matrices, we can consider A to be of size g x k, B to be of size g x g, D to be of size (n kg) x (k + g), and E to be of size (n kg) x (n kg). For ease of explanation, the following embodiments of this disclosure will describe the case where C is a zero matrix and E is an identity matrix, but in essence, the methods presented in the embodiments of this disclosure are not necessarily limited to this.

[0127] The main objective of this disclosure is to propose a method for designing a basis matrix such that the position index of each element 1 in each row of the basis matrix is ​​partitioned into multiple sets according to a predetermined rule based on the use of multiple block parallel processors, wherein the number of elements in these multiple sets is similar to each other. For convenience, the partitioning of the position index of each element 1 in each row of the basis matrix into sets where the number of elements is similar according to the predetermined rule is called balanced. In other words, balanced means the maximum uniformity of allocation when allocating each element 1 in each row to two or more sets according to the predetermined rule.

[0128] In this context, a perfect balance is defined as the difference between the number of element 1s in rows assigned to two or more sets that is equal to or less than 1, while a weak balance is defined as the difference between the number of element 1s in rows assigned to two or more sets that is equal to or less than 2.

[0129] In other words, balance means classifying the elements 1 in each row into two or more groups as uniformly as possible according to predetermined rules. In this case, if the difference between the number of elements 1 included in the two or more groups is equal to or less than 1, it is called a perfect balance, while if the difference between the number of elements 1 in the rows assigned to the two or more sets is equal to or less than 2, it is called a weak balance.

[0130] In other words, when expressing this balance, the balance of the basis matrix can mean that the elements 1 in each row can be classified into two or more groups or sets according to a predetermined rule, and the case in which the difference between the number of elements 1 included in each group or set or the difference between the number of their indices is equal to or less than 1 can be expressed as the basis matrix satisfies perfect balance, while the case in which the difference is equal to or less than 2 can be expressed as the basis matrix satisfies weak balance.

[0131] On the other hand, in embodiments of this disclosure, the terms first balance, second balance, and third balance can be used to express balances with different characteristics, such as perfect balance, weak balance, and strong balance. The basis matrix designed above is used to reduce idle time when LDPC decoding is performed using block parallel processors based on position indices corresponding to the respective sets, where the number of block parallel processors corresponds to the number of sets. Here, it is evident that the position indices can have numbers from 0 to (n-1).

[0132] Before designing the basis matrix, assume that the possible number of block-parallel processors to be used when performing LDPC decoding using the parity check matrix of the LDPC code with the corresponding basis matrix corresponds to q1, q2, ..., q P In other words, assuming that it uses q1, q2, ..., q P The basis matrix is ​​designed to handle all cases of parallel processors. If we assume that LDPC decoding is performed using qi (i = 1, 2, ..., P) block processors, to minimize idle time, the indexes of the positions of 1 in each row of degree d in the basis matrix are j1, j2, ..., j... d It should be divided into q elements that have the same number of elements to the maximum extent. i Partial matrix. This should be constructed in the same way for all rows.

[0133] Examples that satisfy these characteristics are as follows.

[0134] First, as described in mathematical expression 7, for l = 1, 2, ..., P, define q. l A set.

[0135] [Mathematical Expression 7]

[0136] S i ={x|x≡i(mod q)} l ), x = 0, 1, ..., n-1

[0137] i = 0, 1, 2, ..., q l -1

[0138] To aid understanding, a simple example of mathematical expression 7 is shown in mathematical expression 8 below.

[0139] [Mathematical Expression 8]

[0140] i) When defined as q1 = 2

[0141] S0={x|x≡0(mod 2),x=0,1,...45}={0,2,4,8,...,42,44}

[0142] S1={x|x≡1(mod 2),x=0,1,...45}={1,3,5,7,...,43,45}

[0143] ii) When defined as q2 = 3

[0144] S0={x|x≡0(mod 3),x=0,1,...45}={0,3,6,...,42,45}

[0145] S1={x|x≡1(mod 3), x=0,1,...45}={1,4,7,...,40,43}

[0146] S2={x|x≡2(mod 3), x=0,1,...45}={2,5,8,...,41,44}

[0147] iii) When defined as q3 = 4

[0148] S0={x|x≡0(mod 4),x=0,1,...45}={0,4,8,...,40,44}

[0149] S1={x|x≡1(mod 4), x=0,1,...45}={1,5,9,...,41,45}

[0150] S2={x|x≡2(mod 4), x=0,1,...45}={2,6,10,...,38,42}

[0151] S3={x|x≡3(mod 4), x=0,1,...45}={3,7,11,...,39,43}

[0152] (q1 = the case defined with 2 sets, q2 = the case defined with 3 sets, q3 = the case defined with 4 sets)

[0153] In mathematical expressions 7 and 8, various methods can exist for defining q1 sets. In embodiments of this disclosure, examples expressed in mathematical expressions 7 and 8 will be described for ease of explanation. However, the scope of this disclosure is not limited thereto, and in the case of generally defining q1 sets, the sets need not have the same number of elements, but can be appropriately defined as needed. However, the individual sets S... i There should always be different elements.

[0154] In the base matrix, information about the position of 1 in each row can be expressed as an index set as shown in mathematical expression 9.

[0155] [Mathematical Expression 9]

[0156] Ind(i)={w(i,j)|j=0,1,...,d i -1}, i = 0, 1, ..., NK-1.

[0157] Here, w(i,j) means the position of the j-th 1 in the i-th row within its column, and di means the degree of the i-th row.

[0158] For better understanding, please refer to... Figure 5 The following mathematical expression 10 is a simple example of expressing mathematical expression 9.

[0159] [Mathematical Expression 10]

[0160] Ind(6)={w(6,0)=0, w(6,1)=1, w(6,2)=13, w(6,3)=16, w(6,4)=23, w(6,5)=38}

[0161] Ind(10)={w(10,0)=0, w(10,1)=1, w(10,2)=3, w(10,3)=29, w(10,4)=33, w(10,5)=37,, w(10,6)=42}

[0162] The set of indices expressed in mathematical expression 9 can be divided into q1 partial sets that satisfy the following mathematical expression 11, without having common elements (l = 1, 2, ..., P).

[0163] [Mathematical Expression 11]

[0164] R(i,j)={x|x∈Ind(i)∩S j},

[0165] i=0, 1, ..., NK-1, j=0, 1, ..., q l -1

[0166] Here, S j Ind(i) and Ind(i) are sets defined in mathematical expressions 7 and 9, respectively.

[0167] It should be noted that in mathematical expression 7, for ease of interpretation, the various sets S... j They have almost the same number of elements and are simply partitioned based on the modulo operation. However, in general, it is not important whether the number of elements differs greatly from one another or whether the elements are partitioned under more complex conditions. However, different sets S... j They should be disjoint and not have common elements.

[0168] In embodiments of this disclosure, if the set R(i, j) defined in mathematical expression 11 satisfies the condition of the following mathematical expression 12, then the weight distribution of the basis matrix expressed in mathematical expression 9 is said to be perfectly balanced.

[0169] [Mathematical Expression 12]

[0170] The index set defined in mathematical expression 9 always satisfies the following

[0171] For j1≠j2, (0≤j1, j2<q) l ).||R(i,j1)|-|R(i,j2)||≤1,

[0172] i = 0, 1, ..., NK-1

[0173] In the basis matrix that satisfies the conditions expressed in mathematical expression 12, it can be seen that when the j-th processor in q1 block parallel processors continuously performs LDPC decoding on the cyclic permutation matrix included in the position R(i,j), the idle time is minimized.

[0174] However, it is difficult to design a basis matrix that satisfies the conditions expressed in mathematical expression 12. This is because the distribution of the number of 1s in each row and column of the basis matrix or parity check matrix, and the cyclic properties on the Tanner graph, play important roles in designing a good basis matrix. For example, it is difficult to design a basis matrix that simultaneously satisfies a good weight distribution, good cyclic properties, and the conditions expressed in mathematical expression 12.

[0175] For the reasons mentioned above, with respect to the conditions for the index set defined in mathematical expression 12, the weight distribution of the basis matrix that satisfies the slightly looser conditions expressed in the following mathematical expression 13 is said to be weakly balanced.

[0176] [Mathematical Expression 13]

[0177] The index set defined in mathematical expression 9 always satisfies the following

[0178] For j1≠j2, (0≤j1, j2<q) l ).

[0179] ||R(i,j1)|-|R(i,j2)||≤2, i=0,1,...,NK-1.

[0180] Even when the weight distribution of the basis matrix satisfying the conditions in mathematical expression 13 is weakly balanced, the idle time is significantly reduced when LDPC decoding is performed using multiple processors. However, it is clear that this is inefficient compared to the perfectly balanced case. Nevertheless, in this case, due to the relaxed conditions, it becomes easy to design a good parity check matrix based on the coding performance of LDPC codes.

[0181] A method is proposed in which the design of a well-designed basis matrix that simultaneously considers both perfect and weakly balanced cases is slightly simpler, and idle time can be greatly reduced during LDPC decoding using multiple processors.

[0182] First, the index set defined in mathematical expression 9 will be newly defined in mathematical expression 13 below.

[0183] [Mathematical Expression 14]

[0184] Ind(i)={w(i,j)|j=0,1,...,d i -1}, i = 0, 1, ..., NK-1.

[0185] Here, w(i, j) means the position of the column, where the j-th 1 in the i-th row exists, excluding columns with a degree of 1, and di means the degree of the i-th row, excluding elements in columns with a degree of 1.

[0186] In embodiments of this disclosure, if the set R(i,j) of the index set defined in mathematical expression 11 satisfies the condition of the following mathematical expression 15, then the weight distribution of the basis matrix expressed in mathematical expression 9 is said to be strongly balanced.

[0187] [Mathematical Expression 15]

[0188] The index set defined in mathematical expression 14 always satisfies the following

[0189] For j1≠j2, (0≤j1, j2<q) l ).

[0190] ||R(i,j1)|-|R(i,j2)||≤2, i=0,1,...,NK-1

[0191] In mathematical expression 15, columns with a degree of 1 are excluded from mathematical expression 14. This is because columns with a degree of 1 are more easily and freely assigned to block-parallel processors compared to other columns. The characteristics of strong balance expressed in mathematical expression 15 will now be described below.

[0192] Essentially, the strong balance expressed in mathematical expression 15 has similar properties to the weak balance, which can be expressed as in mathematical expression 13. However, the strong balance differs significantly from the weak balance in excluding the element-1s corresponding to columns with degree 1 when classifying the element-1s of each row of the basis matrix into two or more sets or groups. In other words, a strong balance means that, according to predetermined rules, the remaining element-1s from each row, excluding the element-1s corresponding to columns with degree 1, are uniformly distributed to two or more sets to the greatest extent possible. In this case, if the difference between the number of element-1s to be distributed to two or more sets is equal to or less than 2, it is called a realized strong balance. Furthermore, in other words, when expressing a strong balance, it means that, according to predetermined rules, the remaining element-1s from each row, excluding the element-1s corresponding to columns with degree 1, are uniformly classified into two or more groups to the greatest extent possible. In this case, if the difference between the number of element-1s to be included in two or more groups is equal to or less than 2, it is called a realized strong balance. In other words, a strong balance of the basis matrix means that the remaining elements 1 from each row, excluding those corresponding to columns with degree 1, can be classified into two or more groups or sets according to predetermined rules. In this case, the basis matrix is ​​said to satisfy the strong balance condition as expressed in mathematical expression 15 if the difference between the number of elements 1 to be included in each group or set, or the difference between the number of their indices, is equal to or less than 2. Therefore, given that the strong balance condition expressed in mathematical expression 15 is satisfied, by appropriately allocating the cyclic permutation matrices corresponding to columns with degree 1 to the processor, strong balance has properties very close to those of perfect balance as defined in mathematical expression 12, and thus can significantly reduce processor idle time.

[0193] Figure 7 This is a diagram of an elementary matrix according to an embodiment of the present disclosure.

[0194] refer to Figure 7 To aid understanding, detailed embodiments of this disclosure will be described below. Figure 7 The basis matrix is ​​shown in the diagram. Figure 7 In the basis matrix, it should be noted that an empty block means that the element is 0.

[0195] Figure 7 The position of 1 in each row (i.e., the position where the cyclic permutation matrix is ​​located in the column block of the actual parity check matrix) can be generalized based on the column block as exemplarily expressed as follows (the first row is taken as the zeroth row). ...

[0197] Line-6:{0,1,2,11,25,38}

[0198] Line-7:{1,5,10,14,15,19,20,21,32,39}

[0199] Line -8:{0,1,3,4,9,11,13,28,34,40}

[0200] Line-9:{0,1,6,7,12,26,37,41}

[0201] Line-10:{0,1,3,9,11,14,28,42}

[0202] Line-11:{0,1,2,4,5,8,27,31,43} ...

[0204] Based on using two block parallel processors for... Figure 7 The parity check matrix of the basis matrix performing LDPC decoding can be summarized by the set defined in mathematical expressions 7, 11 and 14 as expressed in the following mathematical expression 16.

[0205] [Mathematical Expression 16]

[0206] S0={x|x≡0(mod 2),x=0,1,...45},

[0207] S1={x|x≡1(mod 2), x=0, 1,..., 45},

[0208] …

[0209] Ind(6)={0,1,2,11,25},

[0210] Ind(7)={1,5,10,14,15,19,20,21,32},

[0211] Ind(8)={0,1,3,4,9,11,13,28,34},

[0212] Ind(9)={0,1,6,7,12,26,37},

[0213] Ind(10)={0,1,3,9,11,14,28},

[0214] Ind(11)={0,1,2,4,5,8,27,31,},

[0215] …

[0216] R(6,0)={0,2,38}, R(6,1)={1,11,25}

[0217] R(7,0)={10,14,20,32}, R(7,1)={1,5,15,19,21}

[0218] R(8,0)={0,4,28,34}, R(8,1)={1,3,9,11,13}

[0219] R(9,0)={0,6,12,26}, R(9,1)={1,7,37}

[0220] …

[0221] refer to Figure 7 And mathematical expression 16, can be identified Figure 7 The basis matrix satisfies mathematical expression 15, and therefore it is a strongly balanced basis matrix. Therefore, it can be considered that the LDPC decoder processes cyclic permutation matrices such as those included in the various row blocks by dividing them into cyclic permutation matrices corresponding to even-numbered column blocks and cyclic permutation matrices corresponding to odd-numbered column blocks. Figure 8 The diagram shows the scheduling via two block parallel processors.

[0222] Figure 8 It is based on embodiments of this disclosure for those having Figure 7 A diagram illustrating the scheduling of LDPC decoding of the elementary matrix parity check matrix using two block parallel processors.

[0223] Figure 8 An example of the scheduling enumeration positions of blocks corresponding to a cyclic permutation matrix processed sequentially by the respective processors is shown. For example, processor 0 processes row -6 in the order of blocks 0, 2, and 38, and then processes row -7 in the order of blocks 10, 14, 20, and 32. In this case, it can be identified that the cyclic permutation matrix corresponding to the column block with a degree of 1 is appropriately arranged in the respective processors. For example, it corresponds to the case where processor 0 processes the cyclic permutation matrix of column block 39 while processing row -7.

[0224] refer to Figure 8 It can be seen that the idle time of each processor has been minimized. Given the practical design of the basis matrix to satisfy the strong balance condition of mathematical expression 15, it becomes easy to design a basis matrix that almost approximates the perfect balance condition of mathematical expression 12.

[0225] exist Figure 8 In this case, when designing the base matrix, both the case where the number of block-parallel processors for the LDPC decoder is 2 and the case where the number of processors is 4 should be considered. For example, for... Figure 8 Assuming there are 4 processors, the basis matrix is ​​then generalized again to the following set defined in mathematical expressions 7 and 11.

[0226] S0={x|x≡0(mod 4), x=0, 1,...45},

[0227] S1={x|x≡1(mod 4), x=0, 1,..., 45},

[0228] S2={x|x≡2(mod 4), x=0, 1,...45},

[0229] S3={x|x≡3(mod 4), x=0, 1,..., 45},

[0230] …

[0231] R(6,0)={0}, R(6,1)={1,25}, R(6,2)={2}, R(6,3)={11}

[0232] R(7,0)={20,32}, R(7,1)={1,5,21}, R(7,2)={10,14}, R(7,3)={15,19}

[0233] R(8,0)={0,4,28}, R(8,1)={1,9,13}, R(8,2)={34}, R(8,3)={3,11}

[0234] R(9,0)={0,12}, R(9,1)={1,37}, R(9,2)={6,26}, R(9,3)={7}

[0235] …

[0236] As mentioned above, when designing a basis matrix with perfectly balanced, weakly balanced, or strongly balanced weight distributions, it is known that the design basis of the basis matrix changes depending on the number of block-parallel processors considered. Figure 8 In the embodiments, a strong balance condition is satisfied for both the case of using two block processors and the case of using four block processors.

[0237] If q1 sets are defined in mathematical expression 7, for convenience, the basis matrices satisfying the equilibrium conditions presented in mathematical expressions 12, 13, and 15 respectively represent perfect q1-equilibrium, weak q1-equilibrium, and strong q1-equilibrium. For example, Figure 8 The basis matrix can simultaneously satisfy weak 2-balance and weak 4-balance, or it can simultaneously satisfy 2-balance and 4-balance.

[0238] If the number of block parallel processors to be used in the LDPC decoder is unclear, and considering the simultaneous use of (q1, q2, ..., q...) P For the case of q1, q2, ..., qn, for convenience, they are expressed as perfect(q1, q2, ..., qn). P- Balanced, weak (q1, q2, ..., q P - Balance and strong (q1, q2, ..., q P )-balance.

[0239] In the embodiments of this disclosure as described above, for convenience, modulo is used to partition the set Si based on specific rules, but this is not a limitation. The partitioning of Si can be appropriately and irregularly defined according to the requirements of the system, and the number of elements in each set can be different. However, the various sets Si should have different elements to maintain the disjoint property.

[0240] In embodiments of this disclosure, a partial windowing-orthogonal condition is described as a method for designing the basis matrix of another LDPC code to minimize idle time when using two or more block parallel processors.

[0241] First, based on Figures 9A to 9C Briefly describe the structure of the base matrix or exponent matrix suitable for existing, well-known hierarchical decoding. For reference, Figure 9B and Figure 9C From Figure 9A An enlarged view of the various parts of the exponential matrix. Figure 9A Each part corresponds to a matrix, in which matrices are combined corresponding to the reference numerals describing each part. Therefore, as... Figure 9A An exponential matrix as shown can be obtained by, for example Figure 9B and Figure 9C The configuration is a combination of the parts shown.

[0242] Figures 9A to 9C This is a diagram of an index matrix according to various embodiments of the present disclosure.

[0243] refer to Figures 9A to 9C We can see that rows 6, 7, and 8 are orthogonal to each other. Here, orthogonality means that the cyclic permutation matrix does not exist in the same column block position in each row. For example, at most one cyclic permutation matrix exists in each column block of the selected rows 6, 7, and 8. Similarly, rows 9, 10, 11, and 12 are orthogonal to each other, and rows 13, 14, 15, 16, and 17 are also orthogonal to each other. However, rows 12 and 13 are not orthogonal to each other (see row 3 block).

[0244] The orthogonal structure described above is suitable for hierarchical decoding, i.e., decoding based on row-parallel processors. Row-parallel processors typically correspond to methods for performing decoding on entire row blocks and generally have a larger size and higher complexity than block-parallel processors, but can perform fast decoding compared to block-parallel processors. In row-parallel processor-based decoding, rows with orthogonal structures can be considered as a single row for decoding, thus enabling very fast decoding. For example, a row-parallel processor can perform decoding on row blocks 6, 7, and 8 with orthogonal structures as a single row block. A row block with orthogonal structures can be considered as a single row block called a valid row block. Hierarchical decoding is characterized by multiple row blocks included in such valid row blocks being orthogonal to each other, but row blocks between valid row blocks are not orthogonal to each other. For example, row blocks 12 and 13 are included in different valid row blocks and are therefore not orthogonal to each other.

[0245] When a block-parallel processor-based LDPC decoder uses two or more processors to perform decoding, a slightly different structure from the orthogonal structure described above is suitable for improving decoding efficiency.

[0246] In embodiments of this disclosure, a partially orthogonal window structure is proposed. First, the orthogonal window structure will be briefly described.

[0247] If a basis matrix exists that satisfies a p-window orthogonal structure, it means that if p row blocks are selected consecutively, they will always satisfy the orthogonal structure. In other words, when selecting the i-th, (i+1), ..., (i+p-1)-th row blocks, the p row blocks are always orthogonal to each other. A basis matrix with a p-window orthogonal structure as described above provides very high decoding efficiency during LDPC decoding, based not only on block-parallel processors but also on row-parallel processors. However, this is a very strong constraint on the basis matrix and can therefore easily lead to degradation of the coding performance of LDPC codes. Therefore, when using... Figure 3 In the LDPC encoding / decoding system with the parity check matrix structure shown, for the [AB] part of the matrix, the orthogonal structure of multiple row blocks is usually not considered; instead, only the parity check matrix is ​​considered. Figure 3 Consider the orthogonal structure of a portion of the basis matrix corresponding to a part of the parity check matrix [DE] or a portion of [DE]. It is readily known that this is suitable for... Figure 9A The exponential matrix presented in the layered decoding is only for... Figure 3 The corresponding parts of the partial matrix [DE] have an orthogonal structure.

[0248] However, orthogonal structures corresponding to a portion of the matrix [DE] or a portion thereof can also significantly constrain the degree distribution of LDPC codes, thereby degrading LDPC coding performance. To address this issue, orthogonal structures are unrestricted for specific predetermined row blocks. For example, refer to... Figure 7 The basis matrix, for the two first column blocks, does not consider orthogonality for the partial matrix [DE]. This may slightly reduce decoding efficiency, but will greatly improve encoding performance. As mentioned above, orthogonality is considered for the remainder of the parity check matrix except for specific row blocks (or rows) and column blocks (or columns) in the entire parity check matrix or its basis matrix, and if p row blocks are always orthogonal to each other when choosing the i-th, (i+1), ..., (i+p-1)-th row blocks for the remainder, then it is called a parity check matrix or basis matrix that satisfies the orthogonal structure of p partial windows.

[0249] refer to Figure 7 For except Figure 7 The remaining matrix, excluding the six upper rows and two first columns, of the base matrix has a permutation property where adjacent rows are always orthogonal. Therefore, Figure 7 This means that the basis matrix satisfies the orthogonal structure of two partial windows.

[0250] In summary, if, for a given basis matrix, the remaining part of the matrix, excluding specific rows and columns, satisfies a p-window orthogonal structure, then the basis matrix is ​​said to satisfy a p-partial window orthogonal structure.

[0251] When designing a basis matrix that satisfies a p-partial window orthogonal structure, in many cases, such as Figure 7 As shown, not targeting Figure 3 The structure corresponding to [AB] in the code is considered for orthogonality, and partial window orthogonality is considered only for the case corresponding to [DE] and excluding specific column blocks, but is not limited to this.

[0252] As a result, the apparatus and method for LDPC encoding and decoding using a parity check matrix having a basis matrix having the balance property and a partially window orthogonal structure proposed in the embodiments of this disclosure are characterized by using two or more block parallel processors to improve encoding performance and maximize decoding efficiency based on LDPC decoding.

[0253] Figure 10 This is a block diagram illustrating the configuration of a transmitting / receiving device according to an embodiment of the present disclosure.

[0254] refer to Figure 7 K ldpc Bits can be configured for the LDPC encoder 1010 of the decoding device 1000. ldpc LDPC information word bits The LDPC encoder 1010 can perform Kldpc A systematic LDPC encoding of N LDPC information word bits, and can generate N ldpc Bit Λ = (c0, c1, ..., c Nldpc-1 )=(i0,i1,...,i Kldpc-1 ,p0,p1,...,p Nldpc-Kldpc-1 LDPC codewords composed of )

[0255] As described above in mathematical expression 1, the method for LDPC encoding includes determining a codeword such that the product of the LDPC codeword and the parity check matrix becomes a zero vector.

[0256] refer to Figure 10 The encoding device includes an LDPC encoder 1010, which can generate LDPC codewords by performing LDPC encoding on input bits based on a parity check matrix or a corresponding exponent matrix or sequence. In this case, the LDPC encoder 1010 can perform LDPC encoding using a parity check matrix that is defined differently according to the code rate (i.e., the code rate of the LDPC code).

[0257] A standard QC LDPC code involves identifying the size of the input bits to be encoded, determining the appropriate block size Z for the corresponding input bits, and performing LDPC encoding based on the LDPC matrix and the determined block size. The decoding process involves a similar procedure to that described above.

[0258] On the other hand, the encoding device may further include a memory (not shown) for storing information regarding the encoding rate, codeword length, and parity check matrix of the LDPC code, and the LDPC encoder 1010 may use such information to perform LDPC encoding. In the case of using the parity matrix proposed in the embodiments of this disclosure, the information regarding the parity check matrix may be stored as information regarding the exponent values ​​of the cyclic matrix.

[0259] Decoding device 1000 may include LDPC decoder 1020. LDPC decoder 1020 performs LDPC decoding on LDPC codewords based on parity check matrix or corresponding exponent matrix or sequence.

[0260] For example, the LDPC decoder 1020 can generate information word bits by performing LDPC decoding through an iterative decoding algorithm, passing the log-likelihood ratio (LLR) value corresponding to the LDPC codeword bits.

[0261] Here, the LLR value is the channel value corresponding to the LDPC codeword bits, and it can be expressed in various ways.

[0262] For example, the LLR value can represent the value obtained by taking the logarithm of the probabilities of a bit being transmitted from the transmitting side through the channel being 0 and 1. Furthermore, the LLR value can be the bit value itself determined by hard decision, or it can be a representative value determined based on a section of the probability of a bit being 0 or 1 transmitted from the transmitting side.

[0263] In this case, the transmitting side can use the LDPC encoder 1010 to generate LDPC codewords.

[0264] In this case, the LDPC decoder 1020 can perform LDPC decoding using a parity check matrix that is defined differently according to the coding rate (i.e., the coding rate of the LDPC code).

[0265] Figure 11A This is a diagram illustrating the structure of a decoding device according to an embodiment of the present disclosure.

[0266] On the other hand, as described above, the LDPC decoder 1020 can use an iterative decoding algorithm to perform LDPC decoding, and in this case, the LDPC decoder 1020 can be configured to... Figure 11A The structure. However, since iterative decoding algorithms are already known, Figure 11A The configuration shown is the same.

[0267] refer to Figure 11A The decoding device 1100 includes an input processor 1101, a memory 1102, a variable node operator 1104, a controller 1106, a verification node operator 1108, and an output processor 1110.

[0268] Input processor 1101 stores input values ​​therein. Specifically, input processor 1101 may store the LLR value of a received signal received via a radio channel.

[0269] The controller 1106 determines the number of values ​​input to the variable node operator 1104, the address value of the memory 1102, the number of values ​​input to the parity node operator 1108, and the address value of the memory 1102 based on the block size (i.e., codeword length) of the received signal received via the radio channel and the parity check matrix corresponding to the coding rate.

[0270] The memory 1102 stores the input and output data of the variable node operator 1104 and the check node operator 1108.

[0271] Variable node operator 1104 receives data input from memory and performs variable node operations based on the address information of the input data input from controller 1106 and information about the number of input data entries. Subsequently, variable node operator 1104 stores the variable node operation result in memory 1102 based on the address information of the output data input from controller 1106 and information about the number of output data entries. Furthermore, variable node operator 1104 inputs the variable node operation result to output processor 1110 based on data input from input processor 1101 and memory 1102.

[0272] The verification node operator 1108 receives data input from the memory 1102 and performs verification node operations based on the address information of the input data input from the controller 1106 and information about the number of input data entries. Subsequently, the verification node operator 1108 stores the variable node operation results in the memory 1102 based on the address information of the output data input from the controller 1106 and information about the number of output data entries.

[0273] The output processor 1110 performs a hard decision on whether the information word bits of the codeword on the transmitting side are 0 or 1 based on the data input from the variable node operator 1104, and then outputs the hard decision result, so that the output value of the output processor 1110 becomes the final decoded value.

[0274] On the other hand, the decoding device 1100 may further include a memory (not shown) for pre-storing information about the encoding rate, codeword length, and parity check matrix of the LDPC code, and the LDPC decoder 1020 may use such information to perform LDPC decoding. However, this is merely a variation, and the corresponding information can be provided from the transmitting side.

[0275] On the other hand, some configurations included in the decoding device 1100 can be omitted, or some configurations can be added to it. Furthermore, the configurations of the input processor, memory, variable node operator, check node operator, and output processor included in the decoding device 1100 can be controlled by the controller 1106.

[0276] Figure 11B This is a diagram illustrating the structure of an encoding device according to an embodiment of the present disclosure.

[0277] The LDPC encoder 1010 can be configured to have, for example: Figure 11B The structure shown.

[0278] refer to Figure 11B The encoding device may consist of a transceiver 1121, a controller 1122, and a memory 1123. In embodiments of this disclosure, the controller may be defined as a circuit, an application-specific integrated circuit, or at least one processor.

[0279] Transceiver 1121 can transmit and receive signals. Controller 1122 can control the operation of the decoding device according to embodiments of the present disclosure. Memory 1123 can store at least one of information transmitted / received by transceiver 1121 and information generated by controller 1122.

[0280] Figure 12 This is a diagram illustrating the structure of a transport block according to an embodiment of the present disclosure.

[0281] refer to Figure 12 You can add <null>The bits are matched to the information length of the LDPC code.

[0282] Based on the foregoing, methods for applying various block sizes based on QC-LDPC codes have been described in communication and broadcasting systems that support LDPC codes of various lengths.

[0283] Figures 13A to 13I This is a diagram illustrating the basis matrices satisfying the balance and partial window orthogonality properties according to various embodiments of this disclosure. Specifically, Figure 13A The basis matrix satisfies strong 2-balance and also satisfies the orthogonality of two partial windows.

[0284] refer to Figures 13A to 13I , Figure 13A The base matrix is ​​90x112 in size, and in the partial matrix corresponding to the 5 upper rows and 27 front columns, there are no columns with a degree of 1. This means that even if any exponent matrix is ​​defined based on this partial matrix, there will be no columns or blocks of columns with a degree of 1 in the parity check matrix corresponding to the exponent matrix. Furthermore, Figures 13B to 13I It is shown Figure 13A Enlarged views of each part of the basis matrix. Figure 13A This is a matrix that combines the matrices corresponding to the reference numerals described in the various parts. Therefore, it can be achieved through combination. Figures 13B to 13I The base matrix is ​​configured to be divided into 2*4 partitions (13b, 13c, ..., 13i).

[0285] Figure 13A The basis matrix shown is further characterized by columns 28 through 112 having a degree of 1. For example, a matrix of size 85x112 and composed of... Figure 13A The base matrix consisting of rows 6 to 90 corresponds to a single parity check code.

[0286] exist Figure 13A In the base matrix, the first 22 columns correspond to the information bits used to perform encoding. Depending on the situation, the information bits are also called code blocks.

[0287] Regarding the position of the element 1 in each row, from Figure 13A The base matrix excludes columns with a degree of 1, where the difference between the number of odd-positioned 1s and the number of even-positioned 1s satisfies a value equal to or less than 2 for all rows. For example, if we define odd and even sets for S1 and S2 as in mathematical expression 7, and classify the 1s in each row to match these sets, then we know that the strong balance property defined in mathematical expression 15 is satisfied. Furthermore, we know that the perfect balance property defined in mathematical expression 12 is satisfied for a partial matrix consisting of 5 upper rows and 27 front columns, which does not include... Figure 13A The columns with a degree of 1 in the basis matrix. As mentioned above, the basis matrix can be designed by combining different balance properties of the various parts of the basis matrix.

[0288] The transmitter generates and transmits codewords using a parity check matrix, wherein the parity check matrix has the following characteristics: Figure 13A The diagram shows a basis matrix with balanced and partially windowed orthogonal properties. In this case, codewords can be transmitted by puncturing a portion of the information bits, as needed. The receiver decodes the transmitted codewords based on the received signal. When decoding is performed using a single block parallel processor, decoding is performed sequentially for a cyclic permutation matrix or cyclic matrix. When decoding is performed using two block parallel processors, decoding can be performed simultaneously for cyclic permutation matrices or cyclic matrices corresponding to that group.

[0289] Figure 14A It is proposed according to the embodiments of this disclosure, having Figure 13A A diagram illustrating the exponential matrix of the basis matrix that satisfies the balance and partial window orthogonality properties. Therefore, with... Figure 14A The parity check matrix corresponding to the exponent matrix also satisfies strong 2-balance for each column block, and also satisfies the orthogonality of two partial windows for each row block.

[0290] Figure 14A The exponent matrix is ​​90x112 in size, and in the partial matrix corresponding to the 5 upper rows and 27 upper columns, there are no columns with a degree of 1. Furthermore, in the exponent matrix of Figure 14, the empty blocks correspond to a zero matrix of size LxL.

[0291] also, Figures 14B to 14I This illustrates various embodiments according to the present disclosure. Figure 14A Enlarged view of each part of the exponential matrix. Figure 14A This is a matrix that combines the matrices corresponding to the reference numerals described in the various parts. Therefore, it can be achieved through... Figures 14B to 14I The combination of parts is used to configure an exponential matrix. Figure 14A In this case, assume that the basis matrix is ​​divided into 2*4 partitions: 14b, 14c, ..., 14i.

[0292] Figure 14A The exponential matrix shown is further characterized by the fact that the degree of columns 28 through 12 is always 1. For example, a matrix of size 85x112 and composed of... Figure 14A The exponent matrix consisting of rows 6 to 90 corresponds to a large number of individual parity check codes.

[0293] because Figure 14A Each element of the exponent matrix corresponds to an index of the cyclic permutation matrix, so the operations of the block parallel processor are performed according to the size LxL of the cyclic permutation matrix. If two block parallel processors are used, decoding can be performed on the individual cyclic permutation matrices corresponding to the defined sets S1 and S2.

[0294] By changing the value of the element for various L values Figure 14A The exponent matrix can be used for LDPC encoding and decoding.

[0295] For example, if we assume Figure 14A The exponential matrix is ​​E = (e i，j ), and the exponential matrix transformed according to the L value is The following conversion formula can usually be applied.

[0296] [Mathematical Expression 17]

[0297]

[0298] or

[0299]

[0300] In mathematical expression 17, f(x,L) can be defined in various forms, and for example, it can be defined as in mathematical expression 18 below.

[0301] [Mathematical Expression 18]

[0302]

[0303] or

[0304]

[0305] or

[0306]

[0307] In mathematical expression 18, mod(a,b) means taking the modulo b operation of a modulo a, and D means a constant as a predefined positive integer.

[0308] According to the system, it can be used as is. Figure 13A and Figure 14A The base matrix and exponent matrix shown can be used, or only a portion thereof. For example, by Figure 13A and Figure 14A The matrix consisting of 46 upper rows and 68 front columns of the base and exponent matrices can be used as the new base and exponent matrices for LDPC encoding and decoding in the system. In this case, if the information word bits corresponding to x information word blocks are punctured, the maximum encoding rate of 22 / (68-x) can be supported without iterative transmission of codeword bits.

[0309] Furthermore, a new basis matrix can be used to apply LDPC encoding and decoding, where the new basis matrix can be obtained by combining the components of the new basis matrix. Figure 13A The partial matrix consisting of the six upper rows of the base matrix and another base matrix corresponding to a single parity check code of size 40x68 are concatenated together. Similarly, LDPC encoding and decoding can be applied using a new base matrix, where the new base matrix is ​​obtained by concatenating the base matrix with the base matrix consisting of the base matrix and the parity check code of size 40x68. Figure 13A The different partial matrices formed by the six upper rows of the basis matrix and Figure 13A The basis matrix is ​​obtained by concatenating the same rows 7 through 46 of each other.

[0310] Typically, the coding rate of LDPC codes can be adjusted by puncturing codeword bits according to the coding rate. When puncturing the parity bits corresponding to columns with a degree of 1, based on... Figure 13A and Figure 14A The LDPC codes with the shown base or exponent matrices can be decoded without using the corresponding parts of the parity check matrix, thus reducing decoding complexity. However, considering encoding performance, the performance of LDPC codes can be improved by adjusting the puncturing order of the parity bits (or the transmission order of the generated LDPC codewords).

[0311] For example, if it corresponds to Figure 13A and Figure 14A If the corresponding information word bits in the two first columns of the exponent matrix are punctured, and both odd and even bits with a degree of 1 are punctured, then LDPC codewords can be transmitted at a coding rate of 22 / 25. However, if the corresponding information word bits in the exponent matrix are punctured, then LDPC codewords can be transmitted. Figure 13A and Figure 14A The information word bits corresponding to the two first columns of the exponent matrix and the basis matrix are punctured, and the parity bits corresponding to the 26th column with a degree of 2 are punctured, while the parity bits corresponding to the 28th column with a degree of 1 in the exponent matrix are not punctured. This allows LDPC codewords to be transmitted at a coding rate of 22 / 25 in the same manner. However, the latter has better performance and can be achieved by using... Figure 13A and Figure 14A After generating LDPC codewords from the corresponding base and exponent matrices, appropriate rate matching is applied to further improve performance. Based on rate matching, the order of columns in the exponent matrix can be appropriately rearranged for application in LDPC encoding.

[0312] As a detailed embodiment of this disclosure, if based on and Figure 13A and Figure 14A By applying LDPC encoding and decoding to the corresponding base and exponent matrices, the following transmission order can be defined. Based on a... Figure 13A and Figure 14A The following pattern is derived by applying LDPC encoding and decoding to a partial matrix consisting of 46 upper rows and 68 upper columns. Furthermore, for convenience, consider the first column to be column 0 and the last column to be column 67.

[0313] Pattern 1:

[0314] 2,3,4,…,20,21,22,23-A,26,24,27,23-B,25,28,29,…,67,0,1

[0315] Pattern 2:

[0316] 2,3,4,…,20,21,22,23-A,26,27,24,23-B,25,28,29,…,67,0,1

[0317] Pattern 1 and Pattern 2 signify transmission in the order of codeword bits corresponding to the columns corresponding to the pattern order. In other words, Pattern 1 and Pattern 2 signify applying punctures to the codeword bits in reverse order. In the case of Pattern 1, for example, when applying punctures to codewords used for rate matching, starting with the codeword bits of size Z corresponding to the first column, punctures are applied sequentially for the necessary length (however, in Pattern 1 and Pattern 2, the order of 0s and 1s can be changed).

[0318] In Pattern 1 and Pattern 2, 23-A and 23-B mean that the codeword bits corresponding to the 23rd column block have been divided into two groups. For example, 23-A could mean the first... Bits, and 23-B can mean the last bit of the codeword corresponding to the 23rd column group. Bits. The bit partitioning of 23-A and 23-B is merely varied, and various methods can be used to partition them (e.g., 23-A is...). Bits, and 23-B is (bit).

[0319] Regarding the transmission order, it is not necessary to perform the transmission in the order of the codeword bit units corresponding to the column blocks, and for performance improvement, the transmission order can be different by dividing the codeword bits corresponding to the column blocks into two or more groups. In other words, to obtain superior coding performance, the transmission order of codeword bits corresponding to at least one column block can be configured differently.

[0320] For reference, transmission in units of codeword bits corresponding to column blocks can mean transmitting codeword bits of one column block without transmitting codeword bits corresponding to another column block.

[0321] The above pattern can be used to apply such a rate matching method, and the method used by the system to perform puncturing from predetermined positions can be applied after appropriate interleaving is performed on the codeword bits. For example, in LTE systems, Redundancy Version (RV) technology can be used. An example of RV technology will be briefly described below.

[0322] First, pattern 1 and pattern 2 are changed into pattern 3 and pattern 4, respectively.

[0323] Pattern 3:

[0324] 0,1,2,3,4,…,20,21,22,23-A,26,24,27,23-B,25,28,29,…,67

[0325] Pattern 4:

[0326] 0,1,2,3,4,…,20,21,22,23-A,26,27,24,23-B,25,28,29,…,67

[0327] If the RV-0 value, indicating the start position of transmission, is configured to be 2 for the codeword, the puncturing to be performed on the codeword bits from columns 0 and 1 can be configured according to the coding rate. Here, various initial transmission sequences can be determined based on the RV-0 value, and by appropriately configuring the RV-1 value, it can be applied to LDPC encoding and decoding techniques such as HARQ. For example, when transmitting additional parity bits after transmitting all codeword bits from columns 2 to 67, the additional codeword bits can be iteratively transmitted starting from columns 0 and 1, or the additional codeword bits can be transmitted in various ways depending on the RV-1 value.

[0328] Furthermore, different patterns or interleaving methods can be applied depending on the modulation order to improve performance. For example, if the coding rate is lower than a certain coding rate R_th, a rate-matching method corresponding to the first pattern is applied, and if the coding rate becomes higher than R_th, a second pattern different from the first pattern can be used (if the coding rate is equal to R_th, the pattern can be selected according to a predetermined method).

[0329] like Figure 13A and Figure 14A The basis and exponent matrices shown can be expressed in various forms, and as examples, they can be expressed using sequences as shown in mathematical expressions 19 and 20 below (for convenience, they are based on a sequence of matrices derived from...). Figure 13A and Figure 14A The partial matrix consisting of 46 upper rows and 68 upper columns is derived to apply the case of LDPC encoding and decoding.

[0330] [Mathematical Expression 19] 0 2 3 4 5 6 7 9 12 15 19 20 22 23 0 1 4 6 10 11 13 16 17 18 19 20 21 23 24 0 1 4 7 8 10 11 12 13 14 15 16 19 21 22 24 25 1 2 3 5 6 8 9 10 12 13 14 15 17 18 20 21 25 26 0 1 2 3 5 7 8 9 11 14 16 17 18 22 26 0 1 22 27 0 1 4 11 21 22 28 1 7 13 14 16 18 19 29 0 1 2 3 5 9 10 30 0 1 4 11 12 15 22 31 0 1 7 8 16 20 21 32 0 1 2 5 17 19 33 0 4 6 9 11 22 341 7 14 16 21 35 0 1 2 3 19 24 36 0 4 5 9 11 37 0 1 7 14 16 22 23 381 2 18 19 39 0 4 5 11 25 40 0 1 8 9 21 41 0 1 7 14 26 42 1 3 16 19 43 0 1 2 5 15 44 0 4 9 11 13 45 1 7 10 14 46 0 12 19 22 47 0 1 16 20 48 0 6 11 17 49 0 2 7 9 50 0 1 14 19 24 51 0 1 10 13 52 1 4 25 53 0 5 16 17 54 0 1 7 23 55 0 1 8 18 56 0 1 11 19 26 57 0 1 9 15 58 0 5 16 23 59 1 7 12 60 0 1 6 25 61 0 3 14 19 62 0 11 24 63 0 1 20 21 64 0 9 16 26 651 10 13 66 0 5 8 67

[0374] [Mathematical Expression 20] 194 25 92 160 98 244 9 248 178 107 40 245 1 0 0 192 118 229 142 157 164 29 235 83 11 129 240 0 0 39 140 178 22 76 33 124 230 73 179 57 126 161 45 0 0 0 185 186 118 171 240 203 251 148 205 162 233 187 255 10 146 104 0 0149222 1 69 177 16 117 222 147 247 214 115 134 1 0 106 29 13 0 195 219 101 126 122 181 0 61 185 146 248 148 40 235 0 233 133 220 174 15 126 173 0 82 208 57 148 211 149 82 0 42 19 216 75 79 47 41 0 5 74 4 54 76 64 0 42 203 53 28 103 20 0 8 3 137 35 78 0 235 251 120 121 119 112 0 86 199 4 89 183 0 50 254 126 250 188 59 177 0 232 123 74 172 0 70 187 249 145 130 0 185 20 200 172 28 0 60 125 236 255 109 0 154 95 29 15 0 135 198 228 156 199 0 14 162 171 76 13 0 96 54 44 112 0 84 98 164 19 0 24 80 249 74 0 57 245 163 90 0 68 77 209 203 0 55 43 205 141 13 0 153 127 230 250 0 236 82 74 0 140 129 25 168 0 87 29 123 139 0 67 170 77 161 0 228 233 123 217 226 0 95 155 233 158 0 80 233 121 138 0 198 240 227 0 175 104 233 2 0 28 19 113 218 0 75 124 134 0 69 72 53 125 0 18 61 92 145 0 183 218 231 0 9 59 196 0

[0420] Mathematical Expression 19 Indicator Figure 13A The position of element 1 in each row of a 46x68 partial matrix within the base matrix. For example, in mathematical expression 19, the third value 5 of the third sequence means that element 1 exists in the third row and fifth column of the base matrix (in the example above, consider that the sequence and element start from 0).

[0421] Mathematical expression 20 indicates Figure 14A The individual element values ​​in each row of a 46x68 partial matrix within the base matrix. For example, in mathematical expression 20, the third value 171 of the third sequence means that the third element value in the third row of the exponent matrix is ​​171, and based on... Figure 13A And mathematical expression 19, the third value means that the index of the cyclic permutation matrix corresponding to the third row block and the fifth column block in the parity check matrix is ​​171.

[0422] If the base matrix and exponent matrix have specific rules, they can be expressed more simply. For example, if the block from column 27 to the last column has a diagonal structure, such as... Figure 13A and Figure 14A If the base matrix and exponent matrix are given, then it is assumed that the element positions and index values ​​are omitted, but the correspondence rules are known.

[0423] As an example, the following mathematical expression 21 shows an example of omitting the position of element 1 in the 27th column block to the last column block.

[0424] [Mathematical Expression 21] 0 2 3 4 5 6 7 9 12 15 19 20 22 23 0 1 4 6 10 11 13 16 17 18 19 20 21 23 24 0 1 4 7 8 10 11 12 13 14 15 16 19 21 22 24 25 1 2 3 5 6 8 9 10 12 13 14 15 17 18 20 21 25 26 0 1 2 3 5 7 8 9 11 14 16 17 18 22 26 0 1 22 0 1 4 11 21 22 1 7 13 14 16 18 19 0 1 2 3 5 9 10 0 1 4 11 12 15 22 0 1 7 8 16 20 21 0 1 2 5 17 19 0 4 6 9 11 22 1 7 14 16 21 0 1 2 3 19 24 0 4 5 9 11 0 1 7 14 16 22 23 1 2 18 19 0 4 5 11 25 0 1 8 9 21 0 1 7 14 26 1 3 16 19 0 1 2 5 15 0 4 9 11 13 1 7 10 14 0 12 19 22 0 1 16 20 0 6 11 17 0 2 7 9 0 1 14 19 24 0 1 10 13 1 4 25 0 5 16 17 0 1 7 23 0 1 8 18 0 1 11 19 26 0 1 9 15 0 5 16 23 1 7 12 0 1 6 25 0 3 14 19 0 11 24 0 1 20 21 0 9 16 26 1 10 13 0 5 8

[0471] As mentioned above, it can be expressed in various ways. Figure 13A and Figure 14A The base matrix and exponent matrix.

[0472] exist Figures 15A to 15C Another embodiment of the basis matrix that satisfies the balance and partial window orthogonality properties proposed in the embodiments of this disclosure is shown.

[0473] Figures 15A to 15C This is a diagram showing a basis matrix of size 20x47.

[0474] refer to Figures 15A to 15C ,exist Figures 15A to 15C In the base matrix, an empty block typically means 0 and indicates a portion corresponding to a zero matrix of size ZxZ in the parity check matrix according to various embodiments of the present disclosure.

[0475] also, Figures 15B to 15C It is shown Figure 15A Enlarged views of each part of the basis matrix. Figure 15A The matrices corresponding to the reference numerals described in the various parts are combined into a single matrix. Therefore, it is possible to... Figure 15B and Figure 15C A base matrix is ​​configured by combining the parts of the matrix.

[0476] It can be easily identified Figure 15A The basis matrix has a strong 2-balance property and a two-part window orthogonal structure. Furthermore, the degree of columns 28 through 47 is all 1. In other words, compared with... Figure 15A All columns corresponding to columns 28 to 47 can be found in Figure 15A The parity check matrix generated by applying a lift to the basis matrix has a degree of 1.

[0477] exist Figures 16A to 16E Another embodiment of a base matrix for LDPC encoding and decoding is shown, wherein the LDPC encoding and decoding supports various encoding rates and encoding lengths based on a base matrix that satisfies the balance and partial window orthogonality properties proposed in the embodiments of this disclosure. Figures 16A to 16E This is a diagram showing a basis matrix of size 25x47. Figures 16A to 16E In the base matrix, an empty block usually means 0 and indicates the part corresponding to the zero matrix of size ZxZ in the parity check matrix.

[0478] Figures 16A to 16E These are illustrations of other elementary matrices according to various embodiments of the present disclosure.

[0479] refer to Figures 16A to 16E , Figures 16B to 16E It is shown Figure 16A Enlarged views of each part of the basis matrix. Figure 16A This is a matrix that combines the matrices corresponding to the reference numerals described in the various parts. Therefore, it can be achieved through... Figures 16B to 16E A basis matrix is ​​configured by combining parts of the matrix. For reference, Figure 15B equal Figure 16D ,and Figure 15C equal Figure 16E .

[0480] Figure 16A The basis matrix shown can be expressed in various forms, and as an example, it can be expressed using the sequence in mathematical expression 22 below. Mathematical expression 22 indicates... Figure 16A The position of element 1 in each row of the base matrix. For example, in mathematical expression 22, the second value 4 of the second sequence means that element 1 exists in the second row and fourth column of the base matrix (in the example above, consider the starting order of elements in the sequence and matrix starting from 0).

[0481] [Mathematical Expression 22] 0 1 2 3 5 6 9 10 11 12 13 15 16 18 19 20 21 22 23 0 2 3 4 5 7 8 9 11 12 14 15 16 17 19 21 22 23 24 0 1 2 4 5 6 7 8 9 10 13 14 15 17 18 19 20 24 25 0 1 3 4 6 7 8 10 11 12 13 14 16 17 18 20 21 22 25 0 1 26 0 1 3 12 16 21 22 27 0 6 10 11 13 17 18 20 28 0 1 4 7 8 14 29 0 1 3 12 16 19 21 22 24 30 0 1 10 11 13 17 18 20 31 1 2 4 7 8 14 32 0 1 12 16 21 22 23 33 0 1 10 11 13 18 34 0 3 7 20 23 35 0 12 15 16 17 21 36 0 1 10 13 18 25 37 1 3 11 20 22 38 0 14 16 17 21 39 1 12 13 18 19 40 0 1 7 8 10 41 0 3 9 11 22 42 1 5 16 20 21 43 0 12 13 17 44 1 2 10 18 45 0 3 4 11 22 46

[0507] If specific rules can be found for parts of the basis matrix, the basis matrix can be expressed more simply. For example, if the 27th column to the last column has a diagonal structure, such as... Figure 16A If the base matrix is ​​given, then it is assumed that the transceiver knows the correspondence rule and can omit element positions or element values. As an example, the following mathematical expression 23 shows an example in which the positions of element 1 are omitted in the 27th column block to the last column block in mathematical expression 22.

[0508] [Mathematical Expression 23] 0 1 2 3 5 6 9 10 11 12 13 15 16 18 19 20 21 22 23 0 2 3 4 5 7 8 9 11 12 14 15 16 17 19 21 22 23 24 0 1 2 4 5 6 7 8 9 10 13 14 15 17 18 19 20 24 25 0 1 3 4 6 7 8 10 11 12 13 14 16 17 18 20 21 22 25 0 1 0 1 3 12 16 21 22 0 6 10 11 13 17 18 20 0 1 4 7 8 14 0 1 3 12 16 19 21 22 24 0 1 10 11 13 17 18 20 1 2 4 7 8 14 0 1 12 16 21 22 23 0 1 10 11 13 18 0 3 7 20 23 0 12 15 16 17 21 0 1 10 13 18 25 1 3 11 20 22 0 14 16 17 21 1 12 13 18 19 0 1 7 8 10 0 3 9 11 22 1 5 16 20 21 0 12 13 17 1 2 10 18 0 3 4 11 22

[0534] Mathematical expression 24 indicates Figure 16A The position of element 1 in each column of the base matrix. For example, in mathematical expression 24, the third value 5 of the third sequence means that element 1 exists in the third row and fifth column of the base matrix (in the example above, consider the starting order of elements in the sequence and matrix starting from 0).

[0535] [Mathematical Expression 24] 0 1 2 3 4 5 6 7 8 9 11 12 13 14 15 17 19 20 22 24 0 2 3 4 5 7 8 9 10 11 12 15 16 18 19 21 23 0 1 2 10 23 0 1 3 5 8 13 16 20 24 1 2 3 7 10 24 0 1 2 21 0 2 3 6 1 2 3 7 10 13 19 1 2 3 7 10 19 0 1 2 20 0 2 3 6 9 12 15 19 23 0 1 3 6 9 12 16 20 24 0 1 3 5 8 11 14 18 22 0 2 3 6 9 12 15 18 22 1 2 3 7 10 17 0 1 2 14 0 1 3 5 8 11 14 17 21 1 2 3 6 9 14 17 22 0 2 3 6 9 12 15 18 23 0 1 2 8 18 0 2 3 6 9 13 16 21 0 1 3 5 8 11 14 17 21 0 1 3 5 8 11 16 20 24 0 1 11 13 1 2 8 2 3 15 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 twenty one twenty two twenty three twenty four

[0583] If specific rules can be found for parts of the basis matrix, the basis matrix can be expressed more simply. For example, if the 27th column to the last column has a diagonal structure, such as... Figure 16A If the base matrix is ​​given, then it is assumed that the transceiver knows the corresponding rules and can omit element positions or element values. As an example, the following mathematical expression 25 shows an example in which the positions of element 1 are omitted in the 27th column block to the last column block of mathematical expression 24.

[0584] [Mathematical Expression 25] 0 1 2 3 4 5 6 7 8 9 11 12 13 14 15 17 19 20 22 24 0 2 3 4 5 7 8 9 10 11 12 15 16 18 19 21 23 0 1 2 10 23 0 1 3 5 8 13 16 20 24 1 2 3 7 10 24 0 1 2 21 0 2 3 6 1 2 3 7 10 13 19 1 2 3 7 10 19 0 1 2 20 0 2 3 6 9 12 15 19 23 0 1 3 6 9 12 16 20 24 0 1 3 5 8 11 14 18 22 0 2 3 6 9 12 15 18 22 1 2 3 7 10 17 0 1 2 14 0 1 3 5 8 11 14 17 21 1 2 3 6 9 14 17 22 0 2 3 6 9 12 15 18 23 0 1 2 8 18 0 2 3 6 9 13 16 21 0 1 3 5 8 11 14 17 21 0 1 3 5 8 11 16 20 24 0 1 11 13 1 2 8 2 3 15

[0611] As mentioned above, the basis matrix and the exponential matrix can be expressed in various ways. By applying permutations to the columns or rows of the basis matrix, the basis matrix and the exponential matrix can be expressed equally by appropriately changing the sequence or the position of the numbers in the sequence in mathematical expressions 19 to 25.

[0612] exist Figure 16A In the basis matrix, by Figure 16B and Figure 16C The partial matrix composed of certain parts may not satisfy the balance property or partial window orthogonality property proposed in the embodiments of this disclosure. However, by using the partial matrix composed of certain parts... Figure 16B and Figure 16C The partial matrix composed of the parts and the matrix composed of the parts in the matrix. Figure 16D and Figure 16E The partial matrices composed of the parts in the matrix are connected to each other, which enables the apparatus and methods for supporting LDPC encoding and decoding with superior performance for various encoding rates and encoding lengths.

[0613] For reference, by targeting what can be based on Figure 16A The LDPC code generated by appropriately shortening and punching parts of the information word bits using the basis matrix becomes capable of supporting LDPC encoding and decoding with various encoding rates and lengths. For example, if we assume that... Figure 16A The information bits corresponding to the two initial columns of the basis matrix are always punched and only exclude those corresponding to the information bits of the basis matrix. Figure 16B If the corresponding odd and even bits are punctured, then it is clear that various coding rates from coding rate 22 / 25 to 22 / 45 can be obtained from... Figure 16A The basis matrix is ​​supported.

[0614] LDPC codes can adjust their encoding rate by applying puncturing to the codeword bits according to the encoding rate. When puncturing the parity bits corresponding to columns with a degree of 1, LDPC codes based on the base matrix or exponent matrix proposed in embodiments of this disclosure can be decoded without using the corresponding parts of the parity check matrix, thus reducing decoding complexity. However, considering encoding performance, the performance of LDPC codes can be improved by adjusting the puncturing order of the parity bits or the transmission order of the generated LDPC codewords.

[0615] Typically, performance can be further improved by applying appropriate rate matching after generating LDPC codewords using the base matrix or exponent matrix proposed in the embodiments of this disclosure. Based on rate matching, the order of columns in the base matrix or exponent matrix can be appropriately rearranged for application in LDPC encoding and decoding.

[0616] The LDPC encoding process may include determining the size of the input bits (or coded block) for which LDPC encoding is applied, determining the block size Z for which LDPC encoding is applied based on the size, determining an appropriate LDPC exponent matrix or sequence based on the block size, and performing LDPC encoding based on the block size Z and the determined exponent matrix or LDPC sequence. In this case, the LDPC exponent matrix or sequence can be applied to LDPC encoding without any transformation, and, depending on the circumstances, LDPC encoding can be performed by appropriately transforming the LDPC exponent matrix or sequence according to the block size Z.

[0617] Similarly, the LDPC decoding process may include determining the size of the input bits (or code blocks) for the transmitted LDPC codeword, determining the block size Z for applying LDPC decoding based on that size, determining the appropriate LDPC exponent matrix or sequence based on the block size, and performing LDPC decoding based on the block size Z and the determined exponent matrix or LDPC sequence. In this case, the LDPC exponent matrix or sequence can be applied to LDPC decoding without any transformation, and, depending on the circumstances, LDPC decoding can be performed by appropriately transforming the LDPC exponent matrix or sequence according to the block size Z.

[0618] Here, the characteristics of the LDPC exponential matrix or the basis matrix of the sequence can be found in... Figure 15A , Figure 16A Or as will be described below Figure 17A The basis matrix.

[0619] exist Figures 17A to 17E Another embodiment of a base matrix for LDPC encoding and decoding is shown, wherein the LDPC encoding and decoding supports various encoding rates and encoding lengths based on a base matrix that satisfies the balance and partial window orthogonality properties proposed in embodiments of this disclosure.

[0620] Figures 17A to 17E These are illustrations of other elementary matrices according to various embodiments of the present disclosure.

[0621] refer to Figure 17A , Figure 17A This is a diagram showing a basis matrix of size 46x68. Figures 17A to 17E In the basis matrix, an empty block typically means 0 and indicates the portion corresponding to a zero matrix of size ZxZ in the parity check matrix. Figure 17A In the base matrices of parts 17B, 17C, 17D, 17E, 17F, 17G, 17H, 17I, and 17J, empty blocks typically mean 0 and indicate the part corresponding to a zero matrix of size ZxZ in the parity check matrix.

[0622] also, Figures 17B to 17E It is shown Figure 17A An enlarged view of the 17B-17E portion of the basis matrix. Figure 17A This is a matrix that combines the matrices corresponding to the reference numerals described in the various parts. Therefore, it can be achieved through... Figures 17B to 17E ,as well as Figure 17A A basis matrix is ​​configured by combining parts of the 17F, 17G, 17H, 17I, and 17J portions. For reference, Figure 16B and Figure 17B They are equal to each other. Figure 16C and Figure 17D They are equal to each other. Figure 15B , Figure 16D and Figure 17D They are equal to each other, and Figure 15C , Figure 16E and Figure 17E They are equal to each other.

[0623] Normally, if Figure 17A If parts of 17F, 17G, and 17I are configured as zero matrices, and parts of 17J are configured as identity matrices or matrices with diagonal structure, then the entire basis matrix structure has an extended form, without significantly differing from the original form. Figures 16A to 16E The basis matrix is ​​thus used, and therefore code concatenation is facilitated.

[0624] In addition, if Figure 17A Each row of the 17H ​​section has orthogonal properties, which makes it easy to implement a decoder that supports high decoding throughput.

[0625] As a result, using Figure 17A The basis matrix of the 17H ​​part, Figure 17A The basis matrix can support and Figure 16A Compared to the basis matrix of more different coding rates, the 17H ​​part of the basis matrix has orthogonal properties in each row, and is also relative to Figures 16A to 16E The basis matrix is ​​preserved in its extended form.

[0626] although Figure 16A and Figure 17A Only "as is" usage is shown. Figure 15A The case of the basis matrix, but usually rearranged Figure 15A The order of the columns of the base matrix can be rearranged, the order of the rows can be rearranged, or the order of both columns and rows can be rearranged. Furthermore, this can be achieved by connecting the rearranged base matrix to... Figure 16B and Figure 16C The basis matrix can be represented as follows: Figure 16A The new basis matrix of the form shown is used in LDPC encoding and decoding methods and apparatuses. For example, by applying the rearranged basis matrix... Figure 16D and Figure 16E The basis matrix can be used to generate a matrix similar to that of . Figure 16A A new basis matrix with a similar form.

[0627] In the same way, by connecting the rearranged base matrix... Figure 17B and Figure 17C The basis matrix can be represented as follows: Figure 17A The new basis matrix of the form shown is used in LDPC encoding and decoding methods and apparatuses. For example, by applying the rearranged basis matrix... Figure 17D and Figure 17E The basis matrix can be used to generate a matrix similar to that of . Figure 17A A new basis matrix with a similar form.

[0628] although Figure 17A Only "as is" usage is shown. Figure 16A The case of the basis matrix, but usually rearranged Figure 16A The order of the columns of the basis matrix can be rearranged, the order of the rows can be rearranged, or the order of both columns and rows can be rearranged. Furthermore, by applying the rearranged basis matrix... Figure 17B , Figure 17C , Figure 17D and Figure 17E The basis matrix can be used with Figure 17A A new basis matrix of similar form is applied to LDPC encoding and decoding methods and apparatuses. As described above, by... Figure 16A The basis matrix is ​​applied to Figure 17A The basis matrix is ​​given by an example of the basis matrix through the LDPC sequence expressed in mathematical expression 26.

[0629] Mathematical expression 26 indicates the position of element 1 in each row of the basis matrix, and as follows: Figure 17A As shown, it can be expressed in the form of an LDPC basis matrix. As the basis matrix corresponding to mathematical expression 26, Figure 17A Parts of sections 17F, 17G, and 17I are configured as zero matrices, and parts of section 17J are configured as identity matrices. Section 17H shows an example of a basis matrix in which each row has orthogonal properties. Furthermore, the basis matrix expressed in mathematical expression 26 can be expressed in various forms using methods similar to those used in mathematical expressions 23 to 25.

[0630] [Mathematical Expression 26] 0 1 2 3 5 6 9 10 11 12 13 15 16 18 19 20 21 22 23 0 2 3 4 5 7 8 9 11 12 14 15 16 17 19 21 22 23 24 0 1 2 4 5 6 7 8 9 10 13 14 15 17 18 19 20 24 250 1 3 4 6 7 8 10 11 12 13 14 16 17 18 20 21 22 250 1 26 0 1 3 12 16 21 22 27 0 6 10 11 13 17 18 20 28 0 1 4 7 8 14 29 0 1 3 12 16 19 21 22 24 30 0 1 10 11 13 17 18 20 31 1 2 4 7 8 14 32 0 1 12 16 21 22 23 33 0 1 10 11 13 18 34 0 3 7 20 23 35 0 12 15 16 17 21 36 0 1 10 13 18 25 37 1 3 11 20 22 38 0 14 16 17 21 39 1 12 13 18 19 40 0 1 7 8 10 41 0 3 9 11 22 42 1 5 16 20 21 43 0 12 13 17 44 1 2 10 18 45 0 3 4 11 22 46 1 6 7 14 47 0 2 4 15 48 1 6 8 49 0 4 19 21 50 1 14 18 25 51 0 10 13 24 52 1 7 22 25 53 0 12 14 24 54 1 2 11 21 55 0 7 15 17 56 1 6 12 22 57 0 14 15 18 58 1 13 23 59 0 9 10 12 60 1 3 7 19 61 0 8 17 62 1 3 9 18 63 0 4 24 64 1 16 18 25 65 0 7 9 22 66 1 6 10 67

[0675] Typically, when using shortening or zero padding of LDPC codes to support variable information word lengths or variable code rates, the performance of LDPC codes can be improved depending on the order of the shortening. If the shortening order is predetermined, coding performance can be improved by appropriately rearranging some or all of the order of a given base matrix.

[0676] An example of a rearranged basis matrix as described above is in Figures 18A to 18E As shown in [the image]. Figures 18A to 18E In the base matrix, an empty block usually means 0 and indicates the part corresponding to the zero matrix of size ZxZ in the parity check matrix.

[0677] Figure 18A , Figure 18B , Figure 18C , Figure 18D and Figure 18E These are illustrations of other elementary matrices according to various embodiments of the present disclosure.

[0678] refer to Figure 18A It is easy to know that Figure 18A The basis matrix has such a structure, where Figure 15A The order of columns 7 and 21 (if we consider the initial columns to be columns 0, 6, and 20) is changed and rearranged, then connected. Figure 16B and Figure 16C The part.

[0679] Figure 18A The basis matrix can only be obtained by rearranging... Figure 15A Examples of basis matrices obtained by using columns can be provided, and new basis matrices can be defined based on performance improvement effects or various purposes. Furthermore, by using... Figure 18B replace Figure 17B ,use Figure 18C replace Figure 17C ,use Figure 18D replace Figure 17D ,use Figure 18E replace Figure 17E It can generate with the same Figure 17A A new basis matrix in a form similar to that of the given form.

[0680] Figure 18A The basis matrices shown can be expressed in various forms, and as an example, they can be expressed using a sequence as shown in mathematical expression 27. Mathematical expression 27 indicates... Figure 18A The position of element 1 in each row of the basis matrix.

[0681] [Mathematical Expression 27] 0 1 2 3 5 6 9 10 11 12 13 15 16 18 19 20 21 22 23 0 2 3 4 5 7 8 9 11 12 14 15 16 17 19 21 22 23 24 0 1 2 4 5 6 7 8 9 10 13 14 15 17 18 19 20 24 25 0 1 3 4 6 7 8 10 11 12 13 14 16 17 18 20 21 22 25 0 1 26 0 1 3 12 16 21 22 27 0 6 10 11 13 17 18 20 28 0 1 4 7 8 14 29 0 1 3 12 16 19 21 22 24 30 0 1 6 10 11 13 17 18 31 1 2 4 7 8 14 32 0 1 12 16 21 22 23 33 0 1 10 11 13 18 34 0 3 6 7 23 35 0 12 15 16 17 21 36 0 1 10 13 18 25 37 1 3 6 11 22 38 0 14 16 17 21 39 1 12 13 18 19 40 0 1 7 8 10 41 0 3 9 11 22 42 1 5 6 16 21 43 0 12 13 17 44 1 2 10 18 45 0 3 4 11 22 46

[0707] If specific rules can be found for parts of the basis matrix, the basis matrix can be expressed more simply. For example, if the 27th column to the last column has a diagonal structure, such as... Figure 18A If the base matrix is ​​given, then it is assumed that the transceiver knows the corresponding rules and can omit element positions or element values. As an example, the following mathematical expression 28 shows an example in which the positions of element 1 are omitted in the 27th column block to the last column block of mathematical expression 27.

[0708] [Mathematical Expression 28] 0 1 2 3 5 6 9 10 11 12 13 15 16 18 19 20 21 22 23 0 2 3 4 5 7 8 9 11 12 14 15 16 17 19 21 22 23 24 0 1 2 4 5 6 7 8 9 10 13 14 15 17 18 19 20 24 25 0 1 3 4 6 7 8 10 11 12 13 14 16 17 18 20 21 22 25 0 1 0 1 3 12 16 21 22 0 6 10 11 13 17 18 20 0 1 4 7 8 14 0 1 3 12 16 19 21 22 24 0 1 6 10 11 13 17 18 1 2 4 7 8 14 0 1 12 16 21 22 23 0 1 10 11 13 18 0 3 6 7 23 0 12 15 16 17 21 0 1 10 13 18 25 1 3 6 11 22 0 14 16 17 21 1 12 13 18 19 0 1 7 8 10 0 3 9 11 22 1 5 6 16 21 0 12 13 17 1 2 10 18 0 3 4 11 22

[0734] As mentioned above, basis matrices and exponential matrices can be expressed in various ways. If a permutation of a column or row of a partial matrix is ​​applied to a basis matrix or a portion of a basis matrix, a new basis matrix can be defined by appropriately changing the sequence or the position of the numbers in the sequence expressed in mathematical expressions 19 to 28.

[0735] As another embodiment of this disclosure, a method for using based on Figure 18A The basis matrix is ​​obtained by applying multiple exponential matrices or LDPC sequences. In other words, the basis matrix is ​​like... Figure 18A As shown, a sequence of exponent matrices or LDPC codes is obtained on a base matrix, and variable-length LDPC encoding and decoding are performed by applying lifting to match the block size included in each large group from the exponent matrix or sequence. In other words, the base matrices of the parity check matrices corresponding to the exponent matrices or sequences of multiple different LDPC codes are equal to each other. According to this method, the elements or numbers constituting the exponent matrix of the LDPC code or LDPC sequence can have different values, but the positions of the corresponding elements or numbers are exactly consistent with each other. As mentioned above, the sequence of exponent matrices or LDPC codes implies the index of the cyclic permutation matrix, i.e., a cyclic permutation value of the bit, and by configuring the positions of the elements or numbers to be equal to each other, the positions of the bits corresponding to the corresponding cyclic permutation matrix can be easily captured.

[0736] First, the block size Z to be supported is divided into multiple large block groups (or sets), as expressed in the mathematical expression 20 below. It should be noted that the block size Z corresponds to the size ZxZ of the cyclic permutation matrix or cyclic matrix in the parity check matrix of the LDPC code.

[0737] [Mathematical Expression 29]

[0738] Z1={3,6,12,24,48,96,192,384}

[0739] Z2 = {11, 22, 44, 88, 176, 352}

[0740] Z3 = {5, 10, 20, 40, 80, 160, 320}

[0741] Z4 = {9, 18, 36, 72, 144, 288}

[0742] Z5 = {2, 4, 8, 16, 32, 64, 128, 256}

[0743] Z6 = {15, 30, 60, 120, 240}

[0744] Z7 = {7, 14, 28, 56, 112, 224}

[0745] Z8 = {13, 26, 52, 104, 208}

[0746] Mathematical expression 29 is simply a variety of possibilities and can use any block size Z value included in the block size group of mathematical expression 29, or block size values ​​included in the appropriate partial matrix expressed in mathematical expression 30 below. Furthermore, appropriate values ​​can be added to the block size group (set) expressed in mathematical expression 29 or 30 to be used.

[0747] [Mathematical Expression 30]

[0748] Z1' = {12, 24, 48, 96, 192, 384}

[0749] Z2'={11,22,44,88,176,352}

[0750] Z3'={10,20,40,80,160,320}

[0751] Z4' = {9, 18, 36, 72, 144, 288}

[0752] Z5' = {8, 16, 32, 64, 128, 256}

[0753] Z6' = {15, 30, 60, 120, 240}

[0754] Z7' = {14, 28, 56, 112, 224}

[0755] Z8' = {13, 26, 52, 104, 208}

[0756] The characteristic of the large groups of blocks expressed in mathematical expressions 29 or 30 is that they have different particle sizes and the ratio of adjacent block sizes is always an integer. In other words, the sizes of blocks included in a group are divisible or multiples of each other. If we assume that the exponent matrix corresponding to the p-th (p = 1, 2, ..., 8) group is... And the exponent matrix corresponding to the Z values ​​included in the p-th group is E p (Z)=(e i，j (Z)), then use f p (x, Z) = x(mod Z) applies the sequence transformation method expressed in Mathematical Expression 17. For example, if the block size Z is determined to be Z = 28, then the exponent matrix corresponding to the 7th large group that includes z = 28 can be used. As shown in the following mathematical expression 31, the exponential matrix E7(28) = (e i，j (28) each element e i，j (28).

[0757] [Mathematical Expression 31]

[0758]

[0759] or

[0760]

[0761] The transformation expressed in mathematical expression 31 can be simply expressed as in mathematical expression 32 below.

[0762] [Mathematical Expression 32]

[0763] E p (Z)=E p (mod Z), Z∈Z p

[0764] The basis matrix and exponent matrix (or LDPC sequence) of the LDPC code designed based on mathematical expressions 29 to 32 are as follows: Figures 19A to 24D As shown. For reference, although the lifting or transformation of the exponent matrix expressed in mathematical expressions 17, 31, or 32 is interpreted under the assumption that it applies to the entire exponent matrix corresponding to the parity check matrix, it can also be applied to a portion of the exponent matrix. For example, the portion of the matrix corresponding to the parity bits of the parity check matrix typically has a special structure for efficient encoding. In this case, the encoding method or complexity may change due to the lifting. Therefore, to maintain the same encoding method or complexity, for a portion of the exponent matrix corresponding to the parity bits in the parity check matrix, lifting may not be applied, or a different lifting method may be applied to the portion of the matrix corresponding to the information word bits than that applied to the exponent matrix. In other words, the lifting method applied to the sequence corresponding to the information word bits in the exponent matrix and the lifting method applied to the sequence corresponding to the parity bits can be configured differently, and depending on the situation, the lifting may not be applied to part or all of the sequence corresponding to the parity bits, and therefore a fixed value may be used without sequence transformation.

[0765] exist Figure 19A and Figure 20A Examples of exponent matrices corresponding to the parity check matrices of QC LDPC codes designed based on mathematical expressions 29 to 32 are shown sequentially (note that in...). Figure 19A and Figure 20A In the exponential matrix, empty blocks are the portions corresponding to zero matrices of size Z x Z. Depending on the situation, in Figure 19A and Figure 20A In the exponential matrix, empty blocks can be represented by specified values, such as -1. Figure 19A and Figure 20A The exponent matrix of the LDPC code shown is characterized by having the same characteristics as... Figure 18A A basis matrix with the same basis matrix.

[0766] Figure 19A and Figure 20A The LDPC exponent matrix of size 25x47 is shown, corresponding to the first and second large subgroups expressed in mathematical expressions 29 and 30, respectively. Furthermore, in the partial matrix consisting of 4 upper rows and 26 front columns in each exponent matrix, there are no columns with a degree of 1. In other words, in the parity matrix generated from the partial matrix by applying lifting, there are no columns or blocks of columns with a degree of 1.

[0767] Figures 19A to 19E This is a diagram illustrating other index matrices according to various embodiments of the present disclosure.

[0768] refer to Figures 19A to 19E , Figures 19B to 19E It is shown Figure 19A Enlarged view of each part of the exponential matrix. Figure 19A A matrix corresponding to the reference numerals in the accompanying drawings and those described in each part. Therefore, it can be understood through... Figures 19B to 19E A base matrix is ​​configured by combining the parts of the matrix.

[0769] Figures 20A to 20E This is a diagram illustrating other index matrices according to various embodiments of the present disclosure.

[0770] refer to Figures 20A to 20E , Figure 20A This is an enlarged view showing the various parts after dividing the index matrices.

[0771] Figure 19A and Figure 20A The exponent matrix shown is further characterized by the fact that the degree of each column from the 28th to the 47th is 1. For example, a base matrix or exponent matrix of size 21x47 consisting of rows 5 to 25 of the exponent matrix corresponds to a large number of individual parity check codes.

[0772] Figure 19A and Figure 20A The exponent matrix shown corresponds to the LDPC code designed based on the block size group defined in mathematical expressions 29 or 30. However, depending on system requirements, it is not necessary to support all block sizes included in the block size group, and depending on the situation, except... Figure 19A and Figure 20A In addition to the block size shown, other values ​​can be added. For example, Figure 19A and Figure 20A The exponent matrix shown can support not only block sizes corresponding to the large groups (sets) of blocks defined in mathematical expressions 29 or 30, but also block sizes corresponding to subsets of each group (set), and, depending on the circumstances, other values.

[0773] Furthermore, according to the system, it can be used as is. Figure 19A and Figure 20A The exponent matrix shown can be used in part, or only a portion thereof. For example, exponents derived from... Figure 19A and Figure 20A The partial matrix of size 5x27 is composed of the 5 upper rows and 27 front columns of each exponent matrix, and is different from the LDPC exponent matrix of size 5x27 and the partial matrix composed of... Figure 19A and Figure 20A The partial matrices of size 20x47, formed by the sixth row to the last row of each exponent matrix, are interconnected for use in LDPC encoding and decoding apparatus and methods based on the new base matrix.

[0774] because Figure 19A and Figure 20A The LDPC exponent matrix has the same characteristics as... Figure 18A They are the same basis matrices, therefore they can be applied to and used with... Figure 17A A new basis matrix with a similar form can be obtained by using... Figure 18B replace Figure 17B ,use Figure 18C replace Figure 17C ,use Figure 18D replace Figure 17D and use Figure 18E replace Figure 17E And obtain. For example, by making Figure 19A and Figure 20A The exponential matrix corresponds to the one with Figure 17B , Figure 17C , Figure 17D and Figure 17E The corresponding partial matrices, and make the appropriate exponential matrix correspond to Figure 17A The 17F, 17G, 17H, 17I, and 17J parts of the new LDPC index matrix are defined for LDPC encoding and decoding devices and methods. In this case, all LDPC index matrices have... Figure 17A The basis matrix, and the basis matrix contains... Figure 17B , Figure 17C , Figure 17D and Figure 17E The corresponding partial matrix becomes equal to Figure 18A Those matrices.

[0775] Typically, this can be achieved by applying [the application] from [the source]. Figure 15A , Figure 16A , Figure 17A and Figure 18A The base matrix is ​​configured by appropriately selecting rows and columns, and a portion of the matrix is ​​used as the new base matrix to perform LDPC encoding and decoding. Similarly, by... Figure 19A and Figure 20A The partial matrix configured by appropriately selecting rows and columns of the exponent matrix can be used as a base matrix in LDPC encoding and decoding devices and methods.

[0776] Figures 21A to 21J These are illustrations of other elementary matrices according to various embodiments of the present disclosure.

[0777] refer to Figures 21A to 21J Another embodiment of the basis matrix and exponent matrix (or LDPC sequence) of the LDPC code designed based on mathematical expressions 29 to 32 is described in Figure 21A , Figure 22A and Figure 23A As shown in the figure. This embodiment proposes a method based on Figure 21A The basis matrix is ​​obtained by applying multiple exponential matrices or LDPC sequences. In other words, the basis matrix is ​​like... Figure 21A As shown, a sequence of exponent matrices or LDPC codes is obtained on a base matrix, and variable-length LDPC encoding and decoding are performed by applying lifting to match the block size included in each large group from the exponent matrix or sequence. In other words, the base matrices of the parity check matrices corresponding to the exponent matrices or sequences of multiple different LDPC codes are equal to each other. According to this method, the elements or numbers constituting the exponent matrix of the LDPC code or LDPC sequence can have different values, but the positions of the corresponding elements or numbers are exactly consistent with each other. As mentioned above, the sequence of exponent matrices or LDPC codes implies the index of the cyclic permutation matrix, i.e., a cyclic permutation value of the bit, and by configuring the positions of the elements or numbers to be equal to each other, the positions of the bits corresponding to the corresponding cyclic permutation matrix can be easily captured.

[0778] Figures 22A to 22D This is a diagram illustrating other index matrices according to various embodiments of the present disclosure.

[0779] refer to Figure 22A ,exist Figure 22A and Figure 23A Examples of exponent matrices corresponding to the parity check matrices of QCLDPC codes designed based on mathematical expressions 29 to 32 are shown consecutively (note that in...). Figure 22A and Figure 23A In the exponential matrix, empty blocks are the portions corresponding to zero matrices of size Z x Z. Depending on the situation, in Figure 22A and Figure 23A In the exponential matrix, empty blocks can be represented by specified values, such as -1. Figure 22A and Figure 23A The exponent matrix of the LDPC code shown is characterized by having the same characteristics as... Figure 21A A basis matrix with the same basis matrix.

[0780] Figure 22A and Figure 23A The LDPC exponent matrix of size 46x68 is shown, corresponding to the fifth and sixth large subgroups expressed in mathematical expressions 29 and 30, respectively. Furthermore, Figures 22B to 22D It is shown Figure 22A An enlarged view of the 22B-22D portion of the exponential matrix. Figure 22A A matrix corresponding to the reference numerals in the accompanying drawings and those described on the various components. Therefore, it can be understood through... Figures 22B to 22D ,as well as Figure 22A A base matrix is ​​configured by combining parts of 22E, 22F, 22G, 22H, 22I, and 22J.

[0781] Figures 23A to 23D This is a diagram illustrating other index matrices according to various embodiments of the present disclosure.

[0782] refer to Figure 23A , Figure 23A This is an enlarged view showing the various parts after dividing the index matrices. For reference, Figure 23A The 23E part equals Figure 22A Part 22E, Figure 23A The 23H part equals Figure 22A Part 22H, Figure 23A The 23F part equals Figure 22A Section 22F. Furthermore... Figure 23A The 23I part equals Figure 22A Part 22I, Figure 23A The 23G portion equals Figure 22A The 22G portion, Figure 23A The 23J part equals Figure 22A Part 22J.

[0783] Figure 22A and Figure 23A The exponent matrix shown corresponds to an LDPC code designed based on the block size group defined in mathematical expressions 29 or 30. However, depending on system requirements, it is not necessary to support all block sizes included in the block size group, and other values ​​may be added in addition to the block sizes expressed in mathematical expressions 29 or 30, depending on the circumstances.

[0784] For example, Figure 22A and Figure 23A The exponent matrix shown can support not only block sizes corresponding to the large groups (sets) of blocks defined in mathematical expressions 29 or 30, but also block sizes corresponding to subsets of each group (set), and, depending on the circumstances, other values.

[0785] Furthermore, according to the system, it can be used as is. Figure 22A and Figure 23A The exponent matrix shown can be used, or only a portion of it can be used. For example, by making... Figure 22A and Figure 23A The base matrix, or the remaining part of the matrix excluding the 21 rows and 21 columns, corresponds to... Figure 17B , 17C 17D and 17E, and make another matrix or LDPC sequence correspond to Figure 17A The 17F, 17G, 17H, 17I, and 17J sections, LDPC encoding and decoding devices, and methods can be used in conjunction with... Figure 17A It is used in a form similar to a base matrix or exponential matrix.

[0786] Typically, this can be achieved by applying [the application] from [the source]. Figure 21A LDPC encoding and decoding are performed by appropriately selecting rows and columns from the base matrix and configuring a portion of the matrix as the new base matrix or exponent matrix. Similarly, by... Figure 22A and Figure 23A The partial matrix configured by appropriately selecting row and column blocks of the exponent matrix can be used as a new exponent matrix in LDPC encoding and decoding devices and methods.

[0787] For reference, the basis matrix for LDPC encoding and decoding of the sequence expressed in mathematical expression 26 can be expressed as in mathematical expression 33 or 34.

[0788] Mathematical expression 33 implies that if it is assumed that the positions of elements or their index values ​​are omitted, but the correspondence rules are known in the case that the blocks from the 27th column to the last column (such as the base matrix) have a diagonal structure, then LDPC sequences can be used. As an example, mathematical expression 33 shows an example in which the position of element 1 is omitted in the blocks from the 27th column to the last column.

[0789] [Mathematical Expression 33] 0 1 2 3 5 6 9 10 11 12 13 15 16 18 19 20 21 22 23 0 2 3 4 5 7 8 9 11 12 14 15 16 17 19 21 22 23 24 0 1 2 4 5 6 7 8 9 10 13 14 15 17 18 19 20 24 25 0 1 3 4 6 7 8 10 11 12 13 14 16 17 18 20 21 22 25 0 1 0 1 3 12 16 21 22 0 6 10 11 13 17 18 20 0 1 4 7 8 14 0 1 3 12 16 19 21 22 24 0 1 10 11 13 17 18 20 1 2 4 7 8 140 1 12 16 21 22 230 1 10 11 13 18 0 3 7 20 23 0 12 15 16 17 210 1 10 13 18 25 1 3 11 20 22 0 14 16 17 21 1 12 13 18 19 0 1 7 8 10 0 3 9 11 22 1 5 16 20 21 0 12 13 17 1 2 10 18 0 3 4 11 22 1 6 7 14 0 2 4 15 1 6 8 0 4 19 21 1 14 18 25 0 10 13 24 1 7 22 25 0 12 14 24 1 2 11 21 0 7 15 17 1 6 12 22 0 14 15 18 1 13 23 0 9 10 12 1 3 7 19 0 8 17 1 3 9 18 0 4 24 1 16 18 25 0 7 9 22 1 6 10

[0833] Mathematical expression 34 indicates the position of element 1 in the basis matrix expressed in mathematical expression 26. For convenience, mathematical expression 34 is an example in which the position of element 1 is omitted from the 27th column block to the last column block, and starting from the 28th column, a sequence can be added and expressed in the order of 4, 5, 6, ...

[0834] [Mathematical Expression 34] 0 1 2 3 4 5 6 7 8 9 11 12 13 14 15 17 19 20 22 24 26 28 30 32 34 3638 40 4244 0 2 3 4 5 7 8 9 10 11 12 15 16 18 19 21 23 25 27 29 31 33 35 37 39 4143 45 0 1 2 10 23 26 33 0 1 3 5 8 13 16 20 24 39 41 1 2 3 7 10 24 26 28 42 0 1 2 21 0 2 3 6 25 27 35 45 1 2 3 7 10 13 19 25 31 34 39 44 1 2 3 7 10 19 27 40 0 1 2 20 38 41 44 0 2 3 6 9 12 15 19 23 30 38 45 0 1 3 6 9 12 16 20 24 33 0 1 3 5 8 11 14 18 22 32 35 38 0 2 3 6 9 12 15 18 22 30 37 1 2 3 7 10 17 25 29 32 36 0 1 2 14 26 34 36 0 1 3 5 8 11 14 17 21 43 1 2 3 6 9 14 17 22 34 40 0 2 3 6 9 12 15 18 23 29 36 41 43 0 1 2 8 18 28 39 0 2 3 6 9 13 16 21 0 1 3 5 8 11 14 17 21 28 33 0 1 3 5 8 11 16 20 24 31 35 44 0 1 11 13 37 1 2 8 30 32 42 2 3 15 29 31 43

[0861] Figures 24A to 24D These are illustrations of other elementary matrices according to various embodiments of the present disclosure.

[0862] refer to Figure 24A The basis matrices for LDPC encoding and decoding of the sequence expressed in mathematical expression 26 can be as follows: Figure 24A As shown. Figure 24A The matrix shown represents a basis matrix of size 46x68. Furthermore, Figures 24B to 24D It is shown Figure 24A An enlarged view of the 24B-24D portion of the exponential matrix.

[0863] Figure 24A The matrix corresponding to the reference numerals in the accompanying drawings and those described in each part is combined. Therefore, it can be achieved through... Figures 24B to 24D ,as well as Figure 24A A base matrix is ​​configured by combining parts from the 24E, 24F, 24G, 24H, 24I, and 24J portions. For reference, Figure 24A The 24E, 24H, 24F, 24I, 24G, and 24J parts are equal to Figure 21A The 21E, 21H, 21F, 21I, 21G, and 21J parts, therefore they are in Figure 24A The middle part is omitted.

[0864] Although this disclosure has been shown and described with reference to various embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as defined by the appended claims and their equivalents.< / null>

Claims

1. A method for channel coding in a communication system, the method being performed by means including a transceiver and at least one processor coupled to the transceiver, the method comprising: The block size is identified by the at least one processor based on the input bits; An encoding process is performed by the at least one processor, the encoding process being used to encode the input bits based on a parity check matrix corresponding to the block size; and The transceiver transmits the encoded input bits. The parity check matrix is ​​identified based on the basis matrix. The base matrix includes a submatrix consisting of multiple rows and columns. Wherein, the column index corresponding to the non-zero element included in two or more consecutive rows in the submatrix includes different values ​​for the two or more consecutive rows. The parity check matrix is ​​identified based on the fact that the value 1 in the base matrix is ​​replaced by a matrix that is not zero. Wherein, the number of rows in the submatrix is ​​less than the number of rows in the base matrix, and the number of columns in the submatrix is ​​less than the number of columns in the base matrix.

2. The method according to claim 1, in, The block size is selected based on the block size group. The large block group includes a first large block group Z1, which includes 24, 48, 96, 192, and 384. The large block group includes a second large block group Z2, which comprises 22, 44, 88, 176, and 352. The large block group includes a third large block group Z3, which includes 20, 40, 80, 160, and 320. The block group includes a fourth block group Z4, which comprises 18, 36, 72, 144, and 288. The block group includes a fifth block group Z5, which comprises 16, 32, 64, 128, and 256. The block group includes a sixth block group Z6, which comprises 15, 30, 60, 120, and 240. The block group includes a seventh block group Z7, which comprises 14, 28, 56, 112, and 224. Among them, the block group includes the eighth block group Z8, and Z8 includes 26, 52, 104, and 208.

3. The method according to claim 1, wherein, The submatrix does not include column indices 0 and 1 of the base matrix.

4. The method according to claim 1, wherein, The matrix is ​​identified by cyclically shifting the identity matrix based on values ​​identified by applying a modulo operation of the block size to the elements of a predetermined matrix.

5. The method according to claim 1, wherein, The base matrix has multiple rows with the following values ​​as column indices: For rows 0, 1, 3, 12, 16, 21, 22, and 27, For rows 0, 6, 10, 11, 13, 17, 18, 20, and 28, For rows 0, 1, 4, 7, 8, 14, and 29, For rows 0, 1, 3, 12, 16, 19, 21, 22, 24, and 30, For rows 0, 1, 10, 11, 13, 17, 18, 20, and 31, For rows 1, 2, 4, 7, 8, 14, and 32, For rows 0, 1, 12, 16, 21, 22, 23, and 33, For rows 0, 1, 10, 11, 13, 18, and 34, For rows 0, 3, 7, 20, 23, and 35, For rows 0, 12, 15, 16, 17, 21, and 36, For rows 0, 1, 10, 13, 18, 25, and 37, For rows 1, 3, 11, 20, 22, and 38, For rows 0, 14, 16, 17, 21, and 39, For rows 1, 12, 13, 18, 19, and 40, For rows 0, 1, 7, 8, 10, and 41, For rows 0, 3, 9, 11, 22, and 42, For rows 1, 5, 16, 20, 21, and 43, For rows 0, 12, 13, 17, and 44, For rows 1, 2, 10, 18, and 45, and For rows 0, 3, 4, 11, 22, and 46, and The submatrix has multiple rows with the following values ​​as column indices: For rows 3, 12, 16, 21, 22, and 27, For rows 6, 10, 11, 13, 17, 18, 20, and 28, For rows 4, 7, 8, 14, and 29, For rows 3, 12, 16, 19, 21, 22, 24, and 30, For rows 10, 11, 13, 17, 18, 20, and 31, For rows 2, 4, 7, 8, 14, and 32, For rows 12, 16, 21, 22, 23, and 33, For rows 10, 11, 13, 18, and 34 among the plurality of rows... For rows 3, 7, 20, 23, and 35, For rows 12, 15, 16, 17, 21, and 36, For rows 10, 13, 18, 25, and 37, For rows 3, 11, 20, 22, and 38, For rows 14, 16, 17, 21, and 39, For rows 12, 13, 18, 19, and 40, For rows 7, 8, 10, and 41, For rows 3, 9, 11, 22, and 42, For rows 5, 16, 20, 21, and 43, For rows 12, 13, 17, and 44, For rows 2, 10, 18, and 45, and For rows 3, 4, 11, 22 and 46 of the plurality of rows.

6. A method for channel decoding in a communication system, the method being performed by means including a transceiver and at least one processor coupled to the transceiver, the method comprising: The transceiver receives the signal corresponding to the input bits. The block size is identified by the at least one processor based on the input bits; as well as The decoding process is performed by the at least one processor, the decoding process being used to encode the signal based on a parity check matrix corresponding to the block size. The parity check matrix is ​​identified based on the basis matrix. The base matrix includes a submatrix consisting of multiple rows and columns. Wherein, the column index corresponding to the non-zero element included in two or more consecutive rows in the submatrix includes different values ​​for the two or more consecutive rows. The parity check matrix is ​​identified based on the fact that the value 1 in the base matrix is ​​replaced by a matrix that is not zero. Wherein, the number of rows in the submatrix is ​​less than the number of rows in the base matrix, and the number of columns in the submatrix is ​​less than the number of columns in the base matrix.

7. The method according to claim 6, in, The block size is selected based on the block size group. The large block group includes a first large block group Z1, which includes 24, 48, 96, 192, and 384. The large block group includes a second large block group Z2, which comprises 22, 44, 88, 176, and 352. The large block group includes a third large block group Z3, which includes 20, 40, 80, 160, and 320. The block group includes a fourth block group Z4, which comprises 18, 36, 72, 144, and 288. The block group includes a fifth block group Z5, which comprises 16, 32, 64, 128, and 256. The block group includes a sixth block group Z6, which comprises 15, 30, 60, 120, and 240. The block group includes a seventh block group Z7, which comprises 14, 28, 56, 112, and 224. Among them, the block group includes the eighth block group Z8, and Z8 includes 26, 52, 104, and 208.

8. The method according to claim 6, wherein, The submatrix does not include column indices 0 and 1 of the base matrix.

9. The method according to claim 6, wherein, The matrix is ​​identified by cyclically shifting the identity matrix based on values ​​identified by applying a modulo operation of the block size to the elements of a predetermined matrix.

10. The method according to claim 6, wherein, The base matrix has multiple rows with the following values ​​as column indices: For rows 0, 1, 3, 12, 16, 21, 22, and 27, For rows 0, 6, 10, 11, 13, 17, 18, 20, and 28, For rows 0, 1, 4, 7, 8, 14, and 29, For rows 0, 1, 3, 12, 16, 19, 21, 22, 24, and 30; for rows 0, 1, 10, 11, 13, 17, 18, 20, and 31; for rows 1, 2, 4, 7, 8, 14, and 32, For rows 0, 1, 12, 16, 21, 22, 23, and 33, and for rows 0, 1, 10, 11, 13, 18, and 34, For rows 0, 3, 7, 20, 23, and 35, For rows 0, 12, 15, 16, 17, 21, and 36, For rows 0, 1, 10, 13, 18, 25, and 37, For rows 1, 3, 11, 20, 22, and 38, For rows 0, 14, 16, 17, 21, and 39, For rows 1, 12, 13, 18, 19, and 40, For rows 0, 1, 7, 8, 10, and 41, For rows 0, 3, 9, 11, 22, and 42, For rows 1, 5, 16, 20, 21, and 43, For rows 0, 12, 13, 17, and 44, For rows 1, 2, 10, 18, and 45, and For rows 0, 3, 4, 11, 22, and 46, and The submatrix has multiple rows with the following values ​​as column indices: For rows 3, 12, 16, 21, 22, and 27, For rows 6, 10, 11, 13, 17, 18, 20, and 28, and for rows 4, 7, 8, 14, and 29, For rows 3, 12, 16, 19, 21, 22, 24, and 30, and for rows 10, 11, 13, 17, 18, 20, and 31, For rows 2, 4, 7, 8, 14, and 32, For rows 12, 16, 21, 22, 23, and 33, For rows 10, 11, 13, 18, and 34 among the plurality of rows... For rows 3, 7, 20, 23, and 35, For rows 12, 15, 16, 17, 21, and 36, For rows 10, 13, 18, 25, and 37, For rows 3, 11, 20, 22, and 38, For rows 14, 16, 17, 21, and 39, For rows 12, 13, 18, 19, and 40, For rows 7, 8, 10, and 41, For rows 3, 9, 11, 22, and 42, For rows 5, 16, 20, 21, and 43, For rows 12, 13, 17, and 44, For rows 2, 10, 18, and 45, and For rows 3, 4, 11, 22 and 46 of the plurality of rows.

11. An apparatus for performing channel coding in a communication system, the apparatus comprising: transceiver; and At least one processor, coupled to the transceiver and configured to: Block size is identified based on input bits. The encoding process is performed to encode the input bits based on a parity check matrix corresponding to the block size. Control the transceiver to send encoded input bits. The parity check matrix is ​​identified based on the basis matrix. The base matrix includes a submatrix consisting of multiple rows and columns. Wherein, the column index corresponding to the non-zero element included in two or more consecutive rows in the submatrix includes different values ​​for the two or more consecutive rows. The parity check matrix is ​​identified based on the fact that the value 1 in the base matrix is ​​replaced by a matrix that is not zero. Wherein, the number of rows in the submatrix is ​​less than the number of rows in the base matrix, and the number of columns in the submatrix is ​​less than the number of columns in the base matrix.

12. The apparatus according to claim 11, in, The block size is selected based on the block size group. The large block group includes a first large block group Z1, which includes 24, 48, 96, 192, and 384. The large block group includes a second large block group Z2, which comprises 22, 44, 88, 176, and 352. The large block group includes a third large block group Z3, which includes 20, 40, 80, 160, and 320. The block group includes a fourth block group Z4, which comprises 18, 36, 72, 144, and 288. The block group includes a fifth block group Z5, which comprises 16, 32, 64, 128, and 256. The block group includes a sixth block group Z6, which comprises 15, 30, 60, 120, and 240. The block group includes a seventh block group Z7, which comprises 14, 28, 56, 112, and 224. Among them, the block group includes the eighth block group Z8, and Z8 includes 26, 52, 104, and 208.

13. The apparatus according to claim 11, wherein, The submatrix does not include column indices 0 and 1 of the base matrix.

14. The apparatus according to claim 11, wherein, The matrix is ​​identified by cyclically shifting the identity matrix based on values ​​identified by applying a modulo operation of the block size to the elements of a predetermined matrix.

15. The apparatus according to claim 11, wherein, The base matrix has multiple rows with the following values ​​as column indices: For rows 0, 1, 3, 12, 16, 21, 22, and 27, For rows 0, 6, 10, 11, 13, 17, 18, 20, and 28, For rows 0, 1, 4, 7, 8, 14, and 29, For rows 0, 1, 3, 12, 16, 19, 21, 22, 24, and 30, For rows 0, 1, 10, 11, 13, 17, 18, 20, and 31, For rows 1, 2, 4, 7, 8, 14, and 32, For rows 0, 1, 12, 16, 21, 22, 23, and 33, For rows 0, 1, 10, 11, 13, 18, and 34, For rows 0, 3, 7, 20, 23, and 35, For rows 0, 12, 15, 16, 17, 21, and 36, For rows 0, 1, 10, 13, 18, 25, and 37, For rows 1, 3, 11, 20, 22, and 38, For rows 0, 14, 16, 17, 21, and 39, For rows 1, 12, 13, 18, 19, and 40, For rows 0, 1, 7, 8, 10, and 41, For rows 0, 3, 9, 11, 22, and 42, For rows 1, 5, 16, 20, 21, and 43, and for rows 0, 12, 13, 17, and 44, For rows 1, 2, 10, 18, and 45, and For rows 0, 3, 4, 11, 22, and 46, and The submatrix has multiple rows with the following values ​​as column indices: For rows 3, 12, 16, 21, 22, and 27; for rows 6, 10, 11, 13, 17, 18, 20, and 28; for rows 4, 7, 8, 14, and 29, For rows 3, 12, 16, 19, 21, 22, 24, and 30; for rows 10, 11, 13, 17, 18, 20, and 31; for rows 2, 4, 7, 8, 14, and 32, For rows 12, 16, 21, 22, 23, and 33, and for rows 10, 11, 13, 18, and 34... For rows 3, 7, 20, 23, and 35, For rows 12, 15, 16, 17, 21, and 36, and for rows 10, 13, 18, 25, and 37, For rows 3, 11, 20, 22, and 38, For rows 14, 16, 17, 21, and 39, For rows 12, 13, 18, 19, and 40, For rows 7, 8, 10, and 41, For rows 3, 9, 11, 22, and 42, For rows 5, 16, 20, 21, and 43, For rows 12, 13, 17, and 44, For rows 2, 10, 18, and 45, and For rows 3, 4, 11, 22 and 46 of the plurality of rows.

16. An apparatus for performing channel decoding in a communication system, the apparatus comprising: transceiver; and At least one processor, coupled to the transceiver, is configured to: The transceiver is controlled to receive signals corresponding to the input bits, and the block size is identified based on the input bits. A decoding process is performed, which encodes the signal based on a parity check matrix corresponding to the block size. The parity check matrix is ​​identified based on the basis matrix. The base matrix includes a submatrix consisting of multiple rows and columns. Wherein, the column index corresponding to the non-zero element included in two or more consecutive rows in the submatrix includes different values ​​for the two or more consecutive rows. The parity check matrix is ​​identified based on the fact that the value 1 in the base matrix is ​​replaced by a matrix that is not zero. Wherein, the number of rows in the submatrix is ​​less than the number of rows in the base matrix, and the number of columns in the submatrix is ​​less than the number of columns in the base matrix.

17. The apparatus according to claim 16, in, The block size is selected based on the block size group. The large block group includes a first large block group Z1, which includes 24, 48, 96, 192, and 384. The large block group includes a second large block group Z2, which comprises 22, 44, 88, 176, and 352. The large block group includes a third large block group Z3, which includes 20, 40, 80, 160, and 320. The block group includes a fourth block group Z4, which comprises 18, 36, 72, 144, and 288. The block group includes a fifth block group Z5, which comprises 16, 32, 64, 128, and 256. The block group includes a sixth block group Z6, which comprises 15, 30, 60, 120, and 240. The block group includes a seventh block group Z7, which comprises 14, 28, 56, 112, and 224. Among them, the block group includes the eighth block group Z8, and Z8 includes 26, 52, 104, and 208.

18. The apparatus according to claim 16, wherein, The submatrix does not include column indices 0 and 1 of the base matrix.

19. The apparatus according to claim 16, wherein, The matrix is ​​identified by cyclically shifting the identity matrix based on values ​​identified by applying a modulo operation of the block size to the elements of a predetermined matrix.

20. The apparatus according to claim 16, wherein, The base matrix has multiple rows with the following values ​​as column indices: For rows 0, 1, 3, 12, 16, 21, 22, and 27, For rows 0, 6, 10, 11, 13, 17, 18, 20, and 28, For rows 0, 1, 4, 7, 8, 14, and 29, For rows 0, 1, 3, 12, 16, 19, 21, 22, 24, and 30, For rows 0, 1, 10, 11, 13, 17, 18, 20, and 31, For rows 1, 2, 4, 7, 8, 14, and 32, For rows 0, 1, 12, 16, 21, 22, 23, and 33, For rows 0, 1, 10, 11, 13, 18, and 34, For rows 0, 3, 7, 20, 23, and 35, For rows 0, 12, 15, 16, 17, 21, and 36, For rows 0, 1, 10, 13, 18, 25, and 37, For rows 1, 3, 11, 20, 22, and 38, For rows 0, 14, 16, 17, 21, and 39, For rows 1, 12, 13, 18, 19, and 40, For rows 0, 1, 7, 8, 10, and 41, For rows 0, 3, 9, 11, 22, and 42, For rows 1, 5, 16, 20, 21, and 43, For rows 0, 12, 13, 17, and 44, For rows 1, 2, 10, 18, and 45, and For rows 0, 3, 4, 11, 22, and 46, and The submatrix has multiple rows with the following values ​​as column indices: For rows 3, 12, 16, 21, 22, and 27, For rows 6, 10, 11, 13, 17, 18, 20, and 28, For rows 4, 7, 8, 14, and 29, For rows 3, 12, 16, 19, 21, 22, 24, and 30, For rows 10, 11, 13, 17, 18, 20, and 31, For rows 2, 4, 7, 8, 14, and 32, For rows 12, 16, 21, 22, 23, and 33; for rows 10, 11, 13, 18, and 34; for rows 3, 7, 20, 23, and 35; for rows 12, 15, 16, 17, 21, and 36; for rows 10, 13, 18, 25, and 37; for rows 3, 11, 20, 22, and 38; for rows 14, 16, 17, 21, and 39; for rows 12, 13, 18, 19, and 40; for rows 7, 8, 10, and 41... For rows 3, 9, 11, 22 and 42, for rows 5, 16, 20, 21 and 43, for rows 12, 13, 17 and 44, for rows 2, 10, 18 and 45, and for rows 3, 4, 11, 22 and 46.

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