A line detection method and device for line balancing

CN117768341BActive Publication Date: 2026-09-25SHANDONG SENTER ELECTRONICS
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Patent Information

Application Number
CN202211173901.1
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2022-09-26
Publication Date
2026-09-25
Estimated Expiration
2042-09-26

AI Technical Summary

Technical Problem

大量数据的采样以及FFT运算,导致现有测量设备测量一次线路纵向平衡度的时间很长,若要减少计算时间,需提高DSP工作主频,将提高设备硬件成本,不便于推广使用

Benefits of technology

[0018]本申请通过上述方案,能够通过控制器实现计算纵向平衡度的需求,较DSP节省成本,且本申请不需进行FFT运算转换成频域信号,而是通过ADC采样的反馈信号,直接在时域信号上计算,减少了计算量,保证了计算效率,降低了工作主频。从而实现了快速测量线路纵向平衡度,降低线路纵向平衡度监控所需的硬件成本的需求。

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Abstract

The application provides a line detection method and device for line balance, which obtains a to-be-tested frequency point of a to-be-tested cable by a controller, and then obtains a feedback signal by a signal acquisition module; the feedback signal is a signal synchronously acquired from one end of the to-be-tested cable inputted with a test signal. In the case that the feedback signal meets a preset condition, a differential mode signal amplitude corresponding to a preset sampling point sequence is determined. The preset condition is that a signal amplitude value of the feedback signal is greater than a first preset value and / or a signal gain value of the feedback signal is greater than a second preset value. The sampling point sequence comprises signal values of corresponding sampling points in multiple sampling periods. The differential mode signal amplitude is inputted into a preset formula to determine a longitudinal balance degree corresponding to the to-be-tested frequency point, and the longitudinal balance degree is sent to a user terminal.
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Description

Technical Field

[0001] This application relates to the field of telecommunications network technology, and in particular to a line detection method and apparatus for line balancing. Background Technology

[0002] Longitudinal balance is used to measure the longitudinal balance performance of a line, that is, the line's unbalanced performance relative to ground. Longitudinal balance is an important indicator of line quality when the line is used for high-speed data transmission. This is mainly because: line-to-ground imbalance can cause a potential difference between the two wires of a pair, thus forming a potential loop between the two wires, generating loop current, and resulting in additional interference. Due to the existence of the potential loop, an electromagnetic field is generated around the line, causing a large amount of external interference to couple into the line, affecting normal communication.

[0003] Existing equipment for measuring line longitudinal balance uses a combination of DSP technology and field programmable gate array (FPGA) at the hardware level, and performs fast Fourier transform (FFT) on the sampled data of the line at the software level to obtain the signal amplitude of the corresponding frequency, and then calculates the line longitudinal balance.

[0004] The aforementioned method for calculating longitudinal balance, in order to increase the accuracy of spectral resolution and signal amplitude, requires multiple samplings of a large amount of data for averaging and FFT calculations. The large amount of data sampling and FFT calculations result in a very long measurement time for existing measurement equipment to measure the longitudinal balance of a line. To reduce the calculation time, the DSP's operating frequency needs to be increased, which will raise the hardware cost of the equipment and hinder its widespread adoption. Summary of the Invention

[0005] This application provides a method and apparatus for line balancing, which can quickly measure the longitudinal balance of a line and reduce the hardware cost required for line longitudinal balance detection.

[0006] On one hand, embodiments of this application provide a line detection method for line balancing, the method comprising:

[0007] The controller acquires the test frequency of the cable under test. A feedback signal is obtained through the signal acquisition module. The feedback signal is a signal synchronously acquired from one end of the cable under test to which the test signal is input. If the feedback signal meets preset conditions, the differential-mode signal amplitude corresponding to a preset sampling point sequence is determined. The preset conditions are that the signal amplitude of the feedback signal is greater than a first preset value and / or the signal gain of the feedback signal is greater than a second preset value. The sampling point sequence includes the signal values ​​of corresponding sampling points across multiple sampling periods. The differential-mode signal amplitude is input into a preset formula to determine the longitudinal balance corresponding to the test frequency, and the longitudinal balance is sent to the user terminal.

[0008] In one implementation of this application, the number of sampling point sequences and the number of sampling points are determined based on the corresponding sampling frequency, sampling period, and frequency value of the test signal of the signal acquisition module. Based on the correspondence between sampling points within the sampling period, the corresponding sampling points of the sampling point sequence and the signal values ​​of the corresponding sampling points of the sampling point sequence are determined. The correspondence refers to the correspondence between the sampling times of each sampling point in different signal periods of the test signal. Based on the number of sequences and the number of sampling points, the signal values ​​of the corresponding sampling points of the sampling point sequence are used as the sampling point sequence in chronological order to determine the differential-mode signal amplitude corresponding to the preset sampling point sequence.

[0009] In one implementation of this application, the average signal value corresponding to each sampling point sequence is calculated based on the sampling period and the sequence of each sampling point. The average signal values ​​are then sorted to determine the maximum and minimum values. The differential signal amplitude is determined based on the difference between the maximum and minimum values.

[0010] In one implementation of this application, if it is determined that the feedback signal does not meet the preset conditions, a gain adjustment command is generated and sent to the signal acquisition module. This causes the first VGA signal amplifier in the signal acquisition module to adjust its gain according to the gain adjustment command and a preset gain adjustment step size. An updated feedback signal after the gain adjustment of the first VGA signal amplifier is then acquired, and it is determined whether the updated feedback signal meets the preset conditions.

[0011] In one implementation of this application, the frequency value and corresponding signal amplitude value corresponding to the frequency point to be tested are determined. The frequency point to be tested corresponds to at least one frequency value of the transmission signal frequency of the cable under test. The frequency value corresponding to the frequency point to be tested is sent to a direct digital frequency synthesizer (DDS) in the signal acquisition module, and the signal amplitude value is sent to a second VGA signal amplifier to generate a test signal corresponding to the frequency point to be tested. The test signal is then input to the other end of the cable under test. A feedback signal from one end of the cable under test, excited by the test signal, is obtained through an analog-to-digital converter (ADC) in the signal acquisition module.

[0012] In one implementation of this application, a clock synchronization signal is sent to the DDS and ADC via the field-programmable gate array (FPGA) of the signal acquisition module.

[0013] In one implementation of this application, the signal amplitude value of the test signal is determined. Based on the signal amplitude value, the differential mode signal amplitude, and a preset formula, the longitudinal balance of the cable under test is determined, which is the longitudinal balance.

[0014] In one implementation of this application, the test signal is the common-mode voltage at the other end of the cable under test.

[0015] In one implementation of this application, the multiple sampling periods of the sampling point sequence are consecutive sampling periods.

[0016] On the other hand, embodiments of this application also provide a line detection device for line balancing, the device comprising:

[0017] The first acquisition module is used by the controller to acquire the frequency point to be tested from the cable under test. The second acquisition module is used to acquire the feedback signal through the signal acquisition module. The feedback signal is a signal synchronously acquired from one end of the cable under test to which the test signal is input. The determination module is used to determine the differential-mode signal amplitude corresponding to a preset sampling point sequence, provided that the feedback signal meets preset conditions. The preset conditions are that the signal amplitude of the feedback signal is greater than a first preset value and / or the signal gain of the feedback signal is greater than a second preset value. The sampling point sequence includes the signal values ​​of corresponding sampling points across multiple sampling periods. The determination and transmission module is used to input the differential-mode signal amplitude into a preset formula, determine the longitudinal balance corresponding to the frequency point under test, and send the longitudinal balance to the user terminal.

[0018] This application, through the aforementioned solution, enables the calculation of longitudinal balance using a controller, saving costs compared to DSP. Furthermore, this application eliminates the need for FFT operations to convert to a frequency domain signal; instead, it directly calculates the longitudinal balance in the time domain using the feedback signal sampled by the ADC, reducing computational load, ensuring computational efficiency, and lowering the operating frequency. This achieves rapid measurement of line longitudinal balance and reduces the hardware costs required for monitoring line longitudinal balance. Attached Figure Description

[0019] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0020] Figure 1 This is a schematic diagram of the hardware structure of a line detection method for line balancing in an embodiment of this application;

[0021] Figure 2 This is a schematic flowchart of a line detection method for line balancing in an embodiment of this application;

[0022] Figure 3 This is a circuit diagram illustrating the common-mode amplitude and differential-mode amplitude of a line detection method for line balancing in an embodiment of this application.

[0023] Figure 4 This is a schematic diagram of feedback signal sampling and processing in a line detection method for line balancing according to an embodiment of this application;

[0024] Figure 5 This is a schematic diagram of another feedback signal for a line detection method for line balancing in an embodiment of this application;

[0025] Figure 6 This is another schematic flowchart of a line detection method for line balancing in an embodiment of this application;

[0026] Figure 7 This is a schematic diagram of a line detection device for line balancing in an embodiment of this application. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0028] Currently, the calculation of longitudinal balance of a line is mostly performed by combining DSP and FPGA. However, to improve the calculation efficiency of longitudinal balance, a DSP with a high operating frequency is required, which greatly increases the calculation cost of longitudinal balance.

[0029] ARM microcontrollers are cheaper than DSPs, but their computation time is longer. If a low-cost ARM microcontroller can replace a DSP while maintaining computational efficiency, the computational cost of vertical balance can be greatly reduced.

[0030] Based on this, the present application provides a line detection method and apparatus for line balancing, which solves the problem of high hardware costs required for rapid measurement and monitoring of line longitudinal balance.

[0031] The various embodiments of this application are described in detail below with reference to the accompanying drawings.

[0032] This application provides a line detection method for line balancing, such as... Figure 1 As shown, this line detection method acquires the frequency point sent by the user terminal 110 through the signal transmission module 120 and sends the frequency point to the ARM microcontroller (data processing module 130). The ARM microcontroller 130 controls the synchronous acquisition control module 180 to perform synchronous control, causing the signal modulation module 140 and the signal amplification module 150 to generate a test signal corresponding to the amplitude information of the frequency point. The front-end protection module 160 sends the test signal received from the signal amplification module 150 to the test cable (twisted pair). The analog front-end processing module 170 receives the signal excited by the test signal from the test cable and synchronously acquires the excited signal through the synchronous acquisition control module 180, and sends the acquired signal to the ARM microcontroller 130 to perform longitudinal balance calculation of the frequency point.

[0033] The signal acquisition module includes: a signal modulation module 140, a signal amplification module 150, a front-end protection module 160, an analog front-end processing module 170, and a synchronous acquisition control module 180. The signal transmission module 120 can be Bluetooth, receiving frequency points sent by the user terminal 110 via Bluetooth. The user terminal 110 can send frequency points via an app or other methods. The data processing module 130 can be an ARM microcontroller. The signal modulation module 140 is a Direct Digital Synthesizer (DDS). The signal amplification module 150 is a VGA signal amplifier. The front-end protection module 160 includes relays and differential transformers. The analog front-end processing module 170 includes a differential driver, a VGA signal amplifier, and a low-pass filter. The synchronous acquisition control module 180 includes a Field Programmable Gate Array (FPGA), an analog-to-digital converter (ADC), and Static Random Access Memory (SRAM). The SRAM is used to buffer the data output by the ADC.

[0034] This application provides a line detection method for line balancing, such as... Figure 2 As shown, the method may include steps S201-S204:

[0035] S201, the controller acquires the frequency point to be tested of the cable under test.

[0036] The controller is an ARM microcontroller, the cable under test is a twisted pair, and the frequency to be tested can be sent by the user terminal to a signal transmission module (Bluetooth) for receiving data. The ARM microcontroller reads the data from Bluetooth. The frequency to be tested corresponds to the frequency of the cable under test, which can be preset and corresponds to a frequency value of the transmitted signal of the cable under test.

[0037] S202, the controller obtains feedback signals through the signal acquisition module.

[0038] The feedback signal is a signal synchronously acquired from one end of the cable under test that receives the input test signal.

[0039] like Figure 3 As shown, the cable under test is a twisted pair, with one end as the branch terminal and the other end as the main terminal. That is, terminal 301 is the test signal input terminal for the cable under test, and the collected feedback signal comes from terminal 302. The controller acquires the feedback signal through the following embodiment, as detailed below:

[0040] First, the controller determines the frequency value and corresponding signal amplitude value of the frequency point under test. The frequency point under test corresponds to at least one frequency value of the transmission signal frequency of the cable under test. Next, the controller sends the frequency value corresponding to the frequency point under test to the Direct Digital Synthesizer (DDS) in the signal acquisition module and sends the signal amplitude value to the second VGA signal amplifier to generate the corresponding test signal for the frequency point under test. This test signal is then input to the other end of the cable under test.

[0041] In other words, after the controller obtains the frequency value and corresponding signal amplitude value of the frequency point under test, it synchronously controls the DDS via the FPGA to generate a signal at the frequency corresponding to the frequency point under test. This signal is then amplified to the amplitude corresponding to the signal amplitude value by the second VGA signal amplifier (signal amplification module). Afterward, the test signal is output to terminal 301 of the cable under test via the front-end protection module. The test signal is a common-mode voltage. A single frequency point corresponds to one frequency value, and multiple frequency points can correspond to the frequency point under test.

[0042] Subsequently, the controller acquires the feedback signal from one end of the cable under test, which is excited by the test signal, through the analog-to-digital converter (ADC) in the signal acquisition module.

[0043] The controller can send clock synchronization signals to the DDS and ADC through the field programmable gate array (FPGA) of the signal acquisition module.

[0044] In other words, the controller can obtain the signal after passing through the differential transformer through the analog front-end processing module, then perform signal filtering and amplification, and then collect the feedback signal through the ADC and send it to the ARM microcontroller for judgment of preset conditions.

[0045] S203, the controller determines the differential signal amplitude corresponding to the preset sampling point sequence when it determines that the feedback signal meets the preset conditions.

[0046] The preset conditions are that the signal amplitude of the feedback signal is greater than a first preset value and / or the signal gain of the feedback signal is greater than a second preset value. The sampling point sequence includes the signal values ​​of corresponding sampling points from multiple sampling periods. The multiple sampling periods of the sampling point sequence are consecutive sampling periods.

[0047] The first preset value and the second preset value are preset by the user, and this application does not specifically limit them. The controller can determine whether the feedback signal meets the preset conditions by comparing whether the signal amplitude value of the feedback signal is greater than the first preset value, or by comparing whether the signal gain value of the feedback signal amplified by the first VGA signal amplifier is greater than the second preset value; or it can judge both.

[0048] When the controller determines that the feedback signal meets preset conditions, it determines the differential signal amplitude corresponding to the preset sampling point sequence, specifically including:

[0049] First, the controller determines the number of sampling point sequences and the number of sampling points based on the corresponding sampling frequency Fs, sampling period T, and frequency value F0 of the test signal from the signal acquisition module.

[0050] In other words, the controller calculates the number of sequences N = Fs / F0 based on the sampling frequency Fs and sampling period T of the ADC in the signal acquisition module, where F0 is the frequency value of the input test signal. The number of sampling points within one sampling period is M = (Fs / F0)*T, i.e., M = N*T. The sampling period must be at least twice the signal period of the test signal.

[0051] Next, based on the correspondence between the sampling points within the sampling period, the controller determines the corresponding sampling points of the sampling point sequence and the signal values ​​of the corresponding sampling points of the sampling point sequence. The correspondence refers to the relationship between the sampling times of each sampling point in different signal periods of the test signal.

[0052] In other words, the controller can determine the correspondence between sampling points in different signal periods based on the sampling times of the sampling points in different signal periods, such as... Figure 4As shown, in signal period 401 and signal period 402, the acquisition time of 1 in signal period 401 corresponds to that of 1 in signal period 402, which are corresponding sampling points and are sampling points of the same sampling point sequence; the acquisition time of 2 in signal period 401 corresponds to that of 2 in signal period 402, which are corresponding sampling points and are sampling points of the same sampling point sequence.

[0053] Next, the controller, based on the number of sequences and the number of sampling points, takes the signal values ​​of the corresponding sampling points of the sampling point sequence as the sampling point sequence in chronological order, in order to determine the differential signal amplitude corresponding to the preset sampling point sequence.

[0054] In other words, the controller can generate a sequence of N sample points containing the signal values ​​of M sample points.

[0055] Subsequently, the controller is able to calculate the average signal value corresponding to each sampling point sequence based on the sampling period and the sequence of each sampling point.

[0056] Specifically, the controller operates according to the formula:

[0057] DA[j]=(D[j+1*N]+D[j+2*N]+D[j+3*N]…+D[j+(n)*N]) / T

[0058] Where DA[j] is the average signal value of the j-th sampling point sequence, where j is a natural number greater than 0 and less than N+1. D[j+n*N] is the sampling point of the n-th signal period of the j-th sampling point sequence, which is the (j+n*N)-th sampling point among the M sampling points.

[0059] The controller then sorts the average values ​​of each signal to determine the maximum and minimum values. Subsequently, the controller determines the differential signal amplitude based on the difference between the maximum and minimum values.

[0060] Specifically, after obtaining the maximum value Dmax and minimum value Dmin of the signal average, the controller can calculate the differential signal amplitude Vc according to the calculation method Vc = (Dmax - Dmin) / 2, such as... Figure 3 Vitamin C.

[0061] In this embodiment, when the controller determines that the feedback signal does not meet the preset conditions, it generates a gain adjustment command and sends the command to the signal acquisition module. This causes the first VGA signal amplifier in the signal acquisition module to adjust its gain according to the gain adjustment command and a preset gain adjustment step size. The controller then reacquires the updated feedback signal after the gain adjustment and determines whether the updated feedback signal meets the preset conditions.

[0062] If the preset conditions are met, the differential mode signal amplitude is calculated and input into a preset formula to determine the corresponding longitudinal balance at the frequency point. The longitudinal balance is then sent to the user terminal. If the preset conditions are not met, a gain adjustment command is regenerated to update the feedback signal until the updated feedback signal meets the preset conditions. The preset gain adjustment step size is set according to actual use, and this application does not specify a particular step size. For example, if the step size is set to 1, the gain of the VGA signal amplifier increases by 1 each time the preset conditions are not met. For instance, if the original gain is 4, the gain after increasing by 1 will be 5.

[0063] In the above scheme, the FPGA can synchronously generate the clock required by the DDS and ADC, so as to achieve the purpose of synchronizing the output test signal and the sampling feedback signal, and ensure more accurate calculation of longitudinal balance.

[0064] S204, the controller inputs the differential mode signal amplitude into a preset formula, determines the longitudinal balance of the frequency point to be measured, and sends the longitudinal balance to the user terminal.

[0065] The controller inputs the differential mode signal amplitude into a preset formula to determine the longitudinal balance at the frequency point to be measured, specifically including:

[0066] The controller can determine the signal amplitude value Vd of the test signal. Then, based on the signal amplitude value Vd, the differential mode signal amplitude Vc, and a preset formula, the longitudinal balance of the cable under test is determined, which is the longitudinal balance. The preset formula is:

[0067] Lb = 20log(Vd / Vc)

[0068] Where Lb is the longitudinal balance and Vc is the amplitude of the differential signal with noise measurement.

[0069] Furthermore, the noise primarily refers to thermal noise, which is caused by the Brownian motion of electrons in passive components such as resistors and feeders in communication equipment. The direction and magnitude of this electron current are random, resulting in a current with a mean of 0. The embodiments of this application, through the above-described scheme, can make the sampled data from the same sampling point more closely approximate the amplitude of the actual signal, thereby smoothing the noise and improving the signal-to-noise ratio. Figure 5 As shown, 501 is a schematic diagram of the feedback signal carrying noise, and 502 is the feedback signal after being processed by the above-mentioned longitudinal balance calculation scheme.

[0070] The above-mentioned solution enables the calculation of longitudinal balance using an ARM microcontroller and FPGA, which saves costs compared to DSP. Furthermore, the calculation of longitudinal balance using an ARM microcontroller does not require FFT conversion to a frequency domain signal. Instead, it directly calculates the longitudinal balance on the time domain signal using the feedback signal sampled by the ADC, reducing the computational load of the ARM microcontroller, ensuring computational efficiency, and lowering the operating frequency.

[0071] Furthermore, this application can obtain the average signal value of multiple signal cycles within one sampling period, reducing the measurement time of longitudinal balance without compromising calculation accuracy. Moreover, averaging the data from each sampling point across multiple signal cycles can reduce noise-induced errors, making the ADC sampling data closer to the actual signal and improving the signal-to-noise ratio.

[0072] Another flowchart of the line detection method for line balancing provided in this application embodiment is as follows: Figure 6 As shown, the specific steps include:

[0073] S601, the frequency point for receiving signals from the APP;

[0074] S602 generates the common-mode voltage of the test signal at a specific frequency.

[0075] S603 sends the common-mode voltage of the test signal to the external cable;

[0076] S604 samples the differential mode signal on the differential line of the external cable and records the sampled data;

[0077] S605, determines the signal amplitude and gain of the sampled data;

[0078] S606, if the preset conditions are not met, increase the gain;

[0079] S607, record the sampling data that meets the preset conditions as the best sampling data;

[0080] S608 processes the optimal sampled data to obtain the differential signal amplitude;

[0081] S609, calculate longitudinal balance.

[0082] Figure 7 This is a schematic diagram of a line detection device for line balancing provided in an embodiment of this application, as shown below. Figure 7 As shown, the device includes:

[0083] The first acquisition module is used by the controller to acquire the frequency point to be tested from the cable under test. The second acquisition module is used to acquire the feedback signal through the signal acquisition module. The feedback signal is a signal synchronously acquired from one end of the cable under test to which the test signal is input. The determination module is used to determine the differential-mode signal amplitude corresponding to a preset sampling point sequence, provided that the feedback signal meets preset conditions. The preset conditions are that the signal amplitude of the feedback signal is greater than a first preset value and / or the signal gain of the feedback signal is greater than a second preset value. The sampling point sequence includes the signal values ​​of corresponding sampling points across multiple sampling periods. The determination and transmission module is used to input the differential-mode signal amplitude into a preset formula, determine the longitudinal balance corresponding to the frequency point under test, and send the longitudinal balance to the user terminal.

[0084] The module is specifically used for:

[0085] Based on the sampling frequency, sampling period, and frequency value of the test signal from the signal acquisition module, the number of sampling point sequences and the number of sampling points are determined. Based on the correspondence between sampling points within the sampling period, the corresponding sampling points and their signal values ​​are determined. The correspondence refers to the relationship between the sampling times of each sampling point in different signal periods of the test signal. According to the number of sequences and sampling points, the signal values ​​of the corresponding sampling points in the sampling point sequence are used as the sampling point sequence in chronological order to determine the corresponding differential-mode signal amplitude of the preset sampling point sequence.

[0086] The module is specifically used for:

[0087] Based on the sampling period and the sequence of each sampling point, the average signal value corresponding to each sampling point sequence is calculated. The average signal values ​​are then sorted to determine the maximum and minimum values. The differential signal amplitude is determined based on the difference between the maximum and minimum values.

[0088] The determination module is also used for:

[0089] If the feedback signal does not meet the preset conditions, a gain adjustment command is generated and sent to the signal acquisition module. This causes the first VGA signal amplifier in the signal acquisition module to adjust its gain according to the gain adjustment command and the preset gain adjustment step size. The updated feedback signal after the gain adjustment of the first VGA signal amplifier is then acquired, and it is determined whether the updated feedback signal meets the preset conditions.

[0090] The second acquisition module is specifically used for:

[0091] The frequency value and corresponding signal amplitude value corresponding to the frequency point to be tested are determined. The frequency point to be tested corresponds to at least one frequency value of the transmission signal frequency of the cable under test. The frequency value corresponding to the frequency point to be tested is sent to the Direct Digital Synthesizer (DDS) in the signal acquisition module, and the signal amplitude value is sent to the second VGA signal amplifier to generate the corresponding test signal for the frequency point to be tested. The test signal is then input to the other end of the cable under test. The feedback signal from one end of the cable under test, excited by the test signal, is obtained through the analog-to-digital converter (ADC) in the signal acquisition module.

[0092] The second acquisition module is also used for:

[0093] The field-programmable gate array (FPGA) of the signal acquisition module sends clock synchronization signals to the DDS and ADC.

[0094] The sending module is specifically used for:

[0095] Determine the signal amplitude value of the test signal. Based on the signal amplitude value, the differential mode signal amplitude, and the preset formula, determine the longitudinal balance of the cable under test.

[0096] In addition, the test signal is the common-mode voltage at one end of the cable under test.

[0097] In addition, the multiple sampling periods of the sampling point sequence are consecutive sampling periods.

[0098] The various embodiments in this application are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the device embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0099] The apparatus and method provided in this application are one-to-one correspondences. Therefore, the apparatus also has similar beneficial technical effects as its corresponding method. Since the beneficial technical effects of the method have been described in detail above, the beneficial technical effects of the apparatus will not be repeated here.

[0100] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0101] The above description is merely an embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of this application should be included within the scope of the claims of this application.

Claims

1. A line detection method for line balancing, characterized in that, The method includes: The controller acquires the frequency point to be measured from the cable under test; The feedback signal is acquired through the signal acquisition module; the feedback signal is a signal synchronously acquired from one end of the cable under test that receives the input test signal. If the feedback signal satisfies a preset condition, the differential signal amplitude corresponding to a preset sampling point sequence is determined; wherein, the preset condition is that the signal amplitude of the feedback signal is greater than a first preset value and / or the signal gain of the feedback signal is greater than a second preset value; the sampling point sequence includes signal values ​​of corresponding sampling points of multiple sampling periods; specifically, it includes: determining the sequence number and the number of sampling points of the sampling point sequence based on the corresponding sampling frequency, sampling period of the signal acquisition module and the frequency value of the test signal; and determining the corresponding sampling points of the sampling point sequence based on the correspondence of each sampling point within the sampling period. The signal values ​​of the corresponding sampling points in the sampling point sequence are used; wherein, the correspondence is the correspondence between the sampling points at different sampling times of the test signal; based on the number of sequences and the number of sampling points, the signal values ​​of the corresponding sampling points in the sampling point sequence are used as the sampling point sequence in chronological order; based on the sampling period and each sampling point sequence, the average signal value corresponding to each sampling point sequence is calculated; the average signal values ​​are sorted to determine the maximum and minimum values ​​among the average signal values; the differential signal amplitude is determined based on the difference between the maximum and the minimum values. The amplitude of the differential signal is input into a preset formula to determine the longitudinal balance of the frequency point to be measured, and the longitudinal balance is sent to the user terminal.

2. The method according to claim 1, characterized in that, The method further includes: If it is determined that the feedback signal does not meet the preset conditions, a gain adjustment command is generated and sent to the signal acquisition module so that the first VGA signal amplifier of the signal acquisition module adjusts the gain of the first VGA signal amplifier according to the gain adjustment command and the preset gain adjustment step size. Obtain the updated feedback signal after the first VGA signal amplifier adjusts the gain, and determine whether the updated feedback signal meets the preset conditions.

3. The method according to claim 1, characterized in that, The feedback signal is acquired through the signal acquisition module, specifically including: Determine the frequency value and corresponding signal amplitude value corresponding to the frequency point to be tested; wherein, the frequency point to be tested corresponds to at least one frequency value of the transmission signal frequency of the cable under test; The frequency value corresponding to the frequency point under test is sent to the Direct Digital Synthesizer (DDS) in the signal acquisition module, and the signal amplitude value is sent to the second VGA signal amplifier to generate a test signal corresponding to the frequency point under test. The test signal is then input to the other end of the cable under test. The analog-to-digital converter (ADC) in the signal acquisition module acquires the feedback signal from one end of the cable under test, which is excited by the test signal.

4. The method according to claim 3, characterized in that, The method further includes: The field-programmable gate array (FPGA) of the signal acquisition module sends clock synchronization signals to the DDS and the ADC.

5. The method according to claim 1, characterized in that, The amplitude of the differential-mode signal is input into a preset formula to determine the longitudinal balance of the frequency point to be measured, specifically including: Determine the signal amplitude value of the test signal; The longitudinal balance of the cable under test is determined based on the signal amplitude value, the differential mode signal amplitude, and a preset formula.

6. The method according to claim 1, characterized in that, The test signal is the common-mode voltage input to one end of the cable under test.

7. The method according to claim 1, characterized in that, The sampling periods of the sampling point sequence are consecutive sampling periods.

8. A line detection device for line balancing, characterized in that, The apparatus is capable of performing a line detection method for line balancing as described in any one of claims 1-7; the apparatus comprises: The first acquisition module is used by the controller to acquire the frequency point to be tested of the cable under test; The second acquisition module is used to acquire a feedback signal through the signal acquisition module; the feedback signal is a signal synchronously acquired from one end of the cable under test that is input with the test signal. The determining module is used to determine the differential mode signal amplitude corresponding to a preset sampling point sequence when the feedback signal meets preset conditions; wherein, the preset conditions are that the signal amplitude value of the feedback signal is greater than a first preset value and / or the signal gain value of the feedback signal is greater than a second preset value; the sampling point sequence includes the signal values ​​of corresponding sampling points of multiple sampling periods; The transmission module is used to input the amplitude of the differential mode signal into a preset formula, determine the longitudinal balance of the frequency point to be measured, and send the longitudinal balance to the user terminal.

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