Semiconductor structure and method of forming the same

Abstract

The present disclosure relates to a semiconductor structure and a method of forming the same. The semiconductor structure includes a substrate, a memory structure on the substrate, including a transistor, the transistor including an active region and a gate structure, the active region including a channel region and first and second source-drain regions on opposite sides of the channel region along a first direction, the channel region being distributed around a periphery of the gate structure, the first direction being parallel to a top surface of the substrate, a word line including at least a word line main portion, the word line main portion extending along a second direction and being electrically connected to the gate structure, the second direction being perpendicular to the top surface of the substrate, and a bit line including at least a bit line main portion, the bit line main portion extending along the second direction and being electrically connected to the first source-drain region, and the first source-drain region being distributed around a periphery of the bit line main portion. The present disclosure improves the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor device in computers and other electronic devices. It consists of multiple memory cells, each of which typically includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line, the source is electrically connected to the bit line, and the drain is electrically connected to the capacitor. The word line voltage on the word line can control the transistor to turn on and off, thereby allowing data information stored in the capacitor to be read or written to the capacitor via the bit line.

[0003] DRAM and other semiconductor structures typically employ buried word line or horizontal word line structures, electrically connecting the bit lines to the transistor faces. In pursuit of faster response times, lower power consumption, and higher storage density, the size of DRAM and other semiconductor structures continues to shrink. This increases the manufacturing difficulty of buried or horizontal word line structures, leading to increased contact resistance between the bit lines and transistors, and consequently, a decline in the electrical performance of the semiconductor structure.

[0004] Therefore, how to improve the electrical performance of semiconductor structures while simplifying the semiconductor structure manufacturing process is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] This disclosure provides semiconductor structures and methods for forming the same in some embodiments, which are used to simplify the manufacturing process of the semiconductor structures and improve their electrical performance.

[0006] According to some embodiments, this disclosure provides a semiconductor structure, including:

[0007] Substrate;

[0008] A memory structure located on the substrate includes a transistor, the transistor including an active region and a gate structure, the active region including a channel region and a first source / drain region and a second source / drain region located on opposite sides of the channel region along a first direction, the channel region surrounding the outer periphery of the gate structure, the first direction being parallel to the top surface of the substrate;

[0009] A word line, including at least a word line body portion, the word line body portion extending along a second direction and electrically connected to the gate structure, the second direction being perpendicular to the top surface of the substrate;

[0010] The bit line includes at least a bit line body portion, which extends along the second direction and is electrically connected to the first source / drain region, and the first source / drain region surrounds the outer periphery of the bit line body portion.

[0011] In some embodiments, two of the storage structures are arranged along the first direction, and the two storage structures arranged along the first direction share a first source-drain region, and the two channel regions are located on opposite sides of the shared first source-drain region;

[0012] The first source / drain region shared by the two memory structures arranged along the first direction surrounds the outer periphery of one of the bit line bodies.

[0013] In some embodiments, the storage structure includes a plurality of transistors spaced apart along the second direction;

[0014] The word line body portion is electrically connected to the gate structure of one of the plurality of transistors arranged at intervals along the second direction within the memory structure;

[0015] The bit line body portion is electrically connected to the first source / drain regions of a plurality of transistors spaced apart along the second direction within the memory structure, and the first source / drain regions of the plurality of transistors spaced apart along the second direction within the memory structure surround the outer periphery of the bit line body portion.

[0016] In some embodiments, the storage structure further includes a capacitor, the capacitor comprising:

[0017] The lower electrode layer continuously covers at least a portion of the surface of the second source / drain region of a plurality of transistors spaced apart along the second direction;

[0018] A dielectric layer that covers the entire surface of the lower electrode layer;

[0019] The upper electrode layer covers the entire surface of the dielectric layer.

[0020] In some embodiments, it also includes:

[0021] A drain isolation layer is located between adjacent transistors along the second direction and covers at least a portion of the surface of the second source-drain region in the active region;

[0022] The lower electrode layer continuously covers the top surface of the second source / drain region, the bottom surface of the second source / drain region, the side surface of the second source / drain region, and the side surface of the drain isolation layer.

[0023] In some embodiments, a plurality of the memory structures are spaced apart along a third direction, the third direction being parallel to the top surface of the substrate, and the first direction intersecting the third direction;

[0024] The word line includes a plurality of word line main bodies spaced apart along the third direction, and word line extensions extending along the third direction and electrically connected to the plurality of word line main bodies spaced apart along the third direction. The plurality of word line main bodies included in the word line are electrically connected one-to-one with the gate structures in the plurality of memory structures spaced apart along the third direction.

[0025] In some embodiments, the bit line further includes:

[0026] The bit line extension is located above the bit line body and is electrically connected to the bit line body. The bit line extension extends along the first direction, and the width of the bit line extension along the third direction is greater than or equal to the width of the bit line body along the third direction. The third direction is parallel to the top surface of the substrate, and the first direction intersects the third direction.

[0027] In some embodiments, the bit line further includes:

[0028] The bit line contact portion extends along the second direction, and the two opposite ends of the bit line contact portion along the second direction are respectively electrically connected to the bit line body portion and the bit line extension portion, and the width of the bit line contact portion along the first direction is greater than or equal to the width of the bit line body portion along the first direction.

[0029] In some embodiments, the channel region, the first source / drain region, and the second source / drain region include the same type of doped ions, and the ion doping concentration of the first source / drain region and the ion doping concentration of the second source / drain region are both greater than the ion doping concentration of the channel region.

[0030] According to other embodiments, this disclosure also provides a method for forming a semiconductor structure, comprising the following steps:

[0031] Provide substrate;

[0032] A semiconductor layer is formed on the substrate, the semiconductor layer including an active region, the active region including a channel region, and a first source / drain region and a second source / drain region located on opposite sides of the channel region along a first direction, the first direction being perpendicular to the top surface of the substrate;

[0033] A gate structure, word lines, and bit lines are formed on the substrate. The channel region surrounds the outer periphery of the gate structure. The word line includes at least a word line body portion, which extends along a second direction and is electrically connected to the gate structure. The bit line includes at least a bit line body portion, which extends along the second direction and is electrically connected to the first source / drain region. The first source / drain region surrounds the outer periphery of the bit line body portion. The second direction is perpendicular to the top surface of the substrate.

[0034] In some embodiments, the plurality of semiconductor layers are spaced apart along the second direction; the step of forming a gate structure, word line, and bit line on the substrate includes:

[0035] A first trench is formed that extends through the first source / drain regions of the first semiconductor layers along the second direction;

[0036] The bit line body portion is formed in the first trench, and the bit line body portion is electrically connected to the first source / drain regions of the plurality of semiconductor layers spaced apart along the second direction.

[0037] A second trench is formed that extends along the second direction through the channel region in the plurality of semiconductor layers;

[0038] The word line body portion and the gate structure are formed in the second trench. The gate structure penetrates the channel region in the semiconductor layer along the second direction. The word line body portion is connected to the gate structure adjacent along the second direction.

[0039] In some embodiments, the semiconductor layer includes a plurality of active regions spaced apart along a third direction, and a plurality of word line bodies penetrate the channel regions of the plurality of active regions one by one along the second direction; the third direction is parallel to the top surface of the substrate, and the first direction intersects the third direction; after forming the word line bodies and the gate structure in the second trench, the method further includes the following steps:

[0040] A character line extension is formed above the character line body portion. The character line extension extends along the third direction and is electrically connected to a plurality of character line bodies arranged at intervals along the third direction. The character line includes the character line body portion and the character line extension portion.

[0041] In some embodiments, the step of forming a gate structure, word line, and bit line on the substrate further includes:

[0042] A bit line extension portion electrically connected to the bit line body portion is formed above the bit line body portion. The bit line extension portion extends along the first direction, and the width of the bit line extension portion along the third direction is greater than or equal to the width of the bit line body portion along the third direction. The bit line includes the bit line body portion and the bit line extension portion. The third direction is parallel to the top surface of the substrate, and the first direction intersects the third direction.

[0043] In some embodiments, the step of forming a bit line extension portion electrically connected to the bit line body portion above the bit line body portion includes:

[0044] A bit line contact portion extending in the second direction is formed on the top surface of the bit line body portion. The bit line contact portion is electrically connected to the bit line body portion. In the second direction, the top surface of the bit line contact portion is located above the top surface of the word line extension portion. The width of the bit line contact portion in the first direction is greater than or equal to the width of the bit line body portion in the first direction.

[0045] The bit line extension is formed on the top surface of the bit line contact portion, and the bit line extension is electrically connected to the bit line contact portion.

[0046] In some embodiments, after forming the gate structure, word line, and bit line on the substrate, the method further includes:

[0047] A lower electrode layer is formed to continuously cover at least a portion of the surface of the second source / drain regions in the plurality of active regions spaced apart along the second direction, respectively.

[0048] A dielectric layer is formed covering the entire surface of the lower electrode layer;

[0049] An upper electrode layer is formed covering the entire surface of the dielectric layer to form a capacitor comprising the lower electrode layer, the dielectric layer, and the upper electrode layer.

[0050] The semiconductor structure and its formation method provided in some embodiments of this disclosure improve the electrical performance of the semiconductor structure by forming a channel-around structure by surrounding the outer periphery of the gate structure with a channel region, and forming a first source-drain region-around structure by surrounding the outer periphery of the bit line body portion with a first source-drain region. Furthermore, the word line body portion electrically connected to the gate structure within the memory structure and the bit line body portion electrically connected to the first source-drain region within the memory structure extend in the same direction (e.g., both extending in a direction perpendicular to the top surface of the substrate), which simplifies the semiconductor structure manufacturing process and reduces the manufacturing cost. Moreover, the bit line body portion is led out through a bit line extension portion, and the word line body portion is subsequently led out through a word line extension portion, which improves the internal space utilization of the semiconductor structure and further simplifies the semiconductor structure manufacturing process. Other embodiments of this disclosure provide a memory structure including multiple parallel transistors, which increases the current inside the memory structure, thereby further improving the electrical performance of the semiconductor structure. Attached Figure Description

[0051] Appendix Figure 1 This is a three-dimensional schematic diagram of a semiconductor structure in one embodiment of a specific implementation of this disclosure;

[0052] Appendix Figure 2 This is a three-dimensional schematic diagram of a semiconductor structure in another embodiment of the specific implementation of this disclosure;

[0053] Appendix Figure 3 It is attached Figure 2 The diagram shows a top view of the semiconductor structure.

[0054] Appendix Figure 4 It is attached Figure 3 Cross-sectional diagrams at positions aa, bb, and cc;

[0055] Appendix Figure 5 This is a schematic diagram of the capacitor structure in a specific embodiment of this disclosure;

[0056] Appendix Figure 6 This is a flowchart of a method for forming a semiconductor structure according to a specific embodiment of this disclosure;

[0057] Appendix Figure 7 -Appendix Figure 12 This is a schematic diagram of the main process structure in the formation of the semiconductor structure according to the specific embodiments of this disclosure. Detailed Implementation

[0058] The specific embodiments of the semiconductor structure and its formation method provided in this disclosure will be described in detail below with reference to the accompanying drawings.

[0059] This specific embodiment provides a semiconductor structure, with appended... Figure 1This is a three-dimensional schematic diagram of a semiconductor structure according to one embodiment of the present disclosure, with attached... Figure 2 This is a three-dimensional schematic diagram of a semiconductor structure in another embodiment of the specific implementation of this disclosure, with attached... Figure 3 It is attached Figure 2 The diagram shows a top view of the semiconductor structure, with accompanying illustrations. Figure 4 It is attached Figure 3 Cross-sectional diagrams at positions aa, bb, and cc. (See diagram.) Figures 1-4 As shown, the semiconductor structure includes:

[0060] Substrate 40;

[0061] The memory structure is located on the substrate 40 and includes a transistor. The transistor includes an active region and a gate structure. The active region includes a channel region 11 and a first source / drain region 10 and a second source / drain region 12 located on opposite sides of the channel region 11 along a first direction D1. The channel region 11 surrounds the outer periphery of the gate structure. The first direction D1 is parallel to the top surface of the substrate 40.

[0062] The word line includes at least a word line body portion 13, which extends along a second direction D2 and is electrically connected to the gate structure. The second direction D2 is perpendicular to the top surface of the substrate 40.

[0063] The bit line includes at least a bit line body portion 15, which extends along the second direction D2 and is electrically connected to a first source / drain region 10, and the first source / drain region 10 surrounds the outer periphery of the bit line body portion 15.

[0064] The semiconductor structure in this specific embodiment can be, but is not limited to, DRAM. This specific embodiment uses DRAM as an example for illustration. Specifically, the substrate 40 can be, but is not limited to, a silicon substrate. This specific embodiment uses silicon as an example for illustration. In other embodiments, the substrate 40 can also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide, or SOI. The substrate 40 is used to support the device structure on it. The top surface of the substrate 40 refers to the surface of the substrate 40 facing the memory structure. The substrate 40 can include multiple memory structures arranged in a two-dimensional or three-dimensional array. This specific embodiment uses one memory structure as an example for illustration. The first source / drain region 10 is used as one of the source and drain regions of a transistor, and the second source / drain region 12 is used as the other of the source and drain regions of a transistor. The gate structure includes a gate conductive structure and a gate dielectric structure. The channel region 11 is separated from the gate conductive structure by the gate dielectric structure, and the gate dielectric structure covers at least the area of ​​the channel region directly opposite the gate conductive structure.

[0065] In this specific embodiment, both the word line main body 13 and the bit line main body 15 extend along the second direction D2. The channel region 11 in the transistor surrounds the outer periphery of the gate structure, and the first source / drain region 10 surrounds the outer periphery of the bit line main body 15. This allows the semiconductor structure to simultaneously possess both a channel-encircling structure and a first source / drain region-encircling structure. This not only increases the overlap area between the channel region 11 and the gate structure and the contact area between the first source / drain region 10 and the bit line main body 15, thereby improving the electrical performance of the semiconductor structure, but also eliminates the need to form a buried bit line structure and a single horizontal word line structure through complex manufacturing processes. This simplifies the semiconductor structure manufacturing process and reduces the manufacturing cost of the semiconductor structure.

[0066] In some embodiments, two storage structures are arranged along a first direction D1, and the two storage structures arranged along the first direction D1 share a first source-drain region 10, and two channel regions 11 are located on opposite sides of the shared first source-drain region 10.

[0067] The common first source / drain region 10 in the two memory structures arranged along the first direction D1 surrounds the outer periphery of the bit line body portion 15.

[0068] Specifically, such as Figure 1 and Figure 2 As shown, the semiconductor structure includes a semiconductor layer 17 located above the substrate 40. The semiconductor layer 17 includes two active regions arranged along a first direction D1. Each active region includes a channel region 11 and a first source / drain region 10 and a second source / drain region 12 located on opposite sides of the channel region 11 along the first direction D1. The two active regions share the first source / drain region 10. The first source / drain region 10 shared by the two memory structures arranged along the first direction D1 surrounds the outer periphery of the bit line body portion 15, that is, the bit line body portion 15 is electrically connected to the two memory structures arranged along the first direction D1, thereby further improving the integration density of the semiconductor structure.

[0069] In some embodiments, the storage structure includes a plurality of transistors spaced apart along a second direction D2;

[0070] The word line body 15 is electrically connected to the gate structure of a plurality of transistors arranged at intervals along the second direction D2 within the memory structure.

[0071] The bit line body portion 15 is electrically connected to the first source / drain region 10 of a plurality of transistors arranged at intervals along the second direction D2 in the memory structure, and the first source / drain region 10 of the plurality of transistors arranged at intervals along the second direction D2 in the memory structure surrounds the outer periphery of a bit line body portion 15.

[0072] For example, such as Figures 2-4As shown, the memory structure includes multiple transistors arranged at intervals along the second direction D2, and the multiple transistors in the same memory structure are electrically connected to the same bit line body 15 and the same word line body 13, so that the memory structure includes multiple transistors connected in parallel, thereby increasing the current inside the memory structure and further improving the electrical performance of the semiconductor structure.

[0073] In one example, such as Figures 2-4 As shown, the semiconductor structure includes multiple semiconductor layers 17 arranged at intervals along the second direction D2. Each semiconductor layer includes two active regions arranged along the first direction D1, and the two active regions share a first source-drain region 10. This allows two adjacent memory structures along the first direction D1 to each include multiple transistors connected in parallel, so that the current flowing through the two adjacent memory structures along the first direction D1 is the same after being turned on, thereby further improving the electrical performance of the semiconductor structure.

[0074] Appendix Figure 5 This is a schematic diagram of the capacitor structure in a specific embodiment of this disclosure. In some embodiments, such as Figure 5 As shown, the storage structure also includes capacitors, which include:

[0075] The lower electrode layer 50 continuously covers at least a portion of the surface of the second source / drain regions 12 of a plurality of transistors arranged at intervals along the second direction D2;

[0076] Dielectric layer 51 covers the entire surface of lower electrode layer 50;

[0077] The upper electrode layer 52 covers the entire surface of the dielectric layer 51.

[0078] In some embodiments, the semiconductor structure further includes:

[0079] The drain isolation layer 32 is located between adjacent transistors along the second direction D2 and covers at least a portion of the surface of the second source-drain region 12 in the active region.

[0080] The lower electrode layer 50 continuously covers the top surface of the second source / drain region 12, the bottom surface of the second source / drain region 12, the side surface of the second source / drain region 12, and the side surface of the drain isolation layer 32.

[0081] Drain isolation layer 32 is used to isolate word lines and capacitors. For example, such as Figure 5The lower electrode layer 50 continuously covers a portion of the surface of the second source / drain regions 12 of all transistors within the memory structure and covers the sidewalls of the drain isolation layer 32. The dielectric 51 continuously covers the entire surface of the lower electrode layer 50, and the upper electrode layer 52 continuously covers the entire surface of the dielectric layer 51. Only one capacitor is provided in the memory structure, and the capacitor is electrically connected to a portion of the top, bottom, and side surfaces of the second source / drain regions of all transistors in the memory structure. On the one hand, this increases the surface area of ​​the capacitor (including the surface area of ​​the lower electrode layer 50, the dielectric layer 51, and the upper electrode layer 52), thereby increasing the capacitance of the capacitor within the memory structure. On the other hand, the length of the capacitor along the first direction D1 can be relatively shortened (i.e., the horizontal length of the capacitor is reduced), which helps to reduce the size of the memory structure and the semiconductor structure. Furthermore, multiple parallel transistors within the memory structure are electrically connected to the same capacitor, eliminating the need to form multiple independent capacitors spaced apart along the second direction D2 within the memory structure, simplifying the semiconductor structure manufacturing process and reducing the manufacturing cost.

[0082] In some embodiments, a plurality of memory structures are arranged at intervals along a third direction D3, the third direction D3 being parallel to the top surface of the substrate 40, and the first direction D1 intersecting the third direction D3.

[0083] The word line includes a plurality of word line main bodies 13 spaced apart along a third direction D3, and a word line extension 14 extending along a third direction D3 and electrically connected to the plurality of word line main bodies 13 spaced apart along a third direction D3. The plurality of word line main bodies 13 included in the word line are electrically connected to the gate structures in a plurality of memory structures spaced apart along a third direction D3.

[0084] Specifically, the semiconductor structure includes multiple memory structures spaced apart along a third direction D3, and a memory region isolation layer 31 located between adjacent memory structures. The memory region isolation layer 31 not only isolates adjacent memory structures along the third direction D3 but also supports the semiconductor structure. In one example, the material of the memory region isolation layer 31 can be a nitride material (e.g., silicon nitride). A word line includes multiple word line body portions 13 spaced apart along a third direction D3. Each word line body portion 13 within the same word line is electrically connected to a gate structure in one of the multiple memory structures spaced apart along the third direction D3. A word line extension portion 14 is located on the top surface of the word line body portion 13 and extends along the third direction D3. The word line extension portion 14 is electrically connected to all word line body portions 13 within the same word line. On the one hand, this allows control signals to be transmitted simultaneously to multiple memory structures through a single word line extension portion 14, simplifying the control operation of the semiconductor structure; on the other hand, it also helps simplify the specific structure of the semiconductor structure and reduce the manufacturing difficulty of the semiconductor structure.

[0085] In some embodiments, the bit line further includes:

[0086] Bit line extension 16 is located above and electrically connected to bit line body 15. Bit line extension 16 extends along a first direction D1, and the width of bit line extension 16 along a third direction D3 is greater than or equal to the width of bit line body 15 along a third direction D3. The third direction D3 is parallel to the top surface of substrate 40, and the first direction D1 intersects the third direction D3.

[0087] In some embodiments, the bit line further includes:

[0088] The bit line contact portion 30 extends along the second direction D2. The two opposite ends of the bit line contact portion 30 along the second direction D2 are respectively connected to the bit line body portion 15 and the bit line extension portion 16. The width of the bit line contact portion 30 along the first direction D1 is greater than or equal to the width of the bit line body portion 15 along the first direction D1.

[0089] Specifically, the semiconductor structure includes multiple memory structures spaced apart along a third direction D3, and multiple bit lines spaced apart along the third direction D3, with each bit line corresponding to one of the multiple memory structures spaced apart along the third direction D3 and electrically connected. Each bit line includes a bit line body portion 15, a bit line contact portion 30 located on the top surface of the bit line body portion 15 and electrically connected to the bit line body portion 15, and a bit line extension portion 16 located on the top surface of the bit line contact portion 30 and electrically connected to the bit line contact portion 30. In one example, along the second direction D2, the top surface of the bit line contact portion 30 is located above the top surface of the word line extension portion 14 to increase the distance between the bit line extension portion 16 and the word line extension portion 14 and reduce the parasitic capacitance effect between the bit line extension portion 16 and the word line extension portion 14. In this specific embodiment, the bit line extension 16 is disposed above the memory structure, and bit line signals are transmitted to the memory structure through the bit line extension 16. On the one hand, the size of the semiconductor structure can be reduced and the integration of the semiconductor structure can be improved; on the other hand, the circuit routing structure between the peripheral control structure and the bit line can be simplified, thereby reducing the manufacturing process difficulty of the semiconductor structure.

[0090] In some embodiments, the channel region 11, the first source / drain region 10, and the second source / drain region 12 contain the same type of doped ions, and the ion doping concentration of the first source / drain region 10 and the ion doping concentration of the second source / drain region 12 are both greater than the ion doping concentration of the channel region 11.

[0091] In other embodiments, the active region is made of an oxide semiconductor material.

[0092] In one example, the transistors in the memory structure are junctionless transistors. For instance, the channel region 11, the first source / drain region 10, and the second source / drain region 12 in the active region all contain N-type doped ions, and both the first source / drain region 10 and the second source / drain region 12 are heavily doped, while the channel region 11 is lightly doped. In another example, the active region is made of an oxide semiconductor material, wherein the oxide semiconductor material is any one or a combination of two or more of In₂O₃ (indium oxide), ZnO (zinc oxide), IZO (indium zinc oxide), IGZO (indium gallium zinc oxide), IZTO (indium tin zinc oxide), and ZnON (zinc oxynitride). Preferably, the active region is made of IGZO.

[0093] This specific embodiment also provides a method for forming a semiconductor structure, attached... Figure 6 This is a flowchart illustrating the method for forming a semiconductor structure according to a specific embodiment of this disclosure, with appended... Figure 7 - Appendix Figure 12 This is a schematic diagram of the main process structure in forming the semiconductor structure according to a specific embodiment of this disclosure. The semiconductor structure formed in this specific embodiment is as follows: Figures 2-5 As shown. Figures 2-12 As shown, the method for forming a semiconductor structure includes the following steps:

[0094] Step S61, provide substrate 40;

[0095] Step S62: Form a semiconductor layer 17 on the substrate 40. The semiconductor layer 17 includes an active region, which includes a channel region 11 and a first source / drain region 10 and a second source / drain region 12 located on opposite sides of the channel region 11 along a first direction D1. The first direction D1 is perpendicular to the top surface of the substrate 40.

[0096] In step S63, a gate structure, word lines, and bit lines are formed on the substrate 40. The channel region 11 surrounds the outer periphery of the gate structure. The word line includes at least a word line body portion 13, which extends along the second direction D2 and is electrically connected to the gate structure. The bit line includes at least a bit line body portion 15, which extends along the second direction D2 and is electrically connected to the first source / drain region 10. The first source / drain region 10 surrounds the outer periphery of the bit line body portion 15. The second direction D2 is perpendicular to the top surface of the substrate 40.

[0097] In some embodiments, a plurality of semiconductor layers 17 are arranged at intervals along a second direction D2; the step of forming a gate structure, word line, and bit line on the substrate 40 includes:

[0098] A first trench is formed that penetrates multiple semiconductor layers 17 along the second direction D2 to form a first source / drain region 10.

[0099] A bit line body portion 15 is formed within the first trench. The bit line body portion 15 is electrically connected to the first source / drain regions 10 of a plurality of semiconductor layers 17 spaced apart along the second direction D2. Figure 2 and Figure 8 As shown, where, Figure 8 (a) in the diagram is a top view of the structure. Figure 8 (b) in the diagram is a cross-sectional view of position aa in (a). Figure 8 (c) in the diagram is a cross-sectional view of position bb in (a). Figure 8 (d) in the diagram is a cross-sectional view of position cc in (a);

[0100] A second trench is formed that penetrates the channel region 11 in the plurality of semiconductor layers 17 along the second direction D2;

[0101] A word line body portion 13 and a gate structure are formed within the second trench. The gate structure penetrates the channel region 11 in the semiconductor layer 17 along the second direction D2. The word line body portion 13 connects to adjacent gate structures along the second direction D2. Figure 2 and Figure 9 As shown, where, Figure 9 (a) in the diagram is a top view of the structure. Figure 9 (b) in the diagram is a cross-sectional view of position aa in (a). Figure 9 (c) in the diagram is a cross-sectional view of position bb in (a). Figure 9 (d) in the diagram is a cross-sectional view of position cc in (a).

[0102] Specifically, an epitaxial growth process can be used to alternately grow a semiconductor layer 17 and an interlayer isolation layer 42 on the top surface of the substrate 40 to form a stacked layer. In one example, the semiconductor layer 17 can be made of Si, and the interlayer isolation layer 42 can be made of SiGe. Then, the stacked layer is etched to form a plurality of memory region isolation trenches spaced apart along a third direction D3. The memory region isolation trenches divide the stacked layer into a plurality of memory regions spaced apart along a third direction, wherein the third direction D3 is parallel to the top surface of the substrate 40, and the first direction D1 intersects the third direction D3. An insulating dielectric material such as a nitride (e.g., silicon nitride) is filled into the memory region isolation trenches to form a memory region isolation layer 31, such as... Figure 3 , Figure 4 and Figure 7 As shown, where, Figure 7 (a) in the diagram is a top view of the structure. Figure 7 (b) in the diagram is a cross-sectional view of position aa in (a). Figure 7 (c) in the diagram is a cross-sectional view of position bb in (a). Figure 7 (d) in the diagram is a cross-sectional view of position cc in (a).

[0103] The stacked layers are etched to form a first trench extending along the second direction D2 and at least penetrating the first source / drain regions 10 of the plurality of semiconductor layers 17 spaced apart along the second direction D2. A conductive material such as TiN, W, Ti, Ru, or Mo is filled into the first trench to form a bit line body 15, such as... Figures 2-4 ,as well as Figure 8 As shown. Multiple bit line bodies 15 are spaced apart along the third direction D3, and each bit line body 15 is electrically connected to a first source / drain region 10 within a plurality of memory regions. Next, the stacked layers are etched again to form a second trench extending along the second direction D2 and at least penetrating the channel regions 11 of the plurality of semiconductor layers 17 spaced apart along the second direction D2. After forming a gate dielectric structure on the inner wall of the second trench, conductive materials such as TiN, W, Ti, Ru, or Mo are filled into the second trench to form a gate conductive structure covering the surface of the gate dielectric structure and word line bodies 13 continuously electrically connected to the plurality of gate conductive structures spaced apart along the second direction D2. The gate dielectric structure and the gate conductive structure together serve as the gate structure, as shown. Figures 2-4 ,as well as Figure 9 As shown.

[0104] In some embodiments, the semiconductor layer 17 includes a plurality of active regions spaced apart along a third direction D3, and a plurality of word line bodies 13 penetrate the channel regions 11 in the plurality of active regions along a second direction D2; the third direction D3 is parallel to the top surface of the substrate 40, and the first direction D1 intersects the third direction D3; after forming the word line bodies 13 and the gate structure in the second trench, the following steps are further included:

[0105] A character line extension 14 is formed above the character line body portion 13. The character line extension 14 extends along a third direction D3 and is electrically connected to a plurality of character line body portions 13 arranged at intervals along the third direction D3. The character line includes the character line body portion 13 and the character line extension 14.

[0106] Specifically, after forming the word line body 13, a drain isolation layer 32 is formed. The drain isolation layer 32 is located between adjacent semiconductor layers 17 along the second direction D2, and covers the channel region 11 and the second source / drain region 12 in the active region, such as... Figure 10 As shown, where, Figure 10 (a) in the diagram is a top view of the structure. Figure 10 (b) in the diagram is a cross-sectional view of position aa in (a). Figure 10 (c) in the diagram is a cross-sectional view of position bb in (a). Figure 10(d) in the diagram is a cross-sectional view of the cc position in (a). In one example, the material of the drain isolation layer 32 can be, but is not limited to, a nitride material (e.g., silicon nitride). The drain isolation layer 32 serves two purposes: firstly, to isolate word lines and subsequently pre-formed capacitors, and secondly, to support the stacked layers and prevent them from tipping over or collapsing during subsequent processes.

[0107] Subsequently, a first dielectric layer 44 is deposited on the top surface of the stacked layers, and the first dielectric layer 44 is etched to form a word line extension trench exposing the top surface of the word line body portion 13. A conductive material is filled into the word line extension trench to form word line extension portions 14 extending along a third direction D3 and electrically connected to a plurality of word line body portions 13 spaced apart along the third direction D3, such as... Figures 2-4 ,as well as Figure 11 As shown, where, Figure 11 (a) in the diagram is a top view of the structure. Figure 11 (b) in the diagram is a cross-sectional view of position aa in (a). Figure 11 (c) in the diagram is a cross-sectional view of position bb in (a). Figure 11 (d) in the diagram is a cross-sectional view of the position dd in (a).

[0108] In some embodiments, the step of forming a gate structure, word line, and bit line on a substrate further includes:

[0109] A bit line extension 16 electrically connected to the bit line body 15 is formed above the bit line body 15. The bit line extension 16 extends along a first direction D1, and the width of the bit line extension 16 along a third direction D3 is greater than or equal to the width of the bit line body 15 along the third direction D3. The bit line includes the bit line body 15 and the bit line extension 16. The third direction D3 is parallel to the top surface of the substrate 40, and the first direction D1 intersects the third direction D3.

[0110] In some embodiments, the step of forming a bit line extension 16 electrically connected to the bit line body 15 above the bit line body 15 includes:

[0111] A bit line contact portion 30 extending along the second direction D2 is formed on the top surface of the bit line body portion 15. The bit line contact portion 30 is electrically connected to the bit line body portion 15. Along the second direction D2, the top surface of the bit line contact portion 30 is located above the top surface of the word line extension portion 14. The width of the bit line contact portion 30 along the first direction D1 is greater than or equal to the width of the bit line body portion 15 along the first direction D1.

[0112] A bit line extension 16 is formed on the top surface of the bit line contact portion 30, and the bit line extension 16 is electrically connected to the bit line contact portion 30, such as... Figure 12 As shown, where, Figure 12 (a) in the diagram is a top view of the structure. Figure 12 (b) in the diagram is a cross-sectional view of position aa in (a). Figure 12 (c) in the diagram is a cross-sectional view of position bb in (a). Figure 12 (d) in the diagram is a cross-sectional view of position cc in (a).

[0113] In some embodiments, after forming the gate structure, word line, and bit line on the substrate, the method further includes:

[0114] A lower electrode layer 50 is formed to continuously cover at least a portion of the surface of the second source / drain region 12 in a plurality of active regions spaced apart along the second direction D2.

[0115] A dielectric layer 51 is formed covering the entire surface of the lower electrode layer 50;

[0116] An upper electrode layer 52 is formed covering the entire surface of the dielectric layer 51 to form a capacitor including a lower electrode layer 50, a dielectric layer 51, and an upper electrode layer 52, such as... Figure 5 As shown.

[0117] For example, the substrate 40 includes a plurality of stacked layers (semiconductor layers including a plurality of semiconductor layers 17 spaced apart along a first direction D1) spaced apart along a second direction D2. After forming a gate structure, word line, and bit line in each stacked layer, second source / drain regions 12 of two adjacent stacked layers along the first direction D1 are distributed opposite to each other. Next, a lower electrode material is deposited such that the lower electrode material continuously covers at least a portion of the surface of the plurality of second source / drain regions 12 spaced apart along the second direction D2 in two adjacent stacked layers along the first direction D1. Subsequently, a dielectric material is formed covering the entire surface of the lower electrode material, and an upper electrode material is formed covering the entire surface of the dielectric material and filling the gap between two adjacent stacked layers. Next, the lower electrode material, dielectric material, and upper electrode material are etched along the second direction D2 to form a partition trench that penetrates the lower electrode material, dielectric material, and upper electrode material along the second direction D2, forming two capacitors separated by the partition trench. Each capacitor includes a lower electrode layer 50 covering at least a portion of the surface of a plurality of active regions 12 arranged at intervals along the second direction D2 in a stacked layer, a dielectric layer 51 covering the entire surface of the lower electrode layer 50, and an upper electrode layer 52 covering the entire surface of the dielectric layer 51.

[0118] The semiconductor structure and its formation method provided in some embodiments of this specific embodiment improve the electrical performance of the semiconductor structure by forming a channel-around structure by surrounding the outer periphery of the gate structure with the channel region, and forming a first source-drain region-around structure by surrounding the outer periphery of the bit line body portion with the first source-drain region. Furthermore, the word line body portion electrically connected to the gate structure within the memory structure and the bit line body portion electrically connected to the first source-drain region within the memory structure extend in the same direction (e.g., both extending in a direction perpendicular to the top surface of the substrate), which simplifies the semiconductor structure manufacturing process and reduces the manufacturing cost. Moreover, the bit line body portion is led out through a bit line extension portion, and the word line body portion is subsequently led out through a word line extension portion, which improves the internal space utilization of the semiconductor structure and further simplifies the semiconductor structure manufacturing process. Other embodiments of this specific embodiment provide a memory structure including multiple parallel transistors, which increases the current inside the memory structure, thereby further improving the electrical performance of the semiconductor structure.

[0119] The above are merely preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of this disclosure, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; A memory structure located on the substrate includes a plurality of transistors. Each transistor includes an active region and a gate structure. The active region includes a channel region and a first source-drain region and a second source-drain region located on opposite sides of the channel region along a first direction. The channel region surrounds the outer periphery of the gate structure. The first direction is parallel to the top surface of the substrate. The plurality of transistors are arranged at intervals along a second direction. A word line includes at least a word line body portion, the word line body portion extending along a second direction, and the word line body portion being electrically connected to the gate structure of a plurality of transistors spaced apart along the second direction within the memory structure, the second direction being perpendicular to the top surface of the substrate; The bit line includes at least a bit line body portion, which extends along the second direction and is electrically connected to the first source / drain region, and the first source / drain region surrounds the outer periphery of the bit line body portion.

2. The semiconductor structure according to claim 1, characterized in that, The two storage structures are arranged along the first direction, and the two storage structures arranged along the first direction share a first source-drain region, and the two channel regions are located on opposite sides of the shared first source-drain region; The first source / drain region shared by the two memory structures arranged along the first direction surrounds the outer periphery of the bit line body.

3. The semiconductor structure according to claim 1, characterized in that, The bit line body portion is electrically connected to the first source / drain regions of a plurality of transistors spaced apart along the second direction within the memory structure, and the first source / drain regions of the plurality of transistors spaced apart along the second direction within the memory structure surround the outer periphery of one bit line body portion.

4. The semiconductor structure according to claim 3, characterized in that, The storage structure further includes a capacitor, the capacitor comprising: The lower electrode layer continuously covers at least a portion of the surface of the second source / drain region of a plurality of transistors spaced apart along the second direction; A dielectric layer that covers the entire surface of the lower electrode layer; The upper electrode layer covers the entire surface of the dielectric layer.

5. The semiconductor structure according to claim 4, characterized in that, Also includes: A drain isolation layer is located between adjacent transistors along the second direction and covers at least a portion of the surface of the second source-drain region in the active region; The lower electrode layer continuously covers the top surface of the second source / drain region, the bottom surface of the second source / drain region, the side surface of the second source / drain region, and the side surface of the drain isolation layer.

6. The semiconductor structure according to claim 1, characterized in that, The plurality of the memory structures are arranged at intervals along a third direction, the third direction being parallel to the top surface of the substrate, and the first direction intersecting the third direction; The word line includes a plurality of word line main bodies spaced apart along the third direction, and word line extensions extending along the third direction and electrically connected to the plurality of word line main bodies spaced apart along the third direction. The plurality of word line main bodies included in the word line are electrically connected one-to-one with the gate structures in the plurality of memory structures spaced apart along the third direction.

7. The semiconductor structure according to claim 1, characterized in that, The bit line also includes: The bit line extension is located above the bit line body and is electrically connected to the bit line body. The bit line extension extends along the first direction, and the width of the bit line extension along the third direction is greater than or equal to the width of the bit line body along the third direction. The third direction is parallel to the top surface of the substrate, and the first direction intersects the third direction.

8. The semiconductor structure according to claim 7, characterized in that, The bit line also includes: The bit line contact portion extends along the second direction, and the two opposite ends of the bit line contact portion along the second direction are respectively electrically connected to the bit line body portion and the bit line extension portion, and the width of the bit line contact portion along the first direction is greater than or equal to the width of the bit line body portion along the first direction.

9. The semiconductor structure according to claim 1, characterized in that, The channel region, the first source / drain region, and the second source / drain region contain the same type of doped ions, and the ion doping concentration of the first source / drain region and the ion doping concentration of the second source / drain region are both greater than the ion doping concentration of the channel region.

10. A method for forming a semiconductor structure, characterized in that, Includes the following steps: Provide substrate; Multiple semiconductor layers are formed on the substrate, each semiconductor layer including an active region, the active region including a channel region, and a first source / drain region and a second source / drain region located on opposite sides of the channel region along a first direction, the first direction being perpendicular to the top surface of the substrate, and the multiple semiconductor layers being arranged at intervals along a second direction. A gate structure, word lines, and bit lines are formed on the substrate. The channel regions surround the outer periphery of the gate structure. The word lines include at least a word line body portion, which extends along a second direction and is electrically connected to the gate structures in a plurality of channel regions spaced apart along the second direction. The bit lines include at least a bit line body portion, which extends along the second direction and is electrically connected to a first source / drain region. The first source / drain region surrounds the outer periphery of the bit line body portion. The second direction is perpendicular to the top surface of the substrate.

11. The method for forming a semiconductor structure according to claim 10, characterized in that, The steps of forming a gate structure, word line, and bit line on the substrate include: A first trench is formed that extends through the first source / drain regions of the first semiconductor layers along the second direction; The bit line body portion is formed in the first trench, and the bit line body portion is electrically connected to the first source / drain regions of the plurality of semiconductor layers spaced apart along the second direction. A second trench is formed that extends along the second direction through the channel region in the plurality of semiconductor layers; The word line body portion and the gate structure are formed in the second trench. The gate structure penetrates the channel region in the semiconductor layer along the second direction. The word line body portion is connected to the gate structure adjacent along the second direction.

12. The method for forming a semiconductor structure according to claim 11, characterized in that, The semiconductor layer includes a plurality of active regions spaced apart along a third direction, and a plurality of word line bodies penetrate the channel regions of the plurality of active regions one by one along the second direction; the third direction is parallel to the top surface of the substrate, and the first direction intersects the third direction; after forming the word line bodies and the gate structure in the second trench, the method further includes the following steps: A character line extension is formed above the character line body portion. The character line extension extends along the third direction and is electrically connected to a plurality of character line bodies arranged at intervals along the third direction. The character line includes the character line body portion and the character line extension portion.

13. The method for forming a semiconductor structure according to claim 12, characterized in that, The step of forming the gate structure, word line, and bit line on the substrate further includes: A bit line extension portion electrically connected to the bit line body portion is formed above the bit line body portion. The bit line extension portion extends along the first direction, and the width of the bit line extension portion along the third direction is greater than or equal to the width of the bit line body portion along the third direction. The bit line includes the bit line body portion and the bit line extension portion. The third direction is parallel to the top surface of the substrate, and the first direction intersects the third direction.

14. The method for forming a semiconductor structure according to claim 13, characterized in that, The step of forming a bit line extension portion electrically connected to the bit line body portion above the bit line body portion includes: A bit line contact portion extending in the second direction is formed on the top surface of the bit line body portion. The bit line contact portion is electrically connected to the bit line body portion. In the second direction, the top surface of the bit line contact portion is located above the top surface of the word line extension portion. The width of the bit line contact portion in the first direction is greater than or equal to the width of the bit line body portion in the first direction. The bit line extension is formed on the top surface of the bit line contact portion, and the bit line extension is electrically connected to the bit line contact portion.

15. The method for forming a semiconductor structure according to claim 11, characterized in that, After forming the gate structure, word line, and bit line on the substrate, the method further includes: A lower electrode layer is formed that continuously covers at least a portion of the surface of the second source / drain regions in a plurality of active regions spaced apart along the second direction; A dielectric layer is formed covering the entire surface of the lower electrode layer; An upper electrode layer is formed covering the entire surface of the dielectric layer to form a capacitor comprising the lower electrode layer, the dielectric layer, and the upper electrode layer.

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