Semiconductor structure and method of manufacturing the same

Abstract

A method for fabricating a semiconductor structure includes: forming a first substrate, the first substrate including a first substrate and active regions arranged in an array along a first direction and a second direction within the first substrate, word lines disposed within the first substrate, the word lines extending along the second direction and at least covering opposite sides of the active regions; forming a charge storage structure on the first substrate, the charge storage structure being electrically connected to a first end of the active regions; forming a second substrate, the second substrate including a second substrate and bit lines disposed within the second substrate, the bit lines extending along the first direction; connecting the first substrate and the second substrate using a first surface of the first substrate facing away from the charge storage structure and a second surface of the second substrate having the bit line structure as connecting surfaces, wherein the bit lines are electrically connected to a second end of the active regions, and the first end and the second end are disposed opposite to each other.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuits, and more particularly to a semiconductor structure and its fabrication method. Background Technology

[0002] Semiconductor devices commonly used in computers and other electronic devices, such as Dynamic Random Access Memory (DRAM), consist of multiple memory cells, each typically including a transistor and a capacitor. The gate electrode of the transistor is electrically connected to the word line, the source electrode is electrically connected to the bit line, and the drain electrode is electrically connected to the capacitor. The word line voltage on the word line can control the transistor to turn on and off, thereby allowing data information stored in the capacitor to be read or written to the capacitor via the bit line.

[0003] Currently, the mainstream structure of these semiconductor devices is that the bit line and capacitor are both on the same side of the word line. In DRAM fabrication, the word line is formed first, then the bit line, and finally the capacitor. In this DRAM structure, because the bit line and capacitor are located on the same side of the word line, the space on that side is relatively crowded, which is not conducive to the fabrication of the bit line and capacitor, increasing the difficulty of the fabrication process.

[0004] Therefore, how to reduce the difficulty of the preparation process is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] The technical problem to be solved by this disclosure is to provide a semiconductor structure and a method for fabricating the same, which can reduce the difficulty of the fabrication process.

[0006] To address the aforementioned problems, this disclosure provides a method for fabricating a semiconductor structure, comprising: forming a first substrate, the first substrate including a first substrate and active regions arranged in an array along a first direction and a second direction within the first substrate, word lines disposed within the first substrate, the word lines extending along the second direction and at least covering opposite sides of the active regions; forming a charge storage structure on the first substrate, the charge storage structure being electrically connected to a first end of the active regions; forming a second substrate, the second substrate including a second substrate and bit lines disposed within the second substrate, the bit lines extending along the first direction; connecting the first substrate and the second substrate using a first surface of the first substrate facing away from the charge storage structure and a second surface of the second substrate having the bit line structure as connecting surfaces, wherein the bit lines are electrically connected to a second end of the active regions, and the first end and the second end are disposed opposite to each other.

[0007] In one embodiment, a bonding process is used to connect the first substrate and the second substrate.

[0008] In one embodiment, the step of connecting the first substrate to the second substrate further includes: thinning the first substrate to expose a second end of the active region.

[0009] In one embodiment, the process further includes the following step before performing the bonding process: performing plasma treatment on the first surface of the first substrate and the second surface of the second substrate.

[0010] In one embodiment, the step of connecting the first substrate and the second substrate using a bonding process includes: performing a hydrophilic treatment on a first surface of the first substrate and a second surface of the second substrate; bonding the first surface of the first substrate and the second surface of the second substrate together; and performing an annealing process.

[0011] In one embodiment, the bonding process for connecting the first substrate and the second substrate includes the following steps: forming a first contact structure on the first surface of the first substrate, wherein the first contact structure is electrically connected to the second end of the active region; forming a second contact structure on the second surface of the second substrate, wherein the second contact structure is electrically connected to the bit line; and bonding using the first contact structure and the second contact structure as bonding structures.

[0012] In one embodiment, the step of forming a first contact structure on the first surface of the first substrate includes: forming a first contact layer on the first surface of the first substrate, the first contact layer including a first filler layer and a first contact structure disposed within the first filler layer; the step of forming a second contact structure on the second surface of the second substrate includes: forming a second contact layer on the second surface of the second substrate, the second contact layer including a second filler layer and a second contact structure disposed within the second filler layer; the step of bonding the first contact structure and the second contact structure as bonding structures includes: bonding the first contact layer and the second contact layer as bonding layers, the first filler layer being bonded to the second filler layer, and the first contact structure being bonded to the second contact structure.

[0013] In one embodiment, after the step of forming the charge storage structure, the method includes: forming a first interlayer dielectric layer covering the surface of the charge storage structure and the surface of the first substrate; after the step of connecting the first substrate and the second substrate, the method includes: forming a word line lead-out structure, a bit line lead-out structure, and a charge storage lead-out structure from a side of the first substrate away from the second substrate, wherein the word line lead-out structure penetrates the first interlayer dielectric layer and is electrically connected to the word line, the bit line lead-out structure penetrates the first interlayer dielectric layer and the first substrate and is electrically connected to the bit line, and the charge storage lead-out structure penetrates the first interlayer dielectric layer and is electrically connected to the charge storage structure.

[0014] In one embodiment, the semiconductor structure includes a core region and a peripheral region. The word line, the bit line, and the charge storage structure are located in the core region. In the step of forming the first substrate, a word line connection structure is also formed in the peripheral region, and the word line connection structure is electrically connected to the word line. In the step of forming the second substrate, a bit line connection structure is also formed in the peripheral region, and the bit line connection structure is electrically connected to the bit line. In the step of forming the word line lead-out structure, the bit line lead-out structure, and the charge storage lead-out structure from the side of the first substrate away from the second substrate, the word line lead-out structure is formed in the peripheral region and is electrically connected to the word line connection structure, the bit line lead-out structure is formed in the peripheral region and is electrically connected to the bit line connection structure, and the charge storage lead-out structure is formed in the core region.

[0015] In one embodiment, after the step of forming the first interlayer dielectric layer, the method further includes: providing a third substrate; connecting the third substrate to the first substrate using the surface of the first interlayer dielectric layer as a connection surface; and before the step of forming a word line lead-out structure, a bit line lead-out structure, and a charge storage lead-out structure from the side of the first substrate away from the second substrate, the method further includes: removing the third substrate.

[0016] In one embodiment, the step of forming word lines in the first substrate includes: forming a plurality of spaced word line grooves in the first substrate; filling the word line grooves with word line material; removing a portion of the word line material, retaining at least the word line material located on opposite sides of the active region, to form the word lines; and forming a first isolation layer between two adjacent word lines.

[0017] In one embodiment, prior to the step of forming a charge storage structure on the first substrate, the method includes forming a capacitor connection structure on the first substrate, the capacitor connection structure being electrically connected to a first end of the active region.

[0018] In one embodiment, the step of forming a charge storage structure on the first substrate includes: forming an interlayer support layer; forming a capacitor hole that penetrates the interlayer support layer to the capacitor connection structure; forming a lower electrode within the capacitor hole, the lower electrode being connected to the capacitor connection structure, and the sidewall of the lower electrode being spaced from the sidewall of the capacitor hole; forming a capacitor dielectric layer on the sidewall of the lower electrode and the sidewall of the capacitor hole; and forming an upper electrode that covers the surface of the capacitor dielectric layer.

[0019] In one embodiment, the step of forming the second substrate includes: forming a bit line trench in the second substrate; forming a second isolation layer covering the inner wall of the bit line trench in the bit line trench; forming a bit line in the bit line trench, wherein the second isolation layer is disposed between the bit line and the second substrate.

[0020] This disclosure also provides a semiconductor structure comprising: a first substrate including a first substrate and active regions arranged in an array along a first direction and a second direction within the first substrate; word lines disposed within the first substrate, the word lines extending along the second direction and at least covering opposite sides of the active regions; a charge storage structure disposed on the first substrate and electrically connected to a first end of the active regions; and a second substrate disposed on a side of the first substrate away from the charge storage structure, the second substrate including a second substrate and bit lines disposed within the second substrate, the bit lines extending along the first direction and electrically connected to a second end of the active regions, the first end and the second end being disposed opposite to each other.

[0021] In one embodiment, the first substrate has a first surface, the first surface has a first contact structure, the first contact structure being electrically connected to a second end of the active region; the second substrate has a second surface opposite to the first surface, the second surface has a second contact structure, the second contact structure being electrically connected to the bit line and the first contact structure.

[0022] In one embodiment, the system further includes a first filling layer disposed on the first surface and a second filling layer disposed on the second surface, wherein the first contact structure is disposed within the first filling layer, the second contact structure is disposed within the second filling layer, and the first filling layer is connected to the second filling layer.

[0023] In one embodiment, the system further includes: a word line connection structure disposed within the first substrate and electrically connected to the word line; a bit line connection structure disposed within the second substrate and electrically connected to the bit line; a first interlayer dielectric layer covering the first substrate and the charge storage structure; a word line lead-out structure penetrating the first interlayer dielectric layer and electrically connected to the word line connection structure; and a bit line lead-out structure penetrating the first interlayer dielectric layer and the first substrate and electrically connected to the bit line connection structure.

[0024] In one embodiment, the system further includes a core region and a peripheral region, with the word lines and bit lines disposed in the core region and the word line connection structure and bit line connection structure disposed in the peripheral region.

[0025] In one embodiment, a charge storage lead-out structure is further included, which penetrates the first interlayer dielectric layer and is electrically connected to the charge storage structure.

[0026] The fabrication method provided in this disclosure can form word lines and charge storage structures on a first substrate, form bit lines on a second substrate, and then connect the first and second substrates to form a semiconductor structure in which the bit lines and charge storage structures are located on both sides of the word lines. This avoids overcrowding on one side of the word lines, reducing device density on the same side and simplifying the fabrication process. Furthermore, it allows for the separate fabrication of bit lines, avoiding the damage to the device structure caused by forming word lines, bit lines, and charge storage structures on the same substrate, thus improving the reliability and stability of the semiconductor structure. Moreover, the fabrication method provided in this disclosure forms the charge storage structure on the first substrate before connecting the first and second substrates, avoiding any impact from the charge storage structure formation process on the connection between the first and second substrates, further improving the stability and reliability of the semiconductor structure. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the steps in the method for fabricating a semiconductor structure provided in this embodiment.

[0028] Figures 2 to 19 This is a schematic diagram of the semiconductor structure formed by the main steps of the preparation method provided in the embodiments of this disclosure. Detailed Implementation

[0029] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. In describing the embodiments of this disclosure in detail, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to general proportions, and the schematic diagrams are merely examples and should not limit the scope of protection of this disclosure. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included. The semiconductor structure described in the embodiments of this disclosure may be, but is not limited to, DRAM.

[0030] Figure 1 This is a schematic diagram illustrating the steps of the semiconductor structure fabrication method provided in this disclosure embodiment. Please refer to [link / reference]. Figure 1 The fabrication method includes: step S10, forming a first substrate, the first substrate including a first substrate and active regions arranged in an array along a first direction and a second direction within the first substrate, word lines disposed within the first substrate, the word lines extending along the second direction and at least covering opposite sides of the active regions; step S11, forming a charge storage structure on the first substrate, the charge storage structure being electrically connected to a first end of the active regions; step S12, forming a second substrate, the second substrate including a second substrate and bit lines disposed within the second substrate, the bit lines extending along the first direction; step S13, connecting the first substrate and the second substrate using a first surface of the first substrate facing away from the charge storage structure and a second surface of the second substrate having the bit line structure as connecting surfaces, wherein the bit lines are electrically connected to a second end of the active regions, and the first end and the second end are disposed opposite to each other.

[0031] The following is combined with Figures 1 to 18 The method for forming a semiconductor device provided in the embodiments of this disclosure will be described in detail, wherein, Figures 2 to 19 This is a schematic diagram of the semiconductor structure formed by the main steps of the fabrication method provided in this embodiment. The semiconductor structure includes a core region (CORE) and a peripheral region (PERI). The first direction D1 and the second direction D2 are parallel to the top surface of the first substrate 201 and intersect each other. The third direction D3 is perpendicular to the top surface of the first substrate 201. In this embodiment, the first direction D1 is taken as the Y-axis direction in a Cartesian coordinate system, the second direction D2 as the X-axis direction in a Cartesian coordinate system, and the third direction D3 as the Z-axis direction in a Cartesian coordinate system, to illustrate the accompanying drawings.

[0032] Please refer to the following: Figure 1 and Figure 7 ,exist Figure 7In the figure, (a) is a top view of the core region CORE of the semiconductor structure, (b) is a cross-sectional view along line A-A1 in (a), (c) is a cross-sectional view along line B-B1 in (a), (d) is a cross-sectional view along line C-C1 in (a), (e) is a cross-sectional view along line E-E1 in (a), and (f) is a cross-sectional view of the peripheral region PERI of the semiconductor structure; in step S10, a first substrate 200 is formed, the first substrate 200 includes a first substrate 201 and an active region 220 arranged in an array along a first direction D1 and a second direction D2 disposed in the first substrate 201, and a word line 210 is disposed in the first substrate 200, the word line 210 extends along the second direction D2 and at least covers the opposite sides of the active region 220.

[0033] In this embodiment, the word line 210 covers the opposite sides of the active region 220. In other embodiments, the word line surrounds the active region 220, forming a ring gate structure. In this step, the word line 210 is formed in the core region (CORE), and the word line connection structure 213 is formed in the peripheral region (PERI). The word line connection structure 213 is connected to the word line 210 to connect the word line 210 to other conductive structures.

[0034] As an example, this disclosure provides a method for forming the first substrate 200. Specifically, it includes the following steps:

[0035] Please see Figure 2 ,exist Figure 2 In the figure, (a) is a top view of the core region CORE of the semiconductor structure, (b) is a cross-sectional view along line A-A1 in (a), (c) is a cross-sectional view along line B-B1 in (a), (d) is a cross-sectional view along line C-C1 in (a), (e) is a cross-sectional view along line E-E1 in (a), and (f) is a cross-sectional view of the peripheral region PERI of the semiconductor structure; a first substrate 201 is provided, and a plurality of spaced isolation structures 202 are formed in the first substrate 201, the isolation structures 202 extending along a first direction D1.

[0036] The first substrate 201 may include a silicon substrate, a germanium (Ge) substrate, a silicon germanide (SiGe) substrate, an SOI substrate, or a GOI (Germanium-on-Insulator) substrate, etc. The first substrate 201 may also be a substrate containing other elemental semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, or silicon carbide, etc. The first substrate 201 may also be a stacked structure, such as a silicon / germanium-silicon stack, etc. Furthermore, the first substrate 201 may be an ion-doped substrate, which may be P-type doped or N-type doped. Multiple peripheral devices, such as field-effect transistors, capacitors, inductors, and / or diodes, may also be formed in the first substrate 201. In this embodiment, the first substrate 201 is a silicon substrate, which may also include other device structures, such as transistor structures, metal wiring structures, etc., but these are not shown as they are not relevant to this invention.

[0037] The plurality of isolation structures 202 are spaced apart along the second direction D2, and each isolation structure 202 extends along the first direction D1. The first substrate 201 is also divided into a plurality of strip structures by the isolation structures 202. In this embodiment, three isolation structures 202 are schematically shown in the core region CORE, and two isolation structures 202 are schematically shown in the peripheral region PERI.

[0038] In this embodiment, a protective layer 203 is further coated on the surface of the first substrate 201 to protect the first substrate 201 during process steps, and the isolation structure 202 penetrates the protective layer 203. The protective layer 203 may be an oxide layer, such as a silicon dioxide layer. Figure 2 In Figure (a), the isolation structure 202 is obscured by the protective layer 203. The isolation structure 202 is drawn with dashed lines to clearly show the semiconductor structure of the present disclosure embodiment.

[0039] As an example, this disclosure provides a method for forming the isolation structure 202. The method includes: forming a protective layer 203 and a nitride layer on the surface of a first substrate 201; etching portions of the protective layer 203, the nitride layer, and the first substrate 201 to form a plurality of shallow trenches, the shallow trenches extending along a first direction D1, and the plurality of shallow trenches spaced apart along a second direction D2; depositing an isolation material within the shallow trenches; etching back the isolation material and removing the nitride layer to form the isolation structure 202. The isolation structure 202 includes, but is not limited to, an oxide layer, a nitride layer, or a composite structure of an oxide layer and a nitride layer. In this embodiment, the isolation structure 202 is described using an example where only an oxide layer is included, and the oxide layer includes, but is not limited to, a silicon dioxide layer.

[0040] Please see Figure 3 ,exist Figure 3 In the diagram, (a) is a top view of the core region (CORE) of the semiconductor structure; (b) is a cross-sectional view along line A-A1 in (a); (c) is a cross-sectional view along line B-B1 in (a); (d) is a cross-sectional view along line C-C1 in (a); (e) is a cross-sectional view along line E-E1 in (a); and (f) is a cross-sectional view of the peripheral region (PERI) of the semiconductor structure. Multiple word line trenches 211 are formed at intervals within the first substrate 200. These trenches extend along the second direction D2 and pass through the isolation structure 202. The multiple word line trenches 211 are also spaced apart along the first direction D1. The word line trenches 211 are formed not only in the core region (CORE) but also in the peripheral region (PERI).

[0041] In this step, the word line trench 211 can be formed using photolithography and etching processes. Specifically, a patterned mask layer is covered on the surface of the protective layer 203 and the isolation structure 202. The mask layer blocks areas that do not need to be etched, exposing areas that need to be etched. Using the mask layer as a shield, the protective layer 203, the isolation structure 202, and the substrate are etched to form the word line trench 211.

[0042] The word line trench 211 and the isolation structure 202 intersect perpendicularly, dividing the first substrate 201 into a plurality of independent semiconductor pillars, which serve as the active regions of the semiconductor structure. In this embodiment, the word line trench 211 is also formed in the peripheral region PERI.

[0043] In some embodiments, after forming the word line trench 211, the step of forming a word line dielectric layer 212 is further included. Specifically, please refer to... Figure 4 ,exist Figure 4In the diagram, (a) is a top view of the core region (CORE) of the semiconductor structure; (b) is a cross-sectional view along line A-A1 in (a); (c) is a cross-sectional view along line B-B1 in (a); (d) is a cross-sectional view along line C-C1 in (a); (e) is a cross-sectional view along line E-E1 in (a); and (f) is a cross-sectional view of the peripheral region (PERI) of the semiconductor structure. A word line dielectric layer 212 is formed within the word line trench 211, covering the sidewalls of the word line trench 211. The isolation structure 202 is shielded by the word line dielectric layer 212 and is shown as a dashed line. In this step, the word line dielectric layer 212 can be formed using processes such as chemical vapor deposition (CVD) and atomic layer deposition (ALD). The material of the word line dielectric layer 212 includes, but is not limited to, silicon dioxide, high-k dielectric, etc. For example, in this embodiment, an atomic layer deposition process is used to deposit a silicon dioxide layer, which serves as the word line dielectric layer 212. The word line dielectric layer 212 covers the inner walls of the word line trenches 211 in the core region (CORE) and the peripheral region (PERI). It is understood that the word line dielectric layer 212 only covers the inner walls of the word line trenches 211 and does not fill the word line trenches 211 completely, so as to leave enough space for subsequent word line formation.

[0044] Please see Figure 5 ,exist Figure 5 In the figures, (a) is a top view of the core region (CORE) of the semiconductor structure, (b) is a cross-sectional view along line A-A1 in (a), (c) is a cross-sectional view along line B-B1 in (a), (d) is a cross-sectional view along line C-C1 in (a), (e) is a cross-sectional view along line E-E1 in (a), and (f) is a cross-sectional view of the peripheral region (PERI) of the semiconductor structure. Word line material 300 is filled within the word line trench 211. In this embodiment, the word line material 300 includes titanium nitride (TiN) and tungsten (W). In this step, atomic layer deposition is used to deposit titanium nitride (TiN) and tungsten (W) within the word line trench 211. To clearly and concisely illustrate the technical solution of this application embodiment, only one layer structure is schematically shown in the figures. The word line material 300 covers the surface of the word line dielectric layer 212 and fills the word line trench 211.

[0045] Please see Figure 6 ,exist Figure 6In the figure, (a) is a top view of the core region CORE of the semiconductor structure, (b) is a cross-sectional view along line A-A1 in (a), (c) is a cross-sectional view along line B-B1 in (a), (d) is a cross-sectional view along line C-C1 in (a), (e) is a cross-sectional view along line E-E1 in (a), and (f) is a cross-sectional view of the peripheral region PERI of the semiconductor structure. A portion of the word line material 300 is removed, leaving the word line material 300 located on the opposite sidewalls of the word line trench 211, forming two adjacent word lines 210. In this step, a portion of the word line material 300 is etched back to the bottom of the word line trench 211, forming two relatively independent word lines 210, which are respectively disposed on opposite sidewalls of the word line trench 211. The substrate region enclosed by the word lines 210 and the isolation structure 202 is the active region 220. For example, in Figure 6 In this step, word line material located before the adjacent active region 220 is etched to form two word lines, namely word line 210A and word line 210B. The first substrate 201 region surrounded by word line 210A, word line 210B, isolation structure 202A, and isolation structure 202B is the active region 220. Word line 210A and word line 210B together serve as the ring gate of the active region 220, and the active region 220 corresponding to word line 210A and word line 210B serves as the channel region of the subsequently formed transistor. In this step, in the peripheral region PERI, the word line material 300 is etched to form a word line connection structure 213.

[0046] Please continue reading. Figure 7 A first isolation layer 214 is formed between the two adjacent word lines 210. In this step, an isolation material is deposited to form the first isolation layer 214, which also covers the surface of the first substrate 201. Since the isolation structure 202 and the word lines 210 are shielded by the first isolation layer 214, they are shown as dashed lines in the drawings. The first isolation layer 214 serves as an insulating layer between adjacent word lines 210 to prevent them from conducting and affecting the performance of the semiconductor structure.

[0047] After depositing the isolation material, the surface of the isolation material can be polished using a chemical mechanical polishing (CMP) process to obtain a first isolation layer 214 with a flat surface. This provides a good foundation for the subsequent formation of other semiconductor structures on it, thereby reducing the difficulty of the process and improving the reliability of the semiconductor structure. The first isolation layer 214 includes, but is not limited to, a silicon nitride layer, a silicon oxynitride layer, etc.

[0048] In this embodiment, after forming the word line 210 and before forming the charge storage structure 240, the fabrication method further includes: forming a capacitor connection structure 230 on the first substrate 200, wherein the capacitor connection structure 230 is electrically connected to a first end of the active region 220. The capacitor connection structure 230 includes a contact pad 231 and a conductive plug 232, wherein the contact pad 231 is electrically connected to the first end of the active region 220, and the conductive plug 232 is electrically connected to the contact pad 231.

[0049] As an example, this disclosure provides a method for forming the capacitor connection structure 230. The method includes the following steps:

[0050] Please see Figure 8 ,exist Figure 8 In the diagram, (a) is a top view of the core region (CORE) of the semiconductor structure; (b) is a cross-sectional view along line A-A1 in (a); (c) is a cross-sectional view along line B-B1 in (a); (d) is a cross-sectional view along line C-C1 in (a); (e) is a cross-sectional view along line E-E1 in (a); and (f) is a cross-sectional view of the peripheral region (PERI) of the semiconductor structure. A contact pad 231 is formed, which is electrically connected to the first end of the active region 220. The first end of the active region 220 refers to the end of the active region 220 facing the front side of the first substrate 200 on the third direction D3. In this step, a via is formed using photolithography and etching processes. The via penetrates the first isolation layer 214, the first word line dielectric layer 212, and the protective layer 203 to the active region 220. A conductive material is filled within the via to form the contact pad 231. The conductive material includes, but is not limited to, polysilicon.

[0051] After the contact pad 231 is formed, please refer to [the relevant documentation]. Figure 8 A capping layer 310 is formed, which covers only the surface of the semiconductor structure in the core region (CORE) and not the surface of the semiconductor structure in the peripheral region (PERI). Therefore, when the peripheral gate 400 is subsequently formed in the peripheral region (PERI), the capping layer 310 protects the semiconductor structure in the core region (CORE). The capping layer 310 includes, but is not limited to, a silicon nitride layer. In the figures, the contact pad 231 is shielded by the capping layer 310; therefore, the contact pad 231 is shown as a dashed line.

[0052] Please see Figure 9 ,exist Figure 9In the figure, (a) is a top view of the core region CORE of the semiconductor structure, (b) is a schematic cross-section along line A-A1 in (a), (c) is a schematic cross-section along line B-B1 in (a), (d) is a schematic cross-section along line C-C1 in (a), (e) is a schematic cross-section along line E-E1 in (a), and (f) is a schematic cross-section of the peripheral region PERI of the semiconductor structure; a peripheral gate 400 is formed in the peripheral region PERI.

[0053] As an example, this disclosure provides a method for forming the peripheral gate 400, the method comprising: removing the first isolation layer 214 in the peripheral region PERI to expose the word line dielectric layer 212; depositing a polysilicon layer, a titanium nitride layer, a tungsten metal layer, and a silicon nitride layer on the word line dielectric layer 212; removing portions of the polysilicon layer, titanium nitride layer, tungsten metal layer, and silicon nitride layer using photolithography and etching processes to form a gate, the gate corresponding to the active region 220 of the peripheral region PERI; and forming a standing wall on the sidewall of the gate. In the step of removing the polysilicon layer, titanium nitride layer, tungsten metal layer, and silicon nitride layer, the exposed word line dielectric layer 212 is also removed.

[0054] Please see Figure 10 ,exist Figure 10 In the diagram, (a) is a top view of the core region (CORE) of the semiconductor structure, (b) is a cross-sectional view along line A-A1 in (a), (c) is a cross-sectional view along line B-B1 in (a), (d) is a cross-sectional view along line C-C1 in (a), (e) is a cross-sectional view along line E-E1 in (a), and (f) is a cross-sectional view of the peripheral region (PERI) of the semiconductor structure; a second interlayer dielectric layer 320 is formed. In the core region (CORE), the second interlayer dielectric layer 320 covers the cover layer 310, and in the peripheral region (PERI), the second interlayer dielectric layer 320 covers the peripheral gate 400 and the surface of the first substrate 200. The surface of the first substrate 200 includes the first substrate 201 and other semiconductor structures exposed on the surface of the first substrate 201, such as word line interconnect structure 213, protective layer 203, isolation structure 202, etc. In this embodiment, the second interlayer dielectric layer 320 can be formed using processes such as chemical vapor deposition. The second interlayer dielectric layer 320 includes, but is not limited to, a silicon dioxide layer doped with boron and phosphorus.

[0055] Please see Figure 11 ,exist Figure 11In the figure, (a) is a top view of the core region CORE of the semiconductor structure, (b) is a schematic cross-section along line A-A1 in (a), (c) is a schematic cross-section along line B-B1 in (a), (d) is a schematic cross-section along line C-C1 in (a), (e) is a schematic cross-section along line E-E1 in (a), and (f) is a schematic cross-section of the peripheral region PERI of the semiconductor structure. After forming the second interlayer dielectric layer 320, the method includes the following steps:

[0056] A conductive plug 232 is formed, which penetrates the second interlayer dielectric layer 320 and is electrically connected to the contact pad 231. In this step, the second interlayer dielectric layer 320 is etched to form a via, which exposes the contact pad 231. The via is filled with a conductive material to form the conductive plug 232. The conductive plug 232 includes, but is not limited to, a composite layer of titanium nitride and tungsten. In some embodiments, before filling with conductive material, a step of cobaltizing the surface of the contact pad 231 to form a cobalt silicide layer (not shown in the figures) is further included. The conductive plug 232 is formed in the core region (CORE) and the peripheral region (PERI). In the peripheral region (PERI), the conductive plug 232 is connected to the word line connection structure 213 and the active region 220 on one side of the peripheral gate 400. In this embodiment, in the core region (CORE), the conductive plug 232 also penetrates the capping layer 310.

[0057] After forming the conductive plug 232, the fabrication method further includes: depositing a metal material on the surface of the second interlayer dielectric layer 320 and the surface of the conductive plug 232; patterning the metal material to form a connecting pad 233, the connecting pad 233 being connected to the conductive plug 232; and forming a third interlayer dielectric layer 330, the third interlayer dielectric layer 330 covering the upper surface of the second interlayer dielectric layer 320 and filling the spaces between adjacent connecting pads 233. In this embodiment, the third interlayer dielectric layer 330 can be formed using processes such as chemical vapor deposition. The third interlayer dielectric layer 330 includes, but is not limited to, a silicon nitride layer.

[0058] In the core area (CORE), the contact pad 231, the conductive plug 232, and the connecting pad 233 together serve as the capacitor connection structure 230. In the peripheral area (PERI), the conductive plug 232 and the connecting pad 233 together serve as the peripheral connection structure.

[0059] Please refer to the following: Figure 1 and Figure 13 ,exist Figure 13In the diagram, (a) is a top view of the core region (CORE) of the semiconductor structure, (b) is a cross-sectional view along line A-A1 in (a), (c) is a cross-sectional view along line B-B1 in (a), (d) is a cross-sectional view along line C-C1 in (a), (e) is a cross-sectional view along line E-E1 in (a), and (f) is a cross-sectional view of the peripheral region (PERI) of the semiconductor structure. In step S11, a charge storage structure 240 is formed on the first substrate 200, and the charge storage structure 240 is electrically connected to the first end of the active region 220. In this embodiment, after forming the capacitor connection structure 230, the charge storage structure 240 is formed on the third interlayer dielectric layer 330.

[0060] In this embodiment, the charge storage structure is a capacitor structure. The charge storage structure 240 includes a lower electrode 241, a capacitor dielectric layer 242, and an upper electrode 243. The lower electrode 241 is electrically connected to the capacitor connection structure 230, the capacitor dielectric layer 242 covers the surface of the lower electrode 241, and the upper electrode 243 covers the surface of the capacitor dielectric layer 242. In other embodiments, the charge storage structure may further include a magnetic storage element.

[0061] As an example, this disclosure provides a method for forming the charge storage structure 240. The method includes the following steps: [See attached instructions]. Figure 12 ,exist Figure 12 In the figure, (a) is a top view of the core region CORE of the semiconductor structure, (b) is a cross-sectional view along line A-A1 in (a), (c) is a cross-sectional view along line B-B1 in (a), (d) is a cross-sectional view along line C-C1 in (a), (e) is a cross-sectional view along line E-E1 in (a), and (f) is a cross-sectional view of the peripheral region PERI of the semiconductor structure; an interlayer support layer 340 is formed, and a capacitor hole 341 is formed, wherein the capacitor hole 341 penetrates the interlayer support layer 340 to the capacitor connection structure 230.

[0062] In this embodiment, an interlayer support layer 340 is formed on the surface of the third interlayer dielectric layer 330. The interlayer support layer 340 may include a bottom support layer, an intermediate support layer, and a top support layer, for supporting the charge storage structure 240. In this embodiment, only one support layer is schematically shown. The specific structure of the interlayer support layer 340 will not be described in detail here.

[0063] In this step, a capacitor hole 341 is formed using photolithography and etching processes. The capacitor hole 341 penetrates the interlayer support layer 340 and exposes the connecting pad 233.

[0064] Please continue reading. Figure 13A lower electrode 241 is formed within the capacitor hole 341. The lower electrode 241 is connected to the capacitor connection structure 230, and the sidewall of the lower electrode 241 is spaced from the sidewall of the capacitor hole 341. A capacitor dielectric layer 242 is formed on the sidewall of the lower electrode 241 and the sidewall of the capacitor hole 341. An upper electrode 243 is formed, and the upper electrode 243 covers the surface of the capacitor dielectric layer 242.

[0065] In this step, a titanium nitride material layer can be deposited using chemical vapor deposition (CVD) or atomic layer deposition (ALD). The titanium nitride material layer is then etched back to form a lower electrode pillar 241. A gap exists between the lower electrode pillar 241 and the sidewall of the capacitor via 341 to form the capacitor dielectric layer 242 and the upper electrode 243. The capacitor dielectric layer 242 can be a high-k dielectric layer, and the upper electrode 243 can be a titanium nitride layer.

[0066] Please continue reading. Figure 13 In this embodiment, after forming the charge storage structure 240, the following steps are further included: forming a silicon-germanium layer 350, which covers the surface of the charge storage structure 240. In this embodiment, the silicon-germanium layer 350 covers the surface of the upper electrode 243. After forming the silicon-germanium layer 350, a first interlayer dielectric layer 360 is formed, which covers the surface of the silicon-germanium layer 350 and serves to protect the charge storage structure 240. In the peripheral region PERI, the silicon-germanium layer 350 is not formed, and the first interlayer dielectric layer 360 covers the surfaces of the connecting pad 233 and the third interlayer dielectric layer 330. The first interlayer dielectric layer 360 can be a single-layer structure or a multi-layer composite structure. For example, in this embodiment, the first interlayer dielectric layer 360 is a single layer of silicon dioxide; in other embodiments, the first interlayer dielectric layer 360 is a composite structure of a silicon dioxide layer and a silicon nitride layer.

[0067] After forming the first interlayer dielectric layer 360, the method further includes the following steps: providing a third substrate 500; and connecting the first substrate 200 and the third substrate 500 with the side of the first substrate 200 having the charge storage structure 240 as the connecting surface. Specifically, in this embodiment, please refer to... Figure 14 ,exist Figure 14In the diagram, (a) is a top view of the core region (CORE) of the semiconductor structure; (b) is a cross-sectional view along line A-A1 in (a); (c) is a cross-sectional view along line B-B1 in (a); (d) is a cross-sectional view along line C-C1 in (a); (e) is a cross-sectional view along line E-E1 in (a); and (f) is a cross-sectional view of the peripheral region (PERI) of the semiconductor structure. A third substrate 500 is provided, and the first interlayer dielectric layer 360 is used as the connection surface to connect the third substrate 500 to the first substrate 200. A bonding process can be used to connect the surface of the third substrate 500 to the first interlayer dielectric layer 360. In subsequent processes, the third substrate 500 is used to support the first substrate 200 and to protect the semiconductor structure within the first substrate 200. The third substrate 500 may include a silicon substrate, a germanium (Ge) substrate, a silicon germanide (SiGe) substrate, an SOI substrate, or a GOI (Germanium-on-Insulator) substrate, etc. In this embodiment, the third substrate 500 is a silicon substrate.

[0068] Please refer to the following: Figure 1 and Figure 15 ,exist Figure 15 In the diagram, (a) is a top view of the core region (CORE) of the semiconductor structure; (b) is a cross-sectional view along line A-A1 in (a); (c) is a cross-sectional view along line B-B1 in (a); (d) is a cross-sectional view along line C-C1 in (a); (e) is a cross-sectional view along line E-E1 in (a); and (f) is a cross-sectional view of the peripheral region (PERI) of the semiconductor structure. In step S12, a second substrate 600 is formed. The second substrate 600 includes a second substrate 601 and a plurality of spaced bit lines 250 disposed within the second substrate 601. The bit lines 250 extend along the first direction D1. In this step, the surface of the bit lines 250 is exposed to the surface of the second substrate 601 to facilitate subsequent connection with the active region 220.

[0069] The second substrate 601 may include a silicon substrate, a germanium (Ge) substrate, a silicon germanide (SiGe) substrate, an SOI substrate, or a GOI (Germanium-on-Insulator) substrate, etc.; the second substrate 601 may also be a substrate including other elemental semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, or silicon carbide, etc.; the second substrate 601 may also be a stacked structure, such as a silicon / germanium-silicon stack, etc.; in addition, the second substrate 601 may be an ion-doped substrate, which may be p-type doped or n-type doped; multiple peripheral devices, such as field-effect transistors, capacitors, inductors, and / or diodes, may also be formed in the second substrate 601. In this embodiment, the second substrate 601 is a silicon substrate, which may also include other device structures, such as transistor structures, metal wiring structures, etc., but since they are not related to this invention, they are not shown.

[0070] Multiple bit lines 250 are spaced apart along the second direction D2, and the positions of the bit lines 250 correspond to the positions of the active regions 220 within the first substrate 200. A second isolation layer 251 is provided between the bit lines 250 and the second substrate 601. The second isolation layer 251 includes, but is not limited to, an oxide layer, and the bit lines 250 include, but are not limited to, a composite layer of titanium nitride and tungsten.

[0071] The second substrate 600 also includes a core region (CORE) and a peripheral region (PERI). In this step, the bit line 250 is formed in the core region (CORE), and the bit line connection structure 252 is formed in the peripheral region (PERI).

[0072] As an example, this disclosure provides a method for forming the bit line 250. The method includes: forming a bit line trench (not shown in the figures) within a second substrate 601, the bit line trench being located not only in the core region (CORE) but also in the peripheral region (PERI). A second isolation layer 251 is formed within the bit line trench, covering the inner wall of the bit line trench. The bit line 250 is formed within the bit line trench in the core region (CORE), and a bit line connection structure 252 is formed within the bit line trench in the peripheral region (PERI). The second isolation layer 251 is disposed between the bit line 250 and the second substrate 601, and between the bit line connection structure 252 and the second substrate 601.

[0073] Please see Figure 16 ,exist Figure 16In the diagram, (a) is a top view of the core region (CORE) of the semiconductor structure; (b) is a cross-sectional view along line A-A1 in (a); (c) is a cross-sectional view along line B-B1 in (a); (d) is a cross-sectional view along line C-C1 in (a); (e) is a cross-sectional view along line E-E1 in (a); and (f) is a cross-sectional view of the peripheral region (PERI) of the semiconductor structure. Since the active region 220 is not exposed on the back side of the first substrate 200, in this step, the first substrate 201 is thinned on the side of the first substrate 200 facing away from the charge storage structure 240, exposing the second end of the active region 220 for connection with the bit line 250. The second end is the end of the active region 220 on the third direction D3 facing away from the front side of the second substrate 600, with the first end and the second end positioned opposite each other. The method for thinning the first substrate 201 in this step includes, but is not limited to, chemical mechanical polishing (CMP). It is understandable that, in order to avoid the word line 210 from being connected to the bit line 250, the word line 210 is not exposed in this step.

[0074] Please see Figure 17 ,exist Figure 17 In the figure, (a) is a top view of the core region CORE of the semiconductor structure, (b) is a cross-sectional view along line A-A1 in (a), (c) is a cross-sectional view along line B-B1 in (a), (d) is a cross-sectional view along line C-C1 in (a), (e) is a cross-sectional view along line E-E1 in (a), and (f) is a cross-sectional view of the peripheral region PERI of the semiconductor structure; in step S13, the first substrate 200 and the second substrate 600 are connected using the first surface of the first substrate 200 away from the charge storage structure 240 and the second surface of the second substrate 600 having the bit line structure 250 as the connection surface, wherein the bit line 250 is electrically connected to the second end of the active region 220, and the first end and the second end are arranged opposite to each other.

[0075] In this embodiment, a bonding process is used to connect the first substrate 200 and the second substrate 600. Specifically, the thinned surface of the first substrate 220 is used as the first surface, and the surface of the second substrate 600 that exposes the bit line 250 is used as the second surface. The first surface and the second surface serve as the bonding interface, and a bonding process is used to connect the first substrate 220 and the second substrate 600.

[0076] As an example, this disclosure provides a bonding method.

[0077] Before performing the bonding process, the first surface of the first substrate 200 and the second surface of the second substrate 600 are subjected to plasma treatment to activate the first and second surfaces and prepare them for bonding. The plasma treatment may include any one of nitrogen plasma treatment, argon plasma treatment, or neon plasma treatment. The plasma treatment can increase the number of dangling bonds, such as Si-dangling bonds, on the first and second surfaces. The more dangling bonds on the first and second surfaces, the greater the surface energy, and the stronger the bonding strength between the first and second surfaces during subsequent bonding, resulting in a more robust bond.

[0078] The first surface of the first substrate 200 and the second surface of the second substrate 600 are subjected to hydrophilic treatment, forming OH bonds between the first and second surfaces. These OH bonds can combine with Si-dangling bonds to form Si-OH bonds, which have strong adsorption properties, resulting in a stronger bond between the first and second surfaces. In some embodiments, a certain amount of water can be introduced during plasma treatment of the first surface of the first substrate 200 and the second surface of the second substrate 600. The water will ionize to form hydroxyl groups, which will combine with Si-dangling bonds to form Si-OH bonds. In other embodiments, hydrophilic treatment can be performed after plasma treatment, for example, by cleaning the first and second surfaces separately with a chemical cleaning solution. This removes impurities from the first and second surfaces and allows OH bonds to form between them, creating hydrophilic surfaces.

[0079] The first surface of the first substrate 200 and the second surface of the second substrate 600 are bonded together. For example, in some embodiments, the first surface of the first substrate 200 and the second surface of the second substrate 600 are bonded together at room temperature and pressure.

[0080] After the first surface of the first substrate 200 and the second surface of the second substrate 600 are bonded together, an annealing process is performed. The annealing process causes the OH bonds on the first and second surfaces to evaporate as water, achieving a bonding connection between the first and second surfaces. In some embodiments, the annealing temperature ranges from 100 to 250°C, thereby avoiding adverse effects of high temperatures on the semiconductor structure.

[0081] As an example, this disclosure also provides a bonding method. Specifically, please refer to... Figure 18 The bonding process for connecting the first substrate 200 and the second substrate 600 includes the following steps:

[0082] A first contact structure 800 is formed on the first surface of the first substrate 200, and the first contact structure 800 is electrically connected to the second end of the active region 220. In this step, a first contact layer is formed on the first surface of the first substrate 200, the first contact layer including a first filler layer 801 and the first contact structure 800 disposed within the first filler layer 801. In some embodiments, the method of forming the first contact layer includes: forming the first filler layer 801 on the first surface; patterning the first filler layer 801; and filling the pattern of the first filler layer 801 with a conductive material to form the first contact structure 800.

[0083] A second contact structure 810 is formed on the second surface of the second substrate 600, and the second contact structure 810 is electrically connected to the bit line 250. In this step, a second contact layer is formed on the second surface of the second substrate 600, the second contact layer including a second filler layer 811 and the second contact structure 810 disposed within the second filler layer 811. In some embodiments, the method of forming the second contact layer includes: forming the second filler layer 811 on the second surface; patterning the second filler layer 811; and filling the pattern of the second filler layer 811 with a conductive material to form the second contact structure 810.

[0084] The first contact structure 800 and the second contact structure 810 are used as bonding structures for bonding. In this embodiment, in this step, the first contact layer and the second contact layer are used as bonding layers, that is, the first filler layer 801 and the second filler layer 811 are also used as bonding structures for bonding. The first filler layer 801 and the second filler layer 811 can fill the gap between the first surface and the second surface to provide support and sealing.

[0085] The fabrication method provided in this disclosure performs the bonding process after forming the charge storage structure, thereby avoiding the adverse effects of high temperature and other processes during the formation of the charge storage structure on the bonding interface and improving the reliability and stability of the semiconductor structure.

[0086] It is understood that in the formed semiconductor structure, in the peripheral region PERI, on the third direction D3, the bit line connection structure 252 is misaligned with the word line connection structure 213 and the transistor where the peripheral gate 400 is located, in order to avoid the word line connection structure 213 and the transistor where the peripheral gate 400 is located from blocking the bit line connection structure 252, so as to facilitate the subsequent electrical lead-out of the bit line connection structure 252.

[0087] Following the step of connecting the first substrate 200 to the second substrate 600, the method includes: forming a word line lead-out structure 700, a bit line lead-out structure 701, and a charge storage lead-out structure 702 from the side of the first substrate 200 opposite to the second substrate 600. The word line lead-out structure 700 penetrates the first interlayer dielectric layer 360 and is electrically connected to the word line 210; the bit line lead-out structure 701 penetrates the first interlayer dielectric layer 360 and the first substrate 200 and is electrically connected to the bit line 250; and the charge storage lead-out structure 702 penetrates the third interlayer dielectric layer 360 and is electrically connected to the charge storage structure 240. In this embodiment, the word line lead-out structure 700 is electrically connected to the word line 210 through the word line connection structure, and the bit line lead-out structure 701 is electrically connected to the bit line 250 through the bit line connection structure.

[0088] Specifically, in this embodiment, the method for forming the word line lead-out structure 700, the bit line lead-out structure 701, and the charge storage lead-out structure 702 further includes the following steps: Please refer to Figure 19 ,exist Figure 19 In the figure, (a) is a top view of the core region CORE of the semiconductor structure, (b) is a cross-sectional view along line A-A1 in (a), (c) is a cross-sectional view along line B-B1 in (a), (d) is a cross-sectional view along line C-C1 in (a), (e) is a cross-sectional view along line E-E1 in (a), and (f) is a cross-sectional view of the peripheral region PERI of the semiconductor structure; the third substrate 500 is removed, and a word line lead-out structure 700 and a bit line lead-out structure 700 are formed from the side of the first substrate 200 away from the second substrate 600. The device includes a word line lead-out structure 701 and a charge storage lead-out structure 702. The word line lead-out structure 700 is formed in the peripheral region PERI, penetrates the first interlayer dielectric layer 360 and is electrically connected to the word line connection structure. The bit line lead-out structure 701 is formed in the peripheral region PERI, penetrates the first interlayer dielectric layer 360 and the first substrate 200 and is electrically connected to the bit line connection structure. The charge storage lead-out structure 702 is formed in the core region CORE, penetrates the first interlayer dielectric layer 360 and is electrically connected to the charge storage structure 240.

[0089] In this embodiment, the third substrate 500 can be removed using processes such as laser cutting. After removing the third substrate 500, the first interlayer dielectric layer 360 is exposed, and vias can be formed using photolithography and etching processes. In the core region (CORE), the vias expose the silicon-germanium layer 350, and in the peripheral region (PERI), the vias expose the connector pad 233 and the bit line connection structure 252. Conductive material is deposited within the vias to form the word line lead-out structure 700, the bit line lead-out structure 701, and the charge storage lead-out structure 702.

[0090] In this embodiment, in the core region (CORE), the charge storage lead-out structure 702 is connected to the silicon-germanium layer 350, serving as the electrical lead-out of the charge storage structure 240. In the peripheral region (PERI), the word line lead-out structure 700 is electrically connected to the word line connection structure 213 via the connection pad 233 and the conductive plug 232, and the bit line lead-out structure 701 is electrically connected to the bit line connection structure 252, thus realizing the electrical lead-out of the word line 210 and the bit line 250. In some embodiments, a peripheral lead-out structure 703 is also present, electrically connected to the active region 220 of the peripheral gate 400, realizing the electrical lead-out of the peripheral transistor.

[0091] The fabrication method provided in this embodiment can form a semiconductor structure in which the bit line 250 and the charge storage structure 240 are located on both sides of the word line 210. On the one hand, it avoids the situation where one side of the word line 210 is too crowded, reduces the device density on the same side of the word line 210, and reduces the difficulty of the fabrication process. On the other hand, it can fabricate the bit line 250 separately, thereby avoiding adverse effects such as damage to the device structure caused by forming the word line 210, bit line 250 and charge storage structure 240 on the same substrate, and improving the stability of the semiconductor structure.

[0092] This disclosure also provides a semiconductor structure prepared using the above-described method. Please refer to [link to relevant documentation]. Figures 2 to 19 The semiconductor structure includes a first substrate 200, a word line 210, a charge storage structure 240, and a second substrate 600.

[0093] The first substrate 200 includes a first substrate 201 and a plurality of active regions 220 disposed within the first substrate 201. The active regions 220 are arranged in an array along a first direction D1 and a second direction D2. In this embodiment, a protective layer 203 is also provided on the surface of the first substrate 201 to protect the first substrate 201.

[0094] The word line 210 is disposed within the first substrate 200, and extends along the second direction D2 and at least covers the opposite sides of the active region 220. In this embodiment, the word line 210 only covers the opposite sides of the active region 220; in other embodiments, the word line 210 surrounds the active region 220 to form a ring gate structure.

[0095] In this embodiment, multiple word lines 210 are spaced apart along the first direction D1. In the second direction D2, word lines 210 are provided on both sides of the same active region 220. The active region 220 corresponding to these two word lines 210 serves as the channel region of the transistor. For example, please refer to... Figure 6The first substrate 201 region formed by word line 210A, word line 210B, isolation structure 202A, and isolation structure 202B is the active region 220. Then, word line 210A and word line 210B together serve as the gate of the active region 220, and the active region 220 corresponding to word line 210A and word line 210B serves as the channel region of the transistor.

[0096] In this embodiment, a word line dielectric layer 212 is further provided between the word line 210 and the active region 220 for insulating and isolating the word line 210 and the active region 220.

[0097] In this embodiment, in the second direction D2, two word lines 210 are provided between adjacent active regions 220, and a first isolation layer 214 is provided between the two word lines 210. The first isolation layer 214 is used to insulate and isolate the two word lines 210.

[0098] The charge storage structure 240 is disposed on the first substrate 200 and electrically connected to the first end of the active region 220. In this embodiment, the charge storage structure 240 is a capacitor structure, which includes a lower electrode 241, a capacitor dielectric layer 242 covering the surface of the lower electrode 241, and an upper electrode 243 covering the surface of the capacitor dielectric layer 242.

[0099] In this embodiment, the charge storage structure 240 is electrically connected to the first end of the active region 220 via a capacitor connection structure 230. Specifically, one end of the capacitor connection structure 230 is electrically connected to the first end of the active region 220, and the other end is electrically connected to the lower electrode 241 of the charge storage structure 240. The capacitor connection structure 230 includes a contact pad 231 electrically connected to the first end of the active region 220, a conductive plug 232 connected to the contact pad 231, and a connecting pad 233 connected to the conductive plug 232. The connecting pad 233 is electrically connected to the lower electrode 241.

[0100] In this embodiment, the semiconductor structure further includes a silicon-germanium layer 350, which covers the surface of the charge storage structure 240. Specifically, the silicon-germanium layer 350 covers the surface of the upper electrode 243.

[0101] The second substrate 600 is disposed on the side of the first substrate 200 facing away from the charge storage structure 240. The second substrate 600 includes a second substrate 601 and a plurality of spaced bit lines 250 disposed within the second substrate 601. The bit lines 250 extend along the first direction D1 and are electrically connected to the second end of the active region 220. The plurality of bit lines 250 are arranged at intervals along the second direction D2.

[0102] In this embodiment, the semiconductor structure further includes a second isolation layer 251, which is disposed between the bit line 250 and the second substrate 601 to insulate and isolate the second substrate 601 from the bit line 250.

[0103] In this embodiment, please refer to Figure 18 The first substrate 200 has a first surface with a first contact structure 800, which is electrically connected to the second end of the active region 220. The second substrate 600 has a second surface opposite to the first surface with a second contact structure 810, which is electrically connected to the bit line 250 and the first contact structure 800. That is, the active region 220 and the bit line 250 are electrically connected through the first contact structure 800 and the second contact structure 810. The first contact structure 800 and the second contact structure 810 are connected by bonding, and their contact surface is a bonding interface.

[0104] In some embodiments, the semiconductor structure further includes a first filling layer 801 disposed on the first surface and a second filling layer 811 disposed on the second surface. A first contact structure 800 is disposed within the first filling layer 801, and a second contact structure 810 is disposed within the second filling layer 811. The first filling layer 801 and the second filling layer 810 are connected. That is, the filling layer 801 and the second filling layer 811 fill the gap between the first surface and the second surface to provide support and sealing.

[0105] The semiconductor structure further includes a word line connection structure 213, a bit line connection structure 252, a first interlayer dielectric layer 360, a word line lead-out structure 700, and a bit line lead-out structure 701. The word line connection structure 213 is disposed within the first substrate 200 and electrically connected to the word line 210; the bit line connection structure 252 is disposed within the second substrate 600 and electrically connected to the bit line 250. The first interlayer dielectric layer 360 covers the first substrate 600 and the charge storage structure 240. The word line lead-out structure 700 penetrates the first interlayer dielectric layer 360 and is electrically connected to the word line connection structure 213. The bit line lead-out structure 701 penetrates the first interlayer dielectric layer 360 and the first substrate 200 and is electrically connected to the bit line connection structure 252.

[0106] In some embodiments, the semiconductor structure includes a core region (CORE) and a peripheral region (PERI), with word lines 210, bit lines 250, and charge storage structure 240 disposed in the core region (CORE); and word line connection structure 213 and bit line connection structure 252 disposed in the peripheral region (PERI).

[0107] The semiconductor structure further includes a charge storage lead-out structure 702. The charge storage lead-out structure 702 penetrates the first interlayer dielectric layer 360 and is electrically connected to the charge storage structure 240. Specifically, in this embodiment, the charge storage lead-out structure 702 is electrically connected to the silicon-germanium layer 350.

[0108] In the peripheral region PERI, the semiconductor structure is further provided with a peripheral transistor. The peripheral transistor includes a peripheral gate 400 located on the surface of the first substrate 201 and a source / drain region located within the first substrate 201. A conductive plug 232 is also disposed in the peripheral region PERI and is electrically connected to the source / drain region of the peripheral transistor. A connection pad 233 is connected to the conductive plug 232. A peripheral lead-out structure 703 is electrically connected to the connection pad 233. That is, the peripheral lead-out structure 703 is electrically connected to the source / drain region of the peripheral transistor through the connection pad 233 and the conductive plug 232.

[0109] The semiconductor structure provided in this disclosure has bit line 250 and charge storage structure 240 located on both sides of word line 210, which greatly reduces the device density on the same side of word line 210 and provides stability to the semiconductor structure.

[0110] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A first substrate is formed, the first substrate including a first substrate and active regions arranged in an array along a first direction and a second direction within the first substrate, word lines being disposed within the first substrate, the word lines extending along the second direction and at least covering opposite sides of the active regions; A charge storage structure is formed on the first substrate, and the charge storage structure is electrically connected to a first end of the active region; A second substrate is formed, the second substrate including a second substrate and bit lines disposed in the second substrate, the bit lines extending along the first direction; Using the first surface of the first substrate that is away from the charge storage structure and the second surface of the second substrate that has the bit line structure as connecting surfaces, the first substrate and the second substrate are connected, wherein the bit line is electrically connected to the second end of the active region, and the first end and the second end are disposed opposite to each other.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The first substrate and the second substrate are connected using a bonding process.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, Prior to the step of connecting the first substrate to the second substrate, the method further includes: thinning the first substrate to expose a second end of the active region.

4. The method for preparing a semiconductor structure according to claim 2, characterized in that, The following steps are included before performing the bonding process: The first surface of the first substrate and the second surface of the second substrate are subjected to plasma treatment.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that, The steps of connecting the first substrate and the second substrate using a bonding process include: The first surface of the first substrate and the second surface of the second substrate are subjected to hydrophilic treatment; The first surface of the first substrate and the second surface of the second substrate are bonded together; Perform annealing.

6. The method for preparing a semiconductor structure according to claim 2, characterized in that, The bonding process used to connect the first substrate and the second substrate includes the following steps: A first contact structure is formed on the first surface of the first substrate, and the first contact structure is electrically connected to the second end of the active region; A second contact structure is formed on the second surface of the second substrate, and the second contact structure is electrically connected to the bit line; The first contact structure and the second contact structure are used as bonding structures for bonding.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that, The step of forming a first contact structure on the first surface of the first substrate includes: forming a first contact layer on the first surface of the first substrate, the first contact layer including a first filler layer and the first contact structure disposed within the first filler layer; The step of forming a second contact structure on the second surface of the second substrate includes: A second contact layer is formed on the second surface of the second substrate, the second contact layer including a second filler layer and a second contact structure disposed within the second filler layer; The bonding step using the first contact structure and the second contact structure as bonding structures includes: bonding the first contact layer and the second contact layer as bonding layers, bonding the first filler layer to the second filler layer, and bonding the first contact structure to the second contact structure.

8. The method for preparing a semiconductor structure according to claim 1, characterized in that, After the step of forming the charge storage structure, the method includes: forming a first interlayer dielectric layer, the first interlayer dielectric layer covering the surface of the charge storage structure and the surface of the first substrate; after the step of connecting the first substrate and the second substrate, the method includes: forming a word line lead-out structure, a bit line lead-out structure and a charge storage lead-out structure from the side of the first substrate away from the second substrate, the word line lead-out structure penetrating the first interlayer dielectric layer and electrically connected to the word line, the bit line lead-out structure penetrating the first interlayer dielectric layer and the first substrate and electrically connected to the bit line, and the charge storage lead-out structure penetrating the first interlayer dielectric layer and electrically connected to the charge storage structure.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, The semiconductor structure includes a core region and a peripheral region. The word line, the bit line, and the charge storage structure are located in the core region. In the step of forming the first substrate, a word line connection structure is also formed in the peripheral region, and the word line connection structure is electrically connected to the word line. In the step of forming the second substrate, a bit line connection structure is also formed in the peripheral region, and the bit line connection structure is electrically connected to the bit line. In the step of forming the word line lead-out structure, the bit line lead-out structure, and the charge storage lead-out structure from the side of the first substrate away from the second substrate, the word line lead-out structure is formed in the peripheral region and is electrically connected to the word line connection structure, the bit line lead-out structure is formed in the peripheral region and is electrically connected to the bit line connection structure, and the charge storage lead-out structure is formed in the core region.

10. The method for preparing a semiconductor structure according to claim 8, characterized in that, The steps following the formation of the first interlayer dielectric layer also include: Provide a third base; Using the surface of the first interlayer dielectric layer as the connection surface, the third substrate is connected to the first substrate; Before the step of forming the word line lead-out structure, bit line lead-out structure, and charge storage lead-out structure from the side of the first substrate away from the second substrate, the method further includes: removing the third substrate.

11. The method for preparing a semiconductor structure according to claim 1, characterized in that, The step of forming word lines within the first substrate includes: Multiple spaced word line grooves are formed within the first substrate; Fill the grooves with character line material; Remove a portion of the word line material, retaining at least the word line material located on opposite sides of the active region to form the word line; A first isolation layer is formed between two adjacent word lines.

12. The method for preparing a semiconductor structure according to claim 1, characterized in that, Prior to the step of forming a charge storage structure on the first substrate, the method includes: forming a capacitor connection structure on the first substrate, the capacitor connection structure being electrically connected to a first end of the active region.

13. The method for preparing a semiconductor structure according to claim 12, characterized in that, The step of forming a charge storage structure on the first substrate includes: Form an interlayer support layer; A capacitor hole is formed, which penetrates the interlayer support layer to the capacitor connection structure; A lower electrode is formed inside the capacitor hole, the lower electrode is connected to the capacitor connection structure, and the sidewall of the lower electrode is spaced from the sidewall of the capacitor hole. A capacitor dielectric layer is formed on the lower electrode sidewall and the capacitor hole sidewall; An upper electrode is formed, which covers the surface of the capacitor dielectric layer.

14. The method for preparing a semiconductor structure according to claim 1, characterized in that, The steps for forming the second substrate include: Bit line trenches are formed within the second substrate; A second isolation layer is formed within the bit line trench, covering the inner wall of the bit line trench; A bit line is formed within the bit line trench, and the second isolation layer is disposed between the bit line and the second substrate.

15. A semiconductor structure formed by the preparation method according to any one of claims 1-14, characterized in that, include: The first substrate includes a first substrate and active regions arranged in an array along a first direction and a second direction within the first substrate; A word line is disposed within the first substrate, the word line extending along the second direction and at least covering opposite sides of the active region; A charge storage structure is disposed on the first substrate and electrically connected to the first end of the active region; The second substrate is disposed on the side of the first substrate away from the charge storage structure. The second substrate includes a second substrate and a bit line disposed within the second substrate. The bit line extends along the first direction and is electrically connected to the second end of the active region. The first end and the second end are disposed opposite to each other.

16. The semiconductor structure according to claim 15, characterized in that, The first substrate has a first surface, the first surface has a first contact structure, and the first contact structure is electrically connected to the second end of the active region; The second substrate has a second surface opposite to the first surface, the second surface has a second contact structure, and the second contact structure is electrically connected to the bit line and the first contact structure.

17. The semiconductor structure according to claim 16, characterized in that, It also includes a first filling layer disposed on the first surface and a second filling layer disposed on the second surface, wherein the first contact structure is disposed within the first filling layer, the second contact structure is disposed within the second filling layer, and the first filling layer and the second filling layer are connected.

18. The semiconductor structure according to claim 15, characterized in that, Also includes: A word line connection structure is disposed within the first substrate and is electrically connected to the word line; The bit line connection structure is disposed within the second substrate and is electrically connected to the bit line; A first interlayer dielectric layer covers the first substrate and the charge storage structure; The word line lead-out structure penetrates the first interlayer dielectric layer and is electrically connected to the word line connection structure. The bit line lead-out structure penetrates the first interlayer dielectric layer and the first substrate, and is electrically connected to the bit line connection structure.

19. The semiconductor structure according to claim 18, characterized in that, It also includes a core area and a peripheral area, with the word lines and bit lines disposed in the core area, and the word line connection structure and the bit line connection structure disposed in the peripheral area.

20. The semiconductor structure according to claim 18, characterized in that, It also includes a charge storage lead-out structure that penetrates the first interlayer dielectric layer and is electrically connected to the charge storage structure.

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