Semiconductor structure and method of manufacturing the same, memory

Abstract

The embodiments of the present disclosure disclose a semiconductor structure, a manufacturing method thereof and a memory. The semiconductor structure comprises: a substrate; a stack structure on the substrate, comprising at least a plurality of first dielectric layers; a first isolation layer in the stack structure extending along a first direction parallel to the surface of the substrate; the first isolation layer is used to divide the stack structure into a transistor region and a capacitor region; a plurality of stacked transistors in the transistor region; a plurality of stacked capacitor structures in the capacitor region; the capacitor structure comprises a first electrode, a second dielectric layer and a second electrode; the first electrode comprises a plurality of first parts parallel to the surface of the substrate and a plurality of second parts perpendicular to the surface of the substrate, and the first parts and the second parts are alternately connected end to end; a plurality of capacitor contact structures in the first isolation layer, and the capacitor contact structures are connected to the first electrode of the capacitor structure and the transistor on both sides respectively.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of semiconductor manufacturing, specifically to a semiconductor structure and its manufacturing method, and a memory. Background Technology

[0002] The history of semiconductor technology development is essentially a history of transistor size reduction. Starting with the 10-micron node in the 1970s, Moore's Law has guided us step by step to today's 5-nanometer scale. Throughout this process, whenever Moore's Law encountered difficulties, new technologies emerged to propel it forward. GAA (Gate-All-Around) transistors, as the next generation of FinFET (Fin Field Effect Transistor) technology, can further save space. Simultaneously, the use of 3D structural models further expands the spatial footprint, greatly contributing to the development of DRAM. Designing new spatial structures for 3D DRAM is an important research direction in this field. Summary of the Invention

[0003] In view of the above, embodiments of the present disclosure provide a semiconductor structure, a method for manufacturing the same, and a memory.

[0004] In a first aspect, embodiments of this disclosure provide a semiconductor structure comprising:

[0005] Substrate;

[0006] A stacked structure is located on the substrate; the stacked structure includes at least a plurality of first dielectric layers; the first dielectric layers are composed of silicon oxide layers and / or silicon nitride layers.

[0007] A first isolation layer is located in the stacked structure and extends along a first direction parallel to the surface of the substrate; the first isolation layer is used to divide the stacked structure into transistor regions and capacitor regions;

[0008] Multiple stacked transistors are located in the transistor region;

[0009] Multiple stacked capacitor structures are located in the capacitor region; each capacitor structure includes a first electrode, a second dielectric layer, and a second electrode.

[0010] The first electrode includes: a plurality of first portions parallel to the surface of the substrate and a plurality of second portions perpendicular to the surface of the substrate, wherein the first portions and the second portions are alternately connected end to end;

[0011] Multiple capacitive contact structures are located in the first isolation layer, and the two sides of the capacitive contact structures are respectively connected to the transistor and the first electrode of the capacitor structure.

[0012] In some embodiments, the second dielectric layer covers the inner wall and part of the outer wall of the first electrode; wherein the inner wall of the first electrode is located within the region surrounded by the first electrode; and the outer wall of the first electrode is located outside the region surrounded by the first electrode.

[0013] In some embodiments, the second electrode covers the surface of the second dielectric layer; wherein the surface of the second dielectric layer includes a first surface located within the region surrounded by the first electrode and a second surface located outside the region surrounded by the first electrode.

[0014] In some embodiments, the second electrode includes a third portion located within the region surrounded by the first electrode, and a fourth portion located outside the region surrounded by the first electrode.

[0015] In some embodiments, the thickness of the first electrode is 2 nm to 7 nm.

[0016] In some embodiments, a plurality of the first isolation layers are used to divide the stacked structure into a first transistor region, a capacitor region, and a second transistor region arranged in parallel.

[0017] In some embodiments, the capacitor region includes:

[0018] The second isolation layer extends along the first direction and divides the capacitor region into two sub-capacitor regions; wherein the two sub-capacitor regions include a plurality of symmetrically distributed, stacked capacitor structures.

[0019] In some embodiments, the capacitor region includes:

[0020] A plurality of fourth isolation layers extend along a second direction parallel to the substrate; wherein the second direction intersects the first direction; the fourth isolation layers are used to isolate the plurality of capacitor structures in the capacitor region.

[0021] In some embodiments, the transistor region includes:

[0022] A plurality of third isolation layers extend along a second direction parallel to the substrate; wherein the second direction intersects the first direction; the third isolation layers are used to isolate a plurality of transistors in the transistor region.

[0023] Secondly, embodiments of this disclosure also provide a method for manufacturing a semiconductor structure, the method comprising:

[0024] Provide substrate;

[0025] A stacked structure is formed on the substrate; wherein the stacked structure includes an alternately stacked first dielectric layer and a first polysilicon layer; the first dielectric layer is composed of a silicon oxide layer and / or a silicon nitride layer;

[0026] In the stacked structure, a first isolation layer is formed along a first direction parallel to the surface of the substrate; the first isolation layer is used to divide the stacked structure into a transistor region and a capacitor region; wherein, the first polysilicon layer located in the transistor region is used to form a plurality of transistors;

[0027] Remove the first polysilicon layer of the capacitor region to form a multi-layered recessed structure for accommodating the capacitor structure;

[0028] A plurality of capacitive contact structures are formed in the first isolation layer exposed by the recessed structure; the capacitive contact structures are used to connect the capacitor structure and the transistor;

[0029] The capacitor structure is formed in multiple layers based on the morphology of the recessed structure; the capacitor structure includes a first electrode, a second dielectric layer, and a second electrode.

[0030] The first electrode includes: a plurality of first portions parallel to the surface of the substrate and a plurality of second portions perpendicular to the surface of the substrate, wherein the first portions and the second portions are alternately connected end to end.

[0031] In some embodiments, forming the multilayer capacitor structure based on the morphology of the recessed structure includes:

[0032] The first electrode is formed based on the morphology of the inner wall of the recessed structure;

[0033] A second dielectric layer is formed covering the inner wall and part of the outer wall of the first electrode; wherein the inner wall of the first electrode is located within the region surrounded by the first electrode; and the outer wall of the first electrode is located outside the region surrounded by the first electrode.

[0034] A second electrode is formed covering the surface of the second dielectric layer; wherein the surface of the second dielectric layer includes a first surface located within the region surrounded by the first electrode and a second surface located outside the region surrounded by the first electrode.

[0035] In some embodiments, forming the first electrode based on the morphology of the inner wall of the recessed structure includes:

[0036] The inner wall of the recessed structure is covered with a first sacrificial material;

[0037] A second sacrificial material is filled into the recessed structure covered with the first sacrificial material;

[0038] Remove the first sacrificial material to form a first void in the second sacrificial material;

[0039] Atomic layer deposition is performed on the inner wall of the first pore to form the first electrode.

[0040] In some embodiments, forming a second dielectric layer covering the inner wall and a portion of the outer wall of the first electrode includes:

[0041] The second sacrificial material and at least a portion of the first dielectric layer are removed to form a second void; a portion of the outer wall of the first electrode is exposed in the second void;

[0042] A second dielectric layer is formed covering the inner wall of the first electrode and the portion of the outer wall.

[0043] In some embodiments, forming a first isolation layer in the stacked structure along a first direction parallel to the substrate surface includes:

[0044] The stacked structure is etched to form two parallel first trenches; the first trenches divide the stacked structure into a first transistor region, a capacitor region, and a second transistor region arranged in parallel.

[0045] The first trench is filled with a first dielectric material to form a first isolation layer.

[0046] In some embodiments, removing the first polysilicon layer of the capacitor region to form a multilayer recessed structure for accommodating the capacitor structure includes:

[0047] The capacitor region is etched to form a third trench parallel to the first trench, and the third trench divides the capacitor region into two parallel sub-capacitor regions.

[0048] The stacked structure is etched from the third trench to remove each of the first polysilicon layers located in the capacitor region of the stacked structure, and multiple recessed structures for accommodating the capacitor structure are formed on both sides of the third trench.

[0049] In some embodiments, forming a plurality of capacitive contact structures in the first insulating layer exposed by the recessed structure includes:

[0050] The first isolation layer is etched from the third trench to form a capacitor contact hole located at one end of the recessed structure of the two sub-capacitor regions;

[0051] The capacitor contact hole is filled with a first conductive material to form the capacitor contact structure.

[0052] In some embodiments, the method further includes:

[0053] A second medium material is formed to cover the inner wall of the third trench;

[0054] A second isolation layer is formed by filling the third trench, which is covered with the second dielectric material, with polycrystalline silicon material.

[0055] In some embodiments, forming the multilayer capacitor structure based on the morphology of the recessed structure includes:

[0056] Based on the morphology of the recessed structure located in the two sub-capacitor regions, two sets of symmetrically distributed, multi-layered capacitor structures are formed respectively.

[0057] In some embodiments, the method further includes:

[0058] The stacked structure is etched in the capacitor region along a second direction parallel to the substrate to form a plurality of fifth trenches; wherein the second direction intersects the first direction;

[0059] An insulating material is filled into the fifth trench to form a fourth isolation layer; the fourth isolation layer is used to isolate multiple capacitor structures in the capacitor region.

[0060] Thirdly, embodiments of this disclosure provide a memory, including:

[0061] A memory cell array; the memory cell array includes the semiconductor structure described in the first aspect above; and peripheral circuitry coupled to the memory cell array.

[0062] This disclosure provides a semiconductor structure, a method for manufacturing a semiconductor structure, and a memory. The semiconductor structure includes at least a first electrode, which comprises a plurality of first portions parallel to the surface of a substrate and a plurality of second portions perpendicular to the surface of the substrate, with the first portions and second portions alternately connected end-to-end. A second dielectric layer and a second electrode are formed according to the shape of the first electrode, thereby constructing a stacked capacitor structure on a semiconductor device of a certain size. This increases the area of ​​the first and second electrodes facing each other, thereby increasing the capacitance of the stacked capacitor structure and thus improving the storage capacity of the memory equipped with the capacitor structure. Attached Figure Description

[0063] Figure 1 A schematic diagram of a semiconductor structure provided in an embodiment of this disclosure;

[0064] Figures 2A to 2C This is a schematic diagram of the structure of a first electrode in a semiconductor structure proposed in this disclosure embodiment;

[0065] Figures 3A to 3C This is a schematic diagram of another first electrode structure in the semiconductor structure proposed in this disclosure embodiment;

[0066] Figure 4 A schematic diagram of another semiconductor structure provided in an embodiment of this disclosure;

[0067] Figure 5 A top view of a semiconductor structure provided in an embodiment of this disclosure;

[0068] Figure 6 This is a schematic flowchart of a method for forming a semiconductor structure provided in an embodiment of the present disclosure;

[0069] Figures 7 to 30 This is a schematic diagram of the structure corresponding to each step in the process of forming a semiconductor structure, as described in the embodiments of this disclosure.

[0070] Figures 31A to 50D This is a schematic diagram or top view of each cross section of the structure corresponding to each step in the process of forming the semiconductor structure according to the embodiments of this disclosure;

[0071] Figure 51 This is a three-dimensional structural diagram of a transistor and capacitor in a semiconductor structure provided in an embodiment of this disclosure. Detailed Implementation

[0072] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0073] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0074] In the embodiments of this disclosure, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0075] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0076] The deposition processes described in this disclosure include, but are not limited to: chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), sputtering, metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), and combinations thereof.

[0077] The growth processes described in this disclosure include, but are not limited to: vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), molecular beam epitaxy (MBE), ion beam epitaxy, solid phase epitaxy, and combinations thereof.

[0078] The etching processes described in this disclosure include, but are not limited to, dry etching, wet etching, and combinations thereof.

[0079] The semiconductor structure disclosed herein is at least a portion of the structure that will be used in subsequent processes to form the final device structure. Here, the final device may include a DRAM memory, or other memory chip or processing chip containing DRAM memory cells.

[0080] This disclosure provides a semiconductor structure, such as Figure 1 As shown, it includes: substrate 100;

[0081] A stacked structure is located on the substrate 100; the stacked structure includes at least a plurality of first dielectric layers 110; the first dielectric layer 110 is composed of a silicon oxide layer 102 and / or a silicon nitride layer 101.

[0082] A first isolation layer 130 is located in the stacked structure and extends along a first direction parallel to the surface of the substrate; the first isolation layer 130 is used to divide the stacked structure into a transistor region and a capacitor region;

[0083] Multiple stacked transistors 180 are located in the transistor region;

[0084] Multiple stacked capacitor structures are located in the capacitor region; the capacitor structure includes a first electrode 140, a second dielectric layer 150, and a second electrode 160.

[0085] The first electrode 140 includes: a plurality of first portions parallel to the surface of the substrate and a plurality of second portions perpendicular to the surface of the substrate, wherein the first portions and the second portions are alternately connected end to end;

[0086] Multiple capacitive contact structures 170 are located in the first isolation layer 130, and the two sides of the capacitive contact structure 170 are respectively connected to the transistor 180 and the first electrode 140 of the capacitor structure.

[0087] The substrate 100 in this embodiment may include a P-type semiconductor material substrate, such as a silicon (Si) substrate or a germanium (Ge) substrate, an N-type semiconductor substrate, such as an indium phosphide (InP) substrate, a composite semiconductor material substrate, such as a silicon-germanium (SiGe) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GeOI) substrate. Furthermore, the substrate 100 in this embodiment may also be a substrate that has already formed part of a device structure or has some wiring; this is not limited thereto.

[0088] The substrate 100 in this embodiment also has a stacked structure. The stacked structure includes an alternating first dielectric layer 110 and a polysilicon layer 103. The first dielectric layer 110 may include at least two different dielectric materials, such as a first dielectric material and a third dielectric material. The first dielectric material and the third dielectric material may be two dielectric materials with different etch selectivity ratios. In some embodiments, the first dielectric material and the third dielectric material are two dielectric materials with an etch selectivity ratio greater than or equal to a pre-etch selectivity value K, thereby allowing selective removal of either the first dielectric material or the third dielectric material.

[0089] In some embodiments, the first dielectric material is silicon nitride, and the third dielectric material is silicon oxide. The stacked structure includes a plurality of alternately stacked silicon nitride layers 101, polysilicon layers 103, silicon nitride layers 101, and silicon oxide layers 102. The stacked silicon nitride layers 101, polysilicon layers 103, silicon nitride layers 101, and silicon oxide layers 102 can be an alternating structure 120 in the stacked structure. That is, the stacked structure includes a plurality of alternating structures 120.

[0090] The semiconductor structure also includes a first isolation layer 130, which can be formed of a low dielectric constant material. That is, a dielectric with a relatively low dielectric constant (k) (lower than SiO2), including but not limited to inorganic porous materials (e.g., porous silicon oxide, porous silicon nitride, etc.) and organic porous materials (e.g., porous polyethylene, etc.). The first isolation layer 130 is used to divide the stacked structure into transistor regions and capacitor regions. Figure 1As shown, the first isolation layer 130 is a transistor region 300 along the negative X direction and a capacitor region 400 along the positive X direction. That is, the transistor region 300 and the capacitor region 400 are in the X direction, and the first isolation layer 130 extends along the Y direction, which intersects the X direction. Both the X and Y directions are parallel to the surface of the substrate. In this embodiment, the following description takes the X and Y directions being perpendicular as an example. It should be understood that in other embodiments, the X and Y directions are located in a plane parallel to the substrate surface, and they may have an angle other than perpendicular.

[0091] Transistor region 300 includes multiple stacked transistors 180. A polysilicon layer 103 in an alternating structure 120 is part of transistor 180.

[0092] The capacitor region 400 includes multiple stacked capacitor structures. One stacked capacitor structure includes a first electrode 140, a second dielectric layer 150, and a second electrode 160.

[0093] The first electrode 140 includes a plurality of first portions parallel to the substrate surface and a plurality of second portions perpendicular to the substrate surface, wherein the first portions and the second portions are alternately connected end-to-end. In some embodiments, the first electrode has the following shape: Figure 2A and Figure 2B As shown, Figure 2A The image shows a first portion of a first electrode, which includes a first planar structure 201, a second planar structure 202, a third planar structure 203, and a fourth planar structure 204 parallel to the substrate surface. Figure 2B The image shows a second portion of the first electrode, which includes a first vertical structure 211, a second vertical structure 212, a third vertical structure 213, and a fourth vertical structure 214 that are perpendicular to the substrate surface (i.e., perpendicular to the first and second directions).

[0094] Combination Figure 2A and Figure 2B The connection relationship between the first part and the second part is as follows: the first planar structure 201 is connected to the first vertical structure 211, the first vertical structure 211 is connected to the fourth planar structure 204, the fourth planar structure 204 is connected to the fourth vertical structure 214, the fourth vertical structure 214 is connected to the third planar structure 203, the third planar structure 203 is connected to the third vertical structure 213, the third vertical structure 213 is connected to the second planar structure 202, the second planar structure 202 is connected to the second vertical structure 212, and the second vertical structure 212 is connected to the first planar structure 201. In this way, the first part and the second part are connected end to end alternately.

[0095] The shape of the first electrode can also be as follows: Figure 3A and Figure 3B As shown, Figure 3AThe image shows a first portion of a first electrode, which includes a first planar structure 201, a second planar structure 202, a third planar structure 203, a fourth planar structure 204, a fifth planar structure 205, and a sixth planar structure 206 parallel to the surface of the substrate. Figure 3B The image shows a second portion of the first electrode, which includes a first vertical structure 211, a second vertical structure 212, a third vertical structure 213, a fourth vertical structure 214, a fifth vertical structure 215, and a sixth vertical structure 216 that are perpendicular to the substrate surface (i.e., perpendicular to the first and second directions).

[0096] Combination Figure 3A and Figure 3B The first planar structure 201 connects to the first vertical structure 211, the first vertical structure 211 connects to the sixth planar structure 206, the sixth planar structure 206 connects to the sixth vertical structure 216, the sixth vertical structure 216 connects to the fifth planar structure 205, the fifth planar structure 205 connects to the fifth vertical structure 215, the fifth vertical structure 215 connects to the fourth planar structure 204, the fourth planar structure 204 connects to the fourth vertical structure 214, the fourth vertical structure 214 connects to the third planar structure 203, the third planar structure 203 connects to the third vertical structure 213, the third vertical structure 213 connects to the second planar structure 202, the second planar structure 202 connects to the second vertical structure 212, and the second vertical structure 212 connects to the first planar structure 201. In this way, the first part and the second part are alternately connected end to end.

[0097] The above are just two implementation examples of the first electrode, such as Figure 2C The first electrode shown includes a recessed structure 220, such as Figure 3C The first electrode 140 shown includes two recessed structures 220. In this embodiment of the present disclosure, the first electrode may also be other structures including two or more recessed structures 220.

[0098] The first isolation layer 130 also includes a plurality of capacitive contact structures 170, which are used to connect the transistor 180 to the first electrode 140 of the capacitor structure. The material used for the capacitive contact structure is a first conductive material, such as a metal, alloy, or conductive compound, such as TiN (titanium nitride) or other metal silicides. Exemplarily, metal silicides include, but are not limited to, TiSi2 (titanium silicide), CoSi2 (cobalt silicide), and nickel alloy (e.g., NiPt, NiAl, NiY) silicides. The capacitive contact structure 170 can be used to reduce contact resistance.

[0099] The semiconductor structure in this embodiment includes multiple stacked transistors and multiple stacked capacitor structures. Both the capacitor structures and transistors are three-dimensionally stacked, which increases the number of memory cells (one transistor and one capacitor) contained in the semiconductor structure in the same space.

[0100] The first electrode of the capacitor structure in this embodiment includes a plurality of first portions and a plurality of second portions, which increases the area of ​​the first electrode of the capacitor structure and increases the capacitance of the capacitor structure.

[0101] In this embodiment, the capacitor structure in the capacitor region and the transistor in the transistor region are in contact through a capacitor contact structure, which helps to reduce contact resistance.

[0102] In some embodiments, such as Figure 1 As shown, the second dielectric layer 150 covers the inner wall and / or part of the outer wall of the first electrode 140; wherein the inner wall of the first electrode 140 is located within the area surrounded by the first electrode; and the outer wall of the first electrode 140 is located outside the area surrounded by the first electrode.

[0103] like Figure 2A and Figure 3A This is a schematic diagram of the structure of the first electrode. The first electrode is a hollow, closed structure. The inner wall of the first electrode is the surface that contacts the region 210 enclosed by the first electrode. The outer wall of the first electrode is the surface outside the region 210 enclosed by the first electrode.

[0104] like Figure 1 In the semiconductor structure shown, a portion of the outer wall of the first electrode 140 is in contact with a portion of the first isolation layer 130 and the capacitor contact structure. Therefore, this portion of the outer wall is not covered by the second dielectric layer. The remaining outer walls of the first electrode that are not in contact with other materials or structures, as well as all the inner walls, can be covered by the second dielectric layer 150. By allowing the second dielectric layer 150 to cover as much of the exposed inner and outer walls of the first electrode 140 as possible, the storable capacitance of the capacitor structure formed based on the first electrode 140 can be increased, thereby improving the performance of the DRAM memory.

[0105] In some embodiments, such as Figure 1 As shown, the second electrode 160 covers the surface of the second dielectric layer 150; wherein the surface of the second dielectric layer 150 includes a first surface located within the region surrounded by the first electrode 140 and a second surface located outside the region surrounded by the first electrode 140.

[0106] like Figure 1As shown, the second dielectric layer 150 includes a first portion 151, a second portion 152, and a third portion 153. The first portion 151 is formed on the inner wall of the first electrode 140, and the second and third portions 152 are formed on the outer wall of the first electrode 140, with the second portion 152 located in a recessed structure. A second electrode 160 is covered on the surface of the second dielectric layer 150 that does not contact the first electrode 140. The second electrode 160 includes a first portion 161 of the second electrode covering the first portion 151, a second portion 162 of the second electrode covering the second portion 152, and a third portion 163 of the second electrode covering the third portion 153.

[0107] In some embodiments, such as Figure 1 As shown, the second electrode includes: a third portion, namely the first portion 161 of the second electrode, located within the area surrounded by the first electrode, and a fourth portion, namely the second portion 162 and the third portion 163 of the second electrode, located outside the area surrounded by the first electrode.

[0108] In some embodiments, the thickness of the first electrode can be from 2 nm to 7 nm.

[0109] In some embodiments, such as Figure 4 As shown, multiple first isolation layers 130 are used to divide the stacked structure into a first transistor region 301, a capacitor region 400, and a second transistor region 302 arranged in parallel. In some embodiments, transistor regions can be disposed on both the positive and negative sides of the capacitor region along the X direction, respectively, which are designated as the first transistor region 301 and the second transistor region 302. In some embodiments, a third transistor region can be disposed on the first transistor region 301 along the negative X direction, and another capacitor region 400 can be disposed on the third transistor region along the negative X direction; similarly, a fourth transistor region can be disposed on the second transistor region 302 along the positive X direction, and yet another capacitor region 400 can be disposed on the fourth transistor region along the positive X direction, and so on. This allows the storage capacity of the DRAM memory to be continuously expanded in the X direction.

[0110] In some embodiments, such as Figure 4 As shown, the capacitor region 400 includes:

[0111] The second isolation layer 131 extends along the first direction (i.e., the Y direction) and divides the capacitor region 400 into two sub-capacitor regions; wherein each of the two sub-capacitor regions includes a plurality of symmetrically distributed, stacked capacitor structures. The two sub-capacitor regions include a first sub-capacitor region 411 and a second sub-capacitor region 412. The first sub-capacitor region 411 and the first transistor region 301 form a DRAM memory region, and the second sub-capacitor region 412 and the second transistor region 302 form another DRAM memory region.

[0112] In some embodiments, such as Figure 5 As shown, Figure 5 The capacitor region 400 described above is a top view (i.e., a schematic diagram in the XY plane). The capacitor region 400 includes:

[0113] Multiple fourth isolation layers 132 extend along a second direction (i.e., the X direction) parallel to the substrate; wherein the second direction intersects the first direction (i.e., the Y direction), and this embodiment is described as having the second direction perpendicular to the first direction. The fourth isolation layers 132 are used to isolate multiple capacitor structures 190 of the capacitor region 400. The capacitor region 400 includes multiple stacked capacitor structures, which are located in the XY plane and include multiple non-connected capacitor structures 190 arranged along the Y direction, with fourth isolation layers 132 between the capacitor structures 190. The fourth isolation layers 132 are used to isolate the electrical connections between adjacent capacitor structures 190 and to reduce leakage current in the capacitor structures 190. Figure 1 As shown, the capacitor region 400 is on the XZ plane and includes multiple unconnected capacitor structures 190 stacked along the Z direction.

[0114] In some embodiments, such as Figure 5 As shown, the transistor region 300 includes:

[0115] Multiple third isolation layers 133 extend along a second direction (i.e., the X direction) parallel to the substrate; wherein the second direction intersects a first direction (i.e., the Y direction), and this embodiment is described as having the second direction perpendicular to the first direction. The third isolation layers 133 are used to isolate each transistor 180 in the transistor region 300. The transistor region 300 includes multiple stacked transistors 180 on the XY plane, comprising multiple non-connected transistors 180 arranged along the Y direction, with a third isolation layer 133 between each transistor 180. The third isolation layers 133 isolate the electrical connections between adjacent transistors 180 and reduce leakage current in the transistors 180. Figure 1As shown, the transistor region 300 is located on the XZ plane and includes a plurality of unconnected transistors 180 stacked along the Z direction. In some embodiments, the isolation materials used for each isolation layer may be different. In some embodiments, at least two of the isolation materials used for each isolation layer are the same, or all of them may be the same. This disclosure does not impose any limitations on this.

[0116] This disclosure also provides a method for manufacturing a semiconductor structure, such as... Figure 6 As shown, it includes:

[0117] Step S101: Provide a substrate;

[0118] Step S102: Form a stacked structure on the substrate; wherein the stacked structure includes alternating stacked first dielectric layers and first polysilicon layers; the first dielectric layer is composed of a silicon oxide layer and / or a silicon nitride layer;

[0119] Step S103: In the stacked structure, a first isolation layer is formed along a first direction parallel to the surface of the substrate; the first isolation layer is used to divide the stacked structure into a transistor region and a capacitor region; wherein, the first polysilicon layer located in the transistor region is used to form a plurality of transistors;

[0120] Step S104: Remove the first polysilicon layer of the capacitor region to form a multi-layer recessed structure for accommodating the capacitor structure;

[0121] Step S105: A plurality of capacitive contact structures are formed in the first isolation layer exposed by the recessed structure; the capacitive contact structures are used to connect the capacitor structure and the transistor;

[0122] Step S106: Form a multilayer capacitor structure based on the morphology of the recessed structure; the capacitor structure includes a first electrode, a second dielectric layer, and a second electrode.

[0123] The first electrode includes: a plurality of first portions parallel to the surface of the substrate and a plurality of second portions perpendicular to the surface of the substrate, wherein the first portions and the second portions are alternately connected end to end.

[0124] First, step S101 is performed: providing a substrate. The surface of the substrate can be any surface perpendicular to the substrate thickness direction. The substrate thickness direction or the direction perpendicular to the substrate surface is defined as the Z direction, any direction along the substrate surface is defined as the X direction, and the direction along the substrate surface intersecting the X direction is defined as the Y direction. The substrate used in this embodiment may be a silicon substrate.

[0125] Then, step S102 is performed to form a substrate such as... through a growth process or a deposition process. Figure 7The stacked structure shown includes multiple alternating structures 120, each of which includes at least a first dielectric layer. The first dielectric layer may be a silicon oxide layer 102, a silicon nitride layer 101, or a composite layer of silicon nitride and silicon oxide layers 102. In some embodiments, the process of forming an alternating structure 120 involves first forming a silicon nitride layer 101 on a substrate using a deposition process, then forming a polysilicon layer 103 on the silicon nitride layer using a deposition process, then depositing a silicon nitride layer 101 on the polysilicon layer 103 using a deposition process, and finally depositing a silicon oxide layer 102 on the silicon nitride layer 101 using a deposition process. The process of forming an alternating structure 120 is treated as a cycle, and multiple alternating structures 120 can be deposited on the substrate 100 through multiple cycles. In some embodiments, between steps S101 and S102, an insulating layer 104 may also be deposited on the substrate. The insulating layer 104 is made of an insulating material, such as silicon oxide. The insulating layer 104 is used to isolate the electrical connection between the substrate and the semiconductor devices subsequently formed in the stacked structure. Figure 7 The cross-sectional view of the stacked structure shown along the XZ plane is as follows: Figure 8 As shown.

[0126] Continuing with step S103, the first section X1 of the stacked structure in the X direction is etched along the Y direction parallel to the substrate surface using an etching process. After etching, a first trench 105 can be formed in the stacked structure. The width of the first trench 105 in the X direction is X1. The first trench 105 can extend along the Y direction, meaning its length in the Y direction can be equal to the length of the stacked structure in the Y direction. Figure 9 As shown, the first trench 105 divides the stacked structure into two parts.

[0127] In other embodiments, at least two first trenches 105 may be formed in the stacked structure after etching. Both first trenches 105 extend along the Y direction and divide the stacked structure into at least three parts.

[0128] The following is based on Figure 9 The following describes an embodiment of the present disclosure using the etching process to form a first trench 105 as an example.

[0129] right Figure 9 The first trench 105 in the middle is deposited with a first isolation material using a deposition process, which can form such as Figure 10The diagram shows a semiconductor structure including a first isolation layer 130 located in a first trench. The first isolation material may be a low dielectric constant material. The side of the first isolation layer 130 along the negative X direction may be designated as transistor region 300, which can be used to form multiple transistor layers stacked along the Z direction, each transistor layer forming multiple transistors arranged along the Y direction. The first polysilicon layer 103 in transistor region 300 (i.e., the aforementioned polysilicon layer 103) is used to form transistor layers and further form multiple transistors. The side of the first isolation layer 130 along the positive X direction may be designated as capacitor region 400, which can be used to form multiple capacitor structure layers stacked along the Z direction, each capacitor structure layer forming multiple capacitor structures arranged along the Y direction.

[0130] Continue to step S104, using an etching process, for example, a lateral etching process, to laterally etch the material from the Y or X direction. Figure 10 The first polysilicon layer 103 in the capacitor region 400 shown is removed to form a structure as shown below. Figure 11 The semiconductor structure shown includes a recessed structure 401, which can be used to accommodate a capacitor structure, meaning the capacitor structure can be subsequently formed in the recessed structure 401. When etching the first polysilicon layer 103, in the Z direction, the silicon nitride layer 101 adjacent to the first polysilicon layer 103 can be used as an etch stop layer; in the X direction, the first isolation layer 130 can be used as an etch stop layer. That is, the first isolation material has a low etch selectivity relative to the polysilicon.

[0131] Then proceed to step S105, as follows: Figure 11 As shown, the recessed structure 401 exposes a first isolation layer 130 in contact with the first polysilicon layer in the capacitor region. Further partial etching of the exposed first isolation layer 130 can be performed to form a structure as shown... Figure 12 The capacitor contact hole 402 is shown. The length of the capacitor contact hole 402 in the Z direction is Z1, and its projection in the Z direction can fall entirely within the length Z2 of the recessed structure 401 in the Z direction. When etching the first isolation layer 130 exposed from the recessed structure 401, the polysilicon layer in the transistor region can be used as an etching stop layer in the X direction.

[0132] A first conductive material (e.g., metal silicide) is deposited on the capacitor contact hole 402 using a deposition process to form a structure such that... Figure 13 The capacitor contact structure 170 is shown. The capacitor contact structure 170 is subsequently used to electrically connect the capacitor structure formed in the capacitor region to the transistor formed in the transistor region and reduce the ohmic contact between them.

[0133] Continuing with step S106, a multilayer capacitor structure is deposited based on the morphology of the recessed structure 401. The capacitor structure includes a first electrode, a second dielectric layer, and a second electrode. The shape of the first electrode can be as follows: Figure 2A and Figure 3A As shown.

[0134] In this embodiment of the disclosure, a three-dimensional stacked transistor region 300 and capacitor region 400 are formed by dividing the stacked structure into partitions to form transistor region 300 and capacitor region 400 respectively. The capacitor structure in capacitor region 400 extends parallel to the substrate surface. The capacitor shape of the capacitor region can be formed based on different shapes formed after etching the first polysilicon in the capacitor region.

[0135] In some embodiments, step S106, forming a multilayer capacitor structure based on the morphology of the recessed structure, includes:

[0136] Step S201: Form the first electrode based on the morphology of the inner wall of the recessed structure;

[0137] Step S202: Form a second dielectric layer covering the inner and outer walls of the first electrode; wherein the inner wall of the first electrode is located within the area surrounded by the first electrode; and the outer wall of the first electrode is located outside the area surrounded by the first electrode.

[0138] Step S203: Form a second electrode covering the surface of the second dielectric layer; wherein the surface of the second dielectric layer includes a first surface located within the region surrounded by the first electrode and a second surface located outside the region surrounded by the first electrode.

[0139] In some embodiments, step S106 may be replaced by steps S201 to S203.

[0140] In some embodiments, step S201, forming the first electrode based on the morphology of the inner wall of the recessed structure, includes:

[0141] Step S301: Cover the inner wall of the recessed structure with a first sacrificial material;

[0142] Step S302: Fill the recessed structure covered with the first sacrificial material with a second sacrificial material;

[0143] Step S303: Remove the first sacrificial material and form a first void in the second sacrificial material;

[0144] Step S304: Perform atomic layer deposition (ALD) on the inner wall of the first vacancy to form the first electrode.

[0145] In some embodiments, step S201 can be replaced by steps S301 to S304.

[0146] First, execute step S301, in such a way Figure 13 The inner wall of the recessed structure 401 shown is deposited with a first sacrificial material using a deposition process (e.g., ALD) to form a structure as shown. Figure 14 The semiconductor structure shown is a first sacrificial layer 403 covering the inner wall of the recessed structure 401. The first sacrificial layer 403 can be removed in subsequent steps using a wet etching process or an ashing process. When the first sacrificial material is removed using an ashing process, it can be an organic material (e.g., carbon).

[0147] Then proceed to step S302, as follows: Figure 14 A second sacrificial material continues to be deposited in the recessed structure 401 covered with the first sacrificial material to form a structure like... Figure 15 The second sacrificial layer 404 shown, together with the first sacrificial layer 403, fills the entire recessed structure 401. The second sacrificial material can be silicon nitride or other materials.

[0148] Then, step S303 is performed to remove the first sacrificial material using a wet etching process or an ashing process. In some embodiments, if the first sacrificial material is relative to... Figure 15 Other materials in the semiconductor structure shown (including polysilicon, second sacrificial material, silicon oxide, silicon nitride, etc.) have a higher etch selectivity, allowing the semiconductor structure to be immersed in an etching solution and the first sacrificial layer to be removed using wet etching technology.

[0149] In other embodiments, if the first sacrificial material is an organic substance (e.g., carbon), an ashing process can be used to remove it. Figure 15 The first sacrificial layer in the semiconductor structure shown. The specific steps of the ashing process are as follows: First, the first sacrificial layer 403 in the semiconductor structure is removed by high temperature and ash is generated. Then, the generated ash is dissolved with acid (including but not limited to HNO3, H2SO4, (NH4)2SO4, (NH4)2HPO4).

[0150] Thus, it was formed as follows Figure 16 The first gap 405 shown is located within the second sacrificial material. It should be noted that before performing step S303, the supporting structure 406 can be connected to... Figure 15 The semiconductor structure shown is bonded to prevent the second sacrificial layer 404 from losing its supporting structure after the first sacrificial layer 403 is removed.

[0151] Then proceed to step S304, as follows: Figure 16Atomic layer deposition (ALD) of a second conductive material is performed on the inner wall of the first void 405 to form the first electrode 140. It is important to note that the first electrode 140 is deposited only on the surface of the first void 405, and the deposition thickness can be between 2 nm and 7 nm, without completely filling the first void 405. That is, the shape of the first electrode 140 is completely conformed to the shape of the first void 405. The second conductive material includes, but is not limited to, ruthenium (Ru), tungsten (W), and tantalum (Ta).

[0152] In some embodiments, in step S202, forming a second dielectric layer covering the inner wall and part of the outer wall of the first electrode includes:

[0153] Step S401: Remove the second sacrificial material and at least a portion of the first dielectric layer to form a second void; the outer wall of the first electrode is exposed in the second void;

[0154] Step S402: Form a second dielectric layer covering the inner wall and part of the outer wall of the first electrode.

[0155] In some embodiments, step S202 may be replaced by steps S401 to S402.

[0156] First, perform step S401 and use an etching process to remove... Figure 17 The silicon nitride layer 101 in contact with the surface of the first electrode 140 and the second sacrificial layer 404 in contact with the surface of the first electrode 140 are respectively. In some embodiments, the second sacrificial material may be silicon nitride, so that the silicon nitride layer 101 and the second sacrificial layer 404 can be removed in a single etching process. If the second sacrificial material is a different material from the silicon nitride layer, two etching processes can be used, first removing the silicon nitride layer 101 and then removing the second sacrificial layer 404; or first removing the second sacrificial layer 404 and then removing the silicon nitride layer 101. In this way, a structure is formed as shown in the figure. Figure 18 The semiconductor structure shown includes a second void 407, in which the outer wall of the first electrode 140 is exposed. Figure 18 The diagram shows a schematic of the semiconductor structure after all silicon nitride layers have been removed from the capacitor region.

[0157] In some embodiments, if removed Figure 17 The silicon nitride layer 101 and the second sacrificial layer 404 in the portion in contact with the surface of the first electrode 140 form a structure as shown in the figure. Figure 19 The semiconductor structure shown includes a second void 407 and a thinned silicon nitride layer 101.

[0158] Then, step S402 is performed, using a deposition process as follows: Figure 18In the semiconductor structure shown, a third dielectric material is deposited on both the inner and outer walls of the first electrode to form a structure as shown. Figure 20 The second dielectric layer 150 shown covers the inner and outer walls of the first electrode 140. The third dielectric material can be a high dielectric constant material, which refers to a material with a dielectric constant higher than that of SiO2, where the dielectric constant is 3.7. In fact, the second dielectric layer can be formed not only on the inner and outer walls of the first electrode but also on all exposed surfaces in the capacitor region, such as the sidewall where the second void contacts the first insulating layer and the sidewall where the second void contacts the silicon oxide layer 102.

[0159] In some embodiments, step S103, forming a first isolation layer in the stacked structure along a first direction parallel to the substrate surface, includes:

[0160] Step S501: Etch the stacked structure to form two parallel first trenches; the first trenches divide the stacked structure into a first transistor region, a capacitor region, and a second transistor region arranged in parallel.

[0161] Step S502: Fill the first trench with a first medium material to form a first isolation layer.

[0162] In some embodiments, when it is necessary to form more than two first isolation layers, step S103 can be replaced by steps S501 to S502. The following description takes the formation of two first isolation layers as an example.

[0163] First, step S501 is performed, whereby the first section X1 and the second section X2 of the stacked structure in the X direction are etched along the Y direction parallel to the substrate surface using an etching process. After etching, two first trenches 105 are formed in the stacked structure. The width of one first trench 105 in the X direction is X1, and the width of the other first trench 105 in the X direction is X2. X1 can be the same as or different from X2. Both the first trench and the third trench can extend along the Y direction, that is, their length in the Y direction can be equal to the length of the stacked structure in the Y direction.

[0164] like Figure 21 As shown, the two first grooves 105 will Figure 8 The stacked structure shown is divided into three parts: a first transistor region 301 located on the negative X-direction side of a first trench 105 with a width of X1; a capacitor region 400 located between the first trench 105 with a width of X1 and the first trench 105 with a width of X2; and a second transistor region 302 located on the positive X-direction side of the first trench 105 with a width of X2. Multiple first polysilicon layers 103 located in the first transistor region 301 and the second transistor region 302 can be used to form multiple transistors in subsequent steps.

[0165] In some embodiments, it may be based on, such as Figure 21 The semiconductor structure shown forms multiple 2T1C DRAM memory cells or multiple 1T1C DRAM memory cells.

[0166] Then execute step S502, for Figure 21 The two first trenches 105 in the middle are deposited with a first isolation material using a deposition process, which can form such as Figure 22 The semiconductor structure shown consists of two first isolation layers 130 located in two first trenches 105. The first isolation material may be a low dielectric constant material.

[0167] The embodiments disclosed herein may also form three or more first trenches and three or more first isolation layers to divide more sub-capacitor regions and sub-transistor regions, thereby forming a denser DRAM memory cell array structure.

[0168] In some embodiments, step S104, removing the first polysilicon layer of the capacitor region to form a multilayer recessed structure for accommodating the capacitor structure, includes:

[0169] Step S601: Etch the capacitor region to form a third trench parallel to the first trench, wherein the third trench divides the capacitor region into two parallel sub-capacitor regions.

[0170] Step S602: Etch the stacked structure from the third trench to remove each of the first polysilicon layers located in the capacitor region of the stacked structure, and form multiple recessed structures on both sides of the third trench to accommodate the capacitor structure.

[0171] In some embodiments, step S104 may be replaced by steps S601 to S602.

[0172] Firstly, regarding Figure 10 or Figure 21 Further etching is performed on the capacitor region 400 to form a shape like... Figure 23 The third trench 107 is shown. In some embodiments, the third trench 107 may be formed together with one first trench 105 and / or two first trenches 105; in other embodiments, the third trench may be formed separately from the first and second first trenches. The third interval X3 of the stacked structure in the X direction is etched along the Y direction parallel to the substrate surface using an etching process to form the third interval X3 of the stacked structure as shown. Figure 23The third trench 107 shown is located between the first trench 105 with a width of X1 and the first trench 105 with a width of X2. The area between the first trench 105 with a width of X1 and the third trench 107 is the first sub-capacitor region 411, and the area between the third trench 107 and the first trench 105 with a width of X2 is the second sub-capacitor region 412.

[0173] Then, step S602 is performed: the stacked structure used to form the capacitor region is etched from the third trench using a wet etching process to remove... Figure 23 The first polysilicon layer 103 in the first sub-capacitor region 411 and the second sub-capacitor region 412 forms, as shown in the figure. Figure 24 As shown, multiple recessed structures 401 for accommodating capacitor structures are formed on both sides of the third trench 107. That is, multiple recessed structures 401 can be formed in each sub-capacitor region. When the number of sub-capacitor regions is 2, the storage capacity is doubled compared to when the number of capacitor regions is 1.

[0174] In some embodiments, step S105, forming a plurality of capacitive contact structures in the first insulating layer exposed in the recessed structure, includes:

[0175] Step S701: Etch the first isolation layer from the third trench to form a capacitor contact hole at one end of the recessed structure in the two sub-capacitor regions;

[0176] Step S702: Fill the capacitor contact hole with a first conductive material to form the capacitor contact structure.

[0177] In some embodiments, step S105 can be replaced by steps S701 to S702.

[0178] First, execute step S701, as follows: Figure 25 As shown, the recessed structure 401 exposes a first isolation layer 130 that contacts the first polysilicon layer in the plurality of sub-capacitor regions. Etching can then be performed on all exposed first isolation layers 130 to form... Figure 26A Multiple capacitor contact holes 402 are shown. The length of the capacitor contact hole 402 in the Z direction is Z1, and its projection in the Z direction falls entirely within the length Z2 of the recessed structure 401 in the Z direction. When etching the exposed first isolation layer, the polysilicon layer in each sub-transistor region can be used as an etching stop layer in the X direction.

[0179] Then, step S702 is performed, filling the capacitor contact hole 402 with a first conductive material (e.g., metal silicide) using a deposition process to form a structure as shown in the image. Figure 26B The multiple capacitor contact structures 170 shown are illustrated.

[0180] The capacitor contact structure 170 is subsequently used to connect the capacitor structure formed in the first sub-capacitor region 411 to the transistor formed in the first transistor region 301, and also to connect the capacitor structure formed in the second sub-capacitor region 412 to the transistor formed in the second transistor region 302.

[0181] In some embodiments, between step S302 and step S303, the method further includes:

[0182] Step S801: Form a second medium material covering the inner wall of the third trench;

[0183] Step S802: Fill the third trench covered with the second dielectric material with polycrystalline silicon material to form a second isolation layer.

[0184] After steps S301 and S302 are completed, the inner wall of the recessed structure is covered with a first sacrificial layer and a second sacrificial layer. Then, before step S303, step S801 can be performed, as follows... Figure 27 In the semiconductor structure shown, a second dielectric material is deposited using a deposition process to cover the inner wall of its third trench 107, forming a structure as shown. Figure 28 The second dielectric material layer 108 is shown. The second dielectric material layer 108 may also cover, for example, Figure 27 The upper surface of the semiconductor structure shown.

[0185] The second dielectric material can be a low dielectric constant material. The second dielectric material can be the same as or different from the first insulating material.

[0186] The second dielectric material layer is used to isolate the electrical connection between the first sub-capacitor region and the second sub-capacitor region, and to reduce parasitic capacitance.

[0187] Continue with step S802, and continue using the deposition process to deposit polycrystalline silicon material in the third trench covered with the second dielectric material, forming a structure as shown in the image. Figure 29 The second polysilicon layer 109 is shown. The second polysilicon layer 109 covers not only the second dielectric material layer 108 located in the third trench 107, but also the second dielectric material layer 108 located on the upper surface of the semiconductor structure. The second dielectric material layer 108 and the second polysilicon layer 109 together form the second isolation layer 131. The second polysilicon layer 109 is used to electrically connect the upper electrodes of all capacitor structures in the stacked structure together, and then connect them to ground or other potentials.

[0188] In some embodiments, step S106, forming the multilayer capacitor structure based on the morphology of the recessed structure, includes:

[0189] Step S901: Based on the morphology of the recessed structure located in the two sub-capacitor regions, two sets of symmetrically distributed, multi-layered capacitor structures are formed respectively.

[0190] In some embodiments, steps S801 and S802 may be performed first, followed by steps S601 to S602, to form recessed structures on both sides of the second dielectric layer and the second isolation layer for accommodating capacitor structures.

[0191] Then, step S901 is executed: based on the morphology of the recessed structure located in the two sub-capacitor regions, two sets of symmetrically distributed, multi-layered capacitor structures are formed. That is, the capacitor structure formed by the recessed structure in the first sub-capacitor region is symmetrical to the capacitor structure formed by the recessed structure in the second sub-capacitor region.

[0192] In some embodiments, based on the morphology of the recessed structure located in the two sub-capacitor regions, two sets of symmetrically distributed, multi-layered capacitor structures can be formed simultaneously. That is, the capacitor structures in different sub-capacitor regions are formed simultaneously.

[0193] In other embodiments, based on the morphology of the recessed structure located in the first sub-capacitor region (or the second sub-capacitor region), multiple stacked capacitor structures in the first sub-capacitor region (or the second sub-capacitor region) can be formed first. Then, based on the morphology of the recessed structure located in the second sub-capacitor region (or the first sub-capacitor region), multiple stacked capacitor structures in the second sub-capacitor region (or the first sub-capacitor region) can be formed first. That is, the capacitor structures in different sub-capacitor regions are formed step by step.

[0194] In some embodiments, the method further includes:

[0195] Step S1001: Etch the stacked structure in the capacitor region along a second direction parallel to the substrate to form a plurality of fifth trenches; wherein the second direction intersects the first direction;

[0196] Step S1002: Fill the fifth trench with insulating material to form a fourth isolation layer; the fourth isolation layer is used to isolate multiple capacitor structures in the capacitor region.

[0197] In some embodiments, firstly, a layer of photoresist can be applied to the upper surface of the capacitor region and transistor region of the semiconductor structure. A patterned photomask is then used to align the areas to be removed, followed by exposure. The photoresist can be a negative photoresist, in which case the photoresist corresponding to the photomask pattern is removed, forming a structure like... Figure 30 ( Figure 30 The top view of the semiconductor structure shows a photoresist layer 501 and multiple openings 502, with the openings 502 revealing the uppermost silicon oxide layer of the stacked structure.

[0198] Continue with step S1001, for example... Figure 30 In the semiconductor structure shown, the portion not covered by photoresist, i.e., the multiple openings 502, is etched downwards. The substrate can serve as the etch stop layer for this etching, thus forming multiple fifth trenches 503 separated along the Y direction. The length (extension distance along the X direction) and width (extension distance along the Y direction) of the fifth trenches 503 and the openings 502 can be the same.

[0199] Continue to step S1002, using a deposition process such as... Figure 30 The fifth trench 503 shown is filled with insulating material to form a fourth isolation layer; the fourth isolation layer is used to isolate the plurality of capacitor structures arranged along the Y direction in the capacitor region. The insulating material may be the same as or different from the first dielectric material or the second dielectric material.

[0200] This disclosure also provides a memory, including:

[0201] A memory cell array; the memory cell array includes the semiconductor structure described in the first aspect above; and peripheral circuitry coupled to the memory cell array.

[0202] The semiconductor structure formed in the above embodiments can be used to form a memory cell array and a portion thereof. The memory cell array can be coupled with peripheral circuitry arranged around it to jointly form a memory.

[0203] This disclosure also provides the following examples:

[0204] Step S101: Provide a substrate. The following description will use a Si substrate as an example.

[0205] Step S102: Forming on the Si substrate 100 as shown in the figure Figure 31A The stacked structure shown includes multiple alternating structures 120, each alternating structure 120 including a silicon nitride layer 101, a polysilicon layer 103, a silicon nitride layer 101 and a silicon oxide layer 102.

[0206] Figure 31B For along Figure 31A Cross-sectional view along the AA' direction; Figure 31C For along Figure 31A Cross-sectional view along the BB' direction; Figure 31D For along Figure 31A Cross-sectional view along the CC' direction; Figure 31E For along Figure 31A Cross-sectional view along the DD' direction;

[0207] Figure 31AThe stacked structure is divided into at least 5 regions, wherein the first region 10 is subsequently used to form the first bit line region; the second region 20 is subsequently used to form the first transistor region; the third region 30 is subsequently used to form the capacitor region; the fourth region 40 is subsequently used to form the second transistor region; and the fifth region 50 is subsequently used to form the second bit line region.

[0208] Figure 31A Line AA' is located in the second region 20 and extends in the Y direction. Line DD' is located in the third region 30 and also extends in the Y direction. Line CC' is located at the junction of the third and fourth regions and also extends in the Y direction. Line BB' crosses part of the second region 20, the third region 30, and the fourth region 40 and extends in the X direction.

[0209] Step S501: Etch the stacked structure to form at least two parallel first trenches; the first trenches divide the stacked structure into a first transistor region, a capacitor region, and a second transistor region arranged in parallel.

[0210] In such Figure 31A On the upper surface of the stacked structure shown (i.e., the topmost silicon oxide layer), a second photoresist layer is deposited using a deposition process. A patterned photomask is used to align the areas to be removed, and then exposure is performed. This photoresist can be a negative photoresist; in this case, the photoresist corresponding to the photomask pattern is removed, forming a layer as shown. Figure 32 The third photoresist layer 60 shown covers a portion of the first region, specifically the sixth region 11; it also covers a portion of the second region, specifically the seventh region 21; the third region, specifically the eighth region 31; the fourth region, specifically the ninth region 41; and the fifth region, specifically the tenth region 51. The uncovered stacked structure of the third photoresist layer 60 forms a frame opening 61. The frame opening 61 separates the sixth region 11, the seventh region 21, the eighth region 31, the ninth region 41, and the tenth region 51. The sixth region 11 further defines the effective region actually used to form the first bit line region based on the first region 10; the seventh region 21 further defines the effective region actually used to form the first transistor region based on the second region 20; the eighth region 31 further defines the effective region actually used to form the capacitor region based on the third region 30; the ninth region 41 further defines the effective region actually used to form the second transistor region based on the fourth region 40; and the tenth region 51 further defines the effective region actually used to form the second bit line region based on the fifth region 50.

[0211] like Figure 32As shown, line AA' is located in region 21 (seventh region) and extends along the Y direction. Line DD' is located in region 31 (eighth region) and also extends along the Y direction. Line CC' is located between regions 8 and 9 and extends along the Y direction. Line BB' crosses part of region 21 (seventh region), region 31 (eighth region), and part of region 41 (ninth region) and extends along the X direction.

[0212] The frame opening 61 is etched along the Z direction, that is, the exposed stacked structure below the opening of frame 61 is etched. The cross-sectional view of the etched stacked structure along the AA' direction is shown below. Figure 33A As shown, it illustrates a stacked structure extending along the AA' direction on the substrate 100. A cross-sectional view along the CC' direction is shown below. Figure 33C As shown, it illustrates a first trench 105 extending along the CC' direction on the substrate 100. A cross-sectional view along the DD' direction is shown below. Figure 33D As shown, it illustrates a stacked structure extending along the DD' direction on the substrate 100. A cross-sectional view along the BB' direction is shown below. Figure 33B As shown, it illustrates two parallel first trenches 105 formed after etching; the area between the two first trenches 105 is... Figure 32 The eighth region 31 shown is subsequently used to form the capacitor region.

[0213] Step S502, in such Figure 33B and Figure 33C The first trench 105 shown is filled with a first dielectric material to form a shape as shown in the figure. Figure 34B and 34C The first isolation layer 130 is shown. At this time... Figure 34A and Figure 34D The diagram shows a cross-sectional view of a semiconductor structure including a first isolation layer 130 along the AA' and DD' directions, which is consistent with... Figure 33A , 33D They are all the same.

[0214] The first isolation layer 130 is etched along the CC' direction to form a plurality of second trenches spaced apart within the first isolation layer 130. First, silicon nitride material is deposited using an ALD process to form a second silicon nitride layer 134 located within the second trenches. Then, a deposition process is used to fill the trenches covering the second silicon nitride layer 134 with silicon oxide material to form a second silicon oxide layer 135. Forming such a layer along the CC' direction... Figure 35C The third isolation layer 133, comprising a second silicon nitride layer 134 and a second silicon oxide layer 135, is shown located in the second groove. Figure 35A , Figure 35B as well as Figure 35D Cross-sectional views of the semiconductor structure containing the third isolation layer 133 along the AA', BB', and DD' directions are shown respectively.

[0215] The second silicon nitride layer 134 and the second silicon oxide layer 135 are used to form a Nitride-Oxide-Nitride (NON, nitride-oxide-nitride) structure. Since the dielectric constant of the oxide is lower than that of the nitride, the parasitic capacitance caused by the third isolation layer 133 can be reduced.

[0216] Step S601: Etch the capacitor region to form as shown. Figure 36 As shown ( Figure 36 (A cross-sectional view of the semiconductor structure including the third trench 107 along the BB' direction) shows the third trench 107 parallel to the first trench 105. The third trench 107 divides the capacitor region into two parallel sub-capacitor regions, including a first sub-capacitor region 411 and a second sub-capacitor region 412.

[0217] Step S602: From the third trench, etch the stacked structure to remove the first polysilicon layers located in the two sub-capacitor regions of the stacked structure, and form as shown in the figure on both sides of the third trench. Figure 37B (Cross-section along the BB' direction) and Figure 37D The cross-sectional view along the DD' direction shows multiple recessed structures 401 for accommodating the capacitor structure. At this time... Figure 37A , Figure 37C Cross-sectional views of a semiconductor structure containing multiple recessed structures 401 along the AA' and CC' directions are shown respectively.

[0218] Step S701: Etch the first isolation layer from the third trench to form a layer as shown in the figure. Figure 38 The capacitor contact hole 402 is shown at one end of the recessed structure located in the two sub-capacitor regions.

[0219] Step S702: Fill the capacitor contact hole with a first conductive material to form a structure as shown in the figure. Figure 39B (Cross-sectional view of the semiconductor structure including capacitor contact structure 170 along the BB' direction) and Figure 39C (A cross-sectional view of the semiconductor structure including the capacitor contact structure 170 along the CC' direction) shows the capacitor contact structure 170.

[0220] like Figure 39C As shown, when viewed along the CC' direction, there is a third isolation layer 133 between adjacent capacitor contact structures 170, and when viewed along the Z direction, the semiconductor structure has multiple mutually separated capacitor contact structures 170.

[0221] at this time Figure 39A , Figure 39D Cross-sectional views of a semiconductor structure containing multiple capacitive contact structures are shown along the AA' and DD' directions, respectively.

[0222] Step S301: Cover the inner wall of the recessed structure with a first sacrificial material to form a structure as shown in the figure. Figure 40(A cross-sectional view of the semiconductor structure including the first sacrificial layer 403 along the BB' direction) shows the first sacrificial layer 403; in this embodiment of the present disclosure, the first sacrificial material is deposited not only in the inner wall of the recessed structure, but also in the third trench, i.e., on the exposed sidewall of the stacked structure with the first polysilicon layer removed, forming as shown in the figure. Figure 40 The first sacrificial layer is shown. In this embodiment, the first sacrificial material may be carbon.

[0223] Step S302: Fill the recessed structure covered with the first sacrificial material with a second sacrificial material to form a structure as shown in the figure. Figure 41B The second sacrificial layer 404 is shown in 41D (a cross-sectional view of the semiconductor structure including the second sacrificial layer 404 along the BB' direction) and 41D (a cross-sectional view of the semiconductor structure including the second sacrificial layer 404 along the DD' direction); the second sacrificial layer 404 can fill the recessed structure and the third trench not covered by the first sacrificial layer 403. Figure 41D As shown, along the DD' direction, the second sacrificial layer 404 and the silicon oxide layer are arranged alternately. Figure 41A , Figure 41C Cross-sectional views of a semiconductor structure containing a second sacrificial layer along the AA' and CC' directions are shown respectively.

[0224] In actual manufacturing, the first and second sacrificial layers will also cover the upper surface of the top silicon oxide layer. At this time, CMP (Chemical Mechanical Polishing) can be used to remove the excess first and second sacrificial layers. In this embodiment, the second sacrificial material can be silicon nitride.

[0225] Then you can... Figure 41B The third interval X3 in the X direction is etched downwards, resulting in a shape like... Figure 42 The third trench 107 is shown. Figure 42 The third groove 107 in the middle can be with Figure 37B The third groove 107 in the middle is the same, and it can have the same width X3.

[0226] Step S801: Deposit a second dielectric material using a deposition process to form such a... Figure 43 The second dielectric material layer 108 shown covers the inner wall of the third trench; as shown Figure 43 As shown, the second dielectric material layer 108 not only covers the inner wall of the third trench but also covers the upper surface of the uppermost silicon oxide layer.

[0227] Step S802: Fill the third trench covered with the second dielectric material with polycrystalline silicon material to form a structure as shown in the figure. Figure 44A , 44BThe second polysilicon layer 109 in 44C and 44D. The second polysilicon layer 109 can fill the third trench not covered by the second dielectric material layer 108, and the second polysilicon layer 109 and the second dielectric material layer 108 can be used together to form the second isolation layer 131. Figure 44A , 44B As shown in 44C and 44D, the second polysilicon layer 109 also covers the second dielectric material layer 108 located on the upper surface of the uppermost silicon oxide layer.

[0228] Step S303: Remove the first sacrificial material to form a first void in the second sacrificial material; in this embodiment, the first sacrificial material can be carbon, which can be removed by an ashing process. After removing the first sacrificial material, a void can be formed as follows: Figure 45 The first gap 405 is shown. The first gap 405 is located between the second sacrificial layer 404 and the silicon nitride layer in the Z direction, and between the second dielectric material layer 108 and the capacitor contact structure and part of the first isolation layer in the X direction.

[0229] Step S304: Using a deposition process, atomic layer deposition (ALD) of a second conductive material is performed on the inner wall of the first pore to form a structure as shown in the image. Figure 46B and Figure 46D The first electrode 140 is shown. The first electrode 140 can serve as the lower electrode of a capacitor structure. The first electrode includes: a plurality of first portions parallel to the surface of the substrate in the X direction and a plurality of second portions along the Y direction, with each first portion and second portion alternately connected end-to-end. Figure 46B As shown, the first electrode 140 includes a first portion covering the second sacrificial layer 404 and the silicon nitride layer 101. The first electrode 140 also includes a second portion covering a portion of the second dielectric material layer 108, the capacitive contact structure 170, and a portion of the first insulating layer 130. Figure 46D As shown, the first electrode covers the exposed surface of the silicon nitride layer 101 along the DD' direction. At this time... Figure 46A , Figure 46C Cross-sectional views of the semiconductor structure including the first electrode along the AA' and CC' directions are shown respectively. Step S401: Remove the second sacrificial material layer between the first electrode and the second dielectric material layer, and at least a portion of the silicon nitride layer between the first electrode and the silicon oxide layer. In this embodiment, all the silicon nitride layer in the capacitor region is removed, forming a structure as shown... Figure 47B and Figure 47D The second gap 407 is shown; the outer wall of the first electrode is exposed in the second gap;

[0230] Then, a deposition process is used to fill the capacitor region with silicon oxide to form a structure like... Figure 48BThe third silicon oxide layer 602 shown not only fills the second voids but also fills the interior of the first electrode 140. A photoresist layer is then coated onto the upper surface of the second isolation layer 131, and a patterned photomask is used to align the area to be removed before exposure. This photoresist can be a negative photoresist; the photoresist corresponding to the photomask pattern is then removed, forming a layer as shown. Figure 48B The fourth photoresist layer 601 shown is as follows: Figure 48D As shown, the fourth photoresist layer 601 includes a plurality of mutually separated second openings 603 along the DD' direction. At this time... Figure 48A , Figure 48C Cross-sectional views of the semiconductor structure containing the third silicon oxide layer and the fourth photoresist layer along the AA' and CC' directions are shown respectively. Then, step S1001 is performed, etching the stacked structure downwards in the capacitor region along the Y direction parallel to the substrate, i.e., the extension direction of the second opening, using the substrate as the etching stop layer. Then, the third silicon oxide layer 602 in 48B is removed using a wet etching process, forming... Figure 49B and Figure 49D The semiconductor structure shown. (As shown in the image) Figure 49B As shown, after removing the third silicon oxide layer, the capacitor region includes the second gap 407 and the first electrode 140. Figure 49D As shown, the fifth trench 503 is located on both sides of the first electrode 140 along the DD' direction. The first electrode 140 is located in the second gap 407 along the Z direction.

[0231] Step S1002: Fill the fifth trench with insulating material to form a fourth isolation layer; the fourth isolation layer is used to isolate multiple capacitor structures in the capacitor region.

[0232] Step S402: Deposit a third dielectric material using a deposition process to form, as shown in the figure. Figure 50B and 50D The second dielectric layer 150 shown covers the inner and outer walls of the first electrode 140. The second dielectric layer not only covers the inner and outer walls of the first electrode 140, but also covers the sidewalls where the capacitor region is connected to the first isolation layer 130 and the second dielectric material layer 108.

[0233] Step S403: Deposit a third conductive material using a deposition process to form such a... Figure 50B and 50D The second electrode 160 shown covers the surface of the second dielectric layer 150; wherein the surface of the second dielectric layer 150 includes a first surface located within the region surrounded by the first electrode 140 and a second surface located outside the region surrounded by the first electrode 140. The third conductive material forming the second electrode may be the same as or different from the second conductive material forming the first electrode.

[0234] Steps S402 and S403 form a second dielectric layer surrounding the first electrode and a second electrode surrounding the second dielectric layer. Finally, polysilicon is filled into the gaps in the capacitor region not covered by the first electrode, the second dielectric layer, and the second electrode as a common connection layer for the second electrode, connecting it to the external circuit.

[0235] The embodiments disclosed herein can also be configured as follows: Figure 51 The semiconductor structure shown includes a capacitor structure, a transistor 180, and a capacitor contact structure 170 connected between the transistor 180 and the capacitor structure.

[0236] The capacitor structure includes a first electrode 140 and a second electrode 160, and a second dielectric layer (not shown) located between the first electrode 140 and the second electrode 160. The first electrode 140 includes a plurality of first portions parallel to the surface of the substrate and a plurality of second portions perpendicular to the surface of the substrate, and each first portion and second portion is alternately connected end to end.

[0237] like Figure 51 As shown, transistor 180 can also be connected to bit line structure 181 and word line structure 182. The portion of the first polysilicon layer 103 between bit line structure 181 and word line structure 182 can be the source (or drain), and the other portion of the first polysilicon layer 103 between word line structure 182 and capacitor contact structure 170 can be the drain (or source).

[0238] Both bit line structure 181 and word line structure 182 can be led out using a stepped structure.

[0239] It should be understood that the phrases "some embodiments," "one embodiment," or "an embodiment" throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0240] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0241] The above description is merely an embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, The semiconductor structure includes: Substrate; A stacked structure is located on the substrate; the stacked structure includes at least a plurality of first dielectric layers; the first dielectric layers are composed of silicon oxide layers and / or silicon nitride layers. A first isolation layer is located in the stacked structure and extends along a first direction parallel to the surface of the substrate; the first isolation layer is used to divide the stacked structure into transistor regions and capacitor regions; Multiple stacked transistors are located in the transistor region; Multiple stacked capacitor structures are located in the capacitor region; each capacitor structure includes a first electrode, a second dielectric layer, and a second electrode. The first electrode includes: a plurality of first portions parallel to the surface of the substrate and a plurality of second portions perpendicular to the surface of the substrate, wherein the first portions and the second portions are alternately connected end to end; Multiple capacitive contact structures are located in the first isolation layer, and the two sides of the capacitive contact structures are respectively connected to the transistor and the first electrode of the capacitor structure.

2. The semiconductor structure according to claim 1, characterized in that, The second dielectric layer covers the inner wall and part of the outer wall of the first electrode; wherein the inner wall of the first electrode is located within the area surrounded by the first electrode; and the outer wall of the first electrode is located outside the area surrounded by the first electrode.

3. The semiconductor structure according to claim 2, characterized in that, The second electrode covers the surface of the second dielectric layer; wherein the surface of the second dielectric layer includes a first surface located within the region surrounded by the first electrode and a second surface located outside the region surrounded by the first electrode.

4. The semiconductor structure according to claim 3, characterized in that, The second electrode includes a third portion located within the region surrounded by the first electrode, and a fourth portion located outside the region surrounded by the first electrode.

5. The semiconductor structure according to claim 1, characterized in that, The thickness of the first electrode is 2 nm to 7 nm.

6. The semiconductor structure according to claim 1, characterized in that, The multiple first isolation layers are used to divide the stacked structure into a first transistor region, a capacitor region, and a second transistor region arranged in parallel.

7. The semiconductor structure according to claim 6, characterized in that, The capacitor region includes: The second isolation layer extends along the first direction and divides the capacitor region into two sub-capacitor regions; wherein the two sub-capacitor regions include a plurality of symmetrically distributed, stacked capacitor structures.

8. The semiconductor structure according to claim 1, characterized in that, The capacitor region includes: Multiple fourth isolation layers extend along a second direction parallel to the substrate; wherein the second direction intersects the first direction; the fourth isolation layers are used to isolate multiple capacitor structures in the capacitor region.

9. The semiconductor structure according to claim 1, characterized in that, The transistor region includes: A plurality of third isolation layers extend along a second direction parallel to the substrate; wherein the second direction intersects the first direction; the third isolation layers are used to isolate a plurality of transistors in the transistor region.

10. A method for manufacturing a semiconductor structure, characterized in that, The method includes: Provide substrate; A stacked structure is formed on the substrate; wherein the stacked structure includes an alternately stacked first dielectric layer and a first polysilicon layer; the first dielectric layer is composed of a silicon oxide layer and / or a silicon nitride layer; In the stacked structure, a first isolation layer is formed along a first direction parallel to the surface of the substrate; the first isolation layer is used to divide the stacked structure into a transistor region and a capacitor region; wherein, the first polysilicon layer located in the transistor region is used to form a plurality of transistors; Remove the first polysilicon layer of the capacitor region to form a multi-layered recessed structure for accommodating the capacitor structure; A plurality of capacitive contact structures are formed in the first isolation layer exposed by the recessed structure; the capacitive contact structures are used to connect the capacitor structure and the transistor; The capacitor structure is formed in multiple layers based on the morphology of the recessed structure; the capacitor structure includes a first electrode, a second dielectric layer, and a second electrode. The first electrode includes: a plurality of first portions parallel to the surface of the substrate and a plurality of second portions perpendicular to the surface of the substrate, wherein the first portions and the second portions are alternately connected end to end.

11. The method according to claim 10, characterized in that, The formation of the multilayer capacitor structure based on the morphology of the recessed structure includes: The first electrode is formed based on the morphology of the inner wall of the recessed structure; A second dielectric layer is formed covering the inner wall and part of the outer wall of the first electrode; wherein the inner wall of the first electrode is located within the region surrounded by the first electrode; and the outer wall of the first electrode is located outside the region surrounded by the first electrode. A second electrode is formed covering the surface of the second dielectric layer; wherein the surface of the second dielectric layer includes a first surface located within the region surrounded by the first electrode and a second surface located outside the region surrounded by the first electrode.

12. The method according to claim 11, characterized in that, The formation of the first electrode based on the morphology of the inner wall of the recessed structure includes: The inner wall of the recessed structure is covered with a first sacrificial material; A second sacrificial material is filled into the recessed structure covered with the first sacrificial material; Remove the first sacrificial material to form a first void in the second sacrificial material; Atomic layer deposition is performed on the inner wall of the first pore to form the first electrode.

13. The method according to claim 12, characterized in that, The formation of the second dielectric layer covering the inner wall and part of the outer wall of the first electrode includes: The second sacrificial material and at least a portion of the first dielectric layer are removed to form a second void; a portion of the outer wall of the first electrode is exposed in the second void; A second dielectric layer is formed covering the inner wall and the outer wall of the first electrode.

14. The method according to claim 10, characterized in that, In the stacked structure, forming a first isolation layer along a first direction parallel to the substrate surface includes: The stacked structure is etched to form two parallel first trenches; the first trenches divide the stacked structure into a first transistor region, a capacitor region, and a second transistor region arranged in parallel. The first trench is filled with a first dielectric material to form a first isolation layer.

15. The method according to claim 14, characterized in that, The removal of the first polysilicon layer in the capacitor region to form a multi-layered recessed structure for accommodating the capacitor structure includes: The capacitor region is etched to form a third trench parallel to the first trench, and the third trench divides the capacitor region into two parallel sub-capacitor regions. The stacked structure is etched from the third trench to remove each of the first polysilicon layers located in the capacitor region of the stacked structure, and multiple recessed structures for accommodating the capacitor structure are formed on both sides of the third trench.

16. The method according to claim 15, characterized in that, The formation of multiple capacitive contact structures in the first insulating layer exposed in the recessed structure includes: The first isolation layer is etched from the third trench to form a capacitor contact hole located at one end of the recessed structure of the two sub-capacitor regions; The capacitor contact hole is filled with a first conductive material to form the capacitor contact structure.

17. The method according to claim 15, characterized in that, The method further includes: A second medium material is formed to cover the inner wall of the third trench; A second isolation layer is formed by filling the third trench, which is covered with the second dielectric material, with polycrystalline silicon material.

18. The method according to claim 15, characterized in that, The formation of the multilayer capacitor structure based on the morphology of the recessed structure includes: Based on the morphology of the recessed structure located in the two sub-capacitor regions, two sets of symmetrically distributed, multi-layered capacitor structures are formed respectively.

19. The method according to claim 10, characterized in that, The method further includes: The stacked structure is etched in the capacitor region along a second direction parallel to the substrate to form a plurality of fifth trenches; wherein the second direction intersects the first direction; An insulating material is filled into the fifth trench to form a fourth isolation layer; the fourth isolation layer is used to isolate multiple capacitor structures in the capacitor region.

20. A memory, characterized in that, The memory includes: Memory cell array; the memory cell array comprising the semiconductor structure according to any one of claims 1 to 9; and Peripheral circuitry coupled to the memory cell array.

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