Ferroelectric memory, three-dimensional integrated circuit, electronic device

Abstract

This application provides a ferroelectric memory, a three-dimensional integrated circuit, and an electronic device, relating to the field of semiconductor chip technology, which improves the anti-interference capability of capacitors. The ferroelectric memory includes a capacitor comprising a first stacked layer, a first conductive pillar, a second conductive pillar, a first ferroelectric layer, and a second ferroelectric layer. The first stacked layer includes a first conductive portion and a second conductive portion connected together. The first conductive pillar penetrates the first conductive portion, and the second conductive pillar penetrates the second conductive portion. The first ferroelectric layer penetrates the first conductive portion and is disposed around the first conductive pillar, and the second ferroelectric layer penetrates the second conductive portion and is disposed around the second conductive pillar. The capacitor includes a first capacitor and a second capacitor connected in series. The first capacitor includes a first conductive pillar, a first ferroelectric layer, and a first conductive portion, and the second capacitor includes a second conductive pillar, a second ferroelectric layer, and a second conductive portion. This ferroelectric memory can be applied in three-dimensional integrated circuits to realize data reading and writing.

Description

Technical Field

[0001] This application relates to the field of semiconductor chip technology, and in particular to a ferroelectric memory, a three-dimensional integrated circuit, and an electronic device. Background Technology

[0002] With the development of semiconductor chip technology, planar integrated circuits (2D ICs) used as system-on-chips (SOCs) can no longer meet people's needs for chip functionality, size, and power consumption.

[0003] Currently, stacking multiple chips in three dimensions to form a three-dimensional integrated circuit (3D IC) can improve the bandwidth and energy efficiency of interconnection between multiple chips. Therefore, three-dimensional integrated circuits are gradually attracting attention in the field.

[0004] In 3D integrated circuits, to ensure power integrity (PI), decoupling capacitors (Decap) are required in the power distribution network (PDN) to provide a more stable power supply. However, as operating time increases, the interference immunity of decoupling capacitors deteriorates, causing their capacitance values ​​to change, which in turn leads to the power distribution network failing to provide a stable power supply. Summary of the Invention

[0005] This application provides a ferroelectric memory, a three-dimensional integrated circuit, and an electronic device, which aims to improve the anti-interference capability of decoupling capacitors in chips.

[0006] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0007] Firstly, a ferroelectric memory is provided, which can be either a ferroelectric random access memory (FeRAM) or a ferroelectric field-effect transistor (FeFET) memory, enabling data reading and writing.

[0008] The aforementioned ferroelectric memory includes an array region and a wiring region. The ferroelectric memory includes a memory array disposed in the array region and a capacitor disposed in the wiring region. The capacitor includes a first stacked layer, a first conductive pillar, a second conductive pillar, a first ferroelectric layer, and a second ferroelectric layer. The first stacked layer includes multiple conductive layers and multiple first dielectric layers alternately stacked. The multiple conductive layers include connected first and second conductive portions. The first conductive pillar penetrates the first conductive portion, and the second conductive pillar penetrates the second conductive portion. The first and second ferroelectric layers have cylindrical structures. The first ferroelectric layer penetrates the first conductive portion and is disposed around the first conductive pillar, and the second ferroelectric layer penetrates the second conductive portion and is disposed around the second conductive pillar. The capacitor also includes a first capacitor and a second capacitor connected in series. The first capacitor includes a first conductive pillar, a first ferroelectric layer, and a first conductive portion, and the second capacitor includes a second conductive pillar, a second ferroelectric layer, and a second conductive portion.

[0009] The ferroelectric memory provided in the above embodiments of this application employs a first conductive post penetrating a first conductive portion of a conductive layer, and a first ferroelectric layer surrounding the first conductive post to separate the first conductive post from the first conductive portion. The first conductive post, the first ferroelectric layer, and the first conductive portion form a first capacitor, with the first conductive post and the first conductive portion serving as the two poles of the first capacitor.

[0010] Furthermore, a second conductive post is used to penetrate the second conductive portion of the conductive layer, and a second ferroelectric layer is used to surround the second conductive post to separate the second conductive post from the second conductive portion. The second conductive post, the second ferroelectric layer, and the second conductive portion form a second capacitor, with the second conductive post and the second conductive portion serving as the two poles of the second capacitor.

[0011] By connecting the first conductive part and the second conductive part, one pole of the first capacitor is electrically connected to one pole of the second capacitor, thereby connecting the first capacitor and the second capacitor in series. According to the principle of series voltage division, the potential difference across each capacitor can be reduced, thereby reducing the probability of polarization reversal in the ferroelectric layer of the capacitor, ensuring the stability of the capacitor's capacitance value, and improving the capacitor's anti-interference capability.

[0012] In some embodiments, each conductive layer includes at least one first conductive portion and at least one second conductive portion, wherein the connected first conductive portion and the second conductive portion are located in the same conductive layer, so as to facilitate the connection between the first conductive portion and the second conductive portion.

[0013] In some embodiments, each conductive layer includes a first conductive portion and a second conductive portion, the first conductive portion being connected to the second conductive portion and arranged along a first direction parallel to the bottom surface of the first stacked layer. Multiple first conductive posts penetrate the first conductive portion, equivalent to multiple first capacitors connected in parallel. Multiple second conductive posts penetrate the second conductive portion, equivalent to multiple second capacitors connected in parallel. The first conductive portion and the second conductive portion of the same conductive layer are connected, so that the multiple first capacitors connected in parallel are connected in series with the multiple second capacitors connected in parallel, forming a third capacitor.

[0014] In the above embodiments, the total capacitance of multiple first capacitors connected in parallel is greater than the capacitance of a single first capacitor, the total capacitance of multiple second capacitors connected in parallel is greater than the capacitance of a single second capacitor, and the capacitance of a third capacitor can be increased, thereby increasing the total capacitance of the capacitors.

[0015] Furthermore, the parallel first capacitors are connected in series with the parallel second capacitors to form a third capacitor, which can reduce the potential difference across the parallel capacitors (first capacitors or second capacitors), and reduce the potential difference across each capacitor. This reduces the probability of polarization reversal in the ferroelectric layer of the capacitor, ensures the stability of the capacitor's capacitance, and improves the capacitor's anti-interference capability.

[0016] In some embodiments, the capacitor further includes a first interconnect electrode and a second interconnect electrode, which are planar structures and arranged along a first direction. The first interconnect electrode is electrically connected to the ends of a plurality of first conductive posts to transmit electrical signals to the plurality of first conductive posts. The second interconnect electrode is electrically connected to the ends of a plurality of second conductive posts to transmit electrical signals to the plurality of second conductive posts.

[0017] In some embodiments, the plurality of first conductive pillars are arranged in an array, and / or the plurality of second conductive pillars are arranged in an array, which can improve the uniformity of the arrangement of the plurality of first conductive pillars and the plurality of second conductive pillars, and is beneficial to improving the phenomenon of signal interference between the plurality of capacitors.

[0018] In some embodiments, the capacitor further includes a first interconnect electrode and a second interconnect electrode, the first interconnect electrode and the second interconnect electrode having a comb-like structure, the first interconnect electrode and the second interconnect electrode being arranged along a first direction, the first interconnect electrode including a plurality of first interconnect lines, and the second interconnect electrode including a plurality of second interconnect lines.

[0019] First interconnect lines and second interconnect lines extend along a first direction. Multiple first interconnect lines are electrically connected to the ends of multiple first conductive pillars, and the multiple first interconnect lines are connected on one side of the first stacked layer along the first direction. Multiple second interconnect lines are electrically connected to the ends of multiple second conductive pillars, and the multiple second interconnect lines are connected on the other side of the first stacked layer along the first direction.

[0020] Alternatively, the first interconnect line and the second interconnect line extend along a second direction, and multiple first interconnect lines are electrically connected to the ends of multiple first conductive pillars, and the multiple first interconnect lines are connected on one side of the first stacked layer along the second direction. Multiple second interconnect lines are electrically connected to the ends of multiple second conductive pillars, and the multiple second interconnect lines are connected on one side of the first stacked layer along the second direction, the second direction being parallel to the bottom surface of the first stacked layer and intersecting the first direction.

[0021] In some embodiments, each conductive layer includes a plurality of first conductive portions and a plurality of second conductive portions, the plurality of first conductive portions being connected to the plurality of second conductive portions, and the first conductive portions and second conductive portions being arranged alternately along a first direction, the first direction being parallel to the bottom surface of the first stacked layer. A plurality of first conductive pillars penetrate through the first conductive portions, and a plurality of second conductive pillars penetrate through the second conductive portions.

[0022] In the above embodiments, multiple first conductive pillars penetrate the first conductive portion, equivalent to multiple first capacitors connected in parallel. Multiple second conductive pillars penetrate the second conductive portion, equivalent to multiple second capacitors connected in parallel. Multiple first conductive portions and multiple second conductive portions of the same conductive layer are connected in series, so that the multiple first capacitors connected in parallel and the multiple second capacitors connected in parallel are connected in series to form a third capacitor. By connecting the capacitors in series, the potential difference across each capacitor can be reduced, thereby reducing the probability of polarization reversal in the ferroelectric layer of the capacitor, ensuring the stability of the capacitor's capacitance, and improving the capacitor's anti-interference capability.

[0023] In some embodiments, the capacitor further includes a first interconnect electrode and a second interconnect electrode, which are comb-shaped structures. The first interconnect electrode includes a plurality of first interconnect lines, and the second interconnect electrode includes a plurality of second interconnect lines. The plurality of first interconnect lines and the plurality of second interconnect lines are arranged along a first direction, and the first interconnect lines and the second interconnect lines extend along a second direction.

[0024] Multiple first interconnect lines are electrically connected to the ends of multiple first conductive posts, and these multiple first interconnect lines are connected on one side of the first stacked layer along the second direction, transmitting electrical signals to the multiple first conductive posts through the multiple first interconnect lines of the first interconnect electrodes. Multiple second interconnect lines are electrically connected to the ends of multiple second conductive posts, and these multiple second interconnect lines are connected on the other side of the first stacked layer along the second direction, transmitting electrical signals to the multiple second conductive posts through the multiple second interconnect lines of the second interconnect electrodes.

[0025] In some embodiments, multiple first interconnect lines and multiple second interconnect lines are arranged alternately along a first direction. Alternatively, no second interconnect line is provided between two adjacent first interconnect lines, or multiple second interconnect lines are provided, and no first interconnect line is provided between two adjacent second interconnect lines, or multiple first interconnect lines are provided.

[0026] In some embodiments, the plurality of first conductive posts include multiple rows, and a first interconnect line is electrically connected to a row of first conductive posts to transmit an electrical signal to the row of first conductive posts via the first interconnect line. And / or, the plurality of second conductive posts include multiple rows, and a second interconnect line is electrically connected to a row of second conductive posts to transmit an electrical signal to the row of second conductive posts via the second interconnect line.

[0027] In some embodiments, a first conductive portion and a second conductive portion located on the same conductive layer are integrally disposed to achieve connection between the first conductive portion and the second conductive portion.

[0028] In some embodiments, each conductive layer includes a plurality of spaced conductive blocks. Each conductive block includes a first conductive portion and a second conductive portion connected together. A plurality of first conductive posts penetrate the first conductive portion of the conductive block, equivalent to a plurality of first capacitors connected in parallel. A plurality of second conductive posts penetrate the second conductive portion of the conductive block, equivalent to a plurality of second capacitors connected in parallel. The first conductive portion and the second conductive portion of the same conductive block are connected together, so that the plurality of first capacitors connected in parallel are connected in series with the plurality of second capacitors connected in parallel, forming a third capacitor.

[0029] In two adjacent conductive blocks, multiple second conductive posts passing through one conductive block are electrically connected to multiple first conductive posts passing through the other conductive block, so that the third capacitors of the adjacent conductive blocks are connected in series to form a fourth capacitor.

[0030] In the above embodiments, the total capacitance of multiple first capacitors connected in parallel is greater than the capacitance of a single first capacitor, and the total capacitance of multiple second capacitors connected in parallel is greater than the capacitance of a single second capacitor. The capacitance of a third capacitor and a fourth capacitor can be added to increase the total capacitance of the capacitors.

[0031] Furthermore, multiple first capacitors connected in parallel are connected in series with multiple second capacitors connected in parallel to form a third capacitor. The third capacitors of adjacent conductive blocks are connected in series to form a fourth capacitor, thereby increasing the number of capacitors connected in series. This can further reduce the potential difference across each capacitor, reduce the probability of polarization reversal in the ferroelectric layer of the capacitor, ensure the stability of the capacitor's capacitance, and improve the capacitor's anti-interference capability.

[0032] In some embodiments, the capacitor further includes a second dielectric layer that extends through the first stacked layer and separates adjacent conductive blocks, i.e., the second dielectric layer divides the conductive layer into multiple conductive blocks.

[0033] In some embodiments, each conductive layer includes a first conductive block to an nth conductive block arranged sequentially, where n ≥ 2 and n is a positive integer. The capacitor also includes a first interconnect electrode, at least one second interconnect electrode, and a third interconnect electrode. The first interconnect electrode is electrically connected to a first conductive post penetrating the first conductive block. The second interconnect electrode is electrically connected to a second conductive post penetrating the ith conductive block and a first conductive post penetrating the (i+1)th conductive block, where i = 1 to n-1 and i is a positive integer. The third interconnect electrode is electrically connected to a second conductive post penetrating the nth conductive block.

[0034] In the above embodiment, the first interconnect electrode and the third interconnect electrode receive external electrical signals and transmit the electrical signals to the fourth capacitor.

[0035] In some embodiments, the plurality of conductive layers include a plurality of first conductive portions and a plurality of second conductive portions, wherein the plurality of second conductive portions are located on the side of the plurality of first conductive portions away from the bottom surface of the first stacked layer. A plurality of first conductive posts penetrate the plurality of first conductive portions, equivalent to a plurality of first capacitors connected in parallel. A plurality of second conductive posts penetrate the plurality of second conductive portions, equivalent to a plurality of second capacitors connected in parallel.

[0036] The capacitor also includes a third conductive post that penetrates the first stacked layer. The third conductive post is electrically connected to a plurality of first conductive parts and a plurality of second conductive parts, so that the plurality of first capacitors connected in parallel are connected in series with the plurality of second capacitors connected in parallel.

[0037] In the above embodiments, the total capacitance of multiple first capacitors connected in parallel is greater than the capacitance of a single first capacitor, and the total capacitance of multiple second capacitors connected in parallel is greater than the capacitance of a single second capacitor, thereby increasing the total capacitance of the capacitors.

[0038] Furthermore, connecting multiple first capacitors in parallel with multiple second capacitors in parallel in series can reduce the potential difference across the multiple capacitors (first capacitors or second capacitors) in parallel, thereby reducing the potential difference across each capacitor. This can lower the probability of polarization reversal in the ferroelectric layer of the capacitor, ensure the stability of the capacitor's capacitance, and improve the capacitor's anti-interference capability.

[0039] In some embodiments, the capacitor further includes a first interconnect electrode and a second interconnect electrode. The first interconnect electrode is disposed on the bottom surface of the first stacked layer away from the plurality of first conductive portions and is electrically connected to the ends of the plurality of first conductive posts, transmitting electrical signals to the plurality of first conductive posts through the first interconnect electrode. The second interconnect electrode is disposed on the bottom surface of the plurality of second conductive portions away from the first stacked layer and is electrically connected to the ends of the plurality of second conductive posts, transmitting electrical signals to the plurality of second conductive posts through the second interconnect electrode.

[0040] In some embodiments, the materials of the conductive layer, the first conductive pillar, and the second conductive pillar include at least one of Ti, Au, W, Mo, Al, Cu, Ru, Ag, TiN, and ITO.

[0041] In some embodiments, the material of the first ferroelectric layer and / or the second ferroelectric layer includes at least one of ZrO2, HfO2, HfAlO, HfSiO, HfZrO, HfLaO, and HfYO.

[0042] In some embodiments, the first dielectric layer is a single-layer structure or a stacked structure, and the material of the first dielectric layer includes at least one of SiO2, Al2O3, HfO2, ZrO2, TiO2, Y2O3, and Si3N4.

[0043] In some embodiments, the storage array includes a second stack layer, which includes a plurality of storage cells arranged in an array.

[0044] The second stacked layer includes alternating third dielectric layers and gate layers. A plurality of first dielectric layers in the first stacked layer correspond one-to-one with a plurality of third dielectric layers in the second stacked layer. The corresponding first dielectric layers and third dielectric layers are made of the same material and are disposed in the same layer. A plurality of conductive layers in the first stacked layer correspond one-to-one with a plurality of gate layers in the second stacked layer. The corresponding conductive layers and gate layers are made of the same material, are disposed in the same layer, and are mutually insulated.

[0045] In a second aspect, a method for fabricating a ferroelectric memory is provided. The method includes: forming a first stacked layer, the first stacked layer comprising a plurality of conductive layers and a plurality of first dielectric layers alternately stacked, the plurality of conductive layers including connected first conductive portions and second conductive portions; forming a first contact hole penetrating the first conductive portion and a second contact hole penetrating the second conductive portion; forming a first ferroelectric layer on the sidewall of the first contact hole and a second ferroelectric layer on the sidewall of the second contact hole; forming a first conductive post inside the first ferroelectric layer and a second conductive post inside the second ferroelectric layer.

[0046] The preparation method provided in the above embodiments of this application first forms a first stacked layer, which includes a plurality of conductive layers and a plurality of first dielectric layers alternately stacked. Each conductive layer includes a first conductive portion and a second conductive portion connected together. Then, a first contact hole penetrating the first conductive portion and a second contact hole penetrating the second conductive portion are formed. A first ferroelectric layer and a first conductive pillar are formed on the sidewall of the first contact hole, and a second ferroelectric layer and a second conductive pillar are formed on the sidewall of the second contact hole.

[0047] A first conductive post, a first ferroelectric layer, and a first conductive portion form a first capacitor, with the first conductive post and the first conductive portion serving as the two electrodes of the first capacitor. A second conductive post, a second ferroelectric layer, and a second conductive portion form a second capacitor, with the second conductive post and the second conductive portion serving as the two electrodes of the second capacitor. By connecting the first and second conductive portions, one electrode of the first capacitor is electrically connected to one electrode of the second capacitor, thereby connecting the first and second capacitors in series. This reduces the potential difference across each capacitor, thereby lowering the probability of polarization reversal in the ferroelectric layer of the capacitor, ensuring stable capacitance, and improving the capacitor's anti-interference capability.

[0048] In some embodiments, after forming the first conductive pillar and the second conductive pillar, the method further includes: forming a first interconnect electrode and a second interconnect electrode, wherein the first interconnect electrode is electrically connected to the ends of the plurality of first conductive pillars to transmit electrical signals to the plurality of first conductive pillars. The second interconnect electrode is electrically connected to the ends of the plurality of second conductive pillars to transmit electrical signals to the plurality of second conductive pillars.

[0049] In some embodiments, after forming the first stacked layer, the method further includes: forming at least one isolation trench through the first stacked layer, the at least one isolation trench dividing the conductive layer into a plurality of conductive blocks, each conductive block including a first conductive portion and a second conductive portion, the first conductive portion being connected to the second conductive portion. A second dielectric layer is formed within the isolation trench.

[0050] In the above embodiments, by etching the first stacked layer to form an isolation trench penetrating the first stacked layer, and forming a second dielectric layer in the isolation trench, the conductive layer is divided into multiple conductive blocks to increase the number of capacitors connected in series. This further reduces the potential difference across each capacitor, lowers the probability of polarization reversal in the ferroelectric layer of the capacitor, ensures the stability of the capacitor's capacitance, and improves the capacitor's anti-interference capability.

[0051] In some embodiments, each conductive layer includes a first conductive block to an nth conductive block arranged sequentially, where n ≥ 2 and n is a positive integer.

[0052] After forming the first and second conductive pillars, the process further includes: forming a first interconnect electrode, at least one second interconnect electrode, and a third interconnect electrode. The first interconnect electrode is electrically connected to the first conductive pillar penetrating the first conductive block. The second interconnect electrode is electrically connected to the second conductive pillar penetrating the i-th conductive block and the first conductive pillar penetrating the (i+1)-th conductive block, where i = 1 to n-1, and i is a positive integer. The third interconnect electrode is electrically connected to the second conductive pillar penetrating the n-th conductive block.

[0053] In some embodiments, the ferroelectric memory includes an array region and a trace region, and a second stacked layer is simultaneously formed in the array region during the formation of a first stacked layer in the trace region.

[0054] Thirdly, a method for fabricating a ferroelectric memory is also provided. This method includes: forming a first sub-stack layer, the first sub-stack layer including a plurality of alternatingly stacked first conductive portions and a plurality of first dielectric layers; forming a first contact hole penetrating the plurality of first conductive portions; forming a first ferroelectric layer on the sidewall of the first contact hole; forming a first conductive post inside the first ferroelectric layer; forming an insulating layer covering the first sub-stack layer, the first ferroelectric layer, and the first conductive post; forming a second sub-stack layer on the side of the insulating layer away from the first sub-stack layer, the second sub-stack layer including a plurality of alternatingly stacked second conductive portions and a plurality of first dielectric layers; forming a second contact hole penetrating the plurality of second conductive portions; forming a second ferroelectric layer on the sidewall of the second contact hole; forming a second conductive post inside the second ferroelectric layer; and forming a third conductive post penetrating the second sub-stack layer, the insulating layer, and the first sub-stack layer, and electrically connected to the plurality of first conductive portions and the plurality of second conductive portions.

[0055] The fabrication method provided in the above embodiments of this application first forms a first sub-stacked layer, which includes a plurality of first conductive portions and a plurality of first dielectric layers alternately stacked. Then, a first contact hole is formed penetrating the plurality of first conductive portions, and a first ferroelectric layer and a first conductive pillar are formed on the sidewall of the first contact hole.

[0056] Then, a second sub-stack layer is formed above the first sub-stack layer. The second sub-stack layer includes a plurality of second conductive portions and a plurality of first dielectric layers that are alternately stacked. Then, a second contact hole is formed through the plurality of second conductive portions, and a second ferroelectric layer and a second conductive post are formed on the sidewall of the second contact hole.

[0057] Finally, a third conductive pillar is formed that runs through the second sub-stack layer and the first sub-stack layer. The third conductive pillar is electrically connected to multiple first conductive parts and multiple second conductive parts, so that multiple first capacitors connected in parallel are connected in series with multiple second capacitors connected in parallel. This can reduce the potential difference across each capacitor, thereby reducing the probability of polarization reversal in the ferroelectric layer of the capacitor, ensuring the stability of the capacitor's capacitance value, and improving the capacitor's anti-interference capability.

[0058] Fourthly, a three-dimensional integrated circuit is provided, which includes the ferroelectric memory and processor chip described in any of the above embodiments, wherein the processor chip is stacked on top of the ferroelectric memory and electrically connected to the ferroelectric memory.

[0059] Fifthly, an electronic device is provided, such as a consumer electronics product, a home electronics product, an automotive electronics product, a financial terminal product, or a communication electronics product. The electronic device includes a circuit board and a ferroelectric memory or three-dimensional integrated circuit as described in any of the above embodiments, the ferroelectric memory or three-dimensional integrated circuit being disposed on the circuit board and electrically connected to the circuit.

[0060] It is understood that the beneficial effects of the three-dimensional integrated circuit and electronic device provided in the above embodiments of this application can be referred to the beneficial effects of the ferroelectric memory mentioned above, and will not be repeated here. Attached Figure Description

[0061] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in some embodiments of this application will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this application.

[0062] Figure 1 This is an architectural diagram of an electronic device according to some embodiments;

[0063] Figure 2 An exploded view of an electronic device according to some embodiments;

[0064] Figure 3 This is a structural diagram of a three-dimensional integrated circuit according to some embodiments;

[0065] Figure 4 A top view of a ferroelectric memory according to some embodiments;

[0066] Figure 5 This is an architectural diagram of a storage array for a ferroelectric memory according to some embodiments;

[0067] Figure 6 This is a structural diagram of a decoupling capacitor in related technologies;

[0068] Figure 7 This is a hysteresis loop diagram of the ferroelectric material in a ferroelectric capacitor.

[0069] Figure 8This is a graph showing the relationship between the capacitance of a ferroelectric capacitor and the potential difference between its two electrodes before and after polarization reversal.

[0070] Figure 9 This is a structural diagram of a capacitor according to some embodiments;

[0071] Figure 10 for Figure 9 A top view of the capacitor in the image;

[0072] Figure 11 for Figure 10 A cross-sectional view of the capacitor along section line AA';

[0073] Figure 12 for Figure 11 The equivalent circuit diagram of the capacitor in the image;

[0074] Figure 13 for Figure 11 A magnified view of the capacitor at point M;

[0075] Figure 14 for Figure 13 The equivalent circuit diagram of the capacitor in the image;

[0076] Figure 15 A top view of another capacitor according to some embodiments;

[0077] Figure 16 and Figure 17 A top view of another capacitor according to some embodiments;

[0078] Figure 18 A top view of another capacitor according to some embodiments;

[0079] Figure 19 for Figure 18 The equivalent circuit diagram of the capacitor in the image;

[0080] Figure 20 A top view of yet another capacitor according to some embodiments;

[0081] Figure 21 for Figure 20 The equivalent circuit diagram of the capacitor in the image;

[0082] Figures 22A-22E A diagram illustrating the steps involved in fabricating a capacitor according to some embodiments;

[0083] Figure 23 A top view of yet another capacitor according to some embodiments;

[0084] Figure 24 for Figure 23 A cross-sectional view of the capacitor along section line BB';

[0085] Figure 25 for Figure 24 The equivalent circuit diagram of the capacitor in the image;

[0086] Figures 26A to 26G A diagram illustrating the steps involved in the fabrication of another capacitor according to some embodiments;

[0087] Figure 27 A cross-sectional view of yet another capacitor according to some embodiments;

[0088] Figure 28 for Figure 27 The equivalent circuit diagram of the capacitor in the image;

[0089] Figures 29A to 29K This diagram illustrates the steps involved in preparing another type of capacitor according to some embodiments. Detailed Implementation

[0090] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0091] In the description of this application, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0092] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0093] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0094] In describing some embodiments, the term "connection" and its derivative expressions may be used. For example, the term "connection" may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.

[0095] "At least one of A, B, and C" includes the following combinations of A, B, and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0096] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0097] The use of “configured as” in this article implies an open and inclusive language that does not exclude the applicability to or configuration of devices to perform additional tasks or steps.

[0098] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0099] In the context of this application, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also “on” something with intermediate features or layers in between, and that “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0100] In this application, "same layer" refers to a layer structure formed using the same film deposition process to create a specific pattern, and then using the same photomask to form a single patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0101] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0102] Some embodiments of this application provide an electronic device, which may be, for example, a mobile phone, tablet computer, personal digital assistant (PDA), television, smart wearable products (e.g., smartwatch, smart bracelet), virtual reality (VR) terminal device, augmented reality (AR) terminal device, rechargeable small household appliances (e.g., soymilk maker, robot vacuum cleaner), drone, radar, aerospace equipment, and vehicle-mounted equipment, etc.; the electronic device may also be a network device such as a base station. The embodiments of this application do not impose special limitations on the specific form of the electronic device.

[0103] Figure 1 This is an architectural diagram of an electronic device according to some embodiments.

[0104] See Figure 1 Electronic device 1 includes components such as a storage device 11, a processor 12, an input device 13, and an output device 14. Those skilled in the art will understand that... Figure 1 The architecture of the electronic device 1 shown does not constitute a limitation on the electronic device 1, which may include, for example... Figure 1 The components shown may have more or fewer components, or may be combined as follows: Figure 1 Some of the components shown, or those that can be used with, for example Figure 1 The component arrangements shown are different.

[0105] The storage device 11 is used to store software programs and modules. The storage device 11 mainly includes a program storage area and a data storage area. The program storage area stores and backs up the operating system and application programs required for at least one function (such as sound playback, image playback, etc.). The data storage area stores data created based on the use of the electronic device 1 (such as audio data, image data, phonebook, etc.). Furthermore, the storage device 11 includes an external storage device 111 and an internal storage device 112. Data stored in the external storage device 111 and the internal storage device 112 can be transferred between each other. The external storage device 111 may include, for example, a hard disk, a USB flash drive, or a floppy disk. The internal storage device 112 may include, for example, random access memory (RAM) or read-only memory (ROM).

[0106] Processor 12 is the control center of the electronic device 1. It connects various parts of the electronic device 1 via various interfaces and lines, and performs various functions and processes data by running or executing software programs and / or modules stored in storage device 11, and by calling data stored in storage device 11, thereby providing overall monitoring of the electronic device 1. Optionally, processor 12 may include one or more processing units. For example, processor 12 may include an application processor (AP), a modem processor, a graphics processing unit (GPU), etc. Different processing units can be independent devices or integrated into one or more processors. For example, processor 12 may integrate an application processor and a modem processor, where the application processor mainly handles the operating system, user interface, and applications, while the modem processor mainly handles wireless communication. It is understood that the modem processor may not be integrated into processor 12. The application processor may, for example, be a central processing unit (CPU). Figure 1 Taking processor 12 as an example (CPU), the CPU may include an arithmetic logic unit (ALU) 121 and a control unit 122. The ALU 121 retrieves data stored in the internal memory 112, processes the data stored in the internal memory 112, and the processed result is usually sent back to the internal memory 112. The control unit 122 can control the ALU 121 to process the data, and the control unit 122 can also control the external memory 111 and the internal memory 112 to read or write data.

[0107] Input device 13 is used to receive input numeric or character information and generate key signal inputs related to user settings and function control of the electronic device. For example, input device 13 may include a touchscreen and other input devices. A touchscreen, also known as a touch panel, can collect touch operations performed by the user on or near the touchscreen (e.g., operations performed by the user using a finger, stylus, or any suitable object or accessory on or near the touchscreen) and drive corresponding connected devices according to a pre-set program. The controller 122 in the processor 12 can also control the input device 13 to receive or not receive input signals. Furthermore, the input numeric or character information received by input device 13 and the generated key signal inputs related to user settings and function control of the electronic device can be stored in internal memory 112.

[0108] Output device 14 is used to output signals corresponding to the input data of input device 13 and stored in internal memory 112. For example, output device 14 outputs audio signals or video signals. The controller 122 in the processor 12 can also control output device 14 to output signals or not output signals.

[0109] It should be noted that, Figure 1 The thick arrows in the diagram are used to indicate data transmission, and the direction of the thick arrows indicates the direction of data transmission. For example, a single arrow between input device 13 and internal memory 112 indicates that data received by input device 13 is transmitted to internal memory 112. As another example, a double arrow between arithmetic unit 121 and internal memory 112 indicates that data stored in internal memory 112 can be transmitted to arithmetic unit 121, and data processed by arithmetic unit 121 can be transmitted to internal memory 112. Figure 1 The thin arrows in the diagram indicate components that the controller 122 can control. For example, the controller 122 can control external memory 111, internal memory 112, arithmetic unit 121, input device 13, and output device 14, etc.

[0110] To facilitate further explanation of the structure of electronic device 1, the following description uses a mobile phone as an example.

[0111] Figure 2 An exploded view of an electronic device according to some embodiments.

[0112] See Figure 2 The electronic device 1 may also include a mid-frame 15, a rear housing 16, and a display screen 17. The rear housing 16 and the display screen 17 are located on opposite sides of the mid-frame 15, and the mid-frame 15 and the display screen 17 are disposed within the rear housing 16. The mid-frame 15 includes a support plate 150 for supporting the display screen 17, and a frame 151 surrounding the support plate 150.

[0113] See also Figure 2 The electronic device 1 may also include a circuit board 18 disposed on the side of the carrier plate 150 near the rear housing 16. The electronic device 1 also includes a chip 19 disposed on the circuit board 18, which is electrically connected to the circuit board 18.

[0114] The aforementioned chip 19 can be a ferroelectric memory. For example, the internal memory 112 in electronic device 1 is a ferroelectric memory, which has a high storage density. This ferroelectric memory can be a ferroelectric random access memory or a ferroelectric field-effect transistor memory.

[0115] The aforementioned chip 19 can also be a three-dimensional integrated circuit. Three-dimensional integrated circuits include homogeneous three-dimensional integrated circuits and heterogeneous three-dimensional integrated circuits. Homogeneous three-dimensional integrated circuits include multilayer active devices integrated along their thickness direction, and have the characteristics of low cost and high dimensional accuracy. Heterogeneous three-dimensional integrated circuits include multiple integrated chips with different process architectures, different instruction sets, or different functions. That is, heterogeneous three-dimensional integrated circuits integrate different semiconductor materials, semiconductor processes, semiconductor structures, or semiconductor devices.

[0116] Figure 3 This is a structural diagram of a three-dimensional integrated circuit according to some embodiments.

[0117] See Figure 3 The three-dimensional integrated circuit 2 includes two chips stacked in three dimensions, one of which may be, for example, a ferroelectric memory 21, and the other may be, for example, a processor chip 22, which are electrically connected to each other.

[0118] For example, the processor chip 22 may consist of multiple logic chips, in which case the multiple logic chips are stacked on the ferroelectric memory 21 and electrically connected to the ferroelectric memory 21.

[0119] For example, the processor chip 22 may also adopt a system-on-chip (SOC) architecture design, in which case the system-on-chip is stacked on the ferroelectric memory 21 and electrically connected to the ferroelectric memory 21.

[0120] The aforementioned three-dimensional integrated circuit 2 is a heterogeneous three-dimensional integrated circuit, which has a large memory bandwidth. Therefore, the three-dimensional integrated circuit 2 is suitable for application scenarios with high bandwidth requirements, such as artificial intelligence or data processing applications.

[0121] In the 3D integrated circuit 2, to ensure the power integrity of the chip, decoupling capacitors need to be set in the power distribution network of the chip so that the power distribution network can provide a more stable power supply. The decoupling capacitors can be set in the processor chip 22 of the 3D integrated circuit 2, or they can be set in the ferroelectric memory 21.

[0122] Figure 4 A top view of a ferroelectric memory according to some embodiments; Figure 5 This is an architectural diagram of a ferroelectric memory array according to some embodiments.

[0123] See Figure 4 and Figure 5 Taking the ferroelectric memory 21 as an example of a ferroelectric field-effect transistor memory, the ferroelectric memory 21 includes an array region A1 and a wiring region A2. The ferroelectric memory 21 may include a memory array disposed in the array region A1. The memory array includes a second stacked layer D, which includes a plurality of memory cells U arranged in an array. Along the Z direction, the plurality of memory cells U form a memory cell string 100. In the XY plane, the plurality of memory cell strings 100 can form a memory array. The source layer SL can be electrically connected to the source of the plurality of memory cell strings 100.

[0124] For example, see Figure 5 A storage cell U may include a transistor T, and multiple transistors T are connected together along the direction Z to form a storage cell string 100.

[0125] For example, such as Figure 5 As shown, transistor T is a ferroelectric field-effect transistor (FET). The control electrode of this FET is electrically connected to the word lines (WL1, WL2…WLm-1, WLm), the source is electrically connected to the source layer SL, and the drain is electrically connected to the bit lines (BL1, BL2…BLn-1, BLn). The gate dielectric layer of the FET is made of a ferroelectric material. The FET stores data by changing the polarity of the ferroelectric layer through voltage pulses and obtains the stored data by reading the transistor's current. Its readout mechanism is non-destructive and has high density.

[0126] It should be noted that, Figure 5 The number of transistors T in the memory cell string 100 is only illustrative. The memory cell string 100 of the ferroelectric memory 21 provided in this application embodiment may also include other numbers of transistors T, such as 8, 16, 32, and 64.

[0127] See also Figure 4 and Figure 5The ferroelectric memory 21 also includes a capacitor disposed in the trace area A2, the capacitor including a first stacked layer 30. The capacitor can be used, for example, as a decoupling capacitor, one of which is described below in the related art.

[0128] Figure 6 This is a structural diagram of a decoupling capacitor in related technologies.

[0129] See Figure 4 The decoupling capacitor 3' includes a first conductive layer 31' and a second conductive layer 32', and a dielectric layer 33' disposed between the two. The dielectric layer 33' can be made of a ferroelectric material. Ferroelectric materials have a larger dielectric constant, which is beneficial to increasing the capacitance value of the decoupling capacitor 3'.

[0130] When the dielectric layer 33' is made of ferroelectric material, the decoupling capacitor 3' is a ferroelectric capacitor. Ferroelectric capacitors have a coercive electric field. When the potential difference between the two poles of the ferroelectric capacitor increases and the electric field generated at the poles is greater than the coercive electric field, the ferroelectric domains in the ferroelectric material undergo polarization reversal, and the ferroelectric capacitor changes from one polarization state to another.

[0131] Figure 7 This is a hysteresis loop diagram of the ferroelectric material in a ferroelectric capacitor, where the horizontal axis "V" represents the potential difference between the two poles of the ferroelectric capacitor, and the vertical axis "P" represents the polarization intensity of the ferroelectric material.

[0132] It can be seen that when the potential difference between the two poles of a ferroelectric capacitor increases and the electric field generated by the two poles is greater than the coercive electric field, the ferroelectric domains in the ferroelectric material undergo polarization reversal, and the polarization intensity of the ferroelectric material changes, that is, the polarization state of the ferroelectric capacitor changes. For example, the ferroelectric capacitor changes from the "0" state to the "1" state.

[0133] Figure 8 This is a graph showing the relationship between the capacitance of a ferroelectric capacitor and the potential difference between its two terminals before and after polarization reversal. The horizontal axis “V” represents the potential difference between the two terminals of the ferroelectric capacitor; the vertical axis “C” represents the capacitance of the ferroelectric capacitor; curve “1” is the relationship between the capacitance of the ferroelectric capacitor and the potential difference between its two terminals before polarization reversal; curve “2” is the relationship between the capacitance of the ferroelectric capacitor and the potential difference between its two terminals after polarization reversal.

[0134] It is evident that, assuming the potential difference between the two poles of a ferroelectric capacitor remains constant before and after polarization reversal, the capacitance of the ferroelectric capacitor before polarization reversal is greater than the capacitance of the ferroelectric capacitor after polarization reversal.

[0135] In summary, due to the polarization reversal characteristics of ferroelectric materials, when the potential difference between the two poles of a ferroelectric capacitor is large, the polarization of the ferroelectric material will reverse, causing the capacitance value of the ferroelectric capacitor to change, resulting in poor anti-interference ability of the ferroelectric capacitor.

[0136] To address the aforementioned problems, some embodiments of this application provide a capacitor. Figure 9 This is a structural diagram of a capacitor according to some embodiments; Figure 10 for Figure 9 A top view of the capacitor in the image; Figure 11 for Figure 10 A cross-sectional view of the capacitor along section line AA'; Figure 12 for Figure 11 The equivalent circuit diagram of the capacitor in the image; Figure 13 for Figure 11 A magnified view of the capacitor at point M; Figure 14 for Figure 13 The equivalent circuit diagram of the capacitor in the diagram.

[0137] See Figure 9 The capacitor 3 includes a first stacked layer 30, which includes a plurality of conductive layers 31 and a plurality of first dielectric layers 32 that are alternately stacked, that is, two adjacent conductive layers 31 are separated by a first dielectric layer 32.

[0138] It should be noted that, Figure 9 The number of conductive layers 31 and first dielectric layers 32 is for illustrative purposes only, and the embodiments of this application do not limit this.

[0139] The second stacked layer D mentioned above, which is located in array region A1, includes alternating dielectric layers and gate layers. The plurality of first dielectric layers 32 of the first stacked layer 30 correspond one-to-one with the plurality of dielectric layers of the second stacked layer D. The corresponding first dielectric layers are made of the same material as the dielectric layers of the second stacked layer D and are disposed in the same layer.

[0140] Furthermore, the multiple conductive layers 31 of the first stacked layer 30 correspond one-to-one with the multiple gate layers of the second stacked layer D, and the corresponding conductive layers 31 and gate layers are made of the same material and are disposed in the same layer.

[0141] Furthermore, the conductive layer 31 of the first stacked layer 30 is insulated from the gate layer of the second stacked layer D. For example, the first stacked layer 30 is disposed in the wiring region A2, and the second stacked layer D is disposed in the array region A1. The first stacked layer 30 and the second stacked layer D are disposed in different regions and are discontinuous, that is, the conductive layer 31 of the first stacked layer 30 and the gate layer of the second stacked layer D are disconnected.

[0142] See Figure 10 and Figure 11The multiple conductive layers 31 include a first conductive portion 31a and a second conductive portion 31b connected together.

[0143] For example, such as Figure 9 As shown, a conductive layer 31 includes a first conductive portion 31a and a second conductive portion 31b. The first conductive portion 31a and the second conductive portion 31b of the same conductive layer 31 are located in the same conductive layer and are connected to each other.

[0144] See Figure 11 and Figure 13 The capacitor 3 also includes a first conductive post 33 and a second conductive post 34. The first conductive post 33 penetrates the first conductive part 31a, and the second conductive post 34 penetrates the second conductive part 31b.

[0145] For example, such as Figure 11 As shown, each first conductive post 33 penetrates the first conductive portion 31a of multiple conductive layers 31, and each second conductive post 34 penetrates the second conductive portion 31b of multiple conductive layers 31.

[0146] See also Figure 11 and Figure 13 The capacitor 3 also includes a first ferroelectric layer 35 and a second ferroelectric layer 36, both of which are cylindrical structures.

[0147] The first ferroelectric layer 35 penetrates the first conductive portion 31a and is disposed around the first conductive post 33. The first ferroelectric layer 35 is located between the first conductive post 33 and the first conductive portion 31a to achieve insulation between the first conductive post 33 and the first conductive portion 31a. The second ferroelectric layer 36 penetrates the second conductive portion 31b and is disposed around the second conductive post 34. The second ferroelectric layer 36 is located between the second conductive post 34 and the second conductive portion 31b to achieve insulation between the second conductive post 34 and the second conductive portion 31b.

[0148] For example, such as Figure 11 As shown, each first ferroelectric layer 35 penetrates the first conductive portion 31a of the plurality of conductive layers 31 and is disposed around the first conductive post 33 to separate the first conductive post 33 from the first conductive portion 31a of the plurality of conductive layers 31. Each second ferroelectric layer 36 penetrates the second conductive portion 31b of the plurality of conductive layers 31 and is disposed around the second conductive post 34 to separate the second conductive post 34 from the second conductive portion 31b of the plurality of conductive layers 31.

[0149] It is understandable that, such as Figures 11-14As shown, the first conductive post 33, the first ferroelectric layer 35, and the first conductive portion 31a are configured to form a first capacitor C1, with the first conductive post 33 and the first conductive portion 31a being the two poles of the first capacitor C1. The second conductive post 34, the second ferroelectric layer 36, and the second conductive portion 31b are configured to form a second capacitor C2, with the second conductive post 34 and the second conductive portion 31b being the two poles of the second capacitor C2, and both the first capacitor C1 and the second capacitor C2 are ferroelectric capacitors.

[0150] Since the first conductive part 31a is connected to the second conductive part 31b, that is, one pole of the first capacitor C1 is electrically connected to one pole of the second capacitor C2, the first capacitor C1 and the second capacitor C2 are connected in series.

[0151] The capacitor 3 provided in the above embodiments of this application uses a first conductive post 33 that penetrates the first conductive portion 31a of the conductive layer 31, and uses a first ferroelectric layer 35 that surrounds the first conductive post 33 to separate the first conductive post 33 from the first conductive portion 31a. The first conductive post 33, the first ferroelectric layer 35 and the first conductive portion 31a form a first capacitor C1, and the first conductive post 33 and the first conductive portion 31a serve as the two poles of the first capacitor C1.

[0152] Furthermore, a second conductive post 34 penetrates the second conductive portion 31b of the conductive layer 31, and a second ferroelectric layer 36 is arranged around the second conductive post 34 to separate the second conductive post 34 from the second conductive portion 31b. The second conductive post 34, the second ferroelectric layer 36, and the second conductive portion 31b form a second capacitor C2, with the second conductive post 34 and the second conductive portion 31b serving as the two poles of the second capacitor C2.

[0153] By connecting the first conductive part 31a and the second conductive part 31b, one terminal of the first capacitor C1 is electrically connected to one terminal of the second capacitor C2, thereby connecting the first capacitor C1 and the second capacitor C2 in series. (Reference) Figure 13 The first capacitor C1 and the second capacitor C2 form a series circuit with a potential difference of V1-V2 across the circuit. According to the principle of voltage division in series, the potential difference across the first capacitor C1 should be less than V1-V2, and the potential difference across the second capacitor C2 should also be less than V1-V2. That is, by connecting the capacitors in series, the potential difference across each capacitor can be reduced, thereby reducing the probability of polarization reversal in the ferroelectric layer of the capacitor, ensuring the stability of the capacitor's capacitance, and improving the capacitor's anti-interference capability.

[0154] As can be seen from the preceding text, the series connection of capacitors is achieved by connecting the first conductive part 31a and the second conductive part 31b in the conductive layer 31. Next, the following embodiments of this application provide various arrangements of the first conductive part 31a and the second conductive part 31b to introduce the series connection of capacitors.

[0155] In some embodiments, a conductive layer 31 includes at least one first conductive portion 31a and at least one second conductive portion 31b, and the connected first conductive portion 31a and second conductive portion 31b are located in the same conductive layer so that the first conductive portion 31a and the second conductive portion 31b can be connected.

[0156] For example, see Figure 10 and Figure 11 A conductive layer 31 includes a first conductive portion 31a and a second conductive portion 31b, the first conductive portion 31a and the second conductive portion 31b are connected and are located in the same conductive layer.

[0157] For example, see Figure 11 The first conductive part 31a and the second conductive part 31b, which are located in the same conductive layer, are integrally disposed.

[0158] The first conductive portion 31a and the second conductive portion 31b are arranged along a first direction, which is parallel to the bottom surface P of the first stacked layer 30.

[0159] It should be noted that the first direction can be either the X direction or the Y direction, for example, Figure 10 The first direction is the X direction.

[0160] In some embodiments, see Figure 11 and Figure 12 Multiple first conductive posts 33 penetrate the first conductive portion 31a of a conductive layer 31, equivalent to multiple first capacitors C1 connected in parallel. Multiple second conductive posts 34 penetrate the second conductive portion 31b of a conductive layer 31, equivalent to multiple second capacitors C2 connected in parallel. The first conductive portion 31a and the second conductive portion 31b of the same conductive layer 31 are connected together, so that the multiple first capacitors C1 connected in parallel are connected in series with the multiple second capacitors C2 connected in parallel, forming a third capacitor C3.

[0161] In the above embodiments of this application, the total capacitance of multiple first capacitors C1 connected in parallel is greater than the capacitance of a single first capacitor C1, and the total capacitance of multiple second capacitors C2 connected in parallel is greater than the capacitance of a single second capacitor C2. The capacitance of the third capacitor C3 can be increased, thereby increasing the total capacitance of capacitor 3.

[0162] Furthermore, the multiple first capacitors C1 connected in parallel are connected in series with the multiple second capacitors C2 connected in parallel to form a third capacitor C3. This can reduce the potential difference across the multiple capacitors (first capacitor C1 or second capacitor C2) connected in parallel, and reduce the potential difference across each capacitor. This can reduce the probability of polarization reversal in the ferroelectric layer of the capacitor, ensure the stability of the capacitor's capacitance, and improve the capacitor's anti-interference capability.

[0163] In some embodiments, see Figure 11 and Figure 12 Multiple first conductive pillars 33 penetrate the first conductive part 31a of multiple conductive layers 31, and multiple second conductive pillars 34 penetrate the second conductive part 31b of multiple conductive layers 31, which is equivalent to multiple third capacitors C3 being connected in parallel, and can also increase the total capacitance value of capacitors 3.

[0164] In some embodiments, see Figure 10 and Figure 11 The capacitor 3 also includes a first interconnect electrode 37 and a second interconnect electrode 38. Both the first interconnect electrode 37 and the second interconnect electrode 38 have a comb-like structure, and the first interconnect electrode 37 and the second interconnect electrode 38 are arranged along a first direction.

[0165] Combination Figure 10 The first interconnect electrode 37 includes multiple first interconnect lines 371 and a first connecting part 372. The same end of the multiple first interconnect lines 371 is connected to the first connecting part 372 to form a comb-like structure. The multiple first interconnect lines 371 are the "teeth" of the comb-like structure, and the first connecting part 372 is the "back" of the comb-like structure.

[0166] Similarly, the second interconnect electrode 38 includes multiple second interconnect lines 381 and a second connection portion 382. The same end of the multiple second interconnect lines 381 is connected to the second connection portion 382 to form a comb-like structure. The multiple second interconnect lines 381 are the "tooth" of the comb-like structure, and the second connection portion 382 is the "back" of the comb-like structure.

[0167] See also Figure 10 and Figure 11 Both the first interconnect line 371 and the second interconnect line 381 extend along a second direction, which is parallel to the bottom surface P of the first stacked layer 30 and intersects the first direction, for example, the second direction is perpendicular to the first direction. It is understood that the extension direction of the first interconnect line 371 and the second interconnect line 381 is not the same as the arrangement direction of the first interconnect electrode 37 and the second interconnect electrode 38.

[0168] For example, the first direction is either the X direction or the Y direction, and the second direction is the other, for example... Figure 10 The first direction is the X direction, and the second direction is the Y direction.

[0169] Multiple first interconnect lines 371 are electrically connected to the ends of multiple first conductive posts 33, and multiple first interconnect lines 371 are connected on one side of the first stacked layer 30 along the second direction. That is, the first connection portion 372 of the first interconnect electrode 37 is located on one side of the first stacked layer 30 along the second direction, and electrical signals are transmitted to multiple first conductive posts 33 through the multiple first interconnect lines 371 of the first interconnect electrode 37.

[0170] Multiple second interconnect lines 381 are electrically connected to the ends of multiple second conductive posts 34, and multiple second interconnect lines 381 are connected on one side of the first stacked layer 30 along the second direction. That is, the second connection portion 382 of the second interconnect electrode 38 is located on one side of the first stacked layer 30 along the second direction, and electrical signals are transmitted to multiple second conductive posts 34 through multiple second interconnect lines 381 of the second interconnect electrode 38.

[0171] For example, the first connecting portion 372 and the second connecting portion 382 may be located on the same side of the first stacked layer 30 along the second direction, or they may be located on opposite sides of the first stacked layer 30 along the second direction.

[0172] Figure 15 This is a top view of another capacitor according to some embodiments.

[0173] In some embodiments, see Figure 15 The first interconnect electrode 37 and the second interconnect electrode 38 are also comb-shaped structures, and the first interconnect electrode 37 and the second interconnect electrode 38 are arranged along the first direction.

[0174] For example, Figure 15 The first direction is the Y direction, and the second direction is the X direction.

[0175] The first interconnect line 371 of the first interconnect electrode 37 and the second interconnect line 381 of the second interconnect electrode 38 both extend along a first direction, that is, the extension direction of the first interconnect line 371 and the second interconnect line 381 is the same as the arrangement direction of the first interconnect electrode 37 and the second interconnect electrode 38.

[0176] Multiple first interconnect lines 371 are electrically connected to the ends of multiple first conductive posts 33, and multiple first interconnect lines 371 are connected on one side of the first stacked layer 30 along the first direction. That is, the first connection portion 372 of the first interconnect electrode 37 is located on one side of the first stacked layer 30 along the first direction, and electrical signals are transmitted to multiple first conductive posts 33 through the multiple first interconnect lines 371 of the first interconnect electrode 37.

[0177] Multiple second interconnect lines 381 are electrically connected to the ends of multiple second conductive posts 34, and the multiple second interconnect lines 381 are connected on the other side of the first stacked layer 30 along the first direction. That is, the second connection portion 382 of the second interconnect electrode 38 is located on the other side of the first stacked layer 30 along the first direction, and electrical signals are transmitted to the multiple second conductive posts 34 through the multiple second interconnect lines 381 of the second interconnect electrode 38.

[0178] For example, the first connection portion 372 and the second connection portion 382 are located on opposite sides of the first stacked layer 30 along the first direction.

[0179] In some embodiments, see Figure 15 The plurality of first conductive posts 33 include multiple rows, for example, each row of first conductive posts 33 may extend in the same direction as the first interconnect line 371. A first interconnect line 371 is electrically connected to a row of first conductive posts 33 to transmit an electrical signal to the row of first conductive posts 33 through the first interconnect line 371.

[0180] Alternatively, the plurality of second conductive posts 34 may comprise multiple rows, for example, each row of second conductive posts 34 may extend in the same direction as the second interconnect line 381. A second interconnect line 381 is electrically connected to a row of second conductive posts 34 to transmit an electrical signal to the row of second conductive posts 34 via the second interconnect line 381.

[0181] Alternatively, the plurality of first conductive posts 33 may comprise multiple rows, with a first interconnecting line 371 electrically connected to a row of first conductive posts 33. Furthermore, the plurality of second conductive posts 34 may comprise multiple rows, with a second interconnecting line 381 electrically connected to a row of second conductive posts 34.

[0182] Figure 16 and Figure 17 This is a top view of another capacitor according to some embodiments.

[0183] In some embodiments, see Figure 16 and Figure 17 The first interconnect electrode 37 and the second interconnect electrode 38 are both planar structures, and the first interconnect electrode 37 and the second interconnect electrode 38 are arranged along the first direction.

[0184] For example, Figure 16 The first direction is the X direction, and the second direction is the Y direction; Figure 17 The first direction is the Y direction, and the second direction is the X direction.

[0185] The planar first interconnect electrode 37 is electrically connected to the ends of a plurality of first conductive posts 33 to transmit electrical signals to the plurality of first conductive posts 33 through the first interconnect electrode 37.

[0186] The planar second interconnect electrode 38 is electrically connected to the ends of a plurality of second conductive posts 34 to transmit electrical signals to the plurality of second conductive posts 34 through the second interconnect electrode 38.

[0187] In some embodiments, see Figure 16 and Figure 17 Multiple first conductive pillars 33 are arranged in an array, or multiple second conductive pillars 34 are arranged in an array, or both the multiple first conductive pillars 33 and the multiple second conductive pillars 34 are arranged in an array. This can improve the uniformity of the arrangement of the multiple first conductive pillars 33 and the multiple second conductive pillars 34, and help to improve the signal interference between multiple capacitors.

[0188] Figure 18 A top view of another capacitor according to some embodiments; Figure 19 for Figure 18 The equivalent circuit diagram of the capacitor in the image; Figure 20 A top view of yet another capacitor according to some embodiments; Figure 21 for Figure 20 The equivalent circuit diagram of the capacitor in the diagram.

[0189] In some embodiments, see Figure 18 and Figure 20 A conductive layer 31 may include a plurality of first conductive portions 31a and a plurality of second conductive portions 31b, wherein the plurality of first conductive portions 31a and the plurality of second conductive portions 31b are connected and are all located in the same conductive layer. For example, the plurality of first conductive portions 31a and the plurality of second conductive portions 31b located in the same conductive layer are integrally disposed.

[0190] In this configuration, the first conductive portion 31a and the second conductive portion 31b are arranged alternately along a first direction, for example... Figure 18 and Figure 20 The first direction in all cases is the X direction.

[0191] In some embodiments, see Figure 18 and Figure 19 ,or Figure 20 and Figure 21 Multiple first conductive posts 33 penetrate multiple first conductive portions 31a, equivalent to multiple first capacitors C1 connected in parallel. Multiple second conductive posts 34 penetrate multiple second conductive portions 31b, equivalent to multiple second capacitors C2 connected in parallel. Multiple first conductive portions 31a and multiple second conductive portions 31b of the same conductive layer 31 are connected together, so that the multiple first capacitors C1 connected in parallel and the multiple second capacitors C2 connected in parallel are connected in series to form a third capacitor C3.

[0192] In the above embodiments, by connecting capacitors in series, the potential difference across each capacitor can be reduced, thereby reducing the probability of polarization reversal in the ferroelectric layer of the capacitor, ensuring the stability of the capacitor's capacitance, and improving the capacitor's anti-interference capability.

[0193] In some embodiments, see Figure 18 and Figure 19 ,or Figure 20 and Figure 21 Multiple first conductive pillars 33 penetrate the first conductive part 31a of multiple conductive layers 31, and multiple second conductive pillars 34 penetrate the second conductive part 31b of multiple conductive layers 31, which is equivalent to multiple third capacitors C3 being connected in parallel, and can also increase the total capacitance value of capacitors 3.

[0194] In some embodiments, see Figure 18 and Figure 20The capacitor 3 also includes a first interconnect electrode 37 and a second interconnect electrode 38, both of which have a comb-like structure.

[0195] Combination Figure 18 The first interconnect electrode 37 includes multiple first interconnect lines 371 and a first connecting part 372. The same end of the multiple first interconnect lines 371 is connected to the first connecting part 372 to form a comb-like structure. The multiple first interconnect lines 371 are the "teeth" of the comb-like structure, and the first connecting part 372 is the "back" of the comb-like structure.

[0196] Similarly, the second interconnect electrode 38 includes multiple second interconnect lines 381 and a second connection portion 382. The same end of the multiple second interconnect lines 381 is connected to the second connection portion 382 to form a comb-like structure. The multiple second interconnect lines 381 are the "tooth" of the comb-like structure, and the second connection portion 382 is the "back" of the comb-like structure.

[0197] See also Figure 18 and Figure 20 Multiple first interconnecting lines 371 and multiple second interconnecting lines 381 are arranged along a first direction, and both the first interconnecting lines 371 and the second interconnecting lines 381 extend along a second direction.

[0198] For example, Figure 18 The first direction is the X direction, the second direction is the Y direction, and multiple first interconnecting lines 371 and multiple second interconnecting lines 381 are arranged alternately along the first direction.

[0199] For example, Figure 20 The first direction is the X direction, the second direction is the Y direction, and there may be no second interconnecting line 381 between two adjacent first interconnecting lines 371, or there may be multiple second interconnecting lines 381. There may also be no first interconnecting line 371 between two adjacent second interconnecting lines 381, or there may be multiple first interconnecting lines 371.

[0200] Multiple first interconnect lines 371 are electrically connected to the ends of multiple first conductive posts 33, and multiple first interconnect lines 371 are connected on one side of the first stacked layer 30 along the second direction. That is, the first connection portion 372 of the first interconnect electrode 37 is located on one side of the first stacked layer 30 along the second direction, and electrical signals are transmitted to multiple first conductive posts 33 through the multiple first interconnect lines 371 of the first interconnect electrode 37.

[0201] Multiple second interconnect lines 381 are electrically connected to the ends of multiple second conductive posts 34, and the multiple second interconnect lines 381 are connected on the other side of the first stacked layer 30 along the second direction. That is, the second connection portion 382 of the second interconnect electrode 38 is located on the other side of the first stacked layer 30 along the second direction, and electrical signals are transmitted to the multiple second conductive posts 34 through the multiple second interconnect lines 381 of the second interconnect electrode 38.

[0202] In some embodiments, see Figure 18 and Figure 20 The plurality of first conductive posts 33 include multiple rows, for example, each row of first conductive posts 33 may extend in the same direction as the first interconnect line 371. A first interconnect line 371 is electrically connected to a row of first conductive posts 33 to transmit an electrical signal to the row of first conductive posts 33 through the first interconnect line 371.

[0203] Alternatively, the plurality of second conductive posts 34 may comprise multiple rows, for example, each row of second conductive posts 34 may extend in the same direction as the second interconnect line 381. A second interconnect line 381 is electrically connected to a row of second conductive posts 34 to transmit an electrical signal to the row of second conductive posts 34 via the second interconnect line 381.

[0204] Alternatively, the plurality of first conductive posts 33 may comprise multiple rows, with a first interconnecting line 371 electrically connected to a row of first conductive posts 33. Furthermore, the plurality of second conductive posts 34 may comprise multiple rows, with a second interconnecting line 381 electrically connected to a row of second conductive posts 34.

[0205] In some embodiments, the conductive layer 31 can be divided into multiple blocks to increase the number of capacitors connected in series, thereby further reducing the potential difference across each capacitor, reducing the probability of polarization reversal in the ferroelectric layer of the capacitor, ensuring the stability of the capacitor's capacitance, and improving the capacitor's anti-interference capability.

[0206] Some embodiments of this application also provide a method for manufacturing a capacitor. Figures 22A-22E The diagram illustrates the steps involved in fabricating a capacitor according to some embodiments. The fabrication method includes the following steps:

[0207] See Figure 22A A first stacked layer 30 is formed, which includes a plurality of conductive layers 31 and a plurality of first dielectric layers 32 that are alternately stacked. A conductive layer 31 includes a first conductive portion 31a and a second conductive portion 31b connected together.

[0208] For example, during the formation of the first stacked layer 30 in the wiring area A2, the second stacked layer D is simultaneously formed in the array area A1.

[0209] See Figure 22B The first stacked layer 30 is etched to form a first contact hole H1 penetrating the first conductive portion 31a and a second contact hole H2 penetrating the second conductive portion 31b.

[0210] For example, the first contact hole H1 penetrates the first conductive portion 31a of the plurality of conductive layers 31, and the second contact hole H2 penetrates the second conductive portion 31b of the plurality of conductive layers 31.

[0211] See Figure 22C A first ferroelectric layer 35 is formed on the sidewall of the first contact hole H1, and a second ferroelectric layer 36 is formed on the sidewall of the second contact hole H2.

[0212] See Figure 22D A first conductive pillar 33 is formed on the inner side of the first ferroelectric layer 35, and a second conductive pillar 34 is formed on the inner side of the second ferroelectric layer 36.

[0213] The preparation method provided in the above embodiments of this application first forms a first stacked layer 30, which includes a plurality of conductive layers 31 and a plurality of first dielectric layers 32 alternately stacked. Each conductive layer 31 includes a first conductive portion 31a and a second conductive portion 31b connected together. Then, a first contact hole H1 penetrating the first conductive portion 31a and a second contact hole H2 penetrating the second conductive portion 31b are formed. A first ferroelectric layer 35 and a first conductive pillar 33 are formed on the sidewall of the first contact hole H1, and a second ferroelectric layer 36 and a second conductive pillar 34 are formed on the sidewall of the second contact hole H2.

[0214] A first conductive post 33, a first ferroelectric layer 35, and a first conductive portion 31a form a first capacitor C1, with the first conductive post 33 and the first conductive portion 31a serving as the two electrodes of the first capacitor C1. A second conductive post 34, a second ferroelectric layer 36, and a second conductive portion 31b form a second capacitor C2, with the second conductive post 34 and the second conductive portion 31b serving as the two electrodes of the second capacitor C2. By connecting the first conductive portion 31a and the second conductive portion 31b, one electrode of the first capacitor C1 is electrically connected to one electrode of the second capacitor C2, thereby connecting the first capacitor C1 and the second capacitor C2 in series. This reduces the potential difference across each capacitor, thereby reducing the probability of polarization reversal in the ferroelectric layer of the capacitor, ensuring the stability of the capacitor's capacitance value, and improving the capacitor's anti-interference capability.

[0215] In some embodiments, after forming the first conductive pillar 33 and the second conductive pillar 34, the above preparation method further includes the following steps:

[0216] See Figure 22E A first interconnect electrode 37 and a second interconnect electrode 38 are formed, for example, both the first interconnect electrode 37 and the second interconnect electrode 38 are formed on the top of the first stacked layer 30. The first interconnect electrode 37 is electrically connected to the ends of a plurality of first conductive posts 33 to transmit electrical signals to the plurality of first conductive posts 33. The second interconnect electrode 38 is electrically connected to the ends of a plurality of second conductive posts 34 to transmit electrical signals to the plurality of second conductive posts 34.

[0217] Figure 23 A top view of yet another capacitor according to some embodiments; Figure 24 for Figure 23A cross-sectional view of the capacitor along section line BB'; Figure 25 for Figure 24 The equivalent circuit diagram of the capacitor in the diagram.

[0218] See Figure 23 and Figure 24 A conductive layer 31 includes a plurality of separately arranged conductive blocks 310, which means that a conductive layer 31 is divided into a plurality of conductive blocks 310, and the plurality of conductive blocks 310 are disconnected from each other. Furthermore, a conductive block 310 includes a first conductive portion 31a and a second conductive portion 31b connected together.

[0219] For example, the capacitor 3 further includes a second dielectric layer 40 that extends through the first stacked layer 30 and separates adjacent conductive blocks 310. It is understood that the second dielectric layer 40 divides the conductive layer 31 into multiple conductive blocks 310.

[0220] See Figures 23-25 Multiple first conductive posts 33 penetrate the first conductive portion 31a of a conductive block 310, equivalent to multiple first capacitors C1 connected in parallel. Multiple second conductive posts 34 penetrate the second conductive portion 31b of a conductive block 310, equivalent to multiple second capacitors C2 connected in parallel. The first conductive portion 31a and the second conductive portion 31b of the same conductive block 310 are connected together, so that the multiple first capacitors C1 connected in parallel are connected in series with the multiple second capacitors C2 connected in parallel, forming a third capacitor C3.

[0221] Furthermore, in two adjacent conductive blocks 310, a plurality of second conductive posts 34 penetrating one conductive block 310 are electrically connected to a plurality of first conductive posts 33 penetrating the other conductive block 310, so that the third capacitors C3 of the adjacent conductive blocks 310 are connected in series to form a fourth capacitor C4.

[0222] In the above embodiments of this application, the total capacitance of multiple first capacitors C1 connected in parallel is greater than the capacitance of a single first capacitor C1, and the total capacitance of multiple second capacitors C2 connected in parallel is greater than the capacitance of a single second capacitor C2. The capacitance of a third capacitor C3 and a fourth capacitor C4 can be increased, thereby increasing the total capacitance of capacitor 3.

[0223] Furthermore, multiple first capacitors C1 connected in parallel are connected in series with multiple second capacitors C2 connected in parallel to form a third capacitor C3. The third capacitors C3 of adjacent conductive blocks 310 are connected in series to form a fourth capacitor C4, thereby increasing the number of capacitors connected in series. This can further reduce the potential difference across each capacitor, reduce the probability of polarization reversal in the ferroelectric layer of the capacitor, ensure the stability of the capacitor's capacitance, and improve the capacitor's anti-interference capability.

[0224] In some embodiments, a conductive layer 31 includes a first conductive block to an nth conductive block arranged sequentially, where n ≥ 2 and n is a positive integer.

[0225] For example, see Figure 23 and Figure 24 A conductive layer 31 includes a first conductive block 310a and a second conductive block 310b arranged sequentially, i.e., n=2.

[0226] See also Figure 23 and Figure 24 The capacitor 3 further includes a first interconnect electrode 37, at least one second interconnect electrode 38, and a third interconnect electrode 39. The first interconnect electrode 37 is electrically connected to a first conductive post 33 penetrating the first conductive block. The second interconnect electrode 38 is electrically connected to a second conductive post 34 penetrating the i-th conductive block and to a first conductive post 33 penetrating the (i+1)-th conductive block, where i = 1 to n-1, and i is a positive integer. The third interconnect electrode 39 is electrically connected to a second conductive post 34 penetrating the n-th conductive block.

[0227] For example, see Figure 23 and Figure 24 A conductive layer 31 includes a first conductive block 310a and a second conductive block 310b arranged sequentially, i.e., n=2. In this case, the capacitor 3 includes a second interconnect electrode 38.

[0228] The first interconnect electrode 37 is electrically connected to the first conductive post 33 penetrating the first conductive block 310a, the second interconnect electrode 38 is electrically connected to the second conductive post 34 penetrating the first conductive block 310a and to the first conductive post 33 penetrating the second conductive block 310b, and the third interconnect electrode 39 is electrically connected to the second conductive post 34 penetrating the second conductive block 310b.

[0229] Understandably, in combination Figure 24 and Figure 25 The first interconnect electrode 37 and the third interconnect electrode 39 receive external electrical signals and transmit them to the fourth capacitor C4. The second interconnect electrode 38, as a connection electrode, does not receive external electrical signals.

[0230] Some embodiments of this application also provide a method for manufacturing a capacitor. Figures 26A to 26G The diagram illustrates the steps involved in fabricating another capacitor according to some embodiments. The fabrication method includes the following steps:

[0231] See Figure 26A A first stacked layer 30 is formed, which includes a plurality of conductive layers 31 and a plurality of first dielectric layers 32 that are alternately stacked.

[0232] For example, during the formation of the first stacked layer 30 in the wiring area A2, the second stacked layer D is simultaneously formed in the array area A1.

[0233] See Figure 26B The first stacked layer 30 is etched to form a first contact hole H1 penetrating the first stacked layer 30 and a second contact hole H2 penetrating the first stacked layer 30.

[0234] For example, the first contact hole H1 penetrates through the plurality of conductive layers 31 of the first stacked layer 30, and the second contact hole H2 penetrates through the plurality of conductive layers 31 of the first stacked layer 30.

[0235] See Figure 26C A first ferroelectric layer 35 is formed on the sidewall of the first contact hole H1, and a second ferroelectric layer 36 is formed on the sidewall of the second contact hole H2.

[0236] See Figure 26D A first conductive pillar 33 is formed on the inner side of the first ferroelectric layer 35, and a second conductive pillar 34 is formed on the inner side of the second ferroelectric layer 36.

[0237] In some examples, after forming the first stacked layer 30, the fabrication method further includes the following steps:

[0238] See Figure 26E At least one isolation trench G is formed through the first stacked layer 30. The at least one isolation trench G divides the conductive layer 31 into a plurality of conductive blocks 310. A conductive block 310 includes a first conductive part 31a and a second conductive part 31b, and the first conductive part 31a is connected to the second conductive part 31b.

[0239] Each conductive layer 31 includes the first to the nth conductive blocks arranged sequentially, where n ≥ 2 and n is a positive integer.

[0240] For example, see Figure 26E A conductive layer 31 includes a first conductive block 310a and a second conductive block 310b arranged sequentially, i.e., n=2.

[0241] See Figure 26F A second dielectric layer 40 is formed within the isolation trench G.

[0242] In some examples, after forming the first conductive pillar 33 and the second conductive pillar 34, the fabrication method further includes the following steps:

[0243] See Figure 26GThis forms a first interconnect electrode 37, at least one second interconnect electrode 38, and a third interconnect electrode 39. The first interconnect electrode 37 is electrically connected to a first conductive post 33 penetrating the first conductive block. The second interconnect electrode 38 is electrically connected to a second conductive post 34 penetrating the i-th conductive block and to a first conductive post 33 penetrating the (i+1)-th conductive block, where i = 1 to n-1, and i is a positive integer. The third interconnect electrode 39 is electrically connected to a second conductive post 34 penetrating the n-th conductive block.

[0244] For example, see Figure 26G A conductive layer 31 includes a first conductive block 310a and a second conductive block 310b arranged sequentially, i.e., n=2, in which case a second interconnect electrode 38 is formed.

[0245] The first interconnect electrode 37 is electrically connected to the first conductive post 33 penetrating the first conductive block 310a, the second interconnect electrode 38 is electrically connected to the second conductive post 34 penetrating the first conductive block 310a and to the first conductive post 33 penetrating the second conductive block 310b, and the third interconnect electrode 39 is electrically connected to the second conductive post 34 penetrating the second conductive block 310b.

[0246] The preparation method provided in the above embodiments of this application first forms a first stacked layer 30, which includes a plurality of conductive layers 31 and a plurality of first dielectric layers 32 alternately stacked. Then, a first contact hole H1 penetrating the first conductive portion 31a and a second contact hole H2 penetrating the second conductive portion 31b are formed. A first ferroelectric layer 35 and a first conductive pillar 33 are formed on the sidewall of the first contact hole H1, and a second ferroelectric layer 36 and a second conductive pillar 34 are formed on the sidewall of the second contact hole H2.

[0247] By etching the first stacked layer 30, an isolation trench G is formed that penetrates the first stacked layer 30, and a second dielectric layer 40 is formed in the isolation trench G to divide the conductive layer 31 into multiple conductive blocks 310, thereby increasing the number of capacitors connected in series. This further reduces the potential difference across each capacitor, lowers the probability of polarization reversal in the ferroelectric layer of the capacitor, ensures the stability of the capacitor's capacitance, and improves the capacitor's anti-interference capability.

[0248] Figure 27 A cross-sectional view of yet another capacitor according to some embodiments; Figure 28 for Figure 27 The equivalent circuit diagram of the capacitor in the diagram.

[0249] In some embodiments, see Figure 27The multiple conductive layers 31 include multiple first conductive portions 31a and multiple second conductive portions 31b, with the multiple second conductive portions 31b located on the side of the multiple first conductive portions 31a away from the bottom surface P of the first stacked layer 30.

[0250] For example, a plurality of first conductive portions 31a and a plurality of first dielectric layers 32 are alternately stacked, and a plurality of second conductive portions 31b and a plurality of first dielectric layers 32 are alternately stacked.

[0251] See Figure 27 and Figure 28 Multiple first conductive posts 33 penetrate multiple first conductive parts 31a, which is equivalent to multiple first capacitors C1 connected in parallel. Multiple second conductive posts 34 penetrate multiple second conductive parts 31b, which is equivalent to multiple second capacitors C2 connected in parallel.

[0252] Based on this, the capacitor 3 also includes a third conductive post 41 that penetrates the first stacked layer 30. The third conductive post 41 is electrically connected to a plurality of first conductive parts 31a and a plurality of second conductive parts 31b, so that the plurality of first capacitors C1 connected in parallel are connected in series with the plurality of second capacitors C2 connected in parallel.

[0253] In the above embodiments of this application, the total capacitance of multiple first capacitors C1 connected in parallel is greater than the capacitance of a single first capacitor C1, and the total capacitance of multiple second capacitors C2 connected in parallel is greater than the capacitance of a single second capacitor C2, thereby increasing the total capacitance of capacitor 3.

[0254] Furthermore, connecting multiple first capacitors C1 in parallel with multiple second capacitors C2 in parallel reduces the potential difference across the multiple capacitors (first capacitor C1 or second capacitor C2) in parallel, thereby reducing the potential difference across each capacitor. This reduces the probability of polarization reversal in the ferroelectric layer of the capacitor, ensuring the stability of the capacitor's capacitance and improving its anti-interference capability.

[0255] In some embodiments, see Figure 27 The capacitor 3 also includes a first interconnect electrode 37 and a second interconnect electrode 38. The first interconnect electrode 37 is disposed on the side of the bottom surface P of the first stacked layer 30 away from the plurality of first conductive parts 31a, that is, the first interconnect electrode 37 is disposed at the bottom of the first stacked layer 30, and the first interconnect electrode 37 is electrically connected to the ends of the plurality of first conductive posts 33, and transmits electrical signals to the plurality of first conductive posts 33 through the first interconnect electrode 37.

[0256] The second interconnect electrode 38 is disposed on the side of the plurality of second conductive portions 31b away from the bottom surface P of the first stacked layer 30, that is, the second interconnect electrode 38 is disposed on the top of the first stacked layer 30, and the second interconnect electrode 38 is electrically connected to the ends of the plurality of second conductive posts 34, and transmits electrical signals to the plurality of second conductive posts 34 through the second interconnect electrode 38.

[0257] Some embodiments of this application also provide a method for manufacturing a capacitor. Figures 29A to 29K The diagram illustrates the steps involved in fabricating another type of capacitor according to some embodiments. The fabrication method includes the following steps:

[0258] See Figure 29A A first sub-stacked layer 30a is formed, which includes a plurality of first conductive portions 31a and a plurality of first dielectric layers 32 that are alternately stacked.

[0259] In some examples, a first interconnect electrode 37 is formed before the first sub-stack layer 30a is formed, and the first interconnect electrode 37 is located at the bottom of the first sub-stack layer 30a.

[0260] See Figure 29B This forms a first contact hole H1 that penetrates multiple first conductive parts 31a.

[0261] See Figure 29C A first ferroelectric layer 35 is formed on the sidewall of the first contact hole H1.

[0262] See Figure 29D A first conductive pillar 33 is formed on the inner side of the first ferroelectric layer 35.

[0263] See Figure 29E An insulating layer 42 is formed, which covers the first sub-stacked layer 30a, the first ferroelectric layer 35, and the first conductive pillar 33.

[0264] See Figure 29F A second sub-stacked layer 30b is formed on the side of the insulating layer 42 away from the first sub-stacked layer 30a. The second sub-stacked layer 30b includes a plurality of second conductive portions 31b and a plurality of first dielectric layers 32 that are alternately stacked.

[0265] See Figure 29G This forms a second contact hole H2 that penetrates multiple second conductive parts 31b.

[0266] See Figure 29H A second ferroelectric layer 36 is formed on the sidewall of the second contact hole H2.

[0267] See Figure 29I A second conductive pillar 34 is formed on the inner side of the second ferroelectric layer 36.

[0268] See Figure 29J A third conductive post 41 is formed, which penetrates the second sub-stacked layer 30b, the insulating layer 42 and the first sub-stacked layer 30a, and is electrically connected to a plurality of first conductive parts 31a and a plurality of second conductive parts 31b.

[0269] See in some examples Figure 29K After the third conductive pillar 41 is formed, the second interconnect electrode 38 is formed, which is located on top of the second sub-stack layer 30b.

[0270] The preparation method provided in the above embodiments of this application first forms a first sub-stacked layer 30a, which includes a plurality of alternating first conductive portions 31a and a plurality of first dielectric layers 32. Then, a first contact hole H1 is formed penetrating the plurality of first conductive portions 31a, and a first ferroelectric layer 35 and a first conductive pillar 33 are formed on the sidewall of the first contact hole H1.

[0271] Then, a second sub-stacked layer 30b is formed above the first sub-stacked layer 30a. The second sub-stacked layer 30b includes a plurality of alternately stacked second conductive portions 31b and a plurality of first dielectric layers 32. Then, a second contact hole H2 is formed through the plurality of second conductive portions 31b, and a second ferroelectric layer 36 and a second conductive post 34 are formed on the sidewall of the second contact hole H2.

[0272] Finally, a third conductive post 41 is formed that penetrates the second sub-stacked layer 30b and the first sub-stacked layer 30a. The third conductive post 41 is electrically connected to a plurality of first conductive parts 31a and a plurality of second conductive parts 31b, so that a plurality of first capacitors C1 connected in parallel are connected in series with a plurality of second capacitors C2 connected in parallel. This can reduce the potential difference across each capacitor, thereby reducing the probability of polarization reversal in the ferroelectric layer of the capacitor, ensuring the capacitance value of the capacitor is stable, and improving the anti-interference capability of the capacitor.

[0273] In the above embodiments of this application, the materials of the conductive layer 31, the first conductive pillar 33 and the second conductive pillar 34 include at least one of Ti, Au, W, Mo, Al, Cu, Ru, Ag, TiN and ITO, that is, the materials of the conductive layer 31, the first conductive pillar 33 and the second conductive pillar 34 may include one or more of these materials.

[0274] The material of the first ferroelectric layer 35 includes at least one of ZrO2, HfO2, HfAlO, HfSiO, HfZrO, HfLaO, and HfYO, that is, the material of the first ferroelectric layer 35 may include one or more of these materials. The material of the second ferroelectric layer 36 includes at least one of ZrO2, HfO2, HfAlO, HfSiO, HfZrO, HfLaO, and HfYO, that is, the material of the second ferroelectric layer 36 may include one or more of these materials.

[0275] The first dielectric layer 32 is a single-layer structure or a stacked structure. The material of the first dielectric layer 32 includes at least one of SiO2, Al2O3, HfO2, ZrO2, TiO2, Y2O3, and Si3N4, that is, the material of the first dielectric layer 32 may include one or more of these materials.

[0276] The ferroelectric memory, three-dimensional integrated circuit, and electronic device provided in some embodiments of this application, including the capacitor provided in any of the above embodiments, can achieve the same beneficial effects as the capacitor described above, and will not be repeated here.

[0277] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A ferroelectric memory, characterized in that, The ferroelectric memory includes an array area and a wiring area, wherein the ferroelectric memory includes a storage array disposed in the array area and a capacitor disposed in the wiring area; The capacitor includes: The first stacked layer includes a plurality of conductive layers and a plurality of first dielectric layers arranged in alternating layers; the plurality of conductive layers include connected first conductive portions and second conductive portions; A first conductive post and a second conductive post, wherein the first conductive post penetrates the first conductive portion and the second conductive post penetrates the second conductive portion; A first ferroelectric layer and a second ferroelectric layer, both having a cylindrical structure; the first ferroelectric layer penetrates the first conductive portion and is disposed around the first conductive post; the second ferroelectric layer penetrates the second conductive portion and is disposed around the second conductive post. The capacitor includes a first capacitor and a second capacitor connected in series. The first capacitor includes a first conductive post, a first ferroelectric layer and a first conductive portion. The second capacitor includes a second conductive post, a second ferroelectric layer and a second conductive portion. The plurality of conductive layers include a plurality of first conductive portions and a plurality of second conductive portions, wherein the plurality of second conductive portions are located on the side of the plurality of first conductive portions away from the bottom surface of the first stacked layer; A plurality of first conductive posts penetrate the plurality of first conductive portions, and a plurality of second conductive posts penetrate the plurality of second conductive portions; the capacitor further includes a third conductive post penetrating the first stacked layer, and the third conductive post is electrically connected to the plurality of first conductive portions and the plurality of second conductive portions.

2. The ferroelectric memory according to claim 1, characterized in that, The plurality of first conductive pillars are arranged in an array, and / or the plurality of second conductive pillars are arranged in an array.

3. The ferroelectric memory according to claim 1, characterized in that, The capacitor further includes a first interconnect electrode and a second interconnect electrode; The first interconnect electrode is disposed on the bottom surface of the first stacked layer on the side away from the plurality of first conductive portions, and is electrically connected to the ends of the plurality of first conductive pillars; The second interconnect electrode is disposed on the side of the plurality of second conductive portions away from the bottom surface of the first stacked layer, and is electrically connected to the ends of the plurality of second conductive pillars.

4. The ferroelectric memory according to claim 1, characterized in that, The materials of the conductive layer, the first conductive pillar, and the second conductive pillar include at least one of Ti, Au, W, Mo, Al, Cu, Ru, Ag, TiN, and ITO.

5. The ferroelectric memory according to claim 1, characterized in that, The material of the first ferroelectric layer and / or the second ferroelectric layer includes at least one of ZrO2, HfO2, HfAlO, HfSiO, HfZrO, HfLaO, and HfYO.

6. The ferroelectric memory according to claim 1, characterized in that, The first dielectric layer is a single-layer structure or a stacked structure; The material of the first dielectric layer includes at least one of SiO2, Al2O3, HfO2, ZrO2, TiO2, Y2O3, and Si3N4.

7. The ferroelectric memory according to any one of claims 1 to 6, characterized in that, The storage array includes a second stacking layer, which includes multiple storage cells arranged in an array. The second stacked layer includes alternating third dielectric layers and gate layers; the plurality of first dielectric layers of the first stacked layer correspond one-to-one with the plurality of third dielectric layers of the second stacked layer, and the corresponding first dielectric layers and third dielectric layers are made of the same material and are disposed in the same layer; the plurality of conductive layers of the first stacked layer correspond one-to-one with the plurality of gate layers of the second stacked layer, and the corresponding conductive layers and gate layers are made of the same material, are disposed in the same layer, and are mutually insulated.

8. A method for fabricating a ferroelectric memory, characterized in that, include: A first sub-stacked layer is formed, the first sub-stacked layer comprising a plurality of first conductive portions and a plurality of first dielectric layers alternately stacked; A first contact hole is formed penetrating the plurality of first conductive portions; A first ferroelectric layer is formed on the sidewall of the first contact hole; A first conductive pillar is formed inside the first ferroelectric layer; An insulating layer is formed, which covers the first sub-stacked layer, the first ferroelectric layer, and the first conductive pillar; A second sub-stack layer is formed on the side of the insulating layer away from the first sub-stack layer. The second sub-stack layer includes a plurality of second conductive portions and a plurality of first dielectric layers that are alternately stacked. A second contact hole is formed penetrating the plurality of second conductive portions; A second ferroelectric layer is formed on the sidewall of the second contact hole; A second conductive pillar is formed inside the second ferroelectric layer; A third conductive pillar is formed, which penetrates the second sub-stack layer, the insulating layer and the first sub-stack layer, and is electrically connected to the plurality of first conductive parts and the plurality of second conductive parts.

9. A three-dimensional integrated circuit, characterized in that, include: Ferroelectric memory as described in any one of claims 1 to 7; The processor chip is stacked on top of the ferroelectric memory and electrically connected to the ferroelectric memory.

10. An electronic device, characterized in that, include: Circuit board; The ferroelectric memory as described in any one of claims 1 to 7 or the three-dimensional integrated circuit as described in claim 9 is disposed on the circuit board and electrically connected to the circuit.

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