Liquid ejection head

Abstract

A liquid ejection head is disclosed. The liquid ejection head includes a piezoelectric actuator, a common voltage waveform signal line, a power supply, an auxiliary potential supply, a transistor, a target voltage waveform generation unit, and a control circuit. The power supply supplies a maximum potential that provides maximum deformation to the piezoelectric actuator, a minimum potential that does not provide deformation, and an intermediate potential that provides stable deformation smaller than the maximum deformation. The auxiliary potential supply divides the potential difference between the maximum potential and the intermediate potential and / or the potential difference between the intermediate potential and the minimum potential, and generates an auxiliary potential. The auxiliary potential is stored in a capacitor in a manner that enables charging and discharging of the piezoelectric actuator. The transistor selectively connects the common voltage waveform signal line and a supply line of each potential supplied from the power supply and the auxiliary potential supply. The control circuit compares the target voltage waveform and the common voltage waveform, and controls the transistor in a manner that causes the common voltage waveform to approach the target voltage waveform.

Description

Technical Field

[0001] Embodiments of the present invention relate to liquid ejection heads. Background Technology

[0002] A liquid ejector head is known to supply a predetermined amount of liquid to a predetermined location. The liquid ejector head is mounted on, for example, an inkjet printer, a 3D printer, or a dispensing device. An inkjet printer ejects droplets of ink from its printhead, forming images or the like on the surface of a recording medium. A 3D printer ejects droplets of modeling material from its modeling material ejector head and solidifies them to form a three-dimensional model. A dispensing device ejects droplets of a sample and supplies a predetermined amount to multiple containers or the like.

[0003] The liquid ejector head has multiple channels for ejecting liquid. Each channel includes a nozzle for ejecting liquid, a pressure chamber connected to the nozzle, and a piezoelectric actuator that changes the volume of the pressure chamber. The liquid ejector head also includes a drive circuit that selects the liquid ejection channel from the multiple channels and provides a drive signal to the piezoelectric actuator to drive it. During the liquid ejection action, the piezoelectric actuator and drive circuit generate heat based on the piezoelectric actuator's electrostatic capacitance, charging voltage, number of charging cycles, and number of discharging cycles. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a liquid ejector head that can suppress the heating of the piezoelectric actuator or drive circuit during the liquid ejection action.

[0005] The liquid ejector head according to an embodiment of the present invention includes piezoelectric actuators, a common voltage waveform signal line, a power supply unit, an auxiliary potential supply unit, a transistor array, a target voltage waveform generation unit, and a control circuit. Multiple piezoelectric actuators are configured to eject liquid from a nozzle. The common voltage waveform signal line provides a common voltage waveform to the multiple piezoelectric actuators. The power supply unit supplies: a maximum potential, providing maximum deformation to the piezoelectric actuator; a minimum potential, providing no deformation to the piezoelectric actuator; and an intermediate potential, providing stable deformation to the piezoelectric actuator that is smaller than the maximum deformation. The auxiliary potential supply unit generates an auxiliary potential by dividing the potential difference between the maximum potential and the intermediate potential and / or the potential difference between the intermediate potential and the minimum potential, and stores the charge of the auxiliary potential in a capacitor in a manner capable of charging and discharging the piezoelectric actuators. The transistor array selectively connects the common voltage waveform signal line to the supply lines of each potential supplied from the power supply unit and the auxiliary potential supply unit. The target voltage waveform generation unit generates a target voltage waveform. The control circuit compares the target voltage waveform with the common voltage waveform to control the transistor group in a manner that makes the common voltage waveform approximate the target voltage waveform.

[0006] Another embodiment of the liquid ejector head of the present invention includes a piezoelectric actuator configured to eject liquid from a nozzle; a voltage application unit that provides a voltage waveform to the piezoelectric actuator; a power supply unit that supplies a maximum potential, a minimum potential, and a plurality of intermediate potentials, wherein the maximum potential is the potential that provides the piezoelectric actuator with maximum deformation, the minimum potential is the potential that does not provide deformation to the piezoelectric actuator, and the intermediate potentials are the potentials that provide the piezoelectric actuator with deformation smaller than the maximum deformation; a transistor group consisting of a plurality of transistors that are disconnected from the voltage application unit and connected to the supply lines of each potential supplied from the power supply unit in a manner with variable on-resistance; a target voltage waveform generation unit that generates a target voltage waveform; a comparison unit that compares the target voltage waveform with the voltage waveform of the voltage application unit; and a control circuit that selects a transistor from the transistor group to be turned on based on the result of comparing the target voltage waveform with the voltage waveform of the voltage application unit, and controls the on-resistance of the selected transistor. Attached Figure Description

[0007] Figure 1 This is an overall structural diagram of an inkjet printer equipped with an inkjet head according to an embodiment.

[0008] Figure 2 This is a 3D view of the inkjet head mentioned above.

[0009] Figure 3 This is a partially enlarged cross-sectional view of the head of the inkjet printhead.

[0010] Figure 4 This is a partially enlarged cross-sectional view of the head of the inkjet printhead.

[0011] Figure 5 This is a top view showing a partial magnification of the head of the inkjet printhead.

[0012] Figure 6 This is the drive circuit for the inkjet head mentioned above.

[0013] Figure 7 These are the common voltage waveform and the target voltage waveform generated by the aforementioned driving circuit.

[0014] Figure 8 These are the discrimination circuit and discrimination conditions of the aforementioned driving circuit.

[0015] Figure 9 It is the gate drive circuit of the aforementioned drive circuit.

[0016] Figure 10 It is the VCOM transistor group of the aforementioned drive circuit.

[0017] Figure 11It is the transistor that operates within the aforementioned VCOM transistor group.

[0018] Figure 12 This is a variation of the gate drive circuit described above.

[0019] Figure 13 It is the transistor that operates in the VCOM transistor group when the gate drive circuit is set as described in the above-described variant.

[0020] Figure 14 This is a circuit diagram of the VCOM transistor group when the gate drive circuit is configured as described in the above-described variant.

[0021] Figure 15 It is the auxiliary potential generation circuit of the aforementioned driving circuit.

[0022] Figure 16 This is a variation of the aforementioned auxiliary potential generation circuit.

[0023] Figure 17 It is the selection switch for the aforementioned drive circuit.

[0024] Figure 18 This is an instructional diagram of the actuator's operation, which provides the aforementioned common voltage waveform.

[0025] Explanation of reference numerals in the attached figures

[0026] 10: Inkjet printer; 100-103: Inkjet head; 2: Head; 24: Nozzle; 3: Driver IC; 6: Actuator; 7: VCOM generation circuit; 71, 72: External power supply; 73: Auxiliary potential generation circuit; 74: Target voltage generation circuit; 75: Discrimination circuit; 76: Gate drive circuit; 77: VCOM generation transistor group; Rd: Voltage divider resistor; Cs: Capacitor; Rs: Limiting resistor; OP: Operational amplifier; V1: Maximum potential; V2: Intermediate potential; V0: Minimum potential; V31, V32, V41: Auxiliary potential. Detailed Implementation

[0027] The liquid ejector head according to the embodiment will now be described in detail with reference to the accompanying drawings. Furthermore, the same reference numerals are used to label the same structures in each figure.

[0028] As an example of an image forming apparatus equipped with a liquid ejector head according to the embodiment, an inkjet printer 10 that prints images on a recording medium will be described. Figure 1The outline structure of the inkjet printer 10 is shown. Inside the housing 11, the inkjet printer 10 is arranged the following: a cartridge 12 for storing a sheet S, one example of a recording medium; an upstream transport path 13 for the sheet S; a conveyor belt 14 for transporting the sheet S removed from the cartridge 12; multiple inkjet heads 100-103 for ejecting ink droplets toward the sheet S on the conveyor belt 14; a downstream transport path 15 for the sheet S; an ejection tray 16; and a control board 17. An operation unit 18, serving as a user interface, is located on the upper side of the housing 11.

[0029] Image data printed on the sheet S is generated, for example, by a computer 200, which is an external connection device. The image data generated by the computer 200 is transmitted to the control board 17 of the inkjet printer 10 via cables 201 and connectors 202 and 203.

[0030] Pick-up roller 204 feeds sheets S one by one from cassette 12 to upstream conveyor path 13. Upstream conveyor path 13 consists of feed roller pairs 131 and 132 and sheet guide plates 133 and 134. Sheets S are conveyed to the upper surface of conveyor belt 14 via upstream conveyor path 13. Arrow 104 in the figure shows the conveying path of sheet S from cassette 12 to conveyor belt 14.

[0031] The conveyor belt 14 is a mesh-like annular belt with multiple through holes formed on its surface. Three rollers—drive roller 141, driven rollers 142, and 143—support the conveyor belt 14 for free rotation. A motor 205 rotates the conveyor belt 14 by rotating the drive roller 141. The motor 205 is an example of a drive device. Figure 105 shows the direction of rotation of the conveyor belt 14. A negative pressure container 206 is disposed on the back side of the conveyor belt 14. The negative pressure container 206 is connected to a pressure-reducing fan 207. The fan 207 creates a negative pressure inside the negative pressure container 206 through the airflow, thereby adsorbing and holding the sheet S onto the upper surface of the conveyor belt 14. Figure 106 shows the airflow.

[0032] As an example of a liquid ejector head, inkjet heads 100-103 are configured to face the sheet S held on the conveyor belt 14 with a small gap of, for example, 1 mm. Inkjet heads 100-103 eject ink droplets towards the sheet S. The inkjet heads 100-103 print images as the sheet S passes underneath. Each inkjet head 100-103 has the same structure except for the color of the ejected ink. The ink colors are, for example, cyan, magenta, yellow, and black.

[0033] Inkjet heads 100-103 are connected to ink tanks 315-318 and ink supply pressure adjustment devices 321-324 via ink flow paths 311-314, respectively. Each ink tank 315-318 is positioned above each inkjet head 100-103. In standby mode, to prevent ink from flowing out of the nozzles 24 (see reference 24) of the inkjet heads 100-103... Figure 2 If leakage occurs, the ink supply pressure adjustment devices 321-324 adjust the pressure in each inkjet head 100-103 to a negative pressure relative to atmospheric pressure, for example, -1.2 kPa. During image formation, the ink in each ink tank 315-318 is supplied to each inkjet head 100-103 through the ink supply pressure adjustment devices 321-324.

[0034] After image formation, sheet S is conveyed from conveyor belt 14 to downstream conveyor path 15. Downstream conveyor path 15 consists of feed roller pairs 151, 152, 153, 154 and sheet guide plates 155, 156 that define the conveying path of sheet S. Sheet S is conveyed from discharge port 157 to discharge tray 16 via downstream conveyor path 15. Arrow 107 in the figure shows the conveying path of sheet S.

[0035] Next, the structure of inkjet heads 100-103 will be explained. Refer below. Figures 2-5 The inkjet head 100 will be described, but inkjet heads 101 to 103 have the same structure as inkjet head 100.

[0036] like Figure 2 As shown, the inkjet head 100 includes a head 2, which is an example of a liquid ejection section. The head 2 is connected to a flexible printed wiring board 21, which is an example of a film wiring substrate. The flexible printed wiring board 21 is connected to a printing substrate 22, which is an example of a relay substrate. The head 2 includes a nozzle plate 23, which is an example of a nozzle section. The head 2 is connected to the ink flow path 311. Figure 1 The ink supply pressure adjustment device 321 is connected.

[0037] The nozzles 24 of each ink ejection channel are arranged along a first direction, such as the X direction, of the nozzle plate 23. The nozzle density is set, for example, in the range of 150 to 1200 dpi. The nozzles 24 are not limited to one row, but can also be in multiple rows. The detailed structure of the head 2 will be described later.

[0038] The flexible printed wiring board 21 is, for example, a flexible printed wiring substrate using a synthetic resin film such as polyimide. The flexible printed wiring board 21 is equipped with an integrated circuit (IC) 3 (hereinafter referred to as the driver IC) serving as a driver chip. The printing substrate 22 is a rigid through-hole substrate formed by multiple layers of epoxy resin containing glass fiber and copper wiring layers. The driver IC 3, acting as a control unit, temporarily stores printing data transmitted from the control board 17 of the inkjet printer 10 via the printing substrate 22 and provides drive signals to each channel to eject ink at predetermined timings.

[0039] Figures 3-5This is a partial cross-sectional view of the head 2. The nozzle plate 23 is joined to one side of the pressure chamber substrate 4. The nozzle plate 23 is, for example, a rectangular plate formed of a resin such as polyimide or a metal such as stainless steel. The vibrating plate 5 is joined to the opposite side of the nozzle plate 23 in the pressure chamber substrate 4. The vibrating plate 5 is flexible and deformable when an external force is applied. The vibrating plate 5 is, for example, a thin plate formed of a metal such as nickel or stainless steel. The vibrating plate 5 can also be made of a material other than metal, such as a polyimide film.

[0040] Pressure chambers 42 are formed on pressure chamber substrate 4. Multiple pressure chambers 42 are arranged at the positions of each nozzle 24 and are in communication with each nozzle 24. Pressure chamber substrate 4 is formed of a metal such as stainless steel. As an example, pressure chamber 42 is formed in pressure chamber substrate 4 with a rectangular opening extending through in a second direction, such as the Z direction, and the openings on both sides are blocked by nozzle plate 23 and vibrating plate 5, respectively.

[0041] The pressure chamber 42 is connected to the guide flow path 43 having a narrow section, and is also connected to the ink supply manifold 45 via the ink supply port 44, which serves as an opening through the vibrating plate 5. For each pressure chamber 42, the guide flow path 43 is formed in a groove shape along a third direction, such as the Y direction, on one side of the pressure chamber substrate 4 on the vibrating plate 5 side. The ink supply manifold 45 is formed within a frame 46 that engages with one side of the vibrating plate 5. The ink supply manifold 45 extends in the X direction and is connected to the pressure chamber 42 of each channel via the ink supply port 44 of each channel and the guide flow path 43. The ink supply manifold 45, serving as a common ink chamber, is connected to the ink flow path 311 (see reference). Figure 1 , Figure 2 ).

[0042] The actuators 6 of each channel are arranged in a position opposite to the pressure chamber 42 and the guide flow path 43, separated by the vibrating plate 5. Each actuator 6 is fixed by engaging the side of the actuator 6 opposite to the vibrating plate 5 in the Z direction with the support member 47.

[0043] As an example of a piezoelectric actuator, the actuator 6 is, for example, a stacked piezoelectric actuator formed by alternately stacking piezoelectric elements such as piezoelectric bodies 61, a first internal electrode 62, and a second internal electrode 63 (especially referring to...). Figure 3The polarization directions of each piezoelectric element 61 are arranged opposite to each other in the Z direction, for example, and deformed in the d33 mode. The first internal electrode 62 and the second internal electrode 63 are conductive films formed on the main surfaces of the piezoelectric elements 61, respectively. The first internal electrode 62 is formed on one end face of the actuator 6 in the Y direction and connected to the first external electrode 64 formed on that end face. The second internal electrode 63 is formed on the other end face of the actuator 6 in the Y direction and connected to the second external electrode 65 formed on that end face. The dummy layer 68 is made of the same material as the piezoelectric elements 61. However, since the dummy layer 68 does not have internal electrodes and is not subjected to an electric field, it does not deform. The dummy layer 68 serves as a base for fixing the actuator 6 to the support member 47 (specifically referring to...). Figure 4 ), or polishing allowance for polishing to achieve the precision during or after assembly.

[0044] As an example, in an actuator 6 composed of multiple stacked piezoelectric bodies 61, the first internal electrode 62 and the second internal electrode 63 are respectively deposited on the main surface of each piezoelectric body 61, which is processed into a thin plate shape. Furthermore, the piezoelectric bodies 61 are stacked and fired together to form a single unit. Afterward, the first external electrode 64 and the second external electrode 65 are deposited. Then, the piezoelectric bodies 61 are polarized. The piezoelectric bodies 61 are formed from lead-containing piezoelectric materials such as lead zirconate titanate (PZT) or lead-free piezoelectric materials such as sodium potassium niobate. The first internal electrode 62 and the second internal electrode 63 are deposited using conductive materials that can be fired, such as silver or palladium. The first external electrode 64 and the second external electrode 65 are deposited using known methods such as plating or sputtering, using materials such as Ni, Cr, or Au.

[0045] The first external electrode 64 of each actuator 6 is connected to the independent wiring 66 of the flexible printed wiring board 21 (see reference). Figure 3 The flexible printed wiring board 21 has a substrate 26, individual wirings 66, an adhesive layer 27, and an insulating layer 28. The flexible printed wiring board 21 is configured such that the area where the solder plating layer 29 is formed faces the first external electrode 64, and the first external electrode 64 of each channel is electrically and mechanically connected to the individual wirings 66 by melting the solder. On the other hand, the second external electrode 65 of each channel is connected to a common wiring (not shown), for example, via the flexible printed wiring board 21 to a common potential.

[0046] The support column 60 is disposed between the actuators 6 in each channel via a slot 69. The actuators 6 for driving and the dummy actuators serving as the support columns 60 are formed together using a common piezoelectric element 61, a first internal electrode 62, and a second internal electrode 63, and are divided into individual actuators 6 and support columns 60 by forming the slots 69. The support column 60 is disposed between adjacent pressure chambers 42 at a position abutting against the partition wall 40 (see reference). Figure 4The support column 60 can be formed of other components instead of the piezoelectric element 61 or the like, which is formed in the same way as the actuator 6. For example, the support column can also be integrally formed with the support member 47.

[0047] Figure 6 The diagram shows a drive circuit for generating a common voltage waveform VCOM and supplying it to the actuator 6 to drive the inkjet head 100. The drive circuit consists of a VCOM generation circuit 7 (an example of a control circuit), an auxiliary potential generation circuit 73 connected to external power supplies 71 and 72, and a drive IC 3. The VCOM generation circuit 7 further includes a target voltage generation circuit 74, a discrimination circuit 75, a gate drive circuit 76, a VCOM generation transistor group 77, and a voltage divider circuit 78.

[0048] like Figure 6 As shown, the actuators 6 (Cx1~Cx) of each channel n Each actuator 6 is connected to the output terminal of the drive IC3 via an independent wiring 66 connected to the first external electrode 64. The connection point between the first external electrode 64 and the independent wiring 66 is an independent terminal of the actuator 6. On the other hand, each actuator 6 (Cx1 to Cx2) is connected to the output terminal of the drive IC3 via an independent wiring 66 connected to the first external electrode 64. n The second external electrode 65 is connected to a common potential, such as ground (GND), via a common wiring 67. The connection point between the second external electrode 65 and the common wiring 67 is a common terminal of the actuator 6.

[0049] The actuators 6 in each channel are driven by providing voltage waveforms to individual terminals respectively. Figure 7 The voltage waveform illustrated in (a) is a common voltage waveform VCOM that shows a sequence of ink ejection actions. The common voltage waveform VCOM is an example of the voltage waveform commonly provided to the actuators 6 of each channel. Therefore, it is not necessary to provide a waveform generation circuit for each channel to generate the voltage waveform.

[0050] exist Figure 7 In example (a), the common voltage waveform VCOM is a voltage waveform that causes the voltage to change to a maximum potential V1, a minimum potential V0, an intermediate potential V2, and auxiliary potentials V41, V32, and V31. The maximum potential V1 is the potential that provides the maximum deformation within the deformation range of the actuator 6 during ink ejection. The minimum potential V0 is the potential that does not provide deformation to the actuator 6. The intermediate potential V2 is the potential that provides deformation to the actuator 6 that is smaller than the maximum deformation. The auxiliary potential V41 is the potential between the maximum potential V1 and the intermediate potential V2. The auxiliary potentials V32 and V31 are the potentials between the intermediate potential V2 and the minimum potential V0.

[0051] Here, the deformation of actuator 6 caused by providing an intermediate potential V2 is referred to as "stable deformation". Stable deformation serves as a reference for the operation of ink ejection, for example. For example, in the case of actuator 6 that deforms longitudinally in d33 or d31 mode when the common terminal is connected to a common potential and a voltage is provided to the individual terminal, if stable deformation is used as a reference, it is possible to provide a maximum potential V1 to deform in a first direction (e.g., the direction of stretching) and a minimum potential V0 to deform in a second direction opposite to the first direction (e.g., the direction of contraction).

[0052] The common voltage waveform VCOM is generated using the potentials V1, V41, V2, V32, V31, and V0 supplied from the auxiliary potential generation circuit 73 via the respective supply lines.

[0053] The target voltage generation circuit 74 of the VCOM generation circuit 7 outputs the target voltage waveform V, which forms the basis of the common voltage waveform VCOM. IN Target voltage waveform V IN For example, it is like Figure 7 The waveform shown in (b) is the target voltage waveform V. IN For example, in the case of analog signal output, a voltage waveform identical to or scaled from the voltage waveform to be supplied to actuator 6 is output. Then, within VCOM generation circuit 7, the voltage waveform V is followed. IN The common voltage waveform VCOM is generated using this method. The target voltage waveform V... IN The waveform information is stored in memory 741. The target voltage waveform V stored in memory 741 is... IN The type is not limited to one; it can store multiple target voltage waveforms V. IN The output target voltage waveform V IN An address is provided by address generator 742, read from memory 741, converted into an analog value by D / A converter 743, and output. Target voltage generation circuit 74 is an example of a target voltage waveform generation unit.

[0054] For example, to facilitate analog circuit design, the target voltage waveform V IN The voltage is preferably scaled to a value smaller than the actual target voltage before being output. For example, the actual target voltage is scaled to 1 / 10. When the amplitude of the target voltage waveform is, for example, 20V, the output amplitude of the D / A converter 743 is scaled to 1 / 10 of 2V before being output. The output target voltage waveform V is provided to the discrimination circuit 75 and the gate drive circuit 76, respectively. IN .

[0055] Voltage divider circuit 78 provides feedback to the common voltage waveform VCOM, and its output is able to match the target voltage waveform V.IN The comparison method involves scaling the comparison voltage waveform Vsens. For example, the actual target voltage is scaled to 1 / 10 and set as the target voltage waveform Vsens. IN In this case, the common voltage waveform VCOM is scaled to 1 / 10 and set as the comparison voltage waveform Vsens. The output comparison voltage waveform Vsens is provided to the discrimination circuit 75 and the gate drive circuit 76 respectively.

[0056] like Figure 8 As shown in (a), the discrimination circuit 75, as an example of the comparison unit, compares the target voltage waveform V. IN The signal is compared with the voltage waveform Vsens, and the control signal en-a to en-j is output based on the comparison result. Figure 8 (b) is an example of the discrimination conditions used by the output control signals en-a to en-j of the discrimination circuit 75.

[0057] like Figure 8 As shown in (b), the discrimination circuit 75 detects the target voltage waveform V. IN When the voltage is between the lowest potential V0 and the auxiliary potential V31, when the voltage of the comparison voltage waveform Vsens becomes lower than the target voltage waveform V IN Voltage hours (V) IN >Vsens), making the control signal en-a high and the rest of the control signals low. Conversely, when the voltage of the comparison voltage waveform Vsens becomes higher than the target voltage waveform V... IN When the voltage is high (V) IN <Vsens), sets the control signal en-f to high level and the other control signals to low level. It provides the output control signals en-a and en-f to the gate drive circuit 76.

[0058] The control signals en-a to en-j are used to exclusively control multiple transistors in the VCOM generation transistor group 77. However, in Figure 8 Under the discrimination condition of (b), for example, in the target voltage waveform V IN When passing boundary values ​​such as V31, both control signals en-a and en-b can be at a high level (V IN (When >Vsens). Alternatively, either one can be set to high. The same applies to boundary values ​​for other conditions.

[0059] Similarly, the discrimination circuit 75 detects the target voltage waveform V. IN When the voltage is between the auxiliary potential V31 and the auxiliary potential V32, when the voltage of the comparison voltage waveform Vsens becomes lower than the target voltage waveform V IN Voltage hours (V) IN>Vsens), making the control signal en-b high and the rest of the control signals low. Conversely, when the voltage of the comparison voltage waveform Vsens becomes higher than the target voltage waveform V... IN When the voltage is high (V) IN <Vsens), sets the control signal en-g to high level and the other control signals to low level. It provides the output control signals en-b and en-g to the gate drive circuit 76.

[0060] Similarly, the discrimination circuit 75 detects the target voltage waveform V. IN When the voltage is between the auxiliary potential V32 and the intermediate potential V2, when the voltage of the comparison voltage waveform Vsens becomes lower than that of the target voltage waveform V IN Voltage hours (V) IN >Vsens), making the control signal en-c high and the rest of the control signals low. Conversely, when the voltage of the comparison voltage waveform Vsens becomes higher than the target voltage waveform V... IN When the voltage is high (V) IN <Vsens), sets the control signal en-h to high level and the other control signals to low level. It provides the output control signals en-c and en-h to the gate drive circuit 76.

[0061] Similarly, the discrimination circuit 75 detects the target voltage waveform V. IN When the voltage is between the intermediate potential V2 and the auxiliary potential V41, when the voltage of the comparison voltage waveform Vsens becomes lower than that of the target voltage waveform V IN Voltage hours (V) IN >Vsens), making the control signal en-d high and the rest of the control signals low. Conversely, when the voltage of the comparison voltage waveform Vsens becomes higher than the target voltage waveform V... IN When the voltage is high (V) IN <Vsens), sets the control signal en-i to high level and the other control signals to low level. It provides the output control signals en-d and en-i to the gate drive circuit 76.

[0062] Similarly, the discrimination circuit 75 detects the target voltage waveform V. IN When the voltage is between the auxiliary potential V41 and the maximum potential V1, when the voltage of the comparison voltage waveform Vsens becomes lower than the target voltage waveform V IN Voltage hours (V) IN >Vsens), making the control signal en-e high and the rest of the control signals low. Conversely, when the voltage of the comparison voltage waveform Vsens becomes higher than the target voltage waveform V... IN When the voltage is high (V) IN<Vsens), sets the control signal en-j to high level and the other control signals to low level. It provides the output control signals en-e and en-j to the gate drive circuit 76.

[0063] The gate drive circuit 76 generates and outputs voltages (control voltages C0N to C1P) based on the control signals en-a to en-j input from the discrimination circuit 75. These voltages are used to exclusively control the turn-on of multiple transistors in the VCOM generation transistor group 77, and also control the turn-on resistance of the transistors.

[0064] Regardless of the target voltage waveform V IN What is the value of V? IN When Vsens is equal to the target voltage, the control signals en-a to en-j are all low, meaning the VCOM generation transistor group 77 is completely turned off. To ensure stable circuit operation, a range is defined that can be considered as the target voltage being the same as the detected voltage, and this range is set to Vsens. IN ≈Vsens, at this time, the control signals en-a to en-j can all be made low, so that the VCOM generation transistor group 77 is all turned off.

[0065] Figure 9 This is an example of gate drive circuit 76. Figure 9 The gate drive circuit 76 is composed of multiple differential amplifiers 80-89. The differential amplifiers 80-89 include: differential amplifier groups 80-84, in V... IN > Vsens operation; and differential amplifier groups 85-89, at V IN <Vsens action. V IN The differential amplifiers 80-84, which operate when Vsens is active, connect Vsens to the positive input, causing V... IN Connect to the negative input. Furthermore, connect the anode of diode D to the negative input. On the other hand, connect the inputs of the control signals en-a to en-e assigned to each differential amplifier 80-84 to the cathode of diode D. The resistors connected to the positive and negative inputs of each differential amplifier 80-84 are limiting resistors. In particular, the limiting resistor for the negative input protects diode D.

[0066] On the other hand, V IN Differential amplifiers 85-89, which operate when Vsens is active, also connect Vsens to the positive input, causing V... INConnect it to the negative input. Further, connect the anode of diode D to the positive input. On the other hand, connect the inputs of the control signals en-f to en-j assigned to each differential amplifier 85-89 to the cathode of diode D. The resistors connected to the positive and negative inputs of each differential amplifier 85-89 are limiting resistors. In particular, the limiting resistor for the negative input protects diode D.

[0067] As described, the control signals en-a to en-j input from the discrimination circuit 75 to the gate drive circuit 76 are, for example, as follows: Figure 8 As shown in the discrimination table in (b), under each condition, one is high and the others are low (except when passing boundary values). Therefore, differential amplifiers 80-89 operate exclusively. As an example, as detailed later... Figure 10 The operation of the corresponding transistors in the VCOM generation transistor group 77, together with the operation of the target voltage waveform V, affects the target voltage waveform V. IN The operation of differential amplifiers 80 and 85 when the voltage is between the lowest potential V0 and the auxiliary potential V31 is explained. The voltage of the comparison voltage waveform Vsens is compared with the target voltage waveform V... IN When the voltage is high (V) IN When the control signal en-a is low, the differential amplifier 80 does not perform analog operation and saturates to fix the output C31P at the maximum voltage. Since it sets the gate voltage of the corresponding Pch transistor 96P in the VCOM generation transistor group 77 to the maximum voltage, Pch transistor 96P is fixed to the off operation. At this time, the control signal en-f is high, diode D becomes off, and the differential amplifier 85 performs analog operation. More specifically, the output of the differential amplifier 85 depends on the negative input V... IN The voltage (control voltage) C0N is amplified by the potential difference between the control voltage C0N and the positive input Vsens. The voltage of the control voltage C0N is determined by Vsens. IN The voltage changes due to the potential difference with Vsens. Therefore, the control voltage C0N can change the on-resistance of the corresponding Nch transistor 92 within the VCOM generating transistor group 77.

[0068] When the voltage of the comparison voltage waveform Vsens becomes greater than the target voltage waveform V IN Voltage hours (V) IN When the control signal en-a goes high (>Vsens), diode D turns off, and differential amplifier 80 performs analog operation. More specifically, the output of differential amplifier 80 is determined by the negative input Vsens. IN The voltage (control voltage) C31P is amplified by the potential difference between the control voltage C31P and the positive input Vsens. The voltage of the control voltage C31P is determined by Vsens. INThe voltage C31P changes due to the potential difference with Vsens. Therefore, the control voltage C31P can change the on-resistance of the corresponding Pch transistor 96P within the VCOM generating transistor group 77. At this time, the control signal en-f is low, and the differential amplifier 85 does not perform analog operation but saturates and fixes the output C0N to zero. Since it sets the gate voltage of the corresponding Nch transistor 92 in the VCOM generating transistor group 77 to zero, Nch transistor 92 is fixed in an off-state operation. Similarly, the other differential amplifiers 81-89, in addition to controlling the on / off state of the corresponding transistors, can also change the on-resistance of the transistors through the control voltages CxP and CxN. IN The transistors of transistor group 77, which are valid under the conditions of Vsens, are as follows: Figure 11 As shown.

[0069] VCOM generating transistor group 77 is an example of a waveform generating circuit that generates a common voltage waveform VCOM. VCOM generating transistor group 77 selectively connects the supply lines of multiple potentials V1, V2, V41, V31, V32 supplied from the auxiliary potential generating circuit 73 and the common voltage waveform signal line that provides the common voltage waveform VCOM to the driver IC3.

[0070] Figure 10 This is an example of the structure of a VCOM generating transistor group 77. The VCOM generating transistor group 77 includes a current source switch 91 providing the maximum potential V1, a current sink switch 92 providing the minimum potential V0, a ​​bidirectional switch 93 providing an intermediate potential V2, a bidirectional switch 94 providing an auxiliary potential V41, a bidirectional switch 95 providing an auxiliary potential V32, and a bidirectional switch 96 providing an auxiliary potential V31. Hereinafter, they are sometimes simply referred to as "switches 91 to 96".

[0071] Switches 91 to 96 are constructed using transistors. Switch 91 uses a P-channel Pch transistor, to which a gate voltage C1P is input. The source of the Pch transistor is connected to the maximum potential V1, and its drain is connected to the signal line of the common voltage waveform VCOM. Switch 92 uses an N-channel Nch transistor, to which a gate voltage C0N is input. The drain of the Nch transistor is connected to the signal line of the common voltage waveform VCOM, and its source is connected to the lowest potential V0.

[0072] Because the actuator 6 can be charged and discharged due to the presence of intermediate potential V2 and auxiliary potentials V41, V32, and V31, switches 93-96 are bidirectional switches. Switch 93 connects the P-channel Pch transistor 93P and the N-channel Nch transistor 93N in parallel to form a bidirectional switch. Pch transistor 93P inputs a gate voltage C2P to its gate. The source of Pch transistor 93P is connected to the intermediate potential V2, and its drain is connected to the signal line of the common voltage waveform VCOM. On the other hand, Nch transistor 93N inputs a gate voltage C2N to its gate. The source of Nch transistor 93N is connected to the intermediate potential V2, and its drain is connected to the signal line of the common voltage waveform VCOM. Schottky diodes connected to each transistor prevent reverse current.

[0073] Switch 94 connects the P-channel Pch transistor 94P and the N-channel Nch transistor 94N in parallel to form a bidirectional switch. Pch transistor 94P inputs a gate voltage C41P to its gate. The source of Pch transistor 94P is connected to the auxiliary potential V41, and its drain is connected to the signal line of the common voltage waveform VCOM. Conversely, Nch transistor 94N inputs a gate voltage C41N to its gate. The source of Nch transistor 94N is connected to the auxiliary potential V41, and its drain is connected to the signal line of the common voltage waveform VCOM. Schottky diodes connected to each transistor prevent reverse current.

[0074] Switch 95 connects the P-channel Pch transistor 95P and the N-channel Nch transistor 95N in parallel to form a bidirectional switch. Pch transistor 95P inputs a gate voltage C32P to its gate. The source of Pch transistor 95P is connected to the auxiliary potential V32, and its drain is connected to the signal line of the common voltage waveform VCOM. Conversely, Nch transistor 95N inputs a gate voltage C32N to its gate. The source of Nch transistor 95N is connected to the auxiliary potential V32, and its drain is connected to the signal line of the common voltage waveform VCOM. Schottky diodes connected to each transistor prevent reverse current.

[0075] Switch 96 connects the P-channel Pch transistor 96P and the N-channel Nch transistor 96N in parallel to form a bidirectional switch. Pch transistor 96P inputs a gate voltage C31P to its gate. The source of Pch transistor 96P is connected to the auxiliary potential V31, and its drain is connected to the signal line of the common voltage waveform VCOM. Conversely, Nch transistor 96N inputs a gate voltage C31N to its gate. The source of Nch transistor 96N is connected to the auxiliary potential V31, and its drain is connected to the signal line of the common voltage waveform VCOM. Schottky diodes connected to each transistor prevent reverse current.

[0076] The VCOM generation transistor group 77 exclusively controls the switching on of each transistor in each switch 91-95 using control voltages C0N to C1P input from the gate drive circuit 76. That is, the gate voltage of each transistor is analog-controlled via differential amplifiers 80-89. However, it is configured such that the on-resistance of the transistor changes non-saturatedly according to the voltage, rather than according to on / off states. Thus, it generates, for example, transistors including... Figure 7 The common voltage waveform VCOM of the inclined section is shown in (a).

[0077] As described above Figure 10 The source-side (P) gate input C*P is turned on by a low-level input and a resistor corresponding to that level, and turned off by a high-level input. The source-side (N) gate input C*N is turned on by a high-level input and a resistor corresponding to that level, and turned off by a low-level input. Each transistor is controlled exclusively; when one is turned on with a resistor, the others are turned off. The source-side transistor (P) and the absorber-side transistor (N) connected at the same potential to the bidirectional switches 93-96 can also be turned on simultaneously when the gate of the other is turned on. Furthermore, by using MOS transmission gates (MOS analog switches) for the transistors used, the Schottky diode that blocks reverse current can be omitted. Alternatively, the transistors used can be constructed by connecting a Pch-type DMOS and an Nch-type DMOS in series, omitting the Schottky diode that blocks reverse current.

[0078] When the gate of one side is turned on, and the other side is also turned on simultaneously, as long as the output of the control signals en-a to en-e of the discrimination circuit 75 is used, such as Figure 12 The gate drive circuit 76 shown can be configured as shown. In this case, for V IN Among the VCOM generation transistor group 77 that are valid under various conditions of Vsens, for V IN And Vsens's conditionally valid transistors, such as Figure 13 As shown. Furthermore, when the Schottky diode that blocks reverse current is omitted by using MOS transmission gates (MOS analog switches) for the transistors used, the circuit for generating transistor group 77 of VCOM is as follows: Figure 14 As shown.

[0079] The power supplies for the potentials V1, V2, V41, V32, V31, and V0 used to generate the common voltage waveform VCOM are supplied from the auxiliary potential generation circuit 73. The maximum potential V1, intermediate potential V2, and minimum potential V0 are supplied from external power supplies 71 and 72 connected to the auxiliary potential generation circuit 73. Specifically, the intermediate potential V2 is supplied from the external power supply 71 for voltage V2. The maximum potential V1 is supplied from the external power supplies 71 for voltage V2 and 72 for voltages V1-V2, which are connected in series. The minimum potential V0 is supplied from the negative terminal of the external power supply 71. The values ​​of each potential V1, V2, and V0 can be determined by the structure of the actuator 6, the type of ink, etc. For example, the maximum potential V1 is 30V, the intermediate potential V2 is 18V, and the minimum potential V0 is 0V. The power supplies 71 and 72 for the maximum potential V1, intermediate potential V2, and minimum potential V0 are an example of a power supply unit.

[0080] On the other hand, auxiliary potentials V41, V32, and V31 are not powered by external sources, but are generated by auxiliary potential generation circuit 73. Auxiliary potential V41 is the potential between the maximum potential V1 and the intermediate potential V2. In this example, the potential difference between the maximum potential V1 and the intermediate potential V2 is divided into two equal parts and designated as auxiliary potential V41. For example, V1 = 30V, V2 = 18V, and V41 = 24V. The number of generated auxiliary potentials is not limited to one. That is, the potential difference between the maximum potential V1 and the intermediate potential V2 is divided into m equal parts, generating m-1 auxiliary potentials. "m" is a natural number greater than 2.

[0081] The auxiliary potentials V31 and V32 are different potentials located between the intermediate potential V2 and the lowest potential V0. In this example, the potential difference between the intermediate potential V2 and the lowest potential V0 is divided into three equal parts. One-third of the potential of the intermediate potential V2 is designated as the auxiliary potential V31, and two-thirds of the potential of the intermediate potential V2 is designated as V32. For example, V2 = 18V, V32 = 12V, and V31 = 6V. The number of auxiliary potentials generated is not limited to two. That is, dividing the potential difference between the intermediate potential V2 and the lowest potential V0 into n equal parts generates n-1 auxiliary potentials. "n" is a natural number greater than 2.

[0082] Figure 15This is a preferred example of the auxiliary potential generation circuit 73. The auxiliary potential generation circuit 73 connects two voltage divider resistors Rd1 and Rd2 in series between the maximum potential V1 and the intermediate potential V2 to perform voltage division. The two voltage divider resistors Rd1 and Rd2 use voltage divider resistors with the same resistance value. Thus, the potential difference between the maximum potential V1 and the intermediate potential V2 is divided into two equal parts. Furthermore, two capacitors Cs1 and Cs2 are connected in series between the maximum potential V1 and the intermediate potential V2. The electrostatic capacitance of capacitors Cs1 and Cs2 is made greater than that of all channels of actuator 6 (Cx1 to Cx2). n The total electrostatic capacitance of the actuators is large. Preferably, it is more than ten times greater. For example, in each actuator 6 (Cx1~Cx...) n With an electrostatic capacitance of 1000pF and a channel count of 300ch, the total electrostatic capacitance is 0.3μF. In this case, capacitors Cs1 and Cs2 should each use capacitors with an electrostatic capacitance of 3μF or more, which is more than ten times the capacitance.

[0083] The nodes between voltage divider resistors Rd1 and Rd2 and between capacitors Cs1 and Cs2 are connected via operational amplifier OP1. Operational amplifier OP1 employs a voltage follower structure, connecting the node between voltage divider resistors Rd1 and Rd2 to the positive input and the amplifier's output to the negative input. Furthermore, the limiting resistor R... S1 It is connected between the output of operational amplifier OP1 and the nodes between capacitors Cs1 and Cs2.

[0084] Operational amplifier OP1 uses the auxiliary potential determined by voltage divider resistors Rd1 and Rd2 as the target value to charge and discharge capacitors Cs1 and Cs2. The charge added to the auxiliary potential V41 of capacitors Cs1 and Cs2 is used to charge actuator 6. Furthermore, capacitors Cs1 and Cs2 receive and store the charge from the auxiliary potential V41 discharged from actuator 6. In other words, the charging and discharging of actuator 6 at auxiliary potential V41 is achieved through the transfer of charge between capacitors Cs1 and Cs2 and actuator 6.

[0085] Furthermore, the auxiliary potential generation circuit 73 connects three voltage divider resistors Rd3, Rd4, and Rd5 in series between the intermediate potential V2 and the lowest potential V0 to perform voltage division. The three voltage divider resistors Rd3, Rd4, and Rd5 use voltage divider resistors with the same resistance value. Thus, the potential difference between the intermediate potential V2 and the lowest potential V0 is divided into three equal parts. Furthermore, three capacitors Cs3, Cs4, and Cs5 are connected in series between the intermediate potential V2 and the lowest potential V0. The electrostatic capacitance of capacitors Cs3, Cs4, and Cs5 is respectively greater than that of all channels of actuator 6 (Cx1 to Cx5). n The total electrostatic capacitance is large. Preferably, it is more than ten times greater.

[0086] The nodes between the voltage divider resistors Rd3, Rd4, and Rd5, and the nodes between the capacitors Cs3, Cs4, and Cs5, are connected via operational amplifier OP2. Operational amplifier OP2 employs a voltage follower structure, connecting the node between voltage divider resistors Rd3 and Rd4 to the positive input and the amplifier's output to the negative input. Furthermore, a limiting resistor Rs2 is connected between the output of operational amplifier OP2 and the node between capacitors Cs3 and Cs4. Similarly, operational amplifier OP3 employs a voltage follower structure, connecting the node between voltage divider resistors Rd4 and Rd5 to the positive input and the amplifier's output to the negative input. Furthermore, a limiting resistor Rs3 is connected between the output of operational amplifier OP3 and the node between capacitors Cs4 and Cs5.

[0087] Operational amplifiers OP2 and OP3 use the auxiliary potential determined by voltage divider resistors Rd3, Rd4, and Rd5 as the target value to charge and discharge capacitors Cs3, Cs4, and Cs5. The charge added to the auxiliary potentials V31 and V32 of capacitors Cs3, Cs4, and Cs5 is used to charge actuator 6. Furthermore, capacitors Cs3, Cs4, and Cs5 receive and store the charge from the auxiliary potentials V31 and V32 discharged from actuator 6. In other words, the charging and discharging of actuator 6 at auxiliary potentials V31 and V32 is achieved through the transfer of charge between capacitors Cs3, Cs4, and Cs5 and actuator 6.

[0088] Limiting resistors Rs1, Rs2, and Rs3 prevent operational amplifiers OP1, OP2, and OP3 from over-operating in response to potential changes in auxiliary potentials V41, V31, and V32. Specifically, when the actuator 6 is charged by supplying charge to auxiliary potentials V41, V31, and V32, the voltages of capacitors Cs1, Cs2, Cs3, Cs4, and Cs5 decrease. However, if operational amplifiers OP1, OP2, and OP3 react sensitively to this voltage drop, they consume power. Therefore, limiting resistors Rs1, Rs2, and Rs3 are provided to adjust the response speed of operational amplifiers OP1, OP2, and OP3. Preferably, operational amplifiers OP1, OP2, and OP3 operate only during the initial charging of capacitors Cs1, Cs2, Cs3, Cs4, and Cs5. Furthermore, when operational amplifiers OP1, OP2, and OP3 are used, the resistance values ​​of voltage divider resistors Rd1, Rd2, Rd3, Rd4, and Rd5 can be increased, which also has the advantage of suppressing power consumption.

[0089] The aforementioned auxiliary potential generation circuit 73 is an example of an auxiliary potential supply unit. However, as in Figure 16As shown in the modified example, the auxiliary potential generation circuit 73 may omit the operational amplifiers OP1, OP2, OP3 and the limiting resistors Rs1, Rs2, Rs3.

[0090] The generated common voltage waveform VCOM is provided to the actuators 6 of each channel via the common voltage waveform signal line and the driver IC3. The driver IC3 has a selection switch that selectively provides the common voltage waveform VCOM to the actuators 6 that eject ink. Figure 17 This is an example of a selector switch 97 composed of an analog switch group. The analog switch group is an example of a voltage application unit. For example... Figure 17 As shown, the selection switches 97 for each channel are bidirectional switches to enable charging and discharging of the actuator 6. The driver IC 3 provides control signals Cc1 to Cc2 to the ink-ejecting channels based on the printing data. The corresponding channel selection switches 97 are activated by the control signals Cc1 to Cc2, providing the common voltage waveform VCOM to the actuator 6. The control signals Cc1 to Cc2 are pixel data, for example, input from the control board 17, which serves as the control unit of the printer.

[0091] Next, a common voltage waveform VCOM is generated and selectively provided to actuator 6 to describe the ink ejection action.

[0092] For example, in the initial state, the VCOM generation circuit 7 generates a voltage waveform at the lowest potential V0 and provides it to the independent terminal of the actuator 6. Furthermore, when a sequence of ink ejection actions begins, the VCOM generation circuit 7 generates a voltage waveform that changes from the lowest potential V0 to the intermediate potential V2 and provides it to the actuator 6. That is, within the VCOM generation circuit 7, the target voltage waveform V0 that changes from the lowest potential V0 to the intermediate potential V2 is output. IN And generate a common voltage waveform VCOM in a manner that follows it.

[0093] The actuator 6, supplied with an intermediate potential V2, undergoes stable deformation. Specifically, as... Figure 18 As shown in (a), an electric field is applied in the direction of the polarization axis of the piezoelectric element 61, and the actuator 6 is stretched in the stacking direction (Z direction), causing the volume of the pressure chamber 42 to shrink. This occurs before the ink ejection timing. Furthermore, before the ink ejection operation begins according to the printing data, the intermediate potential V2 is maintained, and the system is set to standby mode.

[0094] After this, when the operation of ejecting one dot of ink begins according to the printing data, the VCOM generation circuit 7 generates a voltage waveform that changes from the intermediate potential V2 to the lowest potential V0 via auxiliary potentials V32 and V31. Meanwhile, the driver IC 3 turns on the selection switch 97 for the ink ejection channel. This provides the ink ejection actuator 6 with a voltage waveform that changes from the intermediate potential V2 to the lowest potential V0 via auxiliary potentials V32 and V31. As a result, as... Figure 18 As shown in (b), the stretched actuator 6 returns to its original position, i.e., contracts relatively, and the volume of the pressure chamber 42 relatively expands. Corresponding to the expansion of the volume of the pressure chamber 42, ink flows into the pressure chamber 42 via the guide flow path 43.

[0095] Then, after the change in driving voltage from V2 to V0 begins, for example, after half the time of the pressure vibration cycle of head 2, the VCOM generation circuit 7 generates a voltage waveform that changes from the lowest potential V0 to the intermediate potential V2 via auxiliary potentials V32 and V31, and provides it to actuator 6. This raises the voltage of actuator 6 from the lowest potential V0 to the intermediate potential V2 via auxiliary potentials V32 and V31, as... Figure 18 As shown in (c), the actuator 6 is stretched in the stacking direction (Z direction), thereby relatively reducing the volume of the pressure chamber 42, so that the ink droplets R are ejected from the nozzle 24.

[0096] Then, after the voltage rises to the intermediate potential V2, for example, after half the pressure vibration cycle of the head 2, the VCOM generation circuit 7 generates a voltage waveform that changes from the intermediate potential V2 to the maximum potential V1 via the auxiliary potential V41, and provides it to the actuator 6. After a predetermined time, the VCOM generation circuit 7 generates a voltage waveform that changes from the maximum potential V1 to the intermediate potential V2 via the auxiliary potential V41, and provides it to the actuator 6. This is achieved through the stretching of the actuator 6 at this time (…). Figure 18 (d) and reset ( Figure 18 (a) This causes the volume of pressure chamber 42 to decrease and reset, thereby attenuating residual vibration. Through this series of actions, a single ink droplet R is ejected. While continuing to eject ink based on print data, the ejection of a single ink droplet, starting at and ending at the intermediate potential V2, is repeated. Then, after the last ink droplet is ejected, as... Figure 7 As shown in (a), the liquid returns to the lowest potential V0, ending a series of liquid ejection actions.

[0097] Voltage waveform of a single ink dot ejected (refer to) Figure 7(a) The voltage waveform starts at and ends at intermediate potential V2. During this period, the potential difference and number of times the head charges the auxiliary potentials V31, V32, and V41 are equal to the potential difference and number of times the head charges the auxiliary potentials V31, V32, and V41. Therefore, during a single ink ejection operation, the auxiliary potentials V31, V32, and V41 regenerate the same charge as the charge discharged from the auxiliary potentials V31, V32, and V41, and the auxiliary potentials V31, V32, and V41 maintain their previous voltage after ink ejection. By supplying and regenerating the charge of the auxiliary potentials V31, V32, and V41, power consumption can be reduced, and the heating of the drive circuit and actuator 6 of the inkjet head 100 can be suppressed. Of course, the voltage waveform for ejecting a single ink dot is not limited to... Figure 7 The voltage waveform of (a) could be, for example, the voltage waveform of multiple drops of ink forming a single point. Furthermore, it is not limited to the aforementioned traction voltage waveform. This is because, during the period from the beginning to the end of the intermediate potential V2, as long as the rule is maintained that the potential difference and number of times the head charges to each auxiliary potential from the beginning are equal to the potential difference and number of times the head charges to the auxiliary potential from the auxiliary potential, then regardless of the voltage waveform, the charge balance of auxiliary potentials V31, V32, and V41 can be maintained. Therefore, the charging amount performed by operational amplifiers OP1, OP2, and OP3 is smaller, thereby saving power consumption.

[0098] Furthermore, since the electrostatic capacitances of capacitors Cs1, Cs2, Cs3, and Cs4 are set relative to those of all channels of actuator 6 (Cx1 to Cx4), n The total electrostatic capacitance of the capacitors is large enough to reduce voltage changes in capacitors Cs1, Cs2, Cs3, and Cs4 within the voltage waveform sequence of a single ink dot ejection. This suppresses excessive power consumption by operational amplifiers OP1, OP2, and OP3. Furthermore, by setting limiting resistors Rs1, Rs2, and Rs3 at the outputs of operational amplifiers OP1, OP2, and OP3, they will not react to minute voltage changes in capacitors Cs1, Cs2, Cs3, and Cs4.

[0099] As explained above, according to any of the above embodiments, it is possible to suppress the heating and power consumption of the actuator 6 and drive circuit during ink ejection. Furthermore, because... Figure 10 Each transistor performs analog operation, thus suppressing the heat generation of actuator 6. In addition, unwanted high-frequency components can be removed from the operation of actuator 6 to stably eject ink.

[0100] Furthermore, the generation methods of auxiliary potentials V31, V32, and V41 differ from those of the intermediate potential V2, but they are also intermediate potentials between the highest and lowest potentials. That is, more than one intermediate potential is set between the highest and lowest potentials. Multiple ink ejection channels do not necessarily need to be provided. Furthermore, the actuator 6 is not limited to a stacked type with multiple piezoelectric elements 61. The piezoelectric element 61 can also be a single-layer actuator. Moreover, the actuator's operation when a driving voltage is applied is not limited to longitudinal vibration. Furthermore, it is not limited to on-demand titration piezoelectric methods, but can also be applied to continuous methods.

[0101] In the above embodiments, the inkjet head 100 of the inkjet printer 10 was described as an example of a liquid ejection device, but the liquid ejection device may also be a modeling material ejection head of a 3D printer or a sample ejection head of a dispensing device.

[0102] The embodiments of the present invention are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are similarly included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A liquid ejector head, characterized in that, have: Multiple piezoelectric actuators are configured to eject liquid from a nozzle; A common voltage waveform signal line provides a common voltage waveform to the plurality of said piezoelectric actuators; The power supply unit supplies a maximum potential, a minimum potential, and an intermediate potential. The maximum potential is the potential that provides the piezoelectric actuator with the maximum deformation, the minimum potential is the potential that does not provide deformation to the piezoelectric actuator, and the intermediate potential is the potential that provides the piezoelectric actuator with a stable deformation smaller than the maximum deformation. An auxiliary potential supply unit generates an auxiliary potential by dividing the potential difference between the maximum potential and the intermediate potential and / or the potential difference between the intermediate potential and the minimum potential, and stores the charge of the auxiliary potential in a capacitor in a manner that enables the piezoelectric actuator to charge and discharge. The transistor array selectively connects the common voltage waveform signal line to the supply lines of each potential supplied from the power supply unit and the auxiliary potential supply unit. A target voltage waveform generation unit generates a target voltage waveform, wherein the target voltage waveform includes a tilted portion, and the tilted portion is varied by the auxiliary potential to any one of the maximum potential, the intermediate potential, and the minimum potential; as well as The control circuit compares the target voltage waveform with the common voltage waveform, generates a voltage corresponding to the magnitude of the potential difference between the target voltage waveform and the common voltage waveform, and provides it to the gate of the transistor for turn-on control, causing the turn-on resistance of the transistor to change in a non-saturated manner, generating a common voltage waveform including the tilted portion, and controlling the transistor group in such a way that the common voltage waveform is close to the target voltage waveform.

2. The liquid ejector head according to claim 1, characterized in that, The target voltage waveform is the waveform that starts at and ends at the intermediate potential when liquid is ejected at each point.

3. The liquid ejector head according to claim 2, characterized in that, The liquid is repeatedly ejected at multiple points. After the liquid ejection at the last point is completed, the common voltage waveform is restored to the lowest potential, thus ending the series of liquid ejection actions.

4. The liquid ejector head according to claim 1, characterized in that, Each transistor in the transistor group is connected to a Schottky diode.

5. The liquid ejector head according to claim 1, characterized in that, The auxiliary potential is generated by dividing the potential difference between the maximum potential and the intermediate potential and / or the potential difference between the intermediate potential and the minimum potential into m equal parts, where m is a natural number greater than 2.

6. A liquid ejector head, characterized in that, have: A piezoelectric actuator configured to eject liquid from a nozzle; The voltage application section provides a voltage waveform to the piezoelectric actuator; The power supply unit supplies a maximum potential, a minimum potential, and multiple intermediate potentials. The maximum potential is the potential that provides the piezoelectric actuator with the maximum deformation, the minimum potential is the potential that does not provide deformation to the piezoelectric actuator, and the intermediate potentials are the potentials that provide the piezoelectric actuator with a deformation smaller than the maximum deformation. A transistor array, consisting of multiple transistors, disconnects or connects the voltage application section to the supply lines of each potential supplied from the power supply section in a manner with variable resistance. The target voltage waveform generation unit generates the target voltage waveform. The comparison unit compares the target voltage waveform with the voltage waveform of the voltage application unit; as well as The control circuit selects a transistor from the transistor group to be turned on, based on a comparison between the target voltage waveform and the voltage waveform of the voltage application unit, and controls the on-resistance of the selected transistor.

7. The liquid ejector head according to claim 6, characterized in that, Exclusive control is applied to each transistor in the transistor group.

8. The liquid ejector head according to claim 6, characterized in that, The liquid is sprayed repeatedly at multiple points, and the series of liquid spraying actions ends after the liquid is sprayed at the last point.

9. The liquid ejector head according to claim 6, characterized in that, The plurality of transistors are connected to Schottky diodes.

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