A method, device and system for testing capacitance of a wafer

Abstract

This invention discloses a method, apparatus, and system for testing the capacitance of a wafer. The wafer contains multiple chips under test (DUTs). Each DUT includes a test plate, a first substrate, a first electrode, and a second electrode. The test plate is insulated from the first substrate. The first electrode is connected to the first substrate, and the second electrode is connected to the test plate. The method includes: detecting a first capacitance value of parasitic capacitance generated by a first detection component and a second detection component; controlling the connection of the first detection component to the first electrode and the connection of the second detection component to the second electrode; detecting a second capacitance value between the first detection component and the second detection component; and obtaining a third capacitance value between the test plate and the first substrate based on the first capacitance value and the second capacitance value.

Description

Technical Field

[0001] This invention relates to the field of wafer technology, and more specifically, to a method for testing the capacitance of a wafer, a device for testing the capacitance of a wafer, and a system for testing the capacitance of a wafer. Background Technology

[0002] In wafer-level chip testing, capacitance testing is a common component. Because the capacitance of chips is relatively small, typically in the range of fF to pF, it is often affected by parasitic capacitance in the testing system, leading to an overestimation of the measured capacitance value.

[0003] When the wafer under test is an uncut wafer, the substrate of all the chips on the wafer is a single unit. When the probe is connected to the electrode connecting the substrate, the entire substrate of the wafer acts as a large electrode, forming a parasitic capacitance between it and the probe above the wafer. Moreover, during wafer-level capacitance testing, if the distance between two probes is too close, parasitic capacitance will also form between the two probes.

[0004] Therefore, it is essential to propose a technical solution that can accurately detect the capacitor under test in a chip. Summary of the Invention

[0005] One objective of this invention is to provide a technical solution that can accurately detect the capacitor under test in a wafer-level chip.

[0006] According to a first aspect of this disclosure, a method for testing the capacitance of a wafer is provided. The wafer has a plurality of chips under test (DUTs). Each DUT includes a test plate, a first substrate, a first electrode, and a second electrode. The test plate is insulated from the first substrate. The first electrode is connected to the first substrate, and the second electrode is connected to the test plate.

[0007] The method includes:

[0008] The first capacitance value of the parasitic capacitance generated by the first detection component and the second detection component is detected;

[0009] Control the connection of the first detection component to the first electrode and the connection of the second detection component to the second electrode;

[0010] Detect the second capacitance value between the first detection component and the second detection component;

[0011] Based on the first capacitance value and the second capacitance value, a third capacitance value is determined between the electrode plate to be tested and the first substrate.

[0012] Optionally, the parasitic capacitance includes at least one of the following: the parasitic capacitance formed by the first detection component and the second detection component, and the parasitic capacitance formed between the second detection component and the first substrate.

[0013] Optionally, at least one reference chip is disposed in the wafer, the reference chip including a second substrate, a third electrode and a fourth electrode, the third electrode being connected to the second substrate, and the second substrate and the first substrate being electrically connected;

[0014] The first capacitance value for detecting the parasitic capacitance generated by the first detection component and the second detection component includes:

[0015] The capacitance value of the parasitic capacitance generated by the first detection component and the second detection component is detected based on the reference chip that is closest to the chip under test, and is used as the first capacitance value.

[0016] Optionally, the wafer is provided with a plurality of reference chips, each reference chip including a second substrate, a third electrode and a fourth electrode, wherein the third electrode is connected to the second substrate and the second substrate and the first substrate are electrically connected;

[0017] The first capacitance value for detecting the parasitic capacitance generated by the first detection component and the second detection component includes:

[0018] The capacitance values ​​of the parasitic capacitance generated by the first detection component and the second detection component are detected by each reference chip respectively;

[0019] The statistical value of the capacitance value of the parasitic capacitance detected by multiple reference chips is determined as the first capacitance value.

[0020] Optionally, detecting the capacitance values ​​of the parasitic capacitances generated by the first and second detection components based on either reference chip includes:

[0021] Control the first detection component to connect to the third electrode of any of the reference chips, and control the second detection component to connect to the fourth electrode of any of the reference chips;

[0022] The capacitance value between the first detection component and the second detection component is detected and used as the capacitance value of the parasitic capacitance generated by the first detection component and the second detection component.

[0023] Optionally, the first capacitance value for detecting the parasitic capacitance generated by the first detection component and the second detection component includes:

[0024] The first detection component is connected to the first electrode, while the second detection component is not connected to the second electrode;

[0025] The capacitance value between the first detection component and the second detection component is detected and used as the first capacitance value.

[0026] Optionally, determining the third capacitance value between the electrode under test and the first substrate based on the first capacitance value and the second capacitance value includes:

[0027] The difference between the second capacitance value and the first capacitance value is determined as the third capacitance value.

[0028] According to a second aspect of this disclosure, a wafer capacitance testing apparatus is provided, characterized in that a plurality of chips under test (DUTs) are disposed in the wafer, each DUT comprising a test plate, a first substrate, a first electrode, and a second electrode, wherein the test plate is insulated from the first substrate, the first electrode is connected to the first substrate, and the second electrode is connected to the test plate.

[0029] The device includes:

[0030] The first detection module is used to detect the first capacitance value of the parasitic capacitance generated by the first detection component and the second detection component;

[0031] The control module is used to control the connection between the first detection component and the first electrode, and the connection between the second detection component and the second electrode;

[0032] The second detection module is used to detect the second capacitance value between the first detection component and the second detection component;

[0033] The capacitance value determination module is used to determine a third capacitance value between the electrode plate under test and the first substrate based on the first capacitance value and the second capacitance value.

[0034] Optionally, at least one reference chip is disposed in the wafer, the reference chip including a second substrate, a third electrode and a fourth electrode, the third electrode being connected to the second substrate, and the second substrate and the first substrate being electrically connected;

[0035] The first detection module is used to detect the capacitance value of the parasitic capacitance generated by the first detection component and the second detection component based on the reference chip that is closest to the chip under test, and use it as the first capacitance value.

[0036] According to a third aspect of this disclosure, a wafer capacitance testing system is provided, including a first detection component, a second detection component, and the apparatus described in the second aspect of this disclosure.

[0037] In this embodiment, before wafer dicing, the first capacitance value of the parasitic capacitance generated by the first detection component and the second detection component is detected. Then, with the first detection component connected to the first electrode and the second detection component connected to the second electrode, the second capacitance value between the first detection component and the second detection component is detected. Based on the first capacitance value and the second capacitance value, the third capacitance value between the test plate of the chip under test and the first substrate can be accurately detected.

[0038] Other features and advantages of the invention will become clear from the following detailed description of exemplary embodiments of the invention with reference to the accompanying drawings. Attached Figure Description

[0039] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments of the invention and, together with their description, serve to explain the principles of the invention.

[0040] Figure 1 A schematic diagram of a wafer provided according to an embodiment of this disclosure;

[0041] Figure 2 This is a flowchart of a wafer capacitance testing method according to an embodiment of the present disclosure;

[0042] Figure 3 This is a schematic diagram of a wafer provided according to an embodiment of the present disclosure;

[0043] Figure 4 for Figure 1 A schematic diagram of the AA cross-section of the middle wafer;

[0044] Figure 5 for Figure 1 A schematic diagram of the AA cross-section of the middle wafer;

[0045] Figure 6 This is a block diagram of a wafer capacitance testing apparatus according to an embodiment of the present disclosure. Detailed Implementation

[0046] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the invention.

[0047] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the invention or its application or use.

[0048] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0049] In all the examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0050] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0051] Figure 1 This is a schematic diagram of a wafer provided according to an embodiment of the present disclosure.

[0052] like Figure 1 As shown, the wafer is composed of a substrate 1-1 and a structural layer 1-2 fabricated by semiconductor technology in the thickness direction. The structural layer 1-2 may include at least one dielectric layer for insulation from the substrate 1-1. Multiple chips under test (DUTs) 1-3 are disposed on the wafer. Each DUT 1-3 includes a test electrode 1-31, a first substrate 1-32, a first electrode 1-33, and a second electrode 1-34. The test electrode 1-31 is located in the structural layer 1-2 of the wafer; therefore, at least one dielectric layer is included between the test electrode 1-31 and the first substrate 1-32.

[0053] The first substrate 1-32 is located on the substrate 1-1 of the wafer. The first electrode 1-33 is connected to the first substrate 1-32. The second electrode 1-34 is connected to the electrode plate to be tested 1-31. The first electrode 1-33 and the second electrode 1-34 form a capacitor.

[0054] Before the wafer is diced, all the first substrates 1-32 of the chips under test 1-3 on the wafer are short-circuited, and each second electrode 1-34 is only connected to the test plate 1-31 of the corresponding chip under test 1-3.

[0055] Figure 2 This is a flowchart of a wafer capacitance testing method provided according to an embodiment of the present disclosure.

[0056] like Figure 2 As shown, the method may include steps S2100 to S2400 as follows:

[0057] Step S2100: Detect the first capacitance value of the parasitic capacitance generated by the first detection component and the second detection component.

[0058] In this embodiment, the detection component can be a probe, and the first and second detection components can move synchronously, making it impossible to control the movement of a single detection component.

[0059] When testing the capacitance between the test plate 1-31 and the first substrate 1-32 using the first detection component 2-1 and the second detection component 2-2, the first detection component 2-1 is connected to the first electrode 1-33, and the second detection component 2-2 is connected to the second electrode 1-34. Figure 1 As shown. Because the first detection component 2-1 and the second detection component 2-2 are close together, a parasitic capacitance Cp_1 can be generated between the first detection component 2-1 and the second detection component 2-2; moreover, because the second detection component 2-2 and the first substrate 1-32 are close together, a parasitic capacitance Cp_2 can also be generated between the second detection component 2-2 and the first substrate 1-32.

[0060] In the first embodiment of this disclosure, as Figure 3 As shown, at least one reference chip 1-4 can be disposed in the wafer. The reference chip may include a reference electrode 1-41, a second substrate 1-42, a third electrode 1-43 and a fourth electrode 1-44. The third electrode 1-43 is connected to the second substrate 1-42, and the reference electrode 1-41 and the fourth electrode 1-44 are disconnected.

[0061] In this embodiment, the reference chip 1-4 and the chip under test 1-3 can be prepared simultaneously. The reference electrode 1-41 of the reference chip 1-4 and the test electrode 1-31 of the chip under test 1-3 can be obtained through the same preparation steps. The position of the reference electrode 1-41 relative to the second substrate 1-42 is the same as the position of the test electrode 1-31 relative to the first substrate 1-32.

[0062] The step of detecting a first capacitance value based on setting at least one reference chip 1-4 in the wafer may include: detecting the capacitance value of the parasitic capacitance generated by the first detection component and the second detection component based on the reference chip that is closest to the chip under test, and using it as the first capacitance value.

[0063] Specifically, based on the capacitance value of the parasitic capacitance generated by the first and second detection components detected by any one of the reference chips, the method may include: controlling the first detection component to connect to the third electrode of the reference chip, controlling the second detection component to connect to the fourth electrode of the reference chip; and detecting the capacitance value between the first and second detection components as the capacitance value of the parasitic capacitance generated by the first and second detection components.

[0064] In this embodiment, when the first detection component 2-1 is connected to the third electrode 1-43 of the reference chip 1-4 and the second detection component 2-2 is connected to the fourth electrode 1-44 of the reference chip 1-4, the capacitance value detected between the first detection component 2-1 and the second detection component 2-2 is the capacitance value of the parasitic capacitance generated by the first detection component 2-1 and the second detection component 2-2.

[0065] Specifically, since the first detection component 2-1 is connected to the third electrode 1-43 and the second substrate 1-42 of the reference chip 1-4, and the second detection component 2-2 is connected to the fourth electrode 1-44, while the reference plate 1-41 is disconnected from the fourth electrode 1-44, the capacitance between the first detection component 2-1 and the second detection component 2-2 does not include the capacitance C0_0 between the reference plate 1-41 and the second substrate 1-42. However, since the first detection component 2-1 and the second detection component 2-2 are close together, a parasitic capacitance Cp_1 can be generated between them; furthermore, since the second detection component 2-2 and the first substrate 1-32 are close together, a parasitic capacitance Cp_2 can also be generated between them.

[0066] Therefore, when the first detection component 2-1 is connected to the third electrode 1-43 and the second detection component 2-2 is not connected to the fourth electrode 1-44, the capacitance between the first detection component 2-1 and the second detection component 2-2 is the parallel capacitance of parasitic capacitance Cp_1 and parasitic capacitance Cp_2. The detected capacitance value of the parasitic capacitance generated by the first detection component 2-1 and the second detection component 2-2 is the sum of the capacitance values ​​of parasitic capacitance Cp_1 and parasitic capacitance Cp_2.

[0067] In this embodiment, a single reference chip may be placed in the wafer, minimizing the impact of the reference chip on the number of chips under test generated on a single wafer. Alternatively, multiple reference chips may be uniformly arranged in the wafer. During capacitance detection, a first capacitance value is determined by the reference chip closest to the chip under test. Subsequently, a third capacitance value between the test plate and the first substrate of the chip under test is detected based on this first capacitance value. This can reduce capacitance errors caused by the positional differences between the reference chip and the chip under test on the wafer.

[0068] Alternatively, based on setting at least one reference chip 1-4 in the wafer, the step of detecting the first capacitance value may include: detecting the capacitance value of the parasitic capacitance generated by the first detection component and the second detection component according to each reference chip; and determining a statistical value of the capacitance values ​​of the parasitic capacitance detected by multiple reference chips as the first capacitance value.

[0069] In this embodiment, the method of detecting the capacitance value of the parasitic capacitance generated by the first detection component and the second detection component by each reference chip can be referred to the aforementioned method of detecting the capacitance value of the parasitic capacitance generated by any one reference chip, and will not be repeated here.

[0070] When the capacitance values ​​of the parasitic capacitances generated by the first and second detection components are detected based on multiple reference chips, a statistical value of these capacitance values ​​can be determined as the first capacitance value. This statistical value can be any one of the average, median, maximum, or minimum values.

[0071] By determining the first capacitance value through this embodiment, and then using the first capacitance value to detect the third capacitance value between the test plate and the first substrate of the chip under test, the detection error of the third capacitance value can be reduced.

[0072] In a second embodiment of this disclosure, detecting the first capacitance value of the parasitic capacitance generated by the first detection component and the second detection component may further include the following steps S2121 to S2122:

[0073] Step S2121: Control the first detection component to connect to the first electrode, and the second detection component to not connect to the second electrode.

[0074] In this embodiment, the first distance is less than the second distance, where the first distance is the minimum distance between the first detection component 2-1 and the wafer, and the second distance is the minimum distance between the second detection component 2-2 and the wafer. Since the first detection component 2-1 and the second detection component 2-2 move synchronously, they can first be controlled to move in a direction parallel to the wafer plane, such that the first detection component 2-1 and the second detection component 2-2 are respectively positioned above the first electrode 1-33 and the second electrode 1-34. Then, the first detection component 2-1 and the second detection component 2-2 are controlled to move closer to the wafer, such that the first detection component 2-1 is connected to the first electrode 1-33, and the second detection component 2-2 is not connected to the second electrode 1-34. Figure 4 As shown.

[0075] Furthermore, when the first detection component is connected to the first electrode and the second detection component is not connected to the second electrode, the closer the second detection component is to the second electrode, the higher the accuracy of the subsequently obtained first capacitance value, and thus the higher the accuracy of the finally obtained third capacitance value.

[0076] Step S2122: Detect the capacitance value between the first detection component and the second detection component, and use it as the first capacitance value.

[0077] When the first detection component 2-1 is connected to the first electrode 1-33 and the second detection component 2-2 is not connected to the second electrode 1-34, the capacitance value detected between the first detection component 2-1 and the second detection component 2-2 is the first capacitance value of the parasitic capacitance generated by the first detection component 2-1 and the second detection component 2-2.

[0078] Specifically, since the first detection component 2-1 is connected to the first substrate 1-32 via the first electrode 1-33, and the second electrode 1-34 is connected to the test plate 1-31, while the second detection component 2-2 is disconnected from the second electrode 1-34, the capacitance between the first detection component 2-1 and the second detection component 2-2 does not include the capacitance C0_1 between the test plate 1-31 and the first substrate 1-32. However, since the first detection component 2-1 and the second detection component 2-2 are close together, a parasitic capacitance Cp_1 can be generated between them; furthermore, since the second detection component 2-2 and the first substrate 1-32 are close together, a parasitic capacitance Cp_2 can also be generated between them.

[0079] Therefore, when the first detection component 2-1 is connected to the first electrode 1-33 and the second detection component 2-2 is not connected to the second electrode 1-34, the capacitance between the first detection component 2-1 and the second detection component 2-2 is the parallel capacitance of parasitic capacitance Cp_1 and parasitic capacitance Cp_2, and the detected first capacitance value is the sum of the capacitance values ​​of parasitic capacitance Cp_1 and parasitic capacitance Cp_2.

[0080] Through this embodiment, the first capacitance value of the parasitic capacitance generated by the first detection component and the second detection component can be accurately detected, and then the third capacitance value between the test plate and the first substrate of the chip under test can be detected more accurately based on the first capacitance value.

[0081] Step S2200: Control the first detection component to connect to the first electrode and the second detection component to the second electrode.

[0082] In obtaining the first capacitance value through the aforementioned first embodiment, based on the connection of the first detection component 2-1 to the third electrode 1-43 of the reference chip 1-4 and the connection of the second detection component 2-2 to the fourth electrode 1-44 of the reference chip 1-4, the first detection component 2-1 and the second detection component 2-2 can be controlled to move away from the wafer, so that neither the first detection component 2-1 nor the second detection component 2-2 is in contact with the wafer. Then, the first detection component 2-1 and the second detection component 2-2 can be controlled to move in a direction parallel to the wafer plane, so that the first detection component 2-1 and the second detection component 2-2 are respectively located above the first electrode 1-33 and the second electrode 1-34 of the chip under test 1-3. Then, the first detection component 2-1 and the second detection component 2-2 can be controlled to move closer to the wafer, so that the first detection component 2-1 is connected to the first electrode 1-33 of the chip under test 1-3 and the second detection component 2-2 is connected to the second electrode 1-34 of the chip under test 1-3.

[0083] In obtaining the first capacitance value through the aforementioned second embodiment, the first detection component 2-1 can be connected to the first electrode 1-33 of the chip under test 1-3, and the second detection component 2-2 can be disconnected from the second electrode 1-34 of the chip under test 1-3. Then, the first detection component 2-1 and the second detection component 2-2 can continue to move closer to the wafer until the second detection component 2-2 connects to the second electrode 1-34 of the chip under test 1-3. At this point, the first detection component 2-1 can deform, while maintaining connection with the first electrode 1-33, such that the first detection component 2-1 is connected to the first electrode 1-33 and the second detection component 2-2 is connected to the second electrode 1-34. Figure 5 As shown.

[0084] Step S2300: Detect the second capacitance value between the first detection component and the second detection component.

[0085] In this embodiment, the second capacitance value can be the capacitance value between the first detection component 2-1 and the second detection component 2-2 when the first detection component 2-1 is connected to the first electrode 1-33 and the second detection component 2-2 is connected to the second electrode 1-34.

[0086] Specifically, since the first detection component 2-1 is connected to the first substrate 1-32 via the first electrode 1-33, and the second detection component 2-2 is connected to the test plate 1-31 via the second electrode 1-34, the capacitance between the first detection component 2-1 and the second detection component 2-2 includes the test capacitance C0_1 between the test plate 1-31 and the first substrate 1-32. Because the first detection component 2-1 and the second detection component 2-2 are close together, a parasitic capacitance Cp_1 can be generated between them; moreover, because the second detection component 2-2 and the first substrate 1-32 are close together, a parasitic capacitance Cp_2 can also be generated between them.

[0087] Therefore, when the first detection component 2-1 is connected to the first electrode 1-33 and the second detection component 2-2 is connected to the second electrode 1-34, the capacitance between the first detection component 2-1 and the second detection component 2-2 is the parallel capacitance of the capacitor under test C0_1, the parasitic capacitance Cp_1 and the parasitic capacitance Cp_2. The detected first capacitance value is the sum of the capacitance values ​​of the capacitor under test C0_1, the parasitic capacitance Cp_1 and the parasitic capacitance Cp_2.

[0088] Step S2400: Based on the first capacitance value and the second capacitance value, obtain the third capacitance value between the plate to be tested and the first substrate.

[0089] In one embodiment of this disclosure, obtaining a third capacitance value between the plate to be tested and the first substrate based on a first capacitance value and a second capacitance value may include: determining the difference between the second capacitance value and the first capacitance value as the third capacitance value.

[0090] In this embodiment, before wafer dicing, the first capacitance value of the parasitic capacitance generated by the first detection component and the second detection component is detected. Then, with the first detection component connected to the first electrode and the second detection component connected to the second electrode, the second capacitance value between the first detection component and the second detection component is detected. Based on the first capacitance value and the second capacitance value, the third capacitance value between the test plate of the chip under test and the first substrate can be accurately detected.

[0091] This disclosure also provides a capacitance testing device for a wafer, wherein a plurality of chips under test are disposed in the wafer, each chip under test including a test plate, a first substrate, a first electrode, and a second electrode. The test plate is insulated from the first substrate. The chip under test includes a first electrode and a second electrode, the first electrode being connected to the first substrate, and the second electrode being connected to the test plate. Figure 6As shown, the capacitance testing device 6000 may include a first detection module 6100, a control module 6200, a second detection module 6300, and a capacitance value determination module 6400.

[0092] The first detection module 6100 is used to detect the first capacitance value of the parasitic capacitance generated by the first detection component and the second detection component.

[0093] The control module 6200 is used to control the connection between the first detection component and the first electrode, and the connection between the second detection component and the second electrode.

[0094] The second detection module 6300 is used to detect the second capacitance value between the first detection component and the second detection component.

[0095] The capacitance value determination module 6400 is used to determine a third capacitance value between the electrode plate to be tested and the first substrate based on the first capacitance value and the second capacitance value.

[0096] In one embodiment of this disclosure, the parasitic capacitance includes at least one of the following: the parasitic capacitance formed by the first detection component and the second detection component, and the parasitic capacitance formed between the second detection component and the first substrate.

[0097] In one embodiment of this disclosure, at least one reference chip is disposed in the wafer, the reference chip including a second substrate, a third electrode and a fourth electrode, the third electrode being connected to the second substrate, and the second substrate and the first substrate being electrically connected;

[0098] The first detection module 6100 can be specifically used for:

[0099] The capacitance value of the parasitic capacitance generated by the first detection component and the second detection component is detected based on the reference chip that is closest to the chip under test, and is used as the first capacitance value.

[0100] In one embodiment of this disclosure, a plurality of reference chips are disposed in the wafer, each reference chip including a second substrate, a third electrode and a fourth electrode, wherein the third electrode is connected to the second substrate, and the second substrate and the first substrate are electrically connected.

[0101] The first detection module 6100 can be specifically used for:

[0102] The capacitance values ​​of the parasitic capacitance generated by the first detection component and the second detection component are detected by each reference chip respectively;

[0103] The statistical value of the capacitance value of the parasitic capacitance detected by multiple reference chips is determined as the first capacitance value.

[0104] In one embodiment of this disclosure, detecting the capacitance value of the parasitic capacitance generated by the first detection component and the second detection component based on either reference chip includes:

[0105] Control the first detection component to connect to the third electrode of any of the reference chips, and control the second detection component to connect to the fourth electrode of any of the reference chips;

[0106] The capacitance value between the first detection component and the second detection component is detected and used as the capacitance value of the parasitic capacitance generated by the first detection component and the second detection component.

[0107] In one embodiment of this disclosure, the first detection module 6100 may specifically be used for:

[0108] The first detection component is connected to the first electrode, while the second detection component is not connected to the second electrode;

[0109] The capacitance value between the first detection component and the second detection component is detected and used as the first capacitance value.

[0110] In one embodiment of this disclosure, the capacitance value determination module is specifically used to: determine the difference between the second capacitance value and the first capacitance value as the third capacitance value.

[0111] This disclosure also provides a wafer capacitance testing system, which may include a first detection component, a second detection component, and the aforementioned capacitance testing device 6000.

[0112] The above embodiments mainly focus on the differences from other embodiments, but those skilled in the art should understand that the above embodiments can be used alone or in combination as needed.

[0113] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on its differences from other embodiments. However, those skilled in the art should understand that the above embodiments can be used individually or in combination as needed. Furthermore, for the apparatus embodiments, since they correspond to the method embodiments, the description is relatively simple; relevant parts can be referred to the corresponding parts of the method embodiments. The system embodiments described above are merely illustrative, and the modules described as separate components may or may not be physically separate.

[0114] This invention can be an apparatus, method, and / or computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for causing a processor to implement various aspects of the invention.

[0115] Computer-readable storage media can be tangible devices capable of holding and storing instructions for use by an instruction execution device. Computer-readable storage media can be, for example—but not limited to—electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical compression devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination of the foregoing. The computer-readable storage media used herein are not to be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0116] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.

[0117] The computer program instructions used to perform the operations of this invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing state information from the computer-readable program instructions. This electronic circuitry can execute the computer-readable program instructions to implement various aspects of the invention.

[0118] Various aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0119] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0120] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0121] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions. It will be known to those skilled in the art that implementation in hardware, implementation in software, and implementation using a combination of software and hardware are equivalent.

[0122] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, and are not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein. The scope of the invention is defined by the appended claims.

Claims

1. A method for testing the capacitance of a wafer, characterized in that, The wafer contains multiple chips under test (DUTs). Each DUT includes a test plate, a first substrate, a first electrode, and a second electrode. The test plate is insulated from the first substrate, the first electrode is connected to the first substrate, and the second electrode is connected to the test plate. The method includes: The first capacitance value of the parasitic capacitance generated by the first detection component and the second detection component is detected; Control the connection of the first detection component to the first electrode and the connection of the second detection component to the second electrode; Detect the second capacitance value between the first detection component and the second detection component; Based on the first capacitance value and the second capacitance value, determine the third capacitance value between the electrode plate to be tested and the first substrate; At least one reference chip is disposed in the wafer. The reference chip includes a second substrate, a third electrode, and a fourth electrode. The third electrode is connected to the second substrate, and the second substrate and the first substrate are electrically connected. The reference chip also includes a reference electrode plate that is fabricated synchronously with the electrode plate under test. The reference electrode plate is disconnected from the fourth electrode. The first capacitance value for detecting the parasitic capacitance generated by the first detection component and the second detection component includes: The first detection component is connected to the third electrode of the reference chip that is closest to the chip under test, and the second detection component is connected to the fourth electrode of the reference chip that is closest to the chip under test. The capacitance value between the first detection component and the second detection component is detected, and this capacitance value is used as the first capacitance value of the parasitic capacitance generated by the first detection component and the second detection component.

2. The method according to claim 1, characterized in that, The parasitic capacitance includes at least one of the following: the parasitic capacitance generated by the first detection component and the second detection component, and the parasitic capacitance generated between the second detection component and the first substrate.

3. The method according to claim 1, characterized in that, The wafer contains multiple reference chips; The first capacitance value for detecting the parasitic capacitance generated by the first detection component and the second detection component includes: The capacitance values ​​of the parasitic capacitance generated by the first detection component and the second detection component are detected by each reference chip respectively; The statistical value of the capacitance value of the parasitic capacitance detected by multiple reference chips is determined as the first capacitance value.

4. The method according to claim 3, characterized in that, The capacitance values ​​of the parasitic capacitances generated by the first and second detection components are detected based on any reference chip, including: Control the first detection component to connect to the third electrode of any of the reference chips, and control the second detection component to connect to the fourth electrode of any of the reference chips; The capacitance value between the first detection component and the second detection component is detected and used as the capacitance value of the parasitic capacitance generated by the first detection component and the second detection component.

5. The method according to claim 1, characterized in that, The step of determining the third capacitance value between the electrode plate under test and the first substrate based on the first capacitance value and the second capacitance value includes: The difference between the second capacitance value and the first capacitance value is determined as the third capacitance value.

6. A wafer capacitance testing device, characterized in that, The wafer contains multiple chips under test (DUTs). Each DUT includes a test plate, a first substrate, a first electrode, and a second electrode. The test plate is insulated from the first substrate, the first electrode is connected to the first substrate, and the second electrode is connected to the test plate. The device includes: The first detection module is used to detect the first capacitance value of the parasitic capacitance generated by the first detection component and the second detection component; The control module is used to control the connection between the first detection component and the first electrode, and the connection between the second detection component and the second electrode; The second detection module is used to detect the second capacitance value between the first detection component and the second detection component; A capacitance value determination module is used to determine a third capacitance value between the electrode plate under test and the first substrate based on the first capacitance value and the second capacitance value; At least one reference chip is disposed in the wafer. The reference chip includes a second substrate, a third electrode, and a fourth electrode. The third electrode is connected to the second substrate, and the second substrate and the first substrate are electrically connected. The reference chip also includes a reference electrode plate that is fabricated synchronously with the electrode plate under test. The reference electrode plate is disconnected from the fourth electrode. The first detection module is used to control the connection of the first detection component to the third electrode of the reference chip that is closest to the chip under test, and to control the connection of the second detection component to the fourth electrode of the reference chip that is closest to the chip under test; and to detect the capacitance value between the first detection component and the second detection component as the first capacitance value of the parasitic capacitance generated by the first detection component and the second detection component.

7. A wafer capacitance testing system, characterized in that, It includes a first detection component, a second detection component, and the device according to claim 6.

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