A computer interlocking system acquisition point-to-point test system and method

Abstract

This invention provides a point-to-point data acquisition and testing system and method for a computer interlocking system. The testing method includes: acquiring logic data using a data acquisition test board and setting the device status of relays; according to the device status of the relays, a WST module sequentially sends several on / off switch control matrices to the data acquisition test board, controlling the sequential closing or opening of a first switch group, a second switch group, ..., an Nth switch group on the data acquisition test board; based on the first test circuit, a second test circuit, ..., an Nth test circuit formed by the closing or opening of the switch groups on the data acquisition test board, electrical data of the corresponding switch groups is obtained; it is determined whether the electrical data matches standard data. If they match, the test circuit is normal, and the relay interface connected to the data acquisition test board is normal; if they do not match, the test circuit is abnormal, and the relay interface connected to the data acquisition test board is abnormal. This method improves testing efficiency and has the advantage of high testing quality.

Description

Technical Field

[0001] This invention belongs to the field of rail transit, and specifically relates to a computer interlocking system for collecting point-to-point test data and a method thereof. Background Technology

[0002] Computer-based interlocking systems are the most basic signal control systems. Unlike other signal control systems, computer-based interlocking systems require connections to a large number of relay interfaces to control different types of trackside equipment. Because these relay interfaces involve core safety functions and are numerous, a method is needed to effectively improve the accuracy and efficiency of relay interface data acquisition and testing. This invention combines the characteristics of computer-based interlocking systems with the point-to-point testing requirements to improve current testing solutions, thereby enhancing testing efficiency and ensuring test quality. Summary of the Invention

[0003] The purpose of this invention is to provide a point-to-point testing system and method for computer interlocking systems, which achieves the advantages of automation and high accuracy in point-to-point testing of interlocking systems.

[0004] To achieve the above objectives, a first aspect of the present invention provides a point-to-point testing system for a computer interlocking system, comprising: two computer interlocking devices connected in communication, each computer interlocking device having a plurality of relay interfaces; each relay interface being connected to a corresponding relay; an SDM module, which is connected to both computer interlocking devices respectively, for recording abnormalities of the computer interlocking devices during testing; and a WST module, which is connected to the corresponding relay interfaces via a plurality of acquisition test boards on the computer interlocking devices, for sending a conduction switch control matrix; each acquisition test board having a plurality of switch groups, each switch group being connected to a corresponding relay interface, and closing or opening the switch group according to the received conduction switch control matrix to obtain the electrical data of the corresponding switch group and complete the acquisition test of the corresponding relay interface.

[0005] Preferably, each of the switch groups includes: a first switch connected in series with a first resistor; a second switch connected in series with a second resistor; the first switch and the second switch are respectively connected to the relay interface to form a test circuit.

[0006] Preferably, each of the acquisition and testing boards is further provided with a microprocessor, which is connected to the WST module and each of the switch groups respectively; the microprocessor receives the on / off switch control matrix and controls the closing or opening of each switch group.

[0007] Preferably, the point-to-point data acquisition and testing system of the computer interlocking system further includes: a handheld terminal module, which is connected to the data acquisition and testing system via a wireless communication module; the handheld terminal module is connected to the WST module and maps the operation interface of the WST module.

[0008] A second aspect of the present invention provides a point-to-point data acquisition and testing method for a computer interlocking system, implemented based on the aforementioned point-to-point data acquisition and testing system for a computer interlocking system, used for testing relay interfaces on computer interlocking equipment. The method includes: acquiring logic data using a data acquisition test board and setting the device status of the relays; according to the device status of the relays, a WST module sequentially sends a plurality of on / off switch control matrices to the data acquisition test board, controlling the sequential closing or opening of a first switch group, a second switch group, ..., an Nth switch group on the data acquisition test board; based on the first test circuit, a second test circuit, ..., an Nth test circuit formed by the closing or opening of the switch groups on the data acquisition test board, obtaining the electrical data of the corresponding switch groups; determining whether the electrical data matches standard data; if they match, the test circuit is normal, and the relay interface connected to the data acquisition test board is normal; if they do not match, the test circuit is abnormal, and the relay interface connected to the data acquisition test board is abnormal.

[0009] Preferably, the logic data collected by the acquisition test board includes 1 or 0; the device status of the relay includes the picked-up or dropped state.

[0010] Preferably, the current and voltage of each resistor in the first test circuit, the second test circuit, ..., the Nth test circuit are tested to obtain the electrical data.

[0011] Preferably, when the relay is in the energized state, the first conduction switch control matrix sent by the WST module to the acquisition and test board is such that all switch groups are in the off state, and the switches in the first switch group, the second switch group, ..., the Nth switch group on the acquisition and test board are all in the off state, forming the first test circuit, the second test circuit, ..., the Nth test circuit.

[0012] Preferably, when the relay is in the energized state, the second conduction switch control matrix sent by the WST module to the acquisition and test board is such that the first switch in the first switch group is in the closed state, the second switch in the first switch group is in the open state, and the switches in the second switch group to the Nth switch group are all in the open state, forming the first test circuit, the second test circuit, ..., the Nth test circuit.

[0013] Preferably, the first standard data corresponding to the first test circuit, the second test circuit, ... the Nth test circuit is that the current value and voltage value of each resistor are all 0; if the measured current value and voltage value of the Nth test circuit are not 0, it indicates that the Nth test circuit is abnormal and the corresponding relay interface is abnormal.

[0014] Preferably, when the relay is in the energized state, the third conduction switch control matrix sent by the WST module to the acquisition and test board is such that the first and second switches in the first switch group are both in the closed state, and the switches in the second to Nth switch groups are all in the open state, forming the first test circuit, the second test circuit, ..., the Nth test circuit.

[0015] Preferably, when the relay is in the energized state, the fourth conduction switch control matrix sent by the WST module to the acquisition and test board is to keep the first and second switches in the first switch group in the closed state, and gradually close the second switch group, the third switch group, ... the Nth switch group in pairs to form the first test circuit, the second test circuit, ... the Nth test circuit.

[0016] Preferably, the second standard data corresponding to the first test circuit is that the current value and voltage value of the first resistor and the second resistor in the first test circuit are equal, and the current value is equal to the ratio of the input voltage to the sum of the first and second resistors. The voltage value and current value of each resistor in the remaining second test circuit, third test circuit, ..., Nth test circuit are always 0. If the measured current value and voltage value in the Nth test circuit are not 0, where N≥2, it indicates that the Nth test circuit is abnormal and the corresponding relay interface is abnormal.

[0017] Preferably, when the relay is in the dropped state, the fifth conduction switch control matrix sent by the WST module to the acquisition and test board is to turn on the first or second switch in the first switch group, the second switch group, ..., the Nth switch group one by one, forming the first test circuit, the second test circuit, ..., the Nth test circuit.

[0018] Preferably, the third standard data corresponding to the first test circuit, the second test circuit, ... the Nth test circuit is that the current value and voltage value of each resistor are all 0; if the measured current value and voltage value of the Nth test circuit are not 0, it indicates that the Nth test circuit is abnormal and the corresponding relay interface is abnormal.

[0019] In summary, compared with the prior art, the point-to-point testing system and method for computer interlocking systems provided by this invention have the following beneficial effects: by setting several switch groups on the acquisition test board, the point-to-point testing of the interlocking system is automated; at the same time, by testing the voltage and current values ​​of the resistors in each switch group, the open circuit status of the test circuit is effectively detected; furthermore, the relay interface connected to a single acquisition test board is tested circuit by circuit, which reduces the acquisition risk, improves the testing efficiency, and ensures the testing quality. Attached Figure Description

[0020] Figure 1 This is a connection diagram of the point-to-point data acquisition and testing system of the computer interlocking system of the present invention;

[0021] Figure 2 This is a schematic diagram of the acquisition test board in the point-to-point acquisition test system of the computer interlocking system of the present invention. Detailed Implementation

[0022] The following will be combined with the appendix in the embodiments of the present invention. Figure 1 ~Attached Figure 2 The technical solutions, structural features, objectives and effects achieved in the embodiments of the present invention will be described in detail.

[0023] It should be noted that the accompanying drawings are in a very simplified form and use non-precise proportions. They are only used to facilitate and clarify the purpose of illustrating the embodiments of the present invention, and are not intended to limit the implementation conditions of the present invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationship, or adjustments to the size should still fall within the scope of the technical content disclosed in the present invention, provided that they do not affect the effects and objectives that the present invention can produce.

[0024] It should be noted that, in this invention, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only the expressly listed elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.

[0025] This invention provides a point-to-point data acquisition and testing system for a computer interlocking system, such as... Figure 1 and Figure 2As shown, it includes: two computer interlocking devices 100 connected in communication (referred to as interlocking A and interlocking B in this embodiment), each computer interlocking device 100 being provided with several relay interfaces 101; each relay interface 101 being connected to a corresponding relay 400; an SDM (Diagnostic Maintenance) module 200, which is connected to the two computer interlocking devices 100 respectively, for recording abnormalities of the computer interlocking devices 100 (i.e., interlocking A and interlocking B) during the test; a WST (Point-to-Point Test Control) module 300, which is connected to the corresponding relay interface 101 through several acquisition test boards 102 set on the computer interlocking devices 100, for sending conduction switch control matrices; each acquisition test board 102 is provided with several switch groups 121, each switch group 121 being connected to the corresponding relay interface 101, and closing or opening the switch group 121 according to the received conduction switch control matrix to obtain the electrical data of the corresponding switch group 121 and complete the acquisition test of the corresponding relay interface 101.

[0026] In this embodiment, as Figure 1 As shown, the SDM module 200 is a computer with maintenance console software for the interlocking system installed. It is connected to interlocking A and interlocking B respectively and is used to record abnormalities of the computer interlocking device 100 during the test. The WST module 300 is a computer terminal such as a laptop or industrial computer with point-to-point test control software installed.

[0027] Each of the switch groups 121 includes: a first switch connected in series with a first resistor; and a second switch connected in series with a second resistor; the first switch and the second switch are respectively connected to the relay interface 101 to form a test circuit. As an exemplary embodiment, such as... Figure 2 As shown, the acquisition and test board 102 is equipped with four switch groups 121. Each switch group 121 includes first switches AZ1, AZ2, AZ3, and AZ4, and first resistors R11, R21, R31, and R41 connected in series with the first switches; second switches AF1, AF2, AF3, and AF4, and second resistors R12, R22, R32, and R42 connected in series with the second switches; the first switch AZ1, the first resistor R11, the relay interface 101, the second resistor R12, and the second switch AF1 are connected in series in sequence to form a first test circuit; the remaining first switches, first resistors, relay interfaces, second resistors, and second switches are connected in the same way to form a second test circuit, a third test circuit, and a fourth test circuit.

[0028] Furthermore, each of the acquisition and testing boards 102 is also equipped with a microprocessor, which is connected to the WST module 300 and each of the switch groups 121 respectively; the microprocessor receives the on / off switch control matrix and controls the switches in each switch group 121 to close or open.

[0029] Furthermore, such as Figure 1 As shown, the point-to-point data acquisition and testing system of the computer interlocking system further includes: a handheld terminal module 500, which is connected to the data acquisition and testing system via a wireless communication module 600; the handheld terminal module 500 is connected to the WST module 300 and maps the operating interface of the WST module 300. As an optional embodiment, a handheld PAD (tablet computer) is used as the handheld terminal module 500 and accesses the system via WIFI, facilitating on-site testing by maintenance personnel.

[0030] Based on the aforementioned point-to-point data acquisition and testing system for a computer interlocking system, this invention also provides a point-to-point data acquisition and testing method for a computer interlocking system, used to test relay interfaces 101 on a computer interlocking device 100. This testing method requires testing each relay interface 101 individually. The relays 400 connected to the tested relay interfaces 101 need to change their states during the test execution, completing one traversal test under different states. Specifically, the method includes the following steps: the data acquisition test board 102 acquires logic data and sets the device state of the relays 400; based on the device state of the relays 400, the WST module 30... 0 sequentially sends several on / off switch control matrices to the acquisition and testing board 102, controlling the sequential closing or opening of the first switch group, the second switch group, ..., the Nth switch group on the acquisition and testing board; based on the first test circuit, the second test circuit, ..., the Nth test circuit formed by the closing or opening of the switch group 121 on the acquisition and testing board 102, the electrical data of the corresponding switch group 121 is obtained; it is determined whether the electrical data matches the standard data. If they match, the test circuit is normal, and the relay interface 101 connected to the acquisition and testing board 102 is normal; if they do not match, the test circuit is abnormal, and the relay interface connected to the acquisition and testing board 102 is abnormal.

[0031] In this embodiment, a schematic diagram of the data acquisition and testing board 102 is shown below. Figure 2As shown, it includes four test circuits. The principle of multi-channel acquisition is the same; for example, 16-channel acquisition requires setting up 16 test circuits. The testing principle of this method is as follows: During the test, the first resistors R11, R21, R31, R41 and the second resistors R12, R22, R32, R42 of the first, second, third, and fourth test circuits need to be tested for current and voltage in real time to obtain the electrical data (i.e., the voltage and current values ​​of each resistor). Because there are no other loads on the acquisition circuit, and the resistance values ​​of the first resistors R11, R21, R31, R41 and the second resistors R12, R22, R32, R42 are equal, during the test, when the test circuit is formed, the voltage and current values ​​of the first resistor R11 and the second resistor R12, the first resistor R21 and the second resistor R22, the first resistor R31 and the second resistor R32, and the first resistor R41 and the second resistor R42 should be the same. Inconsistent voltage and current values ​​indicate a problem with the test circuit, requiring inspection by a test engineer. The first switches AZ1, AZ2, AZ3, AZ4 and the second switches AF1, AF2, AF3, AF4 are controlled by a microprocessor. The acquisition test board 102 receives a conduction switch control matrix containing control status information for the first and second switches every cycle. It then sends the operating states of the first and second switches, forming a conduction switch connection matrix, along with the corresponding voltage and current values ​​for the first and second resistors, to the WST module 300 for logic checks to generate the final test results. The acquisition test board 102 sends the conduction switch connection matrix to the WST module 300 for further consistency verification of the control status and connectivity messages, ensuring test reliability.

[0032] The logic data collected by the acquisition and testing board 102 includes 1 or 0; the device state of the relay 400 includes either a pulled-up or a dropped-down state. The logic data and the device state of the relay 400 are set according to requirements. For example, in this embodiment, when the logic data is 1, the device state of the relay 400 is pulled up; when the logic data is 0, the device state of the relay 400 is dropped. In other embodiments, the device state of the relay 400 corresponding to the logic data may be the opposite of that in this embodiment.

[0033] Furthermore, the timing sequence of the test process for the point-to-point data acquisition test method of the computer interlocking system provided in this embodiment is as follows:

[0034] Step S1: When the relay 400 is in the energized state, the first conduction switch control matrix sent by the WST module 300 to the acquisition and test board 102 is that all switch groups are in the off state, that is, the first switches AZ1, AZ2, AZ3, AZ4 and the second switches AF1, AF2, AF3, AF4 are all in the off state. The acquisition and test board 102 performs current and voltage tests on the first resistors R11, R21, R31, R41 and the second resistors R12, R22, R32, R42 of the first test circuit, the second test circuit, the third test circuit and the fourth test circuit. The standard data corresponding to the first test circuit, the second test circuit, the third test circuit and the fourth test circuit is that the current value and voltage value of each resistor are 0. If the measured current value and voltage value of the Nth test circuit are not 0, it indicates that the Nth test circuit is abnormal and the corresponding relay interface 101 is abnormal.

[0035] Step S2: When the relay 400 is in the energized state, the second conduction switch control matrix sent by the WST module 300 to the acquisition and test board 102 is such that the first switch AZ1 in the first switch group is closed, the second switch AF1 in the first switch group is open, and the first switches AZ2, AZ3, AZ4 and the second switches AF2, AF3, AF4 in the second to fourth switch groups are all open. The acquisition and test board 102 performs current and voltage tests on the first resistors R11, R21, R31, R41 and the second resistors R12, R22, R32, R42 of the first, second, third, and fourth test circuits. The standard data for the first, second, third, and fourth test circuits is that the current and voltage values ​​of each resistor are all 0. If the measured current and voltage values ​​of the Nth test circuit are not 0, it indicates that the Nth test circuit is abnormal, and the corresponding relay interface 101 is abnormal.

[0036] Step S3: When the relay 400 is in the energized state, the third conduction switch control matrix sent by the WST module 300 to the acquisition and test board 102 ensures that the first switch AZ1 and the second switch AF1 in the first switch group are both closed, and the first switches AZ2, AZ3, AZ4 and the second switches AF2, AF3, AF4 in the second to fourth switch groups are all open. The acquisition and test board 102 controls the first resistor R11, R21, R31, R41 and the second resistor R12 in the first test circuit, the second test circuit, the third test circuit, and the fourth test circuit. R22, R32, and R42 are used for current and voltage testing. The second standard data corresponding to the first test circuit is that the current and voltage values ​​of the first resistor R11 and the second resistor R12 in the first test circuit are equal, and the current value is equal to the ratio of the input voltage to the sum of the first and second resistors (i.e., R11 + R12). The voltage and current values ​​of each resistor in the other second, third, and fourth test circuits are always 0. If the measured current and voltage values ​​in the Nth test circuit are not 0, where N ≥ 2, it indicates that the Nth test circuit is abnormal, and the corresponding relay interface 101 is abnormal.

[0037] Step S4: When the relay 400 is in the energized state, the fourth conduction switch control matrix sent by the WST module 300 to the acquisition and test board 102 keeps the first switch AZ1 and the second switch AF1 in the first switch group closed, and gradually closes the second switch group (AZ2, AF2), the third switch group (AZ3, AF3), and the fourth switch group (AZ4, AF4) in pairs. During the process of closing each switch group in sequence, the current value and voltage value of the first resistor R11 and the second resistor R12 in the first test circuit are equal, and the current value is equal to the ratio of the input voltage to the first resistor plus the second resistor (i.e., R11+R12). The voltage value and current value of each resistor in the other second test circuit, third test circuit, and fourth test circuit are always 0. If the measured current value and voltage value in the Nth test circuit are not 0, where N≥2, it indicates that the Nth test circuit is abnormal, and the corresponding relay interface 101 is abnormal.

[0038] Step S5: When the relay 400 is in the dropped state, the fifth conduction switch control matrix sent by the WST module 300 to the acquisition and test board 102 is to turn on the first switch AZ1, AZ2, AZ3, AZ4 or the second switch AF1, AF2, AF3, AF4 in the first switch group, the second switch group, the third switch group, and the fourth switch group one by one. That is, during the test, only one switch in each switch group is closed, and the rest of the switches are in the open state. During this test, the standard data corresponding to the first test circuit, the second test circuit, the third test circuit, and the fourth test circuit is that the current value and voltage value of each resistor are all 0. If the measured current value and voltage value of the Nth test circuit are not 0, it indicates that the Nth test circuit is abnormal, and the corresponding relay interface 101 is abnormal.

[0039] Repeat steps S1 to S5 to complete the data acquisition and testing of all relay interfaces 101 on the computer interlocking device 100, so as to ensure that each relay interface of each computer interlocking device is acquired and tested, thereby improving the comprehensiveness and accuracy of the data acquisition and testing.

[0040] In summary, compared with the prior art, the point-to-point acquisition and testing system and method for computer interlocking systems provided by the present invention automates the point-to-point testing of the interlocking system by setting several switch groups on the acquisition and testing board 102; at the same time, by testing the voltage and current values ​​of the resistors in each switch group, the open circuit status of the test circuit is effectively detected; furthermore, the relay interface 101 connected to a single acquisition and testing board 102 is tested circuit by circuit, which reduces the acquisition risk, improves the testing efficiency, and ensures the testing quality.

[0041] Although the present invention has been described in detail through the preferred embodiments above, it should be understood that the above description should not be considered as a limitation of the present invention. Various modifications and substitutions to the present invention will be apparent to those skilled in the art after reading the above description. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A point-to-point acquisition test system for a computer interlocking system, characterized by, include: Two computer interlocking devices are connected in communication. Each computer interlocking device is equipped with several relay interfaces; each relay interface is connected to a corresponding relay. The SDM module is connected to both of the aforementioned computer interlocking devices and is used to record any abnormalities in the computer interlocking devices during the testing process. The WST module, which is connected to the corresponding relay interface through several acquisition and test boards set on the computer interlocking equipment, is used to send the conduction switch control matrix; Each of the aforementioned acquisition and test boards is equipped with several switch groups, and each switch group is connected to a corresponding relay interface. According to the received on / off switch control matrix, the switch group is closed or opened to obtain the electrical data of the corresponding switch group and complete the acquisition and test of the corresponding relay interface. Each of the switch groups includes: a first switch connected in series with a first resistor; a second switch connected in series with a second resistor; the first switch and the second switch are respectively connected to the relay interface to form a test circuit; In this configuration, the first control matrix ensures that all switch groups are in the off state, and the switches in the first switch group, the second switch group, ..., the Nth switch group on the acquisition and test board are all in the off state. The second conduction switch control matrix is ​​such that the first switch in the first switch group is in the closed state, the second switch in the first switch group is in the open state, and the switches in the second switch group to the Nth switch group are all in the open state. The third control matrix for conducting switches is such that the first and second switches in the first switch group are both in the closed state, and the switches in the second to Nth switch groups are all in the open state. The fourth control matrix is ​​designed to keep both the first and second switches in the first switch group closed. The fifth control matrix turns on the first switch in the first switch group, the second switch group, ..., the Nth switch group, and turns on the first or second switch in turn.

2. The point-to-point acquisition test system for a computer interlocking system of claim 1, wherein, Each of the acquisition and test boards is also equipped with a microprocessor, which is connected to the WST module and each of the switch groups respectively; the microprocessor receives the on / off switch control matrix and controls the closing or opening of each switch group.

3. The point-to-point acquisition test system for a computer interlocking system of claim 1, wherein, Also includes: A handheld terminal module is connected to the data acquisition and testing system via a wireless communication module; the handheld terminal module is connected to the WST module and maps the operation interface of the WST module.

4. A point-to-point acquisition test method of a computer interlocking system, based on the point-to-point acquisition test system of any one of claims 1 to 3, for testing a relay interface on a computer interlocking device, characterized in that, include: Collect logic data from the test board and set the device status of the relays; Based on the device status of the relay, the WST module sequentially sends several on / off switch control matrices to the acquisition and test board, controlling the first switch group, the second switch group, ..., the Nth switch group on the acquisition and test board to close or open sequentially. Based on the first test circuit, the second test circuit, ..., the Nth test circuit formed by the closing or opening of the switch group on the acquisition test board, the electrical data of the corresponding switch group is obtained; Determine whether the electrical data matches the standard data. If they match, the test circuit is normal and the relay interface connected to the acquisition test board is normal; if they do not match, the test circuit is abnormal and the relay interface connected to the acquisition test board is abnormal.

5. The point-to-point acquisition test method of a computer interlocking system as claimed in claim 4, wherein, The logic data collected by the acquisition test board includes 1 or 0; the device status of the relay includes the state of being picked up or dropped.

6. The point-to-point acquisition test method of a computer interlocking system as claimed in claim 5, wherein, The current and voltage of each resistor in the first test circuit, the second test circuit, ..., the Nth test circuit are tested to obtain the electrical data.

7. The point-to-point data acquisition and testing method for a computer interlocking system as described in claim 6, characterized in that, When the relay is in the energized state, the first on / off switch control matrix sent by the WST module to the acquisition and test board is that all switch groups are in the off state. The switches in the first switch group, the second switch group, ..., the Nth switch group on the acquisition and test board are all in the off state, forming the first test circuit, the second test circuit, ..., the Nth test circuit.

8. The point-to-point acquisition test method of a computer interlocking system as claimed in claim 6, wherein, When the relay is in the energized state, the second conduction switch control matrix sent by the WST module to the acquisition and test board is such that the first switch in the first switch group is in the closed state, the second switch in the first switch group is in the open state, and the switches in the second switch group to the Nth switch group are all in the open state, forming the first test circuit, the second test circuit, ..., the Nth test circuit.

9. The point-to-point acquisition test method of a computer interlocking system as claimed in claim 7 or 8, characterized by, The first standard data for the first test circuit, the second test circuit, ..., the Nth test circuit is that the current value and voltage value of each resistor are all 0; if the measured current value and voltage value of the Nth test circuit are not 0, it indicates that the Nth test circuit is abnormal and the corresponding relay interface is abnormal.

10. The point-to-point data acquisition and testing method for a computer interlocking system as described in claim 6, characterized in that, When the relay is in the energized state, the third conduction switch control matrix sent by the WST module to the acquisition and test board is such that the first and second switches in the first switch group are both in the closed state, and the switches in the second to Nth switch groups are all in the open state, forming the first test circuit, the second test circuit, ..., the Nth test circuit.

11. The point-to-point acquisition test method of a computer interlocking system as claimed in claim 10, wherein, When the relay is in the energized state, the fourth conduction switch control matrix sent by the WST module to the acquisition and test board keeps the first and second switches in the first switch group closed, and gradually closes the second switch group, the third switch group, ..., the Nth switch group in pairs to form the first test circuit, the second test circuit, ..., the Nth test circuit.

12. The point-to-point acquisition test method of a computer interlocking system as claimed in claim 10 or 11, characterized by, The second standard data corresponding to the first test circuit is that the current and voltage values ​​of the first and second resistors in the first test circuit are equal, and the current value is equal to the ratio of the input voltage to the sum of the first and second resistors. The voltage and current values ​​of each resistor in the remaining second, third, ..., Nth test circuits are always 0. If the measured current and voltage values ​​in the Nth test circuit are not 0, where N≥2, it indicates that the Nth test circuit is abnormal and the corresponding relay interface is abnormal.

13. The point-to-point acquisition test method of a computer interlocking system as claimed in claim 6, wherein, When the relay is in the dropped state, the fifth conduction switch control matrix sent by the WST module to the acquisition test board is to turn on the first switch or the second switch in the first switch group, the second switch group, ..., the Nth switch group one by one, forming the first test circuit, the second test circuit, ..., the Nth test circuit.

14. The point-to-point acquisition test method of a computer interlocking system as claimed in claim 13, wherein, The third standard data for the first test circuit, the second test circuit, ..., the Nth test circuit is that the current value and voltage value of each resistor are all 0; if the measured current value and voltage value of the Nth test circuit are not 0, it indicates that the Nth test circuit is abnormal and the corresponding relay interface is abnormal.

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