A universal beam-shifting method, system, and apparatus based on FPGA

Abstract

The application discloses a general beam shift method, system and device based on FPGA, and belongs to the technical field of radar signal processing.The method comprises the following steps: receiving and analyzing control parameters; instantiating J shift sub-modules, each of which realizes beam left shift and right shift corresponding distance gates and outputs; using J shift FIFOs to buffer the data output by the J shift sub-modules respectively; using a state machine to cyclically read the data of the J shift FIFOs in sequence, reading one distance gate each time; only taking the data in the shift FIFOs which buffer the data after left shift and right shift corresponding distance gates as screened data; and outputting the shift FIFOs to obtain the shifted beam data.The application can realize the adjustment of the number of shift beams and the shift order by changing the configuration parameters, and can meet the multi-beam requirement of FPGA data processing in the field of radar signal processing.

Description

Technical Field

[0001] This invention belongs to the field of radar signal processing technology, specifically relating to a general beam shifting method, system, and device based on FPGA. Background Technology

[0002] With the development of digital phased array radar, radar products are becoming more and more powerful, and radar signal processing algorithms are becoming more and more complex. These have become inevitable trends in radar development.

[0003] To achieve high performance targets for radar functions, signal processing requires the use of multi-beams for air situation detection and signal sampling, in order to obtain as much external air situation information as possible. This necessitates the radar array generating data from multiple channels to meet the multi-beam requirements of signal processing.

[0004] To fully utilize the capabilities of existing radar components and reduce equipment production costs, a general beam shifting system needs to be designed to shift the beam to the left or right by a certain number of range gates, increasing the beam's degrees of freedom, meeting the signal processing requirements for multiple beams, improving the performance of signal processing algorithms, and enhancing the radar's detection capabilities. Summary of the Invention

[0005] The purpose of this invention is to provide a general beam shifting method, system, and device based on FPGA, which can adjust the number of shifted beams and the number of shift orders by changing configuration parameters, and can meet the multi-beam requirements of FPGA data processing in the field of radar signal processing.

[0006] Specifically, on the one hand, the present invention provides a general beam shifting method based on FPGA, comprising:

[0007] The control parameters are received and parsed, including the number of beams N to be shifted, the shift order M, and the maximum supported shift order J.

[0008] J shift submodules are instantiated. Each shift submodule implements and outputs the corresponding distance gates for left and right beam shift according to the control parameters.

[0009] Use J shift FIFOs to buffer the data output from the J shift submodules after shifting left and right to the corresponding distances behind the gate;

[0010] A state machine is used to sequentially read the data from the J shift FIFOs, reading one distance gate at a time; based on the shift order M, only the data in the shift FIFOs that buffer the data after the corresponding left and right shift distance gates are taken as the filtered data;

[0011] The filtered data is output through an output FIFO buffer to obtain the shifted beam data.

[0012] Furthermore, each shift submodule, based on the control parameters, implements left and right beam shifts corresponding distance gates and outputs the following:

[0013] When the shift order M is even, the beams after the M-order shift are: N beams shifted left by L range gates, N beams not shifted, and N beams shifted right by R range gates, where L = 1~M / 2-1 and R = 1~M / 2.

[0014] When the shift order M is odd, the beams after the M-order shift are: N beams shifted left by L range gates, N beams not shifted, and N beams shifted right by R range gates, where L = 1 ~ (M-1) / 2 and R = 1 ~ (M-1) / 2.

[0015] Furthermore, each shift submodule, based on the control parameters, implements left and right beam shifts corresponding distance gates and outputs the following:

[0016] Based on the control parameters, the number of shift distance gates for each shift submodule is calculated to be M. i M i Let i be the number of gates for the i-th shift submodule among J shift submodules, where i ranges from 0 to J-1.

[0017] The beam data that needs to be shifted is buffered in the corresponding shift FIFO of each shift submodule, and the data is truncated or padded with zeros through the state machine; J shift FIFOs are used to buffer the shift results output by J shift submodules respectively, and the left shift result is first entered into the shift FIFO at the front;

[0018] When shifting the distance gate to the left by L, the first N*L points of the beam data to be shifted are truncated, the remaining points are retained, and then N*L zeros are added to the end.

[0019] When shifting the distance gate to the right by R distances, add N*R zero values ​​before the beam data that needs to be shifted, and truncate the last N*R points.

[0020] Furthermore, the step of using a state machine to sequentially and cyclically read the data from the J shift FIFOs, with each reading of a distance gate including:

[0021] Starting with the first shift FIFO, when the shift FIFO is not empty and the output FIFO buffer is not full, a FIFO read enable signal of one clock cycle is generated, and then the state machine jumps to the next state; similar to the first shift FIFO, J FIFO read enable signals are generated in sequence, and the data of J shift FIFOs are read in a loop; according to the shift order M, only the data of the shift FIFOs that are shifted left by L distance gates, not shifted, or shifted right by R distance gates are taken, and the data output by the other shift FIFOs is set to invalid.

[0022] On the other hand, the present invention also provides a general beam shifting system based on FPGA for implementing the above-mentioned general beam shifting method based on FPGA, including a configuration parameter parsing module, a shifting module, a shifting FIFO, a FIFO read control module and an output FIFO;

[0023] The configuration parameter parsing module receives and parses configuration packets via the standard AXI protocol to obtain control parameters, which are then output to the shift module.

[0024] The shifting module instantiates J shifting sub-modules; each shifting sub-module shifts the beam according to control parameters.

[0025] The shift results of the J shift submodules are respectively buffered in the corresponding shift FIFOs. The left shift result is first entered into the shift FIFO at the front. The FIFO read control module controls which shift FIFO data to read and outputs the corresponding read enable signal to obtain the filtered data. The filtered data is then buffered and output through the output FIFO.

[0026] In another aspect, the present invention also provides a general beamshifting device based on FPGA, the device including a memory and a processor; the memory stores FPGA compilation results that implement the general beamshifting method based on FPGA, and the processor executes the FPGA compilation results to implement the steps of the above method.

[0027] The beneficial effects of the FPGA-based general beam shifting method of the present invention are as follows:

[0028] This invention employs multi-parameter control, which can simultaneously support M-order shifts of N (N>0) beams, and at most J-order shifts, with backward compatibility and expansion capabilities.

[0029] This invention enables real-time configuration of all parameters, such as beam dimension and shift order, through configuration parameters. Different signal processing systems can be adapted to local conditions. In different signal processing scenarios, the configuration parameters can be modified to change the beam dimension and shift order of the system.

[0030] The interface implementation of this invention is standardized and universal. Parameter configuration, data reception, and transmission use the standard AXI interface. Beam dimension and shift order can be expanded by modifying the configuration package, improving the compatibility and scalability of the shift system. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the system composition in this embodiment.

[0032] Figure 2This is a block diagram of the shifting submodule in this embodiment. Detailed Implementation

[0033] The present invention will now be described in further detail with reference to the embodiments and the accompanying drawings.

[0034] Example 1:

[0035] One embodiment of the present invention is a general beam shifting system based on FPGA, which can shift N (N>0) beams, has M-order shifting capability, and supports up to J-order shifting, where J is configurable.

[0036] like Figure 1 As shown, the FPGA-based universal beamshifting system of the present invention includes: a configuration parameter parsing module, a shifting module, a shift FIFO, a FIFO read control module, and an output FIFO. Among them,

[0037] The configuration parameter parsing module receives and parses configuration packets via the standard AXI protocol to obtain control parameters such as the number of beams to be shifted (ch_num), the shift order (shift_num), and the maximum supported shift order (J), and outputs them to the shift module.

[0038] The shift module instantiates J shift sub-modules. Figure 1 The axi_data_shift modules (1~J) support up to J shift orders. Each shift submodule can shift the beam according to control parameters such as shift_num. The shift distance gate of each shift submodule is: J - CNT - shift_num / 2, where CNT is the sequence number of the J shift submodules.

[0039] Figure 1 All signals in this code are based on the standard AXI protocol, as detailed below: s_config_data: Configuration parameter package; s_config_valid: Signal indicating that the configuration parameter package is valid; s_config_ready: Configuration parameter package backpressure signal; s_axi_data: Input beam data; s_axi_valid: Valid signal for input beam data; s_axi_ready: Input beam data reverse voltage signal; m_axi_data: Output beam data; m_axi_valid: Outputs valid beam data signal; m_axi_ready: Output beam data reverse voltage signal.

[0040] Taking an N-beam that supports a maximum of J-order shifts and performs an M-order shift as an example, then ch_num=N, shift_num=M, and through the shift, a total of M*N shifted beams are finally obtained. After the shift, the beam dimension increases from N-dimensional to M*N-dimensional.

[0041] The shift results of the J shift submodules are buffered in their respective shift FIFOs. The left shift result is first entered into the first shift FIFO. The FIFO read control module controls which shift FIFO data to read and outputs the corresponding read enable signal (valid). Finally, the data is output after being buffered in the output FIFO.

[0042] The specific implementation process of the FPGA-based general beam shifting method of the present invention is as follows:

[0043] The configuration parameter parsing module receives and parses the configuration packet to obtain control parameters such as the number of beams N to be shifted, the shift order M, and the maximum supported shift order J, and outputs them to the shift module.

[0044] 2. The shift module instantiates J shift sub-modules. Each shift sub-module implements the corresponding distance gate for left and right beam shift according to the control parameters and outputs the result.

[0045] When the shift order M is even, the beams after the M-order shift are: N beams shifted left by L range gates, N beams not shifted, and N beams shifted right by R range gates, where L = 1~M / 2-1 and R = 1~M / 2.

[0046] When the shift order M is odd, the beams after the M-order shift are: N beams shifted left by L range gates, N beams not shifted, and N beams shifted right by R range gates, where L = 1 ~ (M-1) / 2 and R = 1 ~ (M-1) / 2.

[0047] 2-1) The shift module calculates the number of shift distance gates for each shift submodule based on the control parameters, which is M. i M i Mi represents the shift distance gate number of the i-th shift submodule among J shift submodules, where i ranges from 0 to J-1. For example, when M is even, Mi = J + M / 2 - i.

[0048] 2-2) The beam data that needs to be shifted is buffered in the corresponding shift FIFO of each shift submodule, and the data is truncated or padded with zeros through the state machine;

[0049] When shifting the beam data to the left by L distance gates, the first N*L points of the beam data to be shifted are truncated, the remaining points are retained, and L*N zeros are added at the end to ensure that the beam length remains unchanged.

[0050] For example, when shifting left by one distance gate, the first N*1 points need to be truncated. When the state machine enters the left shift state, it generates an N*1 clock cycle FIFO read enable signal to read out the first N*1 points. At the same time, it assigns an invalid signal to these data, meaning that the first N*1 points will not be written into the subsequent shift FIFO. The points after the first N*1 points are read out normally from the shift FIFO. After all points are read out, an N*1 clock cycle valid signal is generated. The data under this valid signal is zero.

[0051] When shifting left by two distance gates, the first N*2 points of the beam data to be shifted need to be truncated. The operation method is the same as shifting left by one point above.

[0052] When shifting the beam data to the right by R distance gates, add N*R zero values ​​before the beam data that needs to be shifted and truncate the last N*R points to ensure that the beam length does not change.

[0053] For example, when shifting the beam data one distance gate to the right, N*1 zero values ​​need to be added before the beam data to be shifted. When the state machine enters the right shift state, it first generates N*1 valid clock signals, and the data under the valid signals is zero. Then, it reads the beam data in the shift FIFO and sets the valid signals corresponding to the last N*1 points to 0 (i.e. invalid).

[0054] When shifting two distance gates to the right, add N*2 zero values ​​before the beam data that needs to be shifted, and truncate the last N*2 points. The operation method is the same as shifting one point to the right above.

[0055] 2-3) Use J shift FIFOs to buffer the shift results output by J shift submodules respectively, and put the left shift result into the shift FIFO with the first one in the order of shifts.

[0056] 3. Use J shift FIFOs to buffer the data output from the J shift submodules after the corresponding left and right shift distances.

[0057] The shift results of J shift submodules are respectively fed into a shift FIFO ( Figure 1 The left-shifted result is first entered into the shifted FIFO (J~0) and then cached in the middle FIFO.

[0058] IV. The FIFO read enable control module uses a state machine to sequentially and cyclically read the data of the J shift FIFOs, reading one distance gate at a time; according to the shift order M, only the data in the shift FIFO that has buffered the data after the corresponding left and right shift distance gates is taken as the filtered data.

[0059] Starting with the first shift FIFO, when the shift FIFO is not empty and Figure 1When the output FIFO is not full, a FIFO read enable signal of one clock cycle is generated, and then the state machine jumps to the next state; similar to the first shift FIFO, J FIFO read enable signals are generated in sequence, and the data of J shift FIFOs are read in a loop; according to the shift order M, only the data of the shift FIFOs that are shifted left by L distance gates, not shifted, or shifted right by R distance gates are taken, and the data output by the other shift FIFOs is set to invalid.

[0060] V. The filtered data is processed through... Figure 1 The output is buffered by a FIFO to obtain the shifted beam data, resulting in a beam of M*N dimensions.

[0061] For ease of description, the following example illustrates a 4-beam (N=16) 4th-order shift, supporting a maximum of 10th-order shifts. The steps of this embodiment are as follows:

[0062] The configuration parameter parsing module parses the configuration package to obtain parameters such as the number of beams to be shifted (ch_num, denoted by N), the shift order (shift_num, denoted by M), and the maximum supported shift order (denoted by J). ch_num=16, shift_num=4, J=10. The final shifted beam result is 16 beams shifted left by 1 range gate, 16 beams not shifted, 16 beams shifted right by 1 range gate, and 16 beams shifted right by 2 range gates, for a total of 64 beams.

[0063] 2. Instantiate 10 shift sub-modules. The shift results of the 10 shift sub-modules are buffered in shift FIFOs (left shift results are first entered into the first shift FIFO). The FIFO read control module controls which shift FIFOs to read and the valid output signals. Finally, the data is output through an output FIFO. The specific implementation process is as follows:

[0064] 2-1) The shift length M of each shift submodule is calculated from the channel configuration parameters of the shift submodule. i =J+M / 2-i=12-i, i ranges from 0 to 9;

[0065] 2-2) Input data is buffered in a shift FIFO, and a state machine is used for data truncation or padding with zeros:

[0066] When shifting left by one distance gate, the first 1*16 points are truncated. When the state machine enters the left shift state, a FIFO read enable signal of 1*16 clock cycles is generated to read out the first 1*16 points. At the same time, an invalid signal is assigned to these data, that is, the first 1*16 points will not be written into the subsequent shift FIFO. The points after the first 1*16 points are read out normally from the shift FIFO. After all points are read out, a valid signal of 1*16 clock cycles is generated. The data under this valid signal is zero.

[0067] When moving the gate two distances to the left, cut off the first 16*2 points. The operation method is the same as moving it one point to the left above.

[0068] When shifting right by one distance gate, 1*16 zero values ​​are added before the beam data to be shifted. When the state machine enters the right shift state, 1*16 clock valid signals are generated first. The data under the valid signal is zero. Then the beam data in the shift FIFO is read and the valid signals corresponding to the last 1*16 points are set to 0 (i.e. invalid).

[0069] 2-3) After truncating or padding the data according to the left and right shift operations, the truncated or padded data is buffered in 10 shift FIFOs, which are the data output by the 10 shift submodules after the corresponding shift distance gate.

[0070] 3. The FIFO read enable control module uses another state machine to sequentially read data from 10 shift FIFOs, reading one distance gate at a time:

[0071] The first shift FIFO begins when the shift FIFO is not empty and Figure 1 When the output FIFO buffer is not full, a FIFO read enable signal of one clock cycle is generated, and then the state machine jumps to the next state. Similar to the first shift FIFO, 10 FIFO read enable signals are generated in sequence, and the data of 10 shift FIFOs are read in a loop.

[0072] Based on the configuration parameter that the shift order is 4, only the shift FIFO data corresponding to shifting left by 1 distance gate, no shift, shifting right by 1 distance gate, and shifting right by 2 distance gates are taken, and the data output by the other shift FIFOs is set to invalid.

[0073] The data filtered by the FIFO read enable control module is output through the output FIFO buffer to obtain the shifted beam data, which consists of a total of 16*4=64 dimensions of beam.

[0074] This invention employs multi-parameter control, which can simultaneously support M-order shifts of N (N>0) beams, and at most J-order shifts, with backward compatibility and expansion capabilities.

[0075] This invention enables real-time configuration of all parameters, such as beam dimension and shift order, through configuration parameters. Different signal processing systems can be adapted to local conditions. In different signal processing scenarios, the configuration parameters can be modified to change the beam dimension and shift order of the system.

[0076] The interface implementation of this invention is standardized and universal. Parameter configuration, data reception, and transmission use the standard AXI interface. Beam dimension and shift order can be expanded by modifying the configuration package, improving the compatibility and scalability of the shift system.

[0077] In some embodiments, certain aspects of the above-described technology can be implemented by an FPGA-based general-purpose beamshifting device, including a processor and a memory. The memory stores the FPGA compilation results of a computer program implementing the FPGA-based general-purpose beamshifting method. The processor executes the FPGA compilation results to implement the steps of the FPGA-based general-purpose beamshifting method described above. The processor receives configuration parameters sent by a host computer, and the FPGA-based general-purpose beamshifting device operates according to the configuration parameters. It should be noted that the memory can be integrated into the processor or independent of the processor. The device may also include a bus. The processor is connected to the memory via the bus. The memory may include readable storage and random access memory.

[0078] While the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the invention. Any equivalent changes or modifications made without departing from the spirit and scope of the invention are also within the scope of protection of the invention. Therefore, the scope of protection of the present invention should be determined by the claims of this application.

Claims

1. A general beam shifting method based on FPGA, characterized in that, include: The control parameters are received and parsed, including the number of beams N to be shifted, the shift order M, and the maximum supported shift order J. J shift submodules are instantiated. Each shift submodule implements and outputs the corresponding distance gates for left and right beam shift according to the control parameters. Use J shift FIFOs to buffer the data output from the J shift submodules after shifting left and right to the corresponding distances behind the gate; A state machine is used to sequentially read the data from the J shift FIFOs, reading one distance gate at a time; based on the shift order M, only the data in the shift FIFOs that buffer the data after the corresponding left and right shift distance gates are taken as the filtered data; The filtered data is output through an output FIFO buffer to obtain the shifted beam data; Each shift submodule, based on the control parameters, implements left and right beam shifts corresponding distance gates and outputs the following: Based on the control parameters, the number of shift distance gates for each shift submodule is calculated to be M. i M i Let i be the number of gates for the i-th shift submodule among J shift submodules, where i ranges from 0 to J-1. The beam data that needs to be shifted is buffered in the corresponding shift FIFO of each shift submodule, and the data is truncated or padded with zeros through the state machine; J shift FIFOs are used to buffer the shift results output by J shift submodules respectively, and the left shift result is first entered into the shift FIFO at the front; When shifting the distance gate to the left by L, the first N*L points of the beam data that needs to be shifted are truncated, the remaining points are kept, and then N*L zeros are added to the end. When shifting the distance gate to the right by R distances, add N*R zero values ​​before the beam data that needs to be shifted, and truncate the last N*R points.

2. The FPGA-based general beamshifting method according to claim 1, characterized in that, Each shift submodule, based on the control parameters, implements left and right beam shifts corresponding distance gates and outputs the following: When the shift order M is even, the beams after the M-order shift are: N beams shifted left by L range gates, N beams not shifted, and N beams shifted right by R range gates, where L = 1~M / 2-1 and R = 1~M / 2. When the shift order M is odd, the beams after the M-order shift are: N beams shifted left by L range gates, N beams not shifted, and N beams shifted right by R range gates, where L = 1 ~ (M-1) / 2 and R = 1 ~ (M-1) / 2.

3. The FPGA-based general beamshifting method according to claim 1, characterized in that, The process of using a state machine to sequentially and cyclically read the data from the J shift FIFOs, with each reading of a distance gate including: Starting with the first shift FIFO, when the shift FIFO is not empty and the output FIFO buffer is not full, a FIFO read enable signal of one clock cycle is generated, and then the state machine jumps to the next state; the same process as the first shift FIFO is used to generate J FIFO read enable signals in sequence, and the data of J shift FIFOs are read in a loop; according to the shift order M, only the data of the shift FIFOs that are shifted left by L distance gates, not shifted, or shifted right by R distance gates are taken, and the data output by the other shift FIFOs is set to invalid.

4. A general-purpose beamshifting system based on FPGA, used to implement the general-purpose beamshifting method based on FPGA according to any one of claims 1-3, characterized in that, It includes a configuration parameter parsing module, a shift module, a shift FIFO, a FIFO read control module, and an output FIFO; The configuration parameter parsing module receives and parses configuration packets via the standard AXI protocol to obtain control parameters, which are then output to the shift module. The shifting module instantiates J shifting sub-modules; each shifting sub-module shifts the beam according to control parameters. The shift results of the J shift submodules are respectively buffered in the corresponding shift FIFOs. The left shift result is first entered into the shift FIFO at the front. The FIFO read control module controls which shift FIFO data to read and outputs the corresponding read enable signal to obtain the filtered data. The filtered data is then buffered and output through the output FIFO.

5. A general-purpose beamshifting device based on FPGA, characterized in that, The device includes a memory and a processor; the memory stores FPGA compilation results implementing a general beamshifting method based on FPGA, and the processor executes the FPGA compilation results to implement the steps of the method according to any one of claims 1-3.

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