Pixel unit, display panel and display device

Abstract

The application provides a pixel unit, a display panel and a display device. The pixel unit comprises a pixel electrode, a first common electrode, a first transistor, a reference electrode, a buffer electrode and a buffer circuit. The control end of the first transistor is used for receiving a first scanning signal. The first connection end of the first transistor is used for receiving a data voltage. The first common electrode and the pixel electrode form a liquid crystal capacitor. The buffer electrode is electrically connected with the second connection end of the first transistor. The reference electrode and the buffer electrode form a buffer capacitor. The buffer circuit is electrically connected between the buffer electrode and the pixel electrode. The first transistor is turned on when the received first scanning signal is an opening level, and the received data voltage is written into the buffer electrode to charge the buffer capacitor. The buffer circuit is disconnected when the received first scanning signal of the first transistor is the opening level, so that the change of the voltage difference between the two ends of the liquid crystal capacitor caused by the data voltage fluctuation is prevented. The pixel unit can improve the crosstalk problem.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a pixel unit, a display panel, and a display device. Background Technology

[0002] Liquid crystal displays (LCDs) are widely used in electronic products such as laptops and televisions due to their advantages such as energy saving, low radiation, small size, light weight, and affordable price.

[0003] A liquid crystal display (LCD) typically includes scan lines for transmitting scan signals, data lines for transmitting data voltages, and multiple pixel units. Each pixel unit includes a scan transistor, a liquid crystal capacitor, and a storage capacitor. The gate of the scan transistor is electrically connected to the scan line, the source is electrically connected to the data line, and the drain is electrically connected to the pixel electrode. One end of the liquid crystal capacitor and the storage capacitor is a common electrode, and the other end is the pixel electrode. During operation, the scan transistor receives the scan signal through the scan line and is turned on, thereby charging the liquid crystal capacitor with the data voltage received from the data line. This generates an electric field in the liquid crystal capacitor (between the pixel electrode and the common electrode), controlling the deflection of the liquid crystal molecules, which in turn allows the pixel unit to transmit light and display different grayscale images.

[0004] However, due to the parasitic capacitance between the common electrode and the data line, when the data voltage on the data line changes abruptly, the common voltage of the common electrode will fluctuate due to the capacitive coupling effect of the parasitic capacitance. As a result, the voltage difference between the common electrode and the pixel electrode will fluctuate, which will cause the deflection direction of the liquid crystal molecules to deviate from the preset direction, resulting in crosstalk and other problems in the display screen, thereby reducing the display effect and the yield of the product. Summary of the Invention

[0005] In view of this, the main purpose of this application is to propose a pixel unit, a display panel, and a display device, which aims to solve the problem that the large number of source driver chips in existing display panels leads to increased display costs.

[0006] To achieve the above objectives, a first aspect of this application provides a pixel unit, comprising a pixel electrode, a first common electrode, and a first transistor. The first transistor includes a control terminal, a first connection terminal, and a second connection terminal. The control terminal of the first transistor is electrically connected to a corresponding first scan line to receive a corresponding first scan signal. The first connection terminal of the first transistor is electrically connected to a corresponding data line to receive a corresponding data voltage. The first common electrode and the pixel electrode are spaced apart to form a liquid crystal capacitor. The pixel unit further includes a reference electrode, a buffer electrode, and a buffer circuit. The reference electrode receives a reference voltage with a constant value. The buffer electrode is electrically connected to the second connection terminal of the first transistor. The reference electrode and the buffer electrode are spaced apart to form a buffer capacitor. The buffer circuit is electrically connected between the buffer electrode and the pixel electrode. The first scan signal includes an on level and an off level. When the first scan signal is on, the first transistor conducts and writes the received data voltage to the buffer electrode to charge the buffer capacitor, thus charging the voltage of the buffer electrode to the data voltage. When the first scan signal received by the first transistor is on, the buffer circuit disconnects the electrical connection between the buffer electrode and the pixel electrode, thereby preventing fluctuations in the data voltage from causing changes in the voltage difference across the liquid crystal capacitor. When the first scan signal received by the first transistor is off, the buffer circuit connects the electrical connection between the buffer electrode and the pixel electrode, allowing the buffer capacitor to write the data voltage to the pixel electrode through the conducting buffer circuit, thereby enabling the pixel unit to display the grayscale corresponding to the data voltage.

[0007] The pixel unit provided in this application forms a buffer capacitor by setting a buffer electrode and a reference electrode. A buffer circuit is set between the buffer electrode and the pixel electrode. When the scan line scans the pixel unit, the buffer circuit disconnects the electrical connection between the pixel electrode and the buffer electrode, so that the buffer capacitor receives the data voltage corresponding to the pixel unit and charges. After the scan is completed, the buffer circuit turns on the electrical connection between the pixel electrode and the buffer electrode, so that the buffer capacitor writes the data voltage to the pixel electrode after completing charging. In this way, the time period of data voltage change is separated from the time period of writing data voltage to the pixel electrode, which can prevent the voltage difference across the liquid crystal capacitor from changing due to the coupling effect of parasitic capacitance when the data voltage jumps, thereby improving the crosstalk problem.

[0008] Optionally, the buffer circuit includes a second transistor, the second transistor including a first connection terminal and a second connection terminal, the first connection terminal of the second transistor being electrically connected to the buffer electrode, and the second connection terminal of the second transistor being electrically connected to the pixel electrode.

[0009] Optionally, both the first transistor and the second transistor are either high-level turn-on transistors or both are low-level turn-on transistors. The second transistor further includes a control terminal, which is electrically connected to the second scan line to receive a corresponding second scan signal, wherein the first scan signal and the second scan signal are inverted.

[0010] Optionally, the first transistor is a high-level on-transistor, and the second transistor is a low-level on-transistor. The second transistor further includes a control terminal, which is electrically connected to the corresponding first scan line to receive the corresponding first scan signal. Alternatively, the first transistor is a low-level on-transistor, and the second transistor is a high-level on-transistor. The second transistor further includes a control terminal, which is electrically connected to the corresponding first scan line to receive the corresponding first scan signal.

[0011] Optionally, both the first transistor and the second transistor are either high-level turn-on transistors or both are low-level turn-on transistors. The buffer circuit further includes an inverter, and the second transistor includes a control terminal. The input terminal of the inverter is electrically connected to the corresponding first scan line to receive the corresponding first scan signal, and the output terminal of the inverter is electrically connected to the control terminal of the second transistor. The inverter is used to invert the received first scan signal and output the inverted first scan signal to the control terminal of the second transistor.

[0012] Optionally, the pixel unit further includes a storage capacitor for storing electrical energy and charging the liquid crystal capacitor when the first scan signal is at an off level, thereby maintaining the voltage of the pixel electrode at the data voltage. The buffer capacitor is reused as the storage capacitor.

[0013] Optionally, the pixel unit further includes a second common electrode, which is arranged at a distance from the pixel electrode to form a storage capacitor. The storage capacitor is used to store electrical energy and charge the liquid crystal capacitor when the first scan signal is at an off level, thereby keeping the voltage of the pixel electrode at the data voltage.

[0014] Optionally, the buffer electrode and the pixel electrode are arranged at intervals in the same layer.

[0015] A second aspect of this application also provides a display panel, the display panel including a plurality of first scan lines, a plurality of data lines, and a plurality of pixel units as described in the first aspect above. The plurality of first scan lines extend along the row direction and are spaced apart along the column direction. The plurality of data lines extend along the column direction and are spaced apart along the row direction. The plurality of pixel units are respectively disposed at a plurality of intersection positions of the plurality of first scan lines and the plurality of data lines.

[0016] A third aspect of this application also provides a display device, the display device including a display panel as described in the second aspect above and a driving circuit, the driving circuit being electrically connected to the display panel and used to drive the display panel to perform a display.

[0017] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0018] Figure 1 This is a circuit diagram of a pixel unit in a related technology;

[0019] Figure 2 for Figure 1 The waveform diagram corresponding to the pixel unit shown;

[0020] Figure 3 This application provides a schematic diagram of the display device structure;

[0021] Figure 4 for Figure 3 The diagram shows a second circuit diagram of a pixel unit in the display device shown.

[0022] Figure 5 for Figure 4 The timing diagram of the first and second scan signals corresponding to the pixel units shown;

[0023] Figure 6 for Figure 3 A schematic diagram of a third type of circuit for a pixel unit in the display device shown;

[0024] Figure 7 for Figure 3 The diagram shows a fourth type of circuit for a pixel unit in the display device shown.

[0025] Figure 8 for Figure 3 A partial cross-sectional structural diagram of a pixel unit in the display device shown.

[0026] The annotations in the attached figures are explained as follows:

[0027] Display device 1

[0028] Display panel 100

[0029] Drive circuit 200

[0030] Scan drive circuit 201

[0031] Data drive circuit 202

[0032] Pixel units P, P'

[0033] Data cable 410

[0034] First scan line 420

[0035] Second scan line 421

[0036] Array substrate 10

[0037] Color film substrate 20

[0038] Liquid crystal layer 30

[0039] Second substrate 21

[0040] First common electrode 22

[0041] First transistor T1

[0042] Second transistor T2

[0043] Liquid crystal capacitor Clc

[0044] Buffer capacitor Cb

[0045] Storage capacitor Cst

[0046] Parasitic capacitance C1

[0047] Inverter D1

[0048] First substrate 11

[0049] First insulating layer 12

[0050] Second insulating layer 13

[0051] Third insulating layer 14

[0052] Pixel Electrode 15

[0053] Buffer electrode 16

[0054] Reference electrode 17

[0055] Second common electrode 18

[0056] Gates 111, 121

[0057] Drain electrodes 112, 122

[0058] Source 113, 123

[0059] Active layers 114 and 124

[0060] The following detailed description, in conjunction with the accompanying drawings, will further illustrate this application. Detailed Implementation

[0061] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0062] Furthermore, the terms "first," "second," etc., used in this specification are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Additionally, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0063] It should be noted that, where there is no conflict, the features in the embodiments of this application can be combined with each other.

[0064] like Figure 1 As shown, a conventional pixel unit P' typically includes a pixel electrode 15, a first common electrode 22, a second common electrode 18, and a first transistor T1.

[0065] The first common electrode 22 is used to receive the first common voltage Vcom1 (also known as the color filter substrate-side common voltage V). CF_COM The second common electrode 18 is used to receive the second common voltage Vcom2 (also known as the array substrate-side common voltage V). A_COMThe first transistor T1 includes a control terminal, a first connection terminal, and a second connection terminal. The control terminal of the first transistor T1 is used to be electrically connected to a corresponding first scan line 420 to receive a corresponding first scan signal. The first connection terminal of the first transistor T1 is used to be electrically connected to a corresponding data line 410 to receive a corresponding data voltage Vdata. The first common electrode 22 and the pixel electrode 15 are arranged at a distance from each other to form a liquid crystal capacitor Clc. The second common electrode 18 and the pixel electrode 15 are arranged at a distance from each other to form a storage capacitor Cst.

[0066] During operation, the first transistor T1 is turned on when the received first scan signal is at the on level, thereby writing the data voltage Vdata provided by the data line 410 into the pixel electrode 15, so that there is a voltage difference between the pixel electrode 15 and the first common electrode 22 and an electric field is generated, thereby driving the liquid crystal molecules between the pixel electrode 15 and the first common electrode 22 to deflect, so that the pixel unit P' displays the gray level corresponding to the data voltage Vdata.

[0067] like Figure 1 As shown, due to the parasitic capacitance C1 between the data line 410 and the first common electrode 22, during the period when the first transistor T1 is conducting to charge the liquid crystal capacitor Clc, if the data voltage Vdata changes abruptly, the first common voltage Vcom1 on the first common electrode 22 will also change abruptly due to the coupling effect of the parasitic capacitance C1. For example... Figure 2 As shown, when the data voltage Vdata changes in the positive direction, the first common voltage Vcom1 will shift in the positive direction due to the coupling effect of the parasitic capacitor C1. When the data voltage Vdata changes in the negative direction, the first common voltage Vcom1 will shift in the negative direction due to the coupling effect of the parasitic capacitor C1. This will change the voltage difference across the liquid crystal capacitor C1, that is, change the electric field strength between the pixel electrode 15 and the first common electrode 22. This will cause a deviation between the actual deflection angle of the liquid crystal molecules between the pixel electrode 15 and the first common electrode 22 and the target deflection angle corresponding to the data voltage Vdata, thereby causing crosstalk and other abnormalities in the display screen.

[0068] In view of this, please refer to Figure 3 This application provides a pixel unit P, which includes a pixel electrode 15, a first common electrode 22, a first transistor T1, a buffer electrode 16, a reference electrode 17, and a buffer circuit 19.

[0069] The first transistor T1 includes a control terminal, a first connection terminal, and a second connection terminal. The control terminal of the first transistor T1 is used to be electrically connected to a corresponding first scan line 420 to receive a corresponding first scan signal. The first connection terminal of the first transistor T1 is used to be electrically connected to a corresponding data line 410 to receive a corresponding data voltage. The first common electrode 22 and the pixel electrode 15 are arranged at relative intervals to form a liquid crystal capacitor Clc.

[0070] The first common electrode 22 is used to receive a first common voltage Vcom1. The reference electrode 17 is used to receive a reference voltage with a constant value. The reference voltage is independent of the first common voltage Vcom1; that is, the first common voltage Vcom1 and the reference voltage come from different voltage sources.

[0071] The buffer electrode 16 is electrically connected to the second connection terminal of the first transistor T1, and the reference electrode 17 and the buffer electrode 16 are arranged at a distance from each other to form a buffer capacitor Cb.

[0072] The buffer circuit 19 is electrically connected between the buffer electrode 16 and the pixel electrode 15. The first scan signal includes an on level and an off level. When the first scan signal is on, the first transistor T1 conducts and writes the received data voltage to the buffer electrode 16 to charge the buffer capacitor Cb, thus charging the voltage of the buffer electrode 16 to the data voltage. When the first scan signal received by the first transistor T1 is on, the buffer circuit 19 disconnects the electrical connection between the buffer electrode 16 and the pixel electrode 15, thereby preventing fluctuations in the data voltage from causing changes in the voltage difference across the liquid crystal capacitor Clc. When the first scan signal received by the first transistor T1 is off, the buffer circuit 19 conducts the electrical connection between the buffer electrode 16 and the pixel electrode 15, allowing the buffer capacitor Cb to write the data voltage to the pixel electrode 15 through the conducting buffer circuit 19, thereby causing the pixel unit P to display the grayscale corresponding to the data voltage.

[0073] The pixel unit P provided in this application forms a buffer capacitor Cb by setting a buffer electrode 16 and a reference electrode 17. A buffer circuit 19 is set between the buffer electrode 16 and the pixel electrode 15. When the pixel unit P is scanned by the scan line 420, the buffer circuit 19 disconnects the electrical connection between the pixel electrode 15 and the buffer electrode 16, so that the buffer capacitor Cb receives the data voltage corresponding to the pixel unit P and is charged. After the scan is completed, the buffer circuit 19 turns on the electrical connection between the pixel electrode 15 and the buffer electrode 16, so that the buffer capacitor Cb writes the data voltage to the pixel electrode 15 after it has finished charging. In this way, the time period of data voltage change is separated from the time period of writing data voltage to the pixel electrode 15. This can prevent the voltage difference across the liquid crystal capacitor C1 from changing due to the coupling effect of the parasitic capacitance C1 when the data voltage jumps, thereby improving the crosstalk problem.

[0074] When the first scan signal is at the on level, i.e., when the scan line 420 scans the pixel unit P, the buffer circuit 19 disconnects the electrical connection between the pixel electrode 15 and the buffer electrode 16, effectively leaving one end of the liquid crystal capacitor Clc floating. At this time, even if the data voltage changes, causing a sudden change in the voltage of the first common electrode 22, the floating end of the liquid crystal capacitor Clc, based on the bootstrap effect, allows it to maintain a constant voltage difference, thus ensuring that the display brightness of the pixel unit P remains unaffected. When the first scan signal is at the off level, i.e., after scanning, the first transistor T1 disconnects the electrical connection between the buffer electrode 16 and the data line 410. The liquid crystal capacitor Clc and the buffer capacitor Cb maintain charge conservation; therefore, the voltage difference across the liquid crystal capacitor Clc is not affected by the coupling effect of the parasitic capacitance C1, and the display brightness of the pixel unit P remains unaffected.

[0075] In this embodiment of the application, the buffer circuit 19 includes a second transistor T2, which includes a first connection terminal and a second connection terminal. The first connection terminal of the second transistor T2 is electrically connected to the buffer electrode 16, and the second connection terminal of the second transistor T2 is electrically connected to the pixel electrode 15.

[0076] Further, in some embodiments, the first transistor T1 is a high-level on-transistor, and the second transistor T2 is a low-level on-transistor. The second transistor T2 further includes a control terminal, which is electrically connected to the corresponding first scan line 420 to receive the corresponding first scan signal; or, the first transistor T1 is a low-level on-transistor, and the second transistor T2 is a high-level on-transistor. The second transistor T2 further includes a control terminal, which is electrically connected to the corresponding first scan line 420 to receive the corresponding first scan signal. For example, as... Figure 3 As shown, the first transistor T1 is an NMOS transistor, and the second transistor T2 is a PMOS transistor.

[0077] Furthermore, in this embodiment, the pixel unit P further includes a second common electrode 18, which is arranged at a distance from the pixel electrode 15 to form a storage capacitor Cst. The storage capacitor Cst is used to store electrical energy and charge the liquid crystal capacitor Clc when the first scan signal is at the off level, thereby keeping the voltage of the pixel electrode 15 at the data voltage.

[0078] Specifically, when the first transistor T1 is turned off, that is, after the scan is completed, the storage capacitor Cst and the buffer capacitor Cb can use the stored electrical energy to continuously power the liquid crystal capacitor Clc, so that the voltage of the pixel electrode 15 is maintained at the data voltage, thereby enabling the pixel unit P to continuously display the gray level corresponding to the data voltage.

[0079] In other embodiments, the first transistor T1 and the second transistor T2 are both high-level conducting transistors or both low-level conducting transistors.

[0080] The second transistor T2 also includes a control terminal, which is electrically connected to the second scan line 421 to receive a corresponding second scan signal, wherein the first scan signal and the second scan signal are out of phase.

[0081] For example, such as Figures 4-5As shown, both the first transistor T1 and the second transistor T2 are NMOS transistors, meaning that the turn-on level of the first scan signal and the turn-off level of the second scan signal are high, and the turn-off level is low. The first scan signal Gn is used to control the first transistor T1 to turn on or off, and the second scan signal Gn' is used to control the second transistor T2 to turn on or off. The first scan signal Gn and the second scan signal Gn' are out of phase; that is, when the first scan signal Gn is at the turn-on level, the second scan signal Gn' is at the turn-off level, and when the first scan signal Gn is at the turn-off level, the second scan signal Gn' is at the turn-on level.

[0082] In other embodiments, the first transistor T1 and the second transistor T2 are both high-level conducting transistors or both low-level conducting transistors.

[0083] The buffer circuit 19 further includes an inverter D1, and the second transistor T2 further includes a control terminal. The input terminal of the inverter D1 is electrically connected to the corresponding first scan line 420 to receive the corresponding first scan signal, and the output terminal of the inverter D1 is electrically connected to the control terminal of the second transistor T2. The inverter D1 is used to invert the received first scan signal and output the inverted first scan signal to the control terminal of the second transistor T2.

[0084] For example, such as Figure 6 As shown, both the first transistor T1 and the second transistor T2 are NMOS transistors. Thus, each pixel unit P requires only one scan signal, simplifying the driving circuit.

[0085] like Figure 7 As shown, in some other embodiments, the buffer capacitor Cb is reused as the storage capacitor Cst. Thus, the... Figure 3 The second common electrode 18 in the pixel unit P shown simplifies the structure of the pixel unit P.

[0086] Please refer to it again. Figure 3 Based on the same inventive concept, this application also provides a display panel 100, which includes multiple first scan lines 420, multiple data lines 410, and multiple pixel units P.

[0087] The plurality of first scan lines 420 extend along the row direction and are arranged at intervals along the column direction.

[0088] The multiple data lines 410 extend along the column direction and are arranged at intervals along the row direction.

[0089] The plurality of pixel units P are the pixel units P described in any of the above embodiments, and the plurality of pixel units P are respectively disposed at multiple intersection positions of the plurality of first scan lines 420 and the plurality of data lines 410.

[0090] Further, please refer to Figure 8 , Figure 8 for Figure 3 The schematic diagram shows a partial cross-sectional structure of the pixel unit P. The display panel 100 includes an array substrate 10, a color filter substrate 20 (also known as an opposing substrate), and a liquid crystal layer 30 sandwiched between the array substrate 10 and the color filter substrate 20.

[0091] In this embodiment, the pixel electrode 15, buffer electrode 16, reference electrode 17, second common electrode 18, first transistor T1, and second transistor T2 in the pixel unit P are all disposed on the array substrate 10. The first common electrode 22 is disposed on the color filter substrate 20.

[0092] The buffer electrode 16 and the pixel electrode 15 are disposed on the array substrate 10 at intervals in the same layer. Specifically, the array substrate 10 further includes a first substrate 11, a first insulating layer 12, a second insulating layer 13, and a third insulating layer 14. The first transistor T1 includes a gate 111, a drain 112, a source 113, and an active layer 114. The second transistor T2 includes a gate 121, a drain 122, a source 123, and an active layer 124. The gate 111, drain 112, and source 113 of the first transistor T1 are respectively a control terminal, a first connection terminal, and a second connection terminal. The gate 121, drain 122, and source 123 of the second transistor T2 are respectively a control terminal, a first connection terminal, and a second connection terminal. The color filter substrate 20 further includes a second substrate 21, and the first common electrode 2 is disposed on the surface of the second substrate 21 near the liquid crystal layer 30.

[0093] Gate 111 and gate 121 are disposed at intervals on the first substrate 11, and the first insulating layer 12 simultaneously covers gate 111 and gate 121. Drain 112, source 113, active layer 114, drain 122, source 123, and active layer 124 are disposed on the surface of the first insulating layer 12 near the liquid crystal layer 30. The second insulating layer 13 simultaneously covers gate 111 and gate 121. Drain 112, source 113, active layer 114, drain 122, source 123, and active layer 124 are also present. The reference electrode 17 is disposed on the surface of the second insulating layer 13 near the liquid crystal layer 30. The third insulating layer 14 covers the reference electrode 17, and the buffer electrode 16 and the pixel electrode 15 are disposed at intervals on the surface of the third insulating layer 14 near the liquid crystal layer 30. The buffer electrode 16 is electrically connected to the source electrode 113 and the drain electrode 122 through vias, and is disposed opposite to the reference electrode 17 to form the buffer capacitor Cb. The pixel electrode 15 is electrically connected to the source electrode 123 through vias, and is disposed opposite to the first common electrode 22 to form the liquid crystal capacitor Clc.

[0094] Based on the same inventive concept, please refer again. Figure 3 This application also provides a display device 1, which includes the display panel 100 described in the above embodiments and a driving circuit 200. The driving circuit 200 is electrically connected to the display panel 100 and is used to drive the display panel 100 to perform display.

[0095] The driving circuit 200 includes a scan driving circuit 201 and a data driving circuit 202. The scan driving circuit 201 is electrically connected to each of the plurality of first scan lines 420 and is used to provide a corresponding scan signal to each of the first scan lines 420. The data driving circuit 202 is electrically connected to each of the plurality of data lines 410 and is used to provide a corresponding data voltage to each of the data lines 410.

[0096] The pixel unit P in the display panel 100 and display device 1 provided in this application is configured with a buffer capacitor Cb by setting a buffer electrode 16 and a reference electrode 17. A buffer circuit 19 is set between the buffer electrode 16 and the pixel electrode 15. When the pixel unit P is scanned by the scan line 420, the buffer circuit 19 disconnects the electrical connection between the pixel electrode 15 and the buffer electrode 16, so that the buffer capacitor Cb receives the data voltage corresponding to the pixel unit P and is charged. After the scan is completed, the buffer circuit 19 turns on the electrical connection between the pixel electrode 15 and the buffer electrode 16, so that the buffer capacitor Cb writes the data voltage to the pixel electrode 15 after it has finished charging. In this way, the time period of data voltage change is separated from the time period of writing data voltage to the pixel electrode 15, which can prevent the voltage difference across the liquid crystal capacitor C1 from changing due to the coupling effect of the parasitic capacitance C1 when the data voltage jumps, thereby improving the crosstalk problem.

[0097] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A pixel unit, comprising a pixel electrode, a first common electrode, and a first transistor, wherein the first transistor includes a control terminal, a first connection terminal, and a second connection terminal, the control terminal of the first transistor being electrically connected to a corresponding first scan line to receive a corresponding first scan signal, the first connection terminal of the first transistor being electrically connected to a corresponding data line to receive a corresponding data voltage, and the first common electrode and the pixel electrode being disposed at a relative interval to form a liquid crystal capacitor, characterized in that, The pixel unit further includes: The reference electrode is used to receive a reference voltage with a constant voltage value. A buffer electrode is electrically connected to the second terminal of the first transistor; the reference electrode and the buffer electrode are spaced apart to form a buffer capacitor; and A buffer circuit is electrically connected between the buffer electrode and the pixel electrode. The first scan signal includes an on level and an off level. When the first scan signal is on, the first transistor conducts and writes the received data voltage to the buffer electrode to charge the buffer capacitor, thereby charging the voltage of the buffer electrode to the data voltage. When the first scan signal received by the first transistor is on, the buffer circuit disconnects the electrical connection between the buffer electrode and the pixel electrode, thereby preventing fluctuations in the data voltage from causing changes in the voltage difference across the liquid crystal capacitor. When the first scan signal received by the first transistor is off, the buffer circuit connects the electrical connection between the buffer electrode and the pixel electrode, allowing the buffer capacitor to write the data voltage to the pixel electrode through the conducting buffer circuit, thereby enabling the pixel unit to display the grayscale corresponding to the data voltage. The buffer circuit includes a second transistor, which includes a first connection terminal and a second connection terminal. The first connection terminal of the second transistor is electrically connected to the buffer electrode, and the second connection terminal of the second transistor is electrically connected to the pixel electrode. The first transistor is a high-level on-transistor, and the second transistor is a low-level on-transistor. The second transistor also includes a control terminal, which is electrically connected to the corresponding first scan line to receive the corresponding first scan signal; or The first transistor is a low-level conducting transistor, the second transistor is a high-level conducting transistor, and the second transistor also includes a control terminal, which is electrically connected to the corresponding first scan line to receive the corresponding first scan signal.

2. The pixel unit as described in claim 1, characterized in that, The pixel unit further includes a storage capacitor, which stores electrical energy and charges the liquid crystal capacitor when the first scan signal is at the off level, thereby maintaining the voltage of the pixel electrode at the data voltage; the buffer capacitor is reused as the storage capacitor.

3. The pixel unit as described in claim 2, characterized in that, The pixel unit further includes a second common electrode, which is arranged at a distance from the pixel electrode to form a storage capacitor. The storage capacitor is used to store electrical energy and charge the liquid crystal capacitor when the first scan signal is at the off level, thereby keeping the voltage of the pixel electrode at the data voltage.

4. The pixel unit as described in claim 1, characterized in that, The buffer electrode and the pixel electrode are arranged at intervals in the same layer.

5. A display panel, characterized in that, include: Multiple first scan lines extend along the row direction and are spaced apart along the column direction; Multiple data lines extend along the column direction and are spaced apart along the row direction; as well as Multiple pixel units as described in any one of claims 1-4 are respectively disposed at multiple intersection positions of the multiple first scan lines and the multiple data lines.

6. A display device, characterized in that, include: The display panel as described in claim 5; as well as A driving circuit is electrically connected to the display panel and is used to drive the display panel to display.

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