A time synchronization precision test method

Abstract

The application discloses a time synchronization precision test method. The method is applied to an upper computer of a time synchronization precision test system, triggers a signal generator in the system to emit a pulse signal according to a preset period, acquires different receiving times of an MCU chip and each SOC chip to the same pulse signal, and different receiving times of the same SOC chip to two adjacent pulse signals, tests a first time precision between the MCU chip and each SOC chip based on the different receiving times of the MCU chip and each SOC chip to the same pulse signal, and tests a second time precision in the same SOC chip based on the different receiving times of the same SOC chip to the two adjacent pulse signals and the preset period. The technical scheme of the application provides a new time synchronization precision test method, measures the time synchronization precision in the early stage of software development, and discovers the time synchronization precision problem in advance.

Description

Technical Field

[0001] This invention relates to the field of time synchronization testing technology, and in particular to a method for testing time synchronization accuracy. Background Technology

[0002] In recent years, with the rapid development of intelligent technology in the automotive industry, there have been significant breakthroughs in the field of intelligent driving, from L1 to L2++, from semi-autonomous driving to autonomous driving in some scenarios. Functions have evolved from the initial single fixed-speed cruise control or lane keeping function to the current adaptive cruise control, automatic braking system, lane keeping assist system and other functions. These functions all require the domain controller to make correct decisions based on sensor information in a short period of time in order to cope with complex driving scenarios. Therefore, the time synchronization of sensor data among the chips involved in decision-making within the domain controller has become particularly important.

[0003] Currently, most time synchronization accuracy testing methods measure it from the perspective of actual functional latency. However, if time synchronization accuracy issues arise during the later integration testing phase of software development, significant time is required to troubleshoot the software problems, impacting project schedules. Therefore, a time synchronization accuracy measurement method that can detect such issues early is needed. Summary of the Invention

[0004] This invention provides a time synchronization accuracy testing method, which allows for the measurement of time synchronization accuracy in the early stages of software development, thus enabling the early detection of time synchronization accuracy problems.

[0005] According to one aspect of the present invention, a time synchronization accuracy testing method is provided. This method is applied to a host computer of a time synchronization accuracy testing system, the time synchronization accuracy testing system further comprising a domain controller and a signal generator. The domain controller includes a microcontroller unit (MCU) chip and at least one system-on-a-chip (SoC). The method includes:

[0006] The signal generator is triggered to emit pulse signals according to a preset period;

[0007] Obtain the different reception times of the same pulse signal for the MCU chip and each SOC chip, as well as the different reception times of the same SOC chip for two adjacent pulse signals;

[0008] Based on the different reception times of the same pulse signal by the MCU chip and each SOC chip, the first time accuracy between the MCU chip and each SOC chip is tested by a preset inter-chip time accuracy algorithm.

[0009] Based on the different reception times of two adjacent pulse signals from the same SOC chip and the preset period, the second time accuracy within the same SOC chip is tested using a preset chip-based time accuracy algorithm.

[0010] According to another aspect of the present invention, a time synchronization accuracy testing device is provided, which is integrated into the host computer of a time synchronization accuracy testing system. The time synchronization accuracy testing system further includes a domain controller and a signal generator. The domain controller includes a microcontroller unit (MCU) chip and at least one system-on-a-chip (SoC). The device includes:

[0011] A pulse signal transmission trigger module is used to trigger the signal generator to transmit pulse signals according to a preset period;

[0012] The pulse signal reception time acquisition module is used to acquire the different reception times of the same pulse signal by the MCU chip and each SOC chip, as well as the different reception times of two adjacent pulse signals by the same SOC chip.

[0013] The inter-chip time accuracy test module is used to test the first time accuracy between the MCU chip and each SOC chip based on the different reception times of the same pulse signal by the MCU chip and each SOC chip, and through a preset inter-chip time accuracy algorithm.

[0014] The in-chip time accuracy test module is used to test the second time accuracy within the same SOC chip based on the different reception times of two adjacent pulse signals of the same SOC chip and the preset period, using a preset in-chip time accuracy algorithm.

[0015] According to another aspect of the present invention, a time synchronization accuracy testing system is provided, the system comprising: a signal generator, a domain controller, and a host computer; the domain controller comprising an MCU chip and at least one SOC chip;

[0016] The signal generator is used to transmit pulse signals according to a preset period;

[0017] The MCU chip and the SOC chip are used to receive the pulse signal and send the time information of receiving the pulse signal to the host computer;

[0018] The host computer is used to execute the time synchronization accuracy testing method described in any embodiment of the present invention.

[0019] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0020] At least one processor; and

[0021] A memory communicatively connected to the at least one processor; wherein,

[0022] The memory stores a computer program that can be executed by the at least one processor, which enables the at least one processor to perform the time synchronization accuracy testing method according to any embodiment of the present invention.

[0023] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to execute and implement the time synchronization accuracy testing method according to any embodiment of the present invention.

[0024] The technical solution of this invention is applied to the host computer of a time synchronization accuracy testing system. The time synchronization accuracy testing system further includes a domain controller and a signal generator. The domain controller includes a microcontroller unit (MCU) chip and at least one system-on-a-chip (SOC) chip. The system triggers the signal generator to emit pulse signals according to a preset period. It acquires the different reception times of the MCU chip and each SOC chip for the same pulse signal, as well as the different reception times of the same SOC chip for two adjacent pulse signals. Based on the different reception times of the MCU chip and each SOC chip for the same pulse signal, a preset inter-chip time accuracy algorithm is used to test the first time accuracy between the MCU chip and each SOC chip. Based on the different reception times of the same SOC chip for two adjacent pulse signals and the preset period, a preset intra-chip time accuracy algorithm is used to test the second time accuracy within the same SOC chip. This provides a new method for testing time synchronization accuracy, allowing for measurement of time synchronization accuracy in the early stages of software development and early detection of time synchronization accuracy problems.

[0025] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1a This is a flowchart of a time synchronization accuracy testing method provided in Embodiment 1 of the present invention;

[0028] Figure 1bThis is a schematic diagram illustrating the pulse signal emission time and the chip's recording of the pulse signal reception time, as provided in Embodiment 1 of the present invention.

[0029] Figure 2 This is a schematic diagram of a time synchronization accuracy testing device provided in Embodiment 2 of the present invention;

[0030] Figure 3a This is a schematic diagram of a time synchronization accuracy testing system provided in Embodiment 3 of the present invention;

[0031] Figure 3b This is a schematic diagram of another time synchronization accuracy testing system provided in Embodiment 3 of the present invention;

[0032] Figure 4 This is a schematic diagram of the structure of an electronic device that implements the time synchronization accuracy testing method of this invention. Detailed Implementation

[0033] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0034] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0035] Example 1

[0036] Figure 1aThis is a flowchart of a time synchronization accuracy testing method provided in Embodiment 1 of the present invention. This embodiment is applicable to the situation of testing the time synchronization accuracy of chips involved in decision-making within a vehicle domain controller. The method can be executed by a time synchronization accuracy testing device, which can be implemented in hardware and / or software. This device can be configured in the host computer of a time synchronization accuracy testing system. The time synchronization accuracy testing system can also include a domain controller and a signal generator. The domain controller can include an MCU (Microcontroller Unit) chip and at least one SOC (System on Chip) chip. Figure 1a As shown, the method includes:

[0037] S110, The trigger signal generator transmits pulse signals according to a preset cycle.

[0038] In this embodiment, for example, a 1Hz pulse signal with a 10% duty cycle and an amplitude of 1.8V can be generated by a signal generator as a time measurement standard for 1 second. The setting of the pulse signal here is only an example and is not a limitation of this embodiment.

[0039] The signal generator can be triggered by the host computer or manually.

[0040] S120: Obtain the different reception times of the same pulse signal by the MCU chip and each SOC chip, as well as the different reception times of two adjacent pulse signals by the same SOC chip.

[0041] The pulse signal emitted by the signal generator can be received by the MCU chip and SOC chip in the domain controller, thereby achieving the purpose of testing the time synchronization accuracy between or within the chip.

[0042] In one optional implementation, obtaining the different reception times of the MCU chip and each SOC chip for the same pulse signal, and the different reception times of the same SOC chip for two adjacent pulse signals, includes: after determining that the signal generator transmits the current pulse signal according to a preset period, obtaining the current first reception time of the MCU chip for the current pulse signal, and obtaining the current second reception time of each SOC chip for the current pulse signal; after determining that the signal generator transmits the next pulse signal according to a preset period, returning to obtain the next first reception time of the MCU chip for the next pulse signal, and obtaining the next second reception time of each SOC chip for the next pulse signal, until the signal generator stops transmitting pulse signals.

[0043] In this embodiment, since the pulse signal is sent periodically, the MCU chip and each SOC chip also receive the pulse signal periodically.

[0044] Taking an MCU chip and a SOC chip as an example, the first transmission time of a pulse signal is recorded as t1. Correspondingly, the MCU chip records its own reception time for this first pulse signal as t3 (the current first reception time), and the SOC chip records its own reception time for this first pulse signal as t5 (the current second reception time). After a preset interval, the pulse signal is transmitted a second time, recorded as t2. The MCU chip records its own reception time for this second pulse signal as the second first reception time t4 (equivalent to the next first reception time), and the SOC chip records its own reception time for this second pulse signal as the second second reception time t6 (equivalent to the next second reception time); and so on, until the signal generator stops transmitting pulse signals. Furthermore, the MCU chip and the SOC chip can promptly upload the recorded reception time information to the host computer, allowing the host computer to obtain the different reception times (e.g., t3 and t5) of the same pulse signal from the MCU chip and the SOC chip, as well as the different reception times (e.g., t5 and t6) of two adjacent pulse signals from the same SOC chip.

[0045] For example, the periodic emission time of the pulse signal, and the reception time of the pulse signal by the MCU chip and the SOC chip can be as follows: Figure 1b As shown.

[0046] It should be noted that if there are multiple SOC chips, each SOC chip can be numbered, and the reception time information recorded by each SOC chip can be uploaded to a directory with the chip number as the directory.

[0047] S130. Based on the different reception times of the same pulse signal by the MCU chip and each SOC chip, the first time accuracy between the MCU chip and each SOC chip is tested by a preset inter-chip time accuracy algorithm.

[0048] In one optional embodiment, the following operations may be performed for each SOC chip: calculating the difference between the current first reception time and the current second reception time as the current first time precision between the MCU chip and the current SOC chip; calculating the difference between the next first reception time and the next second reception time as the next first time precision between the MCU chip and the current SOC chip.

[0049] Specifically, when there is only one SOC chip, continuing with the example of S120, |t5-t3| can be used as the first first time precision (i.e., the current first time precision) between the MCU chip and the SOC chip; |t6-t4| can be used as the second first time precision (i.e., the next first time precision) between the MCU chip and the SOC chip.

[0050] When there are multiple SOC chips, a current SOC chip can be identified sequentially according to its chip number. Replacing the current SOC chip with the SOC chip in the S120 example, |t5-t3| can be used as the first first time precision between the MCU chip and the current SOC chip (i.e., the current first time precision); |t6-t4| can be used as the second first time precision between the MCU chip and the current SOC chip (i.e., the next first time precision). This process continues until all SOC chips have been processed, resulting in multiple first time precisions between the MCU chip and each SOC chip.

[0051] S140. Based on the different reception times and preset periods of two adjacent pulse signals from the same SOC chip, the second time accuracy within the same SOC chip is tested using a preset chip-based time accuracy algorithm.

[0052] In one alternative embodiment, the following operations may be performed for each SOC chip:

[0053] If the current pulse signal is not the first pulse signal, after determining that the current second receiving time of the current pulse signal is obtained by the current SOC chip, the first difference between the current second receiving time and the previous second receiving time adjacent to the current second receiving time is determined; the second difference between the first difference and the preset period is used as the current second time accuracy in the current SOC chip.

[0054] If the current pulse signal is the first pulse signal, after determining the next second reception time of the current pulse signal obtained by the current SOC chip, a new first difference between the current second reception time and the next second reception time is determined; the new second difference between the new first difference and the preset period is used as the next second time precision in the current SOC chip.

[0055] Specifically, when there are one or more SOC chips, the SOC chip in the S120 example is considered as one SOC chip or the current SOC chip among multiple SOC chips, and the current pulse signal in the S120 example is the first pulse signal. Then the second difference is |t6-t5|-1s, and the second difference is used as the second time precision, where |t6-t5| is the first difference.

[0056] If the current pulse signal is not the first pulse signal, after obtaining the previous second receiving time adjacent to the current second receiving time, the method for determining the second time accuracy is the same as the aforementioned scheme.

[0057] Optionally, a time accuracy threshold can be preset (e.g., 200 microseconds), and the current first time accuracy, the next first time accuracy, the current second time accuracy, and the next second time accuracy calculated each time can be compared with the preset time accuracy threshold. A time synchronization accuracy test report can be generated based on the comparison results and displayed to the user, allowing the user to make adaptive adjustments based on the test report.

[0058] The technical solution of this invention is applied to the host computer of a time synchronization accuracy testing system. The time synchronization accuracy testing system further includes a domain controller and a signal generator. The domain controller includes a microcontroller unit (MCU) chip and at least one system-on-a-chip (SOC) chip. The system triggers the signal generator to emit pulse signals according to a preset period. It acquires the different reception times of the MCU chip and each SOC chip for the same pulse signal, as well as the different reception times of the same SOC chip for two adjacent pulse signals. Based on the different reception times of the MCU chip and each SOC chip for the same pulse signal, a preset inter-chip time accuracy algorithm is used to test the first time accuracy between the MCU chip and each SOC chip. Based on the different reception times of the same SOC chip for two adjacent pulse signals and the preset period, a preset intra-chip time accuracy algorithm is used to test the second time accuracy within the same SOC chip. This provides a new method for testing time synchronization accuracy, allowing for measurement of time synchronization accuracy in the early stages of software development and early detection of time synchronization accuracy problems.

[0059] Example 2

[0060] Figure 2 This is a schematic diagram of a time synchronization accuracy testing device provided in Embodiment 2 of the present invention. This device can be integrated into the host computer of a time synchronization accuracy testing system. The time synchronization accuracy testing system may also include a domain controller and a signal generator. The domain controller may include a microcontroller (MCU) chip and at least one system-on-a-chip (SoC), such as… Figure 2 As shown, the device includes: a pulse signal transmission triggering module 210, a pulse signal reception time acquisition module 220, an inter-chip time accuracy testing module 230, and an intra-chip time accuracy testing module 240. Wherein:

[0061] The pulse signal transmission trigger module 210 is used to trigger the signal generator to transmit pulse signals according to a preset period;

[0062] The pulse signal reception time acquisition module 220 is used to acquire the different reception times of the same pulse signal by the MCU chip and each SOC chip, as well as the different reception times of two adjacent pulse signals by the same SOC chip.

[0063] The inter-chip time accuracy test module 230 is used to test the first time accuracy between the MCU chip and each SOC chip based on the different reception times of the same pulse signal by the MCU chip and each SOC chip respectively, and through a preset inter-chip time accuracy algorithm.

[0064] The in-chip time accuracy test module 240 is used to test the second time accuracy within the same SOC chip based on the different reception times of two adjacent pulse signals of the same SOC chip and the preset period, using a preset in-chip time accuracy algorithm.

[0065] The technical solution of this invention is applied to the host computer of a time synchronization accuracy testing system. The time synchronization accuracy testing system further includes a domain controller and a signal generator. The domain controller includes a microcontroller unit (MCU) chip and at least one system-on-a-chip (SOC) chip. The system triggers the signal generator to emit pulse signals according to a preset period. It acquires the different reception times of the MCU chip and each SOC chip for the same pulse signal, as well as the different reception times of the same SOC chip for two adjacent pulse signals. Based on the different reception times of the MCU chip and each SOC chip for the same pulse signal, a preset inter-chip time accuracy algorithm is used to test the first time accuracy between the MCU chip and each SOC chip. Based on the different reception times of the same SOC chip for two adjacent pulse signals and the preset period, a preset intra-chip time accuracy algorithm is used to test the second time accuracy within the same SOC chip. This provides a new method for testing time synchronization accuracy, allowing for measurement of time synchronization accuracy in the early stages of software development and early detection of time synchronization accuracy problems.

[0066] Optionally, the pulse signal receiving time acquisition module 220 can be used for:

[0067] After determining that the signal generator transmits the current pulse signal according to the preset period, the current first reception time of the current pulse signal of the MCU chip is obtained, and the current second reception time of the current pulse signal of each SOC chip is obtained.

[0068] After determining that the signal generator transmits the next pulse signal according to the preset period, the process returns to obtain the next first reception time of the next pulse signal for the MCU chip, and obtains the next second reception time of the next pulse signal for each SOC chip, until the signal generator stops transmitting pulse signals.

[0069] Optional, the inter-chip time accuracy test module 230 can be used for:

[0070] Perform the following operations for each SOC chip:

[0071] The difference between the current first receiving time and the current second receiving time is calculated as the current first time accuracy between the MCU chip and the current SOC chip;

[0072] The difference between the next first reception time and the next second reception time is calculated as the next first time precision between the MCU chip and the current SOC chip.

[0073] Optionally, the on-chip time accuracy test module 240 can be used for:

[0074] Perform the following operations for each SOC chip:

[0075] If the current pulse signal is not the first pulse signal, after determining that the current second receiving time of the current pulse signal is obtained by the current SOC chip, the first difference between the current second receiving time and the previous second receiving time adjacent to the current second receiving time is determined; the second difference between the first difference and the preset period is used as the current second time accuracy in the current SOC chip.

[0076] If the current pulse signal is the first pulse signal, after determining that the next second reception time of the current pulse signal is obtained by the current SOC chip, a new first difference between the current second reception time and the next second reception time is determined; the new second difference between the new first difference and the preset period is used as the next second time precision in the current SOC chip.

[0077] The time synchronization accuracy testing device provided in the embodiments of the present invention can execute the time synchronization accuracy testing method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the method execution.

[0078] Example 3

[0079] Figure 3a This is a schematic diagram of a time synchronization accuracy testing system provided in Embodiment 3 of the present invention. Figure 3a As shown, the system includes: a signal generator 310, a domain controller 320, and a host computer 330; the domain controller 320 includes an MCU chip 3201 and at least one SOC chip 3202;

[0080] The signal generator 310 is used to transmit pulse signals according to a preset period;

[0081] The MCU chip 3201 and the SOC chip 3202 are used to receive the pulse signal and send the time information of receiving the pulse signal to the host computer 330.

[0082] The host computer 330 is used to execute the time synchronization accuracy testing method described in any embodiment of the present invention, the method comprising:

[0083] The signal generator 310 is triggered to emit a pulse signal according to a preset period;

[0084] Obtain the different reception times of the same pulse signal for the MCU chip 3201 and each SOC chip 3202, as well as the different reception times of the same SOC chip 3202 for two adjacent pulse signals;

[0085] Based on the different reception times of the same pulse signal by the MCU chip 3201 and each SOC chip 3202, the first time accuracy between the MCU chip 3201 and each SOC chip 3202 is tested by a preset inter-chip time accuracy algorithm.

[0086] Based on the different reception times of two adjacent pulse signals by the same SOC chip 3202 and the preset period, the second time accuracy within the same SOC chip 3202 is tested by a preset in-chip time accuracy algorithm.

[0087] The technical solution of this invention is applied to the host computer of a time synchronization accuracy testing system. The time synchronization accuracy testing system further includes a domain controller and a signal generator. The domain controller includes a microcontroller unit (MCU) chip and at least one system-on-a-chip (SOC) chip. The system triggers the signal generator to emit pulse signals according to a preset period. It acquires the different reception times of the MCU chip and each SOC chip for the same pulse signal, as well as the different reception times of the same SOC chip for two adjacent pulse signals. Based on the different reception times of the MCU chip and each SOC chip for the same pulse signal, a preset inter-chip time accuracy algorithm is used to test the first time accuracy between the MCU chip and each SOC chip. Based on the different reception times of the same SOC chip for two adjacent pulse signals and the preset period, a preset intra-chip time accuracy algorithm is used to test the second time accuracy within the same SOC chip. This provides a new method for testing time synchronization accuracy, allowing for measurement of time synchronization accuracy in the early stages of software development and early detection of time synchronization accuracy problems.

[0088] Optionally, the time synchronization accuracy testing system may further include: a network harness 340;

[0089] The network harness is used to connect the domain controller and the host computer through the main connector of the domain controller, and to transmit time information between the domain controller and the host computer.

[0090] Optionally, the time synchronization accuracy testing system may further include: a test harness 350;

[0091] The test harness is used to connect the signal generator to the MCU chip and each SOC chip of the domain controller through multiple digital signal test points corresponding to the MCU chip and each SOC chip on the domain controller, respectively.

[0092] For example, Figure 3b This is a schematic diagram of another time synchronization accuracy testing system provided in Embodiment 3 of the present invention. The time synchronization accuracy testing system consists of a domain controller 320, a network harness 340, a host computer 330, a signal generator 310, and a test harness 350. The domain controller 320 is connected to the host computer 330 via the network harness 340, and the signal generator 310 is connected to the domain controller 320 via the test harness 350. The domain controller 320 has an MCU chip 3201, a SOC chip 3202, a harness main connector 3203, and digital signal measurement points 3204. Both the MCU chip 3201 and the SOC chip 3202 can read data from the digital signal test points 3204. The harness main connector 3203 has an interface for the network harness 340.

[0093] Example 4

[0094] Figure 4 A schematic diagram of the structure of an electronic device 400 that can be used to implement embodiments of the present invention is shown. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the invention described and / or claimed herein.

[0095] like Figure 4 As shown, the electronic device 400 includes at least one processor 401 and a memory, such as a read-only memory (ROM) 402 and a random access memory (RAM) 403, communicatively connected to the at least one processor 401. The memory stores computer programs executable by the at least one processor. The processor 401 can perform various appropriate actions and processes based on the computer program stored in the ROM 402 or loaded into the RAM 403 from storage unit 408. The RAM 403 may also store various programs and data required for the operation of the electronic device 400. The processor 401, ROM 402, and RAM 403 are interconnected via a bus 404. An input / output (I / O) interface 405 is also connected to the bus 404.

[0096] Multiple components in electronic device 400 are connected to I / O interface 405, including: input unit 406, such as keyboard, mouse, etc.; output unit 407, such as various types of displays, speakers, etc.; storage unit 408, such as disk, optical disk, etc.; and communication unit 409, such as network card, modem, wireless transceiver, etc. Communication unit 409 allows electronic device 400 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0097] Processor 401 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 401 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 401 performs the various methods and processes described above, such as time synchronization accuracy testing methods.

[0098] In some embodiments, the time synchronization accuracy testing method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 408. In some embodiments, part or all of the computer program may be loaded and / or installed on electronic device 400 via ROM 402 and / or communication unit 409. When the computer program is loaded into RAM 403 and executed by processor 401, one or more steps of the time synchronization accuracy testing method described above may be performed. Alternatively, in other embodiments, processor 401 may be configured to perform the time synchronization accuracy testing method by any other suitable means (e.g., by means of firmware).

[0099] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0100] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0101] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0102] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0103] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or computing systems that include middleware components (e.g., application servers), or computing systems that include frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0104] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0105] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0106] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A time synchronization accuracy testing method, applied to a host computer of a time synchronization accuracy testing system, wherein the time synchronization accuracy testing system further includes a domain controller and a signal generator, the domain controller including a microcontroller unit (MCU) chip and at least one system-on-a-chip (SoC), characterized in that, include: The signal generator is triggered to emit pulse signals according to a preset period; Obtain the different reception times of the same pulse signal for the MCU chip and each SOC chip, as well as the different reception times of the same SOC chip for two adjacent pulse signals; Based on the different reception times of the same pulse signal by the MCU chip and each SOC chip, the first time accuracy between the MCU chip and each SOC chip is tested by a preset inter-chip time accuracy algorithm. Based on the different reception times of two adjacent pulse signals by the same SOC chip and the preset period, the second time accuracy within the same SOC chip is tested by a preset chip-in-chip time accuracy algorithm. Based on the different reception times of the same pulse signal by the MCU chip and each SOC chip, a first time accuracy between the MCU chip and each SOC chip is tested using a preset inter-chip time accuracy algorithm, including: Perform the following operations for each SOC chip: The difference between the current first receiving time and the current second receiving time is calculated as the current first time accuracy between the MCU chip and the current SOC chip; wherein, the current first receiving time is the receiving time of the current pulse signal by the MCU chip, and the current second receiving time is the receiving time of the current pulse signal by the current SOC chip; The difference between the next first reception time and the next second reception time is calculated as the next first time accuracy between the MCU chip and the current SOC chip; Based on the different reception times of two adjacent pulse signals from the same SOC chip and the preset period, a second time accuracy within the same SOC chip is tested using a preset in-chip time accuracy algorithm, including: Perform the following operations for each SOC chip: If the current pulse signal is not the first pulse signal, after determining that the current second receiving time of the current pulse signal is obtained by the current SOC chip, the first difference between the current second receiving time and the previous second receiving time adjacent to the current second receiving time is determined; the second difference between the first difference and the preset period is used as the current second time accuracy in the current SOC chip. If the current pulse signal is the first pulse signal, after determining that the next second reception time of the current pulse signal is obtained by the current SOC chip, a new first difference between the current second reception time and the next second reception time is determined; the new second difference between the new first difference and the preset period is used as the next second time precision in the current SOC chip.

2. The method according to claim 1, characterized in that, Obtain the different reception times of the same pulse signal for the MCU chip and each SOC chip, as well as the different reception times of two adjacent pulse signals for the same SOC chip, including: After determining that the signal generator transmits the current pulse signal according to the preset period, the current first reception time of the current pulse signal of the MCU chip is obtained, and the current second reception time of the current pulse signal of each SOC chip is obtained. After determining that the signal generator transmits the next pulse signal according to the preset period, the process returns to obtain the next first reception time of the next pulse signal for the MCU chip, and obtains the next second reception time of the next pulse signal for each SOC chip, until the signal generator stops transmitting pulse signals.

3. A time synchronization accuracy testing device, integrated into the host computer of a time synchronization accuracy testing system, wherein the time synchronization accuracy testing system further includes a domain controller and a signal generator, the domain controller including a microcontroller unit (MCU) chip and at least one system-on-a-chip (SoC), characterized in that, include: A pulse signal transmission trigger module is used to trigger the signal generator to transmit pulse signals according to a preset period; The pulse signal reception time acquisition module is used to acquire the different reception times of the same pulse signal by the MCU chip and each SOC chip, as well as the different reception times of two adjacent pulse signals by the same SOC chip. The inter-chip time accuracy test module is used to test the first time accuracy between the MCU chip and each SOC chip based on the different reception times of the same pulse signal by the MCU chip and each SOC chip, and through a preset inter-chip time accuracy algorithm. The in-chip time accuracy test module is used to test the second time accuracy within the same SOC chip based on the different reception times of two adjacent pulse signals of the same SOC chip and the preset period, by using a preset in-chip time accuracy algorithm. Specifically, the inter-chip time accuracy testing module is used for: Perform the following operations for each SOC chip: The difference between the current first receiving time and the current second receiving time is calculated as the current first time accuracy between the MCU chip and the current SOC chip; wherein, the current first receiving time is the receiving time of the current pulse signal by the MCU chip, and the current second receiving time is the receiving time of the current pulse signal by the current SOC chip; The difference between the next first reception time and the next second reception time is calculated as the next first time accuracy between the MCU chip and the current SOC chip; The in-chip time accuracy testing module is specifically used for: Perform the following operations for each SOC chip: If the current pulse signal is not the first pulse signal, after determining that the current second receiving time of the current pulse signal is obtained by the current SOC chip, the first difference between the current second receiving time and the previous second receiving time adjacent to the current second receiving time is determined; the second difference between the first difference and the preset period is used as the current second time accuracy in the current SOC chip. If the current pulse signal is the first pulse signal, after determining that the next second reception time of the current pulse signal is obtained by the current SOC chip, a new first difference between the current second reception time and the next second reception time is determined; the new second difference between the new first difference and the preset period is used as the next second time precision in the current SOC chip.

4. A time synchronization accuracy testing system, characterized in that, include: A signal generator, a domain controller, and a host computer; the domain controller includes an MCU chip and at least one SOC chip; The signal generator is used to transmit pulse signals according to a preset period; The MCU chip and the SOC chip are used to receive the pulse signal and send the time information of receiving the pulse signal to the host computer; The host computer is used to execute the time synchronization accuracy test method according to any one of claims 1-2.

5. The system according to claim 4, characterized in that, Also includes: Network harness; The network harness is used to connect the domain controller and the host computer through the main connector of the domain controller, and to transmit time information between the domain controller and the host computer.

6. The system according to claim 4, characterized in that, It also includes test harnesses; The test harness is used to connect the signal generator to the MCU chip and each SOC chip of the domain controller through multiple digital signal test points corresponding to the MCU chip and each SOC chip on the domain controller, respectively.

7. An electronic device, characterized in that, The electronic device includes: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform a time synchronization accuracy testing method according to any one of claims 1-2.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that cause a processor to execute a time synchronization accuracy testing method according to any one of claims 1-2.

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