A battery management system slave module automatic addressing method and a battery management system

Abstract

The application relates to an energy storage battery management system, in particular to a battery management system masterless automatic addressing method and an energy storage battery management system using the method. The application realizes automatic addressing of slave modules without the participation of a master module by setting a square wave with a certain output period low level and high level in the slave module, determining the current address after the next slave module detects the period low level, and then outputting a square wave with a period + step low level and high level, and the next slave module detects and determines the current address, and the process is repeated, so that automatic addressing of the slave modules is realized without the participation of the master module.

Description

Technical Field

[0001] This invention relates to an energy storage battery management system, and more particularly to an automatic addressing method for a slave module of a battery management system and an energy storage battery management system using the method. Background Technology

[0002] A battery management system (BMS), commonly known as a battery nanny or battery steward, is mainly used for intelligent management and maintenance of each battery cell, preventing overcharging and over-discharging, extending battery life, and monitoring battery status.

[0003] A Battery Management System (BMS) typically consists of a master control module, slave control modules, and high-voltage management modules. The slave control modules are responsible for collecting voltage and temperature data from individual battery cells and performing tasks such as equalization and thermal management. The high-voltage management module is responsible for monitoring the insulation of the battery pack and controlling high-voltage components. The master control module receives battery information from the slave control and high-voltage management modules via a CAN bus, performs state estimation and fault diagnosis, and manages the entire battery pack and BMS. When a slave control module is connected to the BMS system, its module address needs to be edited; otherwise, incorrect addresses will cause errors in the battery cell voltage and temperature information transmitted by the slave control module, affecting fault diagnosis and state management of the battery pack.

[0004] Chinese invention patent application (publication number: CN109116238A, publication date: 2019-01-01) discloses an automatic addressing method for a battery management system. The method includes: connecting a slave control module and a high-voltage management module to the battery management system; detecting the multi-channel switching quantities input to the slave control module and the high-voltage management module; encoding the addresses of the slave control module and the high-voltage management module according to the multi-channel switching quantities; transmitting the addresses to the master control module; determining whether the addresses are abnormal; and issuing an alarm message if the addresses are abnormal.

[0005] However, during the use of slave control modules, since the system uses a large number of slave control modules, setting the address of the slave control modules is time-consuming and laborious. Therefore, the slave control modules need to have automatic addressing function. Summary of the Invention

[0006] To address the aforementioned technical problems, the present invention aims to provide an automatic addressing method for slave control modules in a battery management system. This method enables automatic addressing of slave control modules regardless of whether a master control module is involved.

[0007] To achieve the above objectives, the present invention adopts the following technical solution: An automatic addressing method for slave control modules in a battery management system is disclosed. The slave control modules are n, where n is a positive integer greater than or equal to 2. The n slave control modules are connected sequentially, and each slave control module includes at least two I / O ports: an output port IO1 and an input port IO2. The output port IO1 of the previous slave control module is connected to the input port IO2 of the next slave control module. The slave control module also has various functional units such as a communication unit, a timing unit, a storage unit, and a data acquisition unit. Each slave control module communicates with the master control module through the communication unit.

[0008] It has both modes: In Mode 1, when n slave control modules are connected to the master control module via CAN communication, the master control module sends an automatic addressing broadcast command. After time Td1, the slave control modules receive the command and start automatic addressing.

[0009] Mode 2: When n slave control modules are not connected to the master control module via CAN communication, or are connected but have not sent an automatic addressing broadcast command, the slave control modules will start automatic addressing after a period of Td2 time after power-on.

[0010] Initiating automatic addressing involves the following steps: 1) All slave control modules output a high level on their IO1 ports and wait for time Td3; 2) If the slave module detects that the IO2 port level is low and remains low for a duration of Td3, it is the first slave module; 3) All slave control modules that have obtained the serial number output a square wave with a low level for time t1+t2×(m-1) plus a high level for time t3. After sending this wave multiple times, the output is low. Other modules whose address numbers have not been updated continue to output a high level. m is the slave control module number. 4) The next slave module receives a square wave with low and high levels. Through the low level time t1+t2×(m-1), it learns the address number of the previous slave module, which is also its own address number.

[0011] 5) Repeat steps 3)-4), and so on. If the low level time of the IO2 port detected by the (n-1)th slave module is t1+t2×(n-2), then the address number of the module itself is determined to be n-1; the output of the IO1 port of this slave module is a square wave with a low level time of t1+t2×(n-1) and a high level time of t3; if the low level time of the IO2 port detected by the nth slave module is t1+t2×(n-1), then the address number of the module itself is determined to be n. 5) In Mode 1, the slave module informs the master module of its own address code. If the master module does not receive a new address code after waiting for Td4 time, or if the master module confirms whether the slave module's address number is complete through internal configuration parameters, it sends an addressing end command if complete, otherwise it repeats the process. In Mode 2, there is no change.

[0012] In the case of mode two, when starting automatic addressing, step 3) also includes that the IO1 port of the slave control module that obtained the number outputs a square wave with a low level for time t1+t2×(m-1) plus a high level for time t3, and outputs a low level after sending it multiple times; after waiting for time Td5, it outputs a square wave with a high level for time t1+t2×(m-1) plus a low level for time t3, and outputs a low level after sending it multiple times, for repeated verification by the next module.

[0013] In the case of starting automatic addressing in mode two, step 4) also includes verifying the address number by using a high level for t1+t2×(m-1) time.

[0014] As a preferred option, the time Td1 is 1s~5s, the time Td2 is 5s~2min, the time Td3 is 1s~5s, the time Td4 can be set by the number of slave control modules, and is generally 1min~2min, and the time Td5 is 30s~2min.

[0015] As a preferred option, t1 is 2ms~100ms; t2 is 2ms~100ms; t3 is 2ms~100ms.

[0016] Preferably, the duration of multiple square wave transmissions in steps 3) and 4) is 30s to 2min.

[0017] As a preferred option, when replacing modules in the future, automatic addressing can be performed by re-issuing commands through the main control module in Mode 1 or by following Mode 2.

[0018] Furthermore, the present invention also discloses a battery management system, which includes n slave control modules connected in sequence. Each slave control module includes at least two I / O ports. With or without the participation of a master control module, the n slave control modules achieve automatic addressing using the method described above.

[0019] Furthermore, the present invention also discloses a computer device, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the method.

[0020] Furthermore, the present invention also discloses a computer-readable storage medium having a computer program or instructions stored thereon, which, when executed by a processor, implements the method.

[0021] By employing the aforementioned technical solution, this invention achieves automatic addressing of the slave control module by setting the output of a square wave with a certain period of low and high levels related to the address in the slave control module. After the next slave control module detects the low level of this period, it determines the current address and then outputs a square wave with a certain period of low and high levels related to the address. The next slave control module detects and determines the current address, and so on, thus realizing automatic addressing of the slave control module regardless of whether the master control module is involved. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the connection structure of the slave control module in Mode 1 of the present invention. Figure 1 .

[0023] Figure 2 This is a schematic diagram of the connection structure of the slave control module in Mode 1 of the present invention. Figure 2 .

[0024] Figure 3 This is a schematic diagram of the connection structure of the slave control module in Mode 2 of the present invention.

[0025] Figure 4 This is a schematic diagram of the connection structure of the eight slave control modules in Mode 2 of the present invention.

[0026] Figure 5 This is a schematic diagram of the automatic addressing logic flow of the slave control module of the present invention.

[0027] Figure 6 This is a schematic diagram of the signal sent by the control module IO1 of the present invention.

[0028] Figure 7 This is a flowchart of the program design for the present invention. Detailed Implementation

[0029] The technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0030] like Figure 1 As shown, there are n slave control modules, M1-Mn, where n is a positive integer greater than or equal to 2. The n slave control modules are connected in sequence, and each slave control module includes at least two I / O ports: output port I / O1 and input port I / O2. The output port I / O1 of the previous slave control module is connected to the input port I / O2 of the next slave control module. The slave control module also has various functional units such as communication unit, timing unit, storage unit, and acquisition unit. Each slave control module communicates with the master control module M0 through the communication unit, using CAN communication.

[0031] like Figure 2 As shown, the master control module M0 can also be connected to IO2 of the first slave control module M1 to directly send signals. like Figure 3 As shown, the main control module has not yet been connected to the main control module M0 for communication.

[0032] like Figure 4 As shown, the example slave control module has 8 slave control modules connected in sequence, and each slave control module includes at least 2 IO ports. The IO2 terminal of the slave control module is used as an input to receive the signal from the previous slave control module; the IO1 terminal is used as an output to output a signal to the next slave control module.

[0033] like Figure 5 , Figure 6 As shown, the automatic addressing logic flow strategy of the present invention, as well as the output signal of the slave control module IO1, are illustrated in the following embodiments: The automatic addressing logic of this invention has two modes: In Mode 1, when n slave control modules are connected to the master control module via CAN communication, the master control module sends an automatic addressing broadcast command. After time Td1 (1s), the slave control modules receive the command and start automatic addressing.

[0034] Mode 2: When n slave control modules are not connected to the master control module via CAN communication, or are connected but have not sent an automatic addressing broadcast command, the slave control modules will start automatic addressing after a period of Td2 time (60s) after being powered on.

[0035] Initiating automatic addressing involves the following steps: 1) All slave control modules output a high level on their IO1 ports and wait for Td3 time (1s). 2) If the slave module detects that the IO2 port level is low and remains low for Td3 time (1s), it is the first slave module; 3) The IO1 port of the slave control module that has obtained the number outputs a square wave with a low level for time t1+t2×(m-1) plus a high level for time t3. After sending it multiple times, it outputs a low level (the time of multiple square waves is 1 minute). Other modules whose address numbers have not been updated continue to output a high level. 4) The next slave module receives a square wave with low and high levels. Through the low level time t1+t2×(m-1), it learns the address number of the previous slave module, which is also its own address number.

[0036] 5) Repeat steps 3)-4), and so on. If the low level time of the IO2 port detected by the (n-1)th slave module is t1+t2×(n-2), then the address number of the module itself is determined to be n-1; the output of the IO1 port of this slave module is a square wave with a low level time of t1+t2×(n-1) and a high level time of t3; if the low level time of the IO2 port detected by the nth slave module is t1+t2×(n-1), then the address number of the module itself is determined to be n. In this embodiment, t1, t2, and t3 are 50ms. When the first slave control module obtains the address number update, the IO1 port of the first slave control module outputs a square wave with a low level of (50ms + 0ms) followed by a high level of 50ms. The square wave is output multiple times in a row. After the time lasts for 1 minute, the output level is low. The remaining slave control modules continue to output high levels. When the second slave module receives the address number update, the IO1 port of the second slave module outputs a square wave with a low level of (50ms + 50ms) followed by a high level of 50ms. The square wave is output multiple times in a row, and after a duration of 1 minute, it outputs a low level. Except for slave modules 1 and 2, the remaining slave modules continuously output a high level. When the third slave module receives the address number update, the IO1 port of the third slave module outputs a square wave with a low level of (50ms + 100ms) followed by a high level of 50ms. The square wave is output multiple times in a row, and after a duration of 1 minute, it outputs a low level. Except for slave modules 1, 2, and 3, the remaining slave modules continuously output a high level. The remaining slave control modules follow the same pattern. Each slave control module obtains its address number through a low-level period within a square wave.

[0037] 5) In Mode 1, the slave module informs the master module of its own address code. If the master module does not receive a new address code after waiting for Td4 time (1 minute), or if the master module confirms whether the slave module's address number is complete through internal configuration parameters, it sends an addressing end command if complete, otherwise it repeats the process. In Mode 2, there is no change.

[0038] The time required to set 8 slave control modules in mode 1 is: 1s + 1s + 50ms × (1 + 2 + ... + 7) * m ≈ 5s (m = 2, the number of waveform confirmations, the time required to detect more than 2 waveforms meets the requirements). Adding the 60s waiting time of the master control module in step 5), the total time is 65s.

[0039] The time required to set up 8 slave control modules in mode 2 is: 60s + 1s + 50ms × (1 + 2 + ... + 7) * m ≈ 65s (m = 2, the number of waveform confirmations; the time required to detect more than 2 waveforms meets the requirements).

[0040] In the case of mode two, when starting automatic addressing, step 3) also includes that the IO1 port of the slave control module that obtained the number outputs a square wave with a low level for time t1+t2×(m-1) plus a high level for time t3, and outputs a low level after sending it multiple times; after waiting for time Td5 (30s), it outputs a square wave with a high level for time t1+t2×(m-1) plus a low level for time t3, and outputs a low level after sending it multiple times, for repeated verification by the next module.

[0041] In the case of starting automatic addressing in mode two, step 4) also includes verifying the address number by using a high level for t1+t2×(m-1) time.

[0042] When replacing modules in the future, automatic addressing can be performed by re-issuing commands through the main control module in Mode 1 or by following Mode 2.

[0043] Other points to note regarding the method of this invention: 1. The slave control module address numbering using the method of this invention starts from number 1; 2. When replacing modules in the future, automatic addressing needs to be performed again; 3. The I / O connections between the slave and controller modules must not be disconnected and must be maintained.

[0044] like Figure 7 The flowchart shown is a program design flowchart for automatic addressing of the slave control module of the present invention. Some of the code is abstract code, and the specific process involved is as follows: Step 1: The master control module sends a command to the slave control module: Automatic addressing of the slave control module; Start the automatic addressing command loss timer. If the automatic addressing command loss timer is greater than or equal to the set requirement (e.g., set to 5 seconds), proceed to step 10; If the timer is less than the set requirement, and the slave control module receives the command sent by the master control module, the slave control module starts automatic addressing, sets the I01 port to a high level, and proceeds to step 2. In the first mode, the master control module sends a command: the slave control module does not perform automatic addressing; proceed to step 10. When the slave module does not receive a command from the master module in Mode 1, or when the master module is not connected in Mode 2, i.e. when the timer is greater than or equal to the set requirement (e.g., set to 60s) without a command, the slave module will start automatic addressing, set the I01 port to high level, and proceed to step 2. Step 2: Determine whether the slave module has enabled automatic addressing. If the slave module has not enabled automatic addressing, proceed to step 10; if the slave module has enabled automatic addressing, start the program execution timer and proceed to step 3. Step 3: Determine if the program execution time is less than the set requirement (which can be set according to the number of slave control modules, such as setting the execution time requirement to 1min~10min). If it is greater than or equal to, proceed to step 10; if it is less than, proceed to step 4. Step 4: Determine whether the slave control module is performing address allocation. If the slave control module is not performing address allocation, proceed to step 9; if the slave control module is performing address allocation, proceed to step 5. Step 5: Determine whether a low level has been read from the I02 port of the slave module. If no low level has been read from the I02 port of the slave module, proceed to Step 6. If a low level has been read from the I02 port of the slave module, obtain the duration of the continuous low level reading, set the low level flag to 1, and proceed to Step 7. Step 6: Determine if the low-level flag is 1. If the low-level flag is not 1, proceed to step 7. If the low-level flag is 1, obtain the duration of the continuous high-level reading and determine if the high-level count has reached the set requirement (e.g., set to 50ms). If the high-level time requirement has not been met, proceed to step 10. If it has been met, proceed to step 8. Step 7: Determine whether the low-level time count has reached the set requirement (e.g., the first module is set to 1 second, and other modules are judged based on the low-level time output by IO1). If the low-level time has been reached, proceed to step 8; otherwise, proceed to step 5. Step 8: Calculate the slave module address and configure its own address. The slave module finishes address configuration and proceeds to step 9. Step 9: Output a square wave from the I01 port of the control module: a low level for time t1 + t2 × (m-1) followed by a high level for time t3, and send it multiple times (t1, t2, and t3 are 50ms each, and the duration of the multiple square waves is 1 minute); Proceed to Step 2; Step 10: End the process.

[0045] The foregoing description of embodiments of the present invention, through which those skilled in the art are able to implement or use the present invention, will be readily apparent to those skilled in the art. Various modifications to these embodiments will be readily apparent to those skilled in the art. The general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novelty disclosed herein.

Claims

1. A battery management system slave module automatic addressing method, the slave module has n, n is a positive integer greater than or equal to 2, n slave modules are connected in turn, and each slave module includes at least two IO ports, which are an output port IO1 and an input port IO2, the output port IO1 of the previous slave module is connected with the input port IO2 of the next slave module, and the slave module further has a communication unit, a timing unit, a storage unit, a collection unit and other functional units; each slave module is connected with a master module for communication through the communication unit; characterized in that, It has both modes: Mode 1: When n slave control modules are connected to the master control module via CAN communication, the master control module sends an automatic addressing broadcast command. After time Td1, the slave control modules receive the command and start automatic addressing. Mode 2: When n slave control modules are not connected to the master control module via CAN communication, or are connected but have not sent an automatic addressing broadcast command, the slave control module will start automatic addressing after a period of Td2 after power-on. The automatic addressing process includes the following steps: 1) All slave control modules output a high level on their IO1 ports and wait for time Td3; 2) If the slave module detects that the IO2 port level is low and remains low for a duration of Td3, it is the first slave module; 3) All slave control modules that have obtained the serial number output a square wave with a low level for time t1+t2×(m-1) plus a high level for time t3. After sending this wave multiple times, the output is low. Other modules whose address numbers have not been updated continue to output a high level. m is the slave control module number. 4) The next slave module receives a square wave with low and high levels. Through the low level time t1+t2×(m-1), it learns the address number of the previous slave module, which is also its own address number. 5) Repeat steps 3)-4), and so on. If the low level time of the IO2 port detected by the (n-1)th slave module is t1+t2×(n-2), then the address number of the module itself is determined to be n-1; the output of the IO1 port of this slave module is a square wave with a low level time of t1+t2×(n-1) and a high level time of t3; if the low level time of the IO2 port detected by the nth slave module is t1+t2×(n-1), then the address number of the module itself is determined to be n. 5) In Mode 1, the slave module informs the master module of its own address code. If the master module does not receive a new address code after waiting for Td4 time, or if the master module confirms whether the slave module's address number is complete through internal configuration parameters, it sends an addressing end command if complete, otherwise it repeats the process. In Mode 2, there is no change.

2. The method according to claim 1, characterized in that, The automatic addressing also includes: Step 3) also includes the slave control module IO1 port that obtains the number outputting a square wave with a low level for time t1+t2×(m-1) plus a high level for time t3, sending it multiple times and then outputting a low level; after waiting for time Td5, it outputs a square wave with a high level for time t1+t2×(m−1) plus a low level for time t3, sending it multiple times and then outputting a low level, for repeated verification by the next module; Step 4) also includes verifying the address number by using a high-level time t1+t2×(m-1).

3. The method according to claim 1, characterized in that, The time Td1 is 1s~5s, the time Td2 is 5s~2min, the time Td3 is 1s~5s, and the time Td4 can be set by the number of slave control modules, generally 1min~2min.

4. The method according to claim 1, characterized in that, t1 is 2ms~100ms; t2 is 2ms~100ms; t3 is 2ms~100ms.

5. The method according to claim 2, characterized in that, Td5 time is 30s~2min.

6. The method according to claim 1, characterized in that, In steps 3) and 4), the duration of multiple square wave transmissions is 30 seconds to 2 minutes.

7. The method according to claim 1, characterized in that, Automatic addressing can be performed by re-issuing commands through the main control module in Mode 1 or by following Mode 2.

8. The method according to claim 1, characterized in that, The computer program flow of this method includes the following steps: Step 1: The master control module sends a command to the slave control module: Automatic addressing of the slave control module; Start the automatic addressing command loss timer. If the automatic addressing command loss timer is greater than or equal to the set requirement, proceed to step 10; If the timer is less than the set requirement, and the slave control module receives the command sent by the master control module, the slave control module starts automatic addressing, sets the I01 port to high level, and proceeds to step 2. In the first mode, the master control module sends a command: the slave control module does not perform automatic addressing; proceed to step 10; When the slave module does not receive a command from the master module in Mode 1, or when the master module is not connected in Mode 2 (i.e., the timing is greater than or equal to the set requirement without a command), the slave module starts automatic addressing, sets the I01 port to a high level, and proceeds to step 2. Step 2: Determine whether the slave module has enabled automatic addressing. If the slave module has not enabled automatic addressing, proceed to step 10; if the slave module has enabled automatic addressing, start the program execution timer and proceed to step 3. Step 3: Determine if the program execution time is less than the set requirement. If it is greater than or equal to the requirement, proceed to step 10; if it is less than the requirement, proceed to step 4. Step 4: Determine whether the slave control module is performing address allocation. If the slave control module is not performing address allocation, proceed to step 9; if the slave control module is performing address allocation, proceed to step 5. Step 5: Determine whether a low level has been read from the I02 port of the slave module. If no low level has been read from the I02 port of the slave module, proceed to Step 6. If a low level has been read from the I02 port of the slave module, obtain the duration of the continuous low level reading, set the low level flag to 1, and proceed to Step 7. Step 6: Determine if the low-level flag is 1. If the low-level flag is not 1, proceed to step 7. If the low-level flag is 1, obtain the duration of the continuous high-level reading and determine if the high-level count has reached the set requirement. If the high-level time requirement has not been met, proceed to step 10. If it has been met, proceed to step 8. Step 7: Determine whether the low-level time count has reached the set requirement. If the low-level time has been reached, proceed to step 8; otherwise, proceed to step 5. Step 8: Calculate the slave module address and configure its own address. The slave module finishes address configuration and proceeds to step 9. Step 9: Output a square wave from port I01 of the control module: a low level for time t1 + t2 × (m-1) plus a high level for time t3, send multiple times; go to step 2; Step 10: End the process.

9. A battery management system comprising n sequentially connected slave control modules, each slave control module including at least two I / O ports, characterized in that, n slave control modules implement automatic addressing using the method described in any one of claims 1-8.

10. A computer device, comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the method according to any one of claims 1-8.

11. A computer-readable storage medium having a computer program or instructions stored thereon, characterized in that, When the computer program or instructions are executed by a processor, they implement the method described in any one of claims 1-8.

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