A high voltage bandgap reference circuit

Abstract

The application belongs to the field of integrated circuits, and particularly relates to a high-voltage bandgap reference circuit, which comprises: a drain of a PMOS tube M3 connected to a source of a PMOS tube M4, and a source of the PMOS tube M3 connected to a power supply; a start-up circuit connected to a bias current circuit, a bandgap reference circuit and a gate of the PMOS tube M3, which separates the bias current circuit and the bandgap reference circuit from a zero state when an input voltage is powered on; the bias current circuit is connected to the gate of the PMOS tube M3 and the gate of the PMOS tube M4, and generates a positive temperature coefficient current to provide a bias current for the bandgap reference module and a feedback current; the bandgap reference circuit is connected to the drain of the PMOS tube M4 to realize a zero temperature coefficient output voltage; and the feedback circuit is connected to the bandgap reference circuit to improve the matching of a current mirror; the application improves the accuracy of the bandgap reference output voltage, does not need an additional trimming circuit to correct the reference circuit, and has a simple structure and low power consumption.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuits, and specifically relates to a high-voltage bandgap reference circuit. Background Technology

[0002] The voltage reference circuit is a crucial module in a chip, and its performance directly impacts the overall chip performance. For high-voltage power supply chips such as DC-DC converters, the input voltage can reach tens of volts. A commonly used high-voltage bandgap reference circuit topology is as follows: Figure 1 As shown, a voltage regulator circuit first converts the high input voltage into a low output voltage, which serves as the power supply voltage for the bandgap reference circuit. Therefore, this bandgap reference voltage can use a low-voltage circuit structure. In this topology, the voltage regulator module typically uses a Zener diode operating in reverse breakdown mode to generate a stable low output voltage. However, because the Zener diode requires a large reverse breakdown current, its power consumption is relatively high, significantly increasing the overall power consumption of the chip.

[0003] Another traditional high-voltage bandgap reference circuit structure is as follows: Figure 2 As shown, this is a typical bandgap reference circuit structure, where PMOS transistors M1 and M2 are high-voltage transistors, allowing the circuit to withstand high input voltages. However, the matching between the high-voltage MOS transistors is poor, with a maximum matching error exceeding 30%. This results in unequal currents flowing through transistors Q1 and Q2, leading to a significant deviation in the bandgap reference output voltage. Therefore, an additional trimming circuit is needed to correct the output voltage.

[0004] In summary, there is an urgent need for a novel bandgap reference circuit that can be directly applied to high input voltages without requiring a high-to-low voltage regulator circuit, which could significantly reduce chip power consumption. Simultaneously, it solves the problem of poor matching of the high-voltage current mirror, eliminating the need for additional adjustment circuits to correct the output voltage and saving adjustment costs. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention proposes a high-voltage bandgap reference circuit, which includes: a startup circuit, a bias current circuit, a bandgap reference circuit, a feedback circuit, a PMOS transistor M3, and a PMOS transistor M4.

[0006] The drain of PMOS transistor M3 is connected to the source of PMOS transistor M4, and the source of PMOS transistor M3 is connected to the power supply.

[0007] The startup circuit connects the bias current circuit, the bandgap reference circuit, and the gate of PMOS transistor M3. When the input voltage is applied, the startup circuit disconnects the bias circuit and the bandgap reference circuit from their degeneracy points.

[0008] The bias current circuit is connected to the gate of PMOS transistor M3 and the gate of PMOS transistor M4. The bias current circuit generates a current with a positive temperature coefficient to provide bias current for the bandgap reference module and the feedback current.

[0009] The bandgap reference circuit is connected to the drain of the PMOS transistor M4, and the bandgap reference circuit achieves a zero temperature coefficient output voltage;

[0010] The feedback circuit is connected to the bandgap reference circuit. The feedback circuit keeps the drain potential of the PMOS current mirror in the bandgap reference consistent. At the same time, the current mirror in the bandgap reference can use a low-voltage current mirror structure to improve the matching of the current mirror, thereby improving the output voltage accuracy of the bandgap reference circuit.

[0011] Preferably, the startup circuit includes PMOS transistors M14-M15, four NMOS transistors M16-M20, two resistors R7-R8, and an N-channel JFET. The source of PMOS transistor M14 and the drain of JFET J1 are connected to the power supply. The gate of PMOS transistor M14 is connected to the bias current circuit and the gate of PMOS transistor M3, respectively. The drain of PMOS transistor M14 is connected to the source of PMOS transistor M15. The gate of PMOS transistor M15 is connected to the bias current circuit and the gate of PMOS transistor M4, respectively. The drain of PMOS transistor M15 is connected to the drain of NMOS transistor M16 and the drain of NMOS transistor M16. The gates of the NMOS transistor M16, M17, M18, M19, and M20 are connected to the gate of the NMOS transistor M17 and M18, the gate of the NMOS transistor M18, the gate of the NMOS transistor M19, and the gate of the NMOS transistor M20. The drain of the NMOS transistor M19 is connected to the bias current circuit. The drain of the NMOS transistor M20 is connected to the bandgap reference circuit. The sources of the NMOS transistors M16, M17, M18, M19, and M20 and the gate of the JFET J1 are all grounded.

[0012] Preferably, the bias current circuit includes four PMOS transistors M8-M11, two NMOS transistors M12-M13, two NPN transistors Q3-Q4, and two resistors R5-R6. The sources of PMOS transistors M8 and M9 are connected to the power supply. The gate of PMOS transistor M8 is connected to the gate of PMOS transistor M9, the drain of PMOS transistor M10, and the startup circuit. The drain of PMOS transistor M8 is connected to the source of PMOS transistor M10. One end of resistor R6 is connected to the drain of PMOS transistor M10, the gate of PMOS transistor M10 is connected to the gate of PMOS transistor M11 and the gate of PMOS transistor M4, and the other end of resistor R6 is connected to the startup circuit. The circuit consists of: the drain of PMOS transistor M9 connected to the source of PMOS transistor M11; the drain of NMOS transistor M12 connected to the other end of resistor R6; the gate of NMOS transistor M12 connected to the gate of NMOS transistor M13 and the startup circuit; the source of NMOS transistor M12 connected to the startup circuit and the collector of NPN transistor Q3; the drain of PMOS transistor M11 connected to the drain of NMOS transistor M13; the source of NMOS transistor M13 connected to the collector of NPN transistor Q4, the base of NPN transistor Q3, and the base of NPN transistor Q4; the emitter of NPN transistor Q3 connected to one end of resistor R5; and the emitter of NPN transistor Q4 and the other end of resistor R5 grounded.

[0013] Preferably, the bandgap reference circuit includes two PMOS transistors M1-M2, two NPN transistors Q1-Q2, and two resistors R1-R2. The sources of PMOS transistors M1 and M2 are both connected to the drain of PMOS transistor M4, the startup circuit, and the feedback circuit. The gate of PMOS transistor M1 is connected to the drain of PMOS transistor M1 and the gate of PMOS transistor M2. The collector of NPN transistor Q1 is connected to the drain of PMOS transistor M1, and the base of NPN transistor Q1 is connected to the base of NPN transistor Q2 and the feedback circuit. The emitter of NPN transistor Q1 is connected to one end of resistor R1, and the other end of resistor R1 is connected to one end of resistor R2. The collector of NPN transistor Q2 is connected to the drain of PMOS transistor M2 and the feedback circuit, and the emitter of NPN transistor Q2 is connected to one end of resistor R2. The other end of resistor R2 is grounded.

[0014] Preferably, the feedback circuit includes a PMOS transistor M6, two NMOS transistors M5 and M7, and two resistors R3 to R4; the drain of NMOS transistor M5 is connected to the power supply, the gate of NMOS transistor M5 is connected to the source of PMOS transistor M6 and the bandgap reference circuit, and the source of NMOS transistor M5 is connected to one end of resistor R4; the gate of PMOS transistor M6 is connected to the bandgap reference circuit, and the drain of PMOS transistor M6 is connected to the drain of NMOS transistor M7 and the gate of NMOS transistor M7; the other end of resistor R4 is connected to one end of resistor R3 and the bandgap reference circuit, and the other end of resistor R3 and the source of NMOS transistor M7 are both grounded.

[0015] The beneficial effects of this invention are as follows:

[0016] (1) The bandgap reference circuit can operate directly under high input voltage, and a very low supply voltage can be provided to the bandgap reference circuit through a simple feedback circuit. There is no need to use a complex high-voltage to low-voltage regulator circuit. The circuit structure is simple and the power consumption is low.

[0017] (2) The current mirror of the core circuit of the bandgap reference can use a low-voltage tube, which enhances the matching accuracy of the current mirror and inherits the advantages of the low-voltage bandgap reference circuit.

[0018] (3) The bandgap reference circuit further maintains the current in the current mirror of the bandgap reference by a simple feedback circuit, and can eliminate the error of the base current of the NPN transistor in the bandgap reference circuit, thereby further improving the accuracy of the output voltage of the bandgap reference without the need for additional adjustment circuits to correct the reference circuit. Attached Figure Description

[0019] Figure 1 It is a traditional high-voltage bandgap reference topology;

[0020] Figure 2 This is a typical high-voltage bandgap reference circuit structure;

[0021] Figure 3 This is a diagram of the high-voltage bandgap reference circuit in this invention. Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] This invention proposes a high-voltage bandgap reference circuit, such as... Figure 3 As shown, the circuit includes the following:

[0024] The high-voltage bandgap reference circuit proposed in this invention includes a startup circuit, a bias current circuit, a bandgap reference circuit, a feedback circuit, a PMOS transistor M3, and a PMOS transistor M4;

[0025] The drain of PMOS transistor M3 is connected to the source of PMOS transistor M4, and the source of PMOS transistor M3 is connected to the power supply.

[0026] The startup circuit connects the bias current circuit, the bandgap reference circuit, and the gate of PMOS transistor M3. When the input voltage is applied, the startup circuit decouples the bias circuit and the bandgap reference circuit from their degeneracy points. Specifically:

[0027] The startup circuit includes PMOS transistors M14-M15, four NMOS transistors M16-M20, two resistors R7-R8, and an N-channel JFET. The source of PMOS transistor M14 and the drain of JFET J1 are connected to the power supply. The gate of PMOS transistor M14 is connected to the bias current circuit and the gate of PMOS transistor M3. The drain of PMOS transistor M14 is connected to the source of PMOS transistor M15. The gate of PMOS transistor M15 is connected to the bias current circuit and the gate of PMOS transistor M4. The drain of PMOS transistor M15 is connected to the drain of NMOS transistor M16 and the drain of NMOS transistor M20. The gates of M16 and M17 are connected; the source of JFET J1 is connected to one end of resistor R7, the other end of resistor R7 is connected to one end of resistor R8 and the bias current circuit, and the other end of resistor R8 is connected to the drain of NMOS M17, the drain of NMOS M18, the gate of NMOS M18, the gate of NMOS M19, and the gate of M20; the drain of NMOS M19 is connected to the bias current circuit; the drain of M20 is connected to the bandgap reference circuit; the sources of NMOS M16, M17, M18, M19, and M20 and the gate of JFET J1 are all grounded.

[0028] When the power supply voltage VIN is applied, current flows through NMOS transistor M18, pulling the voltage at point D low through M19. This causes the bias current generation circuit to break out of its zero state and begin operation, and also pulls the voltage V1 low through M20. When the bias current generation circuit is operating, it turns on M16, turning off M19 and M20, making the current flowing through M19 and M20 zero, thus completing the startup process.

[0029] The bias current circuit connects the gates of PMOS transistors M3 and M4, generating a positive temperature coefficient current to provide bias current for the bandgap reference module and the feedback current; specifically:

[0030] The bias current circuit includes four PMOS transistors M8-M11, two NMOS transistors M12-M13, two NPN transistors Q3-Q4, and two resistors R5-R6. The sources of PMOS transistors M8 and M9 are connected to the power supply. The gate of PMOS transistor M8 is connected to the gate of PMOS transistor M9, the drain of PMOS transistor M10, and the gate of PMOS transistor M14 in the startup circuit. The drain of PMOS transistor M8 is connected to the source of PMOS transistor M10. One end of resistor R6 is connected to the drain of PMOS transistor M10, and the gate of PMOS transistor M10 is connected to the gate of PMOS transistor M11 and the gate of PMOS transistor M4. The other end of resistor R6 is connected to PMOS transistor M15 in the startup circuit. The gate of the NMOS transistor is connected to the gate of the NMOS transistor M11; the drain of the NMOS transistor M12 is connected to the other end of the resistor R6; the gate of the NMOS transistor M12 is connected to the gate of the NMOS transistor M13 and one end of the resistor R8 in the startup circuit; the source of the NMOS transistor M12 is connected to the drain of the NMOS transistor M19 in the startup circuit and the collector of the NPN transistor Q3; the drain of the PMOS transistor M11 is connected to the drain of the NMOS transistor M13; the source of the NMOS transistor M13 is connected to the collector of the NPN transistor Q4, the base of the NPN transistor Q3, and the base of the NPN transistor Q4; the emitter of the NPN transistor Q3 is connected to one end of the resistor R5; the emitter of the NPN transistor Q4 and the other end of the resistor R5 are grounded.

[0031] The bandgap reference circuit is connected to the drain of PMOS transistor M4, and the bandgap reference circuit achieves a zero-temperature coefficient output voltage; specifically:

[0032] The bandgap reference circuit includes two PMOS transistors M1-M2, two NPN transistors Q1-Q2, and two resistors R1-R2. The sources of PMOS transistors M1 and M2 are connected to the drain, startup, and feedback circuit of PMOS transistor M4. The gate of PMOS transistor M1 is connected to the drain of PMOS transistor M1 and the gate of PMOS transistor M2. The collector of NPN transistor Q1 is connected to the drain of PMOS transistor M1, and the base of NPN transistor Q1 is connected to the base of NPN transistor Q2 and the feedback circuit. The emitter of NPN transistor Q1 is connected to one end of resistor R1, and the other end of resistor R1 is connected to one end of resistor R2. The collector of NPN transistor Q2 is connected to the drain of PMOS transistor M2 and the feedback circuit, and the emitter of NPN transistor Q2 is connected to one end of resistor R2. The other end of resistor R2 is grounded.

[0033] The core circuit of the bandgap reference consists of PMOS transistors M1 and M2, NPN transistors Q1 and Q2, and resistors R1 and R2. Assuming the width-to-length ratio of PMOS transistors M1 and M2 is 1:1, the current mirror formed by M1 and M2 ensures that the currents flowing through Q1 and Q2 are equal. Therefore, the voltage difference V between the base and emitter of NPN transistors Q1 and Q2 is... BE1 and VBE2 They are respectively:

[0034]

[0035]

[0036] Where n is the ratio of the emitter areas of Q1 and Q2, V T = kT / q, therefore the current I1 flowing through Q1 is:

[0037]

[0038] As can be seen from the above formula, I1 is a current that is positively correlated with temperature.

[0039] Then the output voltage V of the bandgap reference REF for:

[0040]

[0041] Among them, V BE2 It is a voltage with a negative temperature coefficient, V T Since the voltage has a positive temperature coefficient, by choosing an appropriate value for n and the ratio of R2 / R1, a zero temperature coefficient output voltage can be obtained.

[0042] Bias current I of the core circuit of the bandgap reference b2 Must meet:

[0043]

[0044] Where k is the ratio of the dimensions of M6 and M1, and I1 is the current flowing through Q1. From the above equation, we can see that I... b2 It must be a current with a positive temperature coefficient, and this current is obtained by biasing a cascode current mirror composed of M8, M9, and resistor R6. Therefore, the current I of this current mirror must be... b1 It should also have a positive temperature coefficient. For example... Figure 3 As shown, current I b1 The current generated by transistors Q3 and Q4 and resistor R5 is:

[0045]

[0046] Where m is the ratio of the emitter areas of transistors Q4 and Q3, and this current has a positive temperature coefficient; V BE3 V represents the voltage difference between the base and emitter of NPN transistor Q3. BE4 This represents the voltage difference between the base and emitter of the NPN transistor Q4. Assume I... b2 and I b1If the current ratio is h:1, then resistors R5 and R1 must satisfy the following relationship:

[0047]

[0048] The feedback circuit is connected to the bandgap reference circuit. The feedback circuit ensures that the drain potential of the PMOS current mirror in the bandgap reference remains consistent. Simultaneously, the current mirror in the bandgap reference can use a low-voltage current mirror structure, improving the current mirror's matching performance and thus enhancing the output voltage accuracy of the bandgap reference circuit. Specifically:

[0049] The feedback circuit includes a PMOS transistor M6, two NMOS transistors M5 and M7, and two resistors R3 to R4. The drain of NMOS transistor M5 is connected to the power supply, and the gate of NMOS transistor M5 is connected to the source of PMOS transistor M6 and the source of PMOS transistor M2 in the bandgap reference circuit. The source of NMOS transistor M5 is connected to one end of resistor R4. The gate of PMOS transistor M6 is connected to the drain of PMOS transistor M2 in the bandgap reference circuit, and the drain of PMOS transistor M6 is connected to the drain of NMOS transistor M7 and the gate of NMOS transistor M7. The other end of resistor R4 is connected to one end of resistor R3 and the gate of NPN transistor Q2 in the bandgap reference circuit. The other end of resistor R3 and the source of NMOS transistor M7 are both grounded.

[0050] The ratio of the tube size of M6 to that of M1 and M2 is k:1. This is achieved by setting a suitable bias current I. b2 This makes the current flowing through M6 equal to k times the current through M2. If the channel length modulation effect is ignored, then V GS1 =V GS6 This ensures that the potentials at points A and B are equal, which further guarantees that the currents flowing through M1 and M2 are equal. It also reduces the error of the base currents of Q1 and Q2, and further improves the accuracy of the bandgap reference output voltage.

[0051] The high-voltage transistor M5 and resistors R3 and R4 clamp the voltage V1, making the voltage V1 as follows:

[0052]

[0053] Among them, V GS_M5 V1 is the gate-source voltage of the high-voltage NMOS transistor M5. By setting an appropriate ratio of the resistance values ​​of R3 and R4, V1 can be made to be a very low voltage. Then, the current mirror composed of MOS transistors M1 and M2 can use a low-voltage PMOS transistor, which has better matching and solves the problem of poor matching of the current mirror composed of high-voltage MOS transistors.

[0054] In summary, the bandgap reference circuit proposed in this invention can operate directly at high input voltages and has a wide operating voltage range. A simple feedback circuit can provide a very low supply voltage to the bandgap reference circuit, replacing the function of the voltage regulator circuit in traditional solutions. The circuit structure is simple and has low power consumption. Furthermore, the current mirror in the core bandgap reference circuit can use a low-voltage transistor, enhancing the matching accuracy of the current mirror. The feedback circuit further ensures that the current in the current mirror remains consistent, greatly improving the accuracy of the output voltage without requiring additional adjustment current to correct the reference circuit.

[0055] The above-described embodiments further illustrate the purpose, technical solution, and advantages of the present invention. It should be understood that the above-described embodiments are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made to the present invention within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A high-voltage bandgap reference circuit, characterized in that, include: Start-up circuit, bias current circuit, bandgap reference circuit, feedback circuit, PMOS transistor M3 and PMOS transistor M4; The drain of PMOS transistor M3 is connected to the source of PMOS transistor M4, and the source of PMOS transistor M3 is connected to the power supply. The startup circuit connects the bias current circuit, the bandgap reference circuit, and the gate of PMOS transistor M3. When the input voltage is applied, the startup circuit removes the bias circuit and the bandgap reference circuit from the zero state. The startup circuit includes PMOS transistors M14~M15, four NMOS transistors M16~M20, two resistors R7~R8, and an N-channel JFET. The source of PMOS transistor M14 and the drain of JFET J1 are connected to the power supply. The gate of PMOS transistor M14 is connected to the bias current circuit and the gate of PMOS transistor M3, respectively. The drain of PMOS transistor M14 is connected to the source of PMOS transistor M15. The gate of PMOS transistor M15 is connected to the bias current circuit and the gate of PMOS transistor M4. The drain of PMOS transistor M15 is connected to the drain, gate, and gate of NMOS transistor M16 and NMOS transistor M17, respectively. The source of JFET J1 is connected to one end of resistor R7. The other end of resistor R7 is connected to one end of resistor R8 and the bias current circuit. The other end of resistor R8 is connected to the drain, drain, gate, gate, and gate of NMOS transistors M17, M18, M18, M19, and M20, respectively. The drain of NMOS transistor M19 is connected to the bias current circuit. The drain of NMOS transistor M20 is connected to the bandgap reference circuit. The sources of NMOS transistors M16, M17, M18, M19, and M20, and the gate of JFET J1 are all grounded. The bias current circuit connects the gates of PMOS transistors M3 and M4, generating a positive temperature coefficient current to provide bias current for the bandgap reference module and feedback current. The bias current circuit includes four PMOS transistors M8-M11, two NMOS transistors M12-M13, two NPN transistors Q3-Q4, and two resistors R5-R6. The sources of PMOS transistors M8 and M9 are connected to the power supply. The gate of PMOS transistor M8 is connected to the gate of PMOS transistor M9, the drain of PMOS transistor M10, and the startup circuit. The drain of PMOS transistor M8 is connected to the source of PMOS transistor M10. One end of resistor R6 is connected to the drain of PMOS transistor M10, and the gate of PMOS transistor M10 is connected to the P4 gate. The gate of MOSFET M11, the gate of PMOS transistor M4, the other end of resistor R6, and the startup circuit are connected; the drain of PMOS transistor M9 is connected to the source of PMOS transistor M11; the drain of NMOS transistor M12 is connected to the other end of resistor R6, the gate of NMOS transistor M12 is connected to the gate of NMOS transistor M13 and the startup circuit, and the source of NMOS transistor M12 is connected to the startup circuit and the collector of NPN transistor Q3; the drain of PMOS transistor M11 is connected to the drain of NMOS transistor M13, the source of NMOS transistor M13 is connected to the collector of NPN transistor Q4, the base of NPN transistor Q3, and the base of NPN transistor Q4; the emitter of NPN transistor Q3 is connected to one end of resistor R5, and the emitter of NPN transistor Q4 and the other end of resistor R5 are grounded; A bandgap reference circuit is connected to the drain of PMOS transistor M4, achieving a zero-temperature coefficient output voltage. The bandgap reference circuit includes two PMOS transistors M1-M2, two NPN transistors Q1-Q2, and two resistors R1-R2. The sources of PMOS transistors M1 and M2 are connected to the drain of PMOS transistor M4, the startup circuit, and the feedback circuit. The gate of PMOS transistor M1 is connected to the drain of PMOS transistor M1 and the gate of PMOS transistor M2. The collector of NPN transistor Q1 is connected to the drain of PMOS transistor M1, and the base of NPN transistor Q1 is connected to the base of NPN transistor Q2 and the feedback circuit. The emitter of NPN transistor Q1 is connected to one end of resistor R1, and the other end of resistor R1 is connected to one end of resistor R2. The collector of NPN transistor Q2 is connected to the drain of PMOS transistor M2 and the feedback circuit, and the emitter of NPN transistor Q2 is connected to one end of resistor R2. The other end of resistor R2 is grounded. The feedback circuit is connected to the bandgap reference circuit. The feedback circuit ensures that the drain potential of the PMOS current mirror in the bandgap reference remains consistent. Simultaneously, the current mirror in the bandgap reference can use a low-voltage current mirror structure to improve the current mirror's matching, thereby improving the output voltage accuracy of the bandgap reference circuit. The feedback circuit includes a PMOS transistor M6, two NMOS transistors M5 and M7, and two resistors R3~R4. The drain of NMOS transistor M5 is connected to the power supply, and the gate of NMOS transistor M5 is connected to the source of PMOS transistor M6 and the bandgap reference circuit. The source of NMOS transistor M5 is connected to one end of resistor R4. The gate of PMOS transistor M6 is connected to the bandgap reference circuit, and the drain of PMOS transistor M6 is connected to the drain and gate of NMOS transistor M7. The other end of resistor R4 is connected to one end of resistor R3 and the bandgap reference circuit, and the other end of resistor R3 and the source of NMOS transistor M7 are both grounded.

Images