Optimized processing method and device of write zero command under abnormal power-off
By caching the command slot ID of the Write Zero command in the SSD and replying to the CQ Entry one by one after the vu trim command is completed, the data inconsistency problem caused by the Write Zero command under abnormal power failure is resolved, and the reliability of processing is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SUZHOU UNIONMEMORY INFORMATION SYST LTD
- Filing Date
- 2023-12-27
- Publication Date
- 2026-07-31
AI Technical Summary
In the event of an abnormal power outage, existing methods for optimizing the execution efficiency of the Write Zero command may lead to inconsistencies between the host and the SSD data.
The command slot IDs of multiple Write Zero commands are cached in the SSD, and the vu trim command is triggered after a preset number is reached. After the trim command is completed, the CQ Entry is replied to one by one.
It improves the reliability of Write Zero command processing and avoids data inconsistency between the host and SSD caused by abnormal power loss.
Smart Images
Figure CN117785049B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of solid-state drive technology, and in particular to an optimized processing method, apparatus, computer device, and storage medium for the Write Zero command under abnormal power loss. Background Technology
[0002] Solid-state drives (SSDs) are widely used in various applications and are gradually replacing traditional HDDs in the PC market, providing users with a better experience in terms of reliability and performance. Currently, most SSDs on the market use the NVMe interface. The Write Zero command is one of the standard commands of the NVMe protocol. Because it does not require the host to allocate dedicated data memory, the Write Zero command is the preferred choice for the host when formatting the SSD NAND.
[0003] To improve the execution efficiency of Write Zero commands, SSD firmware development typically employs a method of caching the LBA ranges of multiple Write Zero commands and merging them into a single VU trim command before sending it to the FTL layer for execution. However, this method prematurely replies to the Complete Queue Entry (CQ entry) of the Write Zero command, which may lead to data inconsistency between the host and the SSD in the event of an abnormal power outage. Summary of the Invention
[0004] Therefore, it is necessary to provide an optimized processing method, apparatus, computer device, and storage medium for Write Zero commands under abnormal power failure to address the above-mentioned technical problems.
[0005] An optimized method for handling the Write Zero command under abnormal power failure, the method comprising:
[0006] SSD obtains the Write Zero command issued by the host;
[0007] The command slot IDs of multiple Write Zero commands are cached in the cmd slot ID buff at the firmware front end;
[0008] Once the number of Write Zero commands cached in the firmware front-end reaches a preset number, the vutrim command is triggered.
[0009] After the vu trim command is executed, the CQ Entry is replied to one by one according to the commandslot id cached in cmd slot id buff.
[0010] In one embodiment, the step of caching the command slot IDs of multiple Write Zero commands in the cmd slot ID buff of the firmware frontend further includes:
[0011] The cmd slot id of the Write Zero command is saved to the cmd slot id buff, but CQ Entry is not responded to at this time.
[0012] In one embodiment, the step of saving the cmd slot id of the Write Zero command to the cmdslot id buff, without replying to the CQ Entry, further includes:
[0013] The host will only determine that the command was executed successfully if it receives a Write Zero command from the CQ Entry.
[0014] In one embodiment, the step of the SSD obtaining the Write Zero command issued by the host further includes:
[0015] Extract the LBA Range carried by the Write Zero command and save it into the lba range buff.
[0016] An optimized processing apparatus for Write Zero commands under abnormal power failure, the apparatus comprising:
[0017] The acquisition module is used by the SSD to acquire the Write Zero command issued by the host;
[0018] A caching module is used to cache the command slot IDs of multiple Write Zero commands in the cmd slot ID buff of the firmware frontend;
[0019] The command triggering module is used to trigger the sending of the vu trim command after the number of Write Zero commands cached in the firmware front end reaches a preset number.
[0020] The response module is used to reply to each CQ Entry one by one according to the command slot ID cached in cmdslot id buff after the vu trim command is executed.
[0021] In one embodiment, the caching module is further configured to:
[0022] The cmd slot id of the Write Zero command is saved to the cmd slot id buff, but CQ Entry is not responded to at this time.
[0023] In one embodiment, the caching module is further configured to:
[0024] The host will only determine that the command was executed successfully if it receives a Write Zero command from the CQ Entry.
[0025] In one embodiment, the device further includes:
[0026] A save module is used to retrieve the LBA Range carried by the Write Zero command and save it into the lba range buff.
[0027] A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of any of the methods described above.
[0028] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of any of the above methods.
[0029] The aforementioned optimized processing method, apparatus, computer device, and storage medium for Write Zero commands under abnormal power loss caches the command slot IDs of multiple Write Zero commands in a cmd slot ID buff in the firmware frontend. Once the number of Write Zero commands cached in the firmware frontend reaches a preset number, a VU trim command is triggered. After the VU trim command is executed, a CQ Entry is replied to one by one according to the command slot IDs cached in the cmd slot ID buff. This invention solves the problem of inconsistency between Host and SSD data caused by abnormal power loss during the caching of multiple Write Zero commands, thus improving the reliability of Write Zero command processing. Attached Figure Description
[0030] Figure 1 This is a schematic diagram of a typical optimization scheme for the Write Zero command in traditional technology;
[0031] Figure 2 This is a flowchart illustrating an optimized processing method for the Write Zero command under abnormal power failure in one embodiment.
[0032] Figure 3This is a flowchart illustrating the optimized processing method for the Write Zero command under abnormal power failure in another embodiment.
[0033] Figure 4 This is a schematic diagram illustrating the optimized processing of the Write Zero command under abnormal power failure in one embodiment;
[0034] Figure 5 This is a structural block diagram of an optimized processing device for Write Zero commands under abnormal power failure in one embodiment;
[0035] Figure 6 This is a structural block diagram of the optimized processing device for Write Zero commands under abnormal power failure in another embodiment;
[0036] Figure 7 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation
[0037] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0038] refer to Figure 1 The diagram illustrates a typical optimization scheme for Write Zero commands in conventional techniques. Upon receiving a Write Zero command, the conventional approach retrieves the LBA range it carries and caches it in the LBA range data buffer. It then immediately replies to the CQ Entry. After a timeout or after caching a certain number of Write Zero commands, the LBA range data buffer is sent to the FTL / NFC via VU trim for execution. Clearly, if an abnormal power outage occurs before execution completes, the data in the host and SSD's respective LBA ranges will become inconsistent.
[0039] Based on this, the present invention provides an optimized processing method for the Write Zero command under abnormal power failure, which aims to solve the problem that the data in the LBA Range related to the Host and SSD will be inconsistent under abnormal power failure.
[0040] In one embodiment, such as Figure 2 As shown, an optimized method for handling the Write Zero command under abnormal power failure is provided. This method includes:
[0041] Step 202: The SSD obtains the Write Zero command issued by the host;
[0042] Step 204: Cache the command slot IDs of multiple Write Zero commands in the cmd slotid buff at the firmware front end;
[0043] Step 206: Once the number of Write Zero commands cached in the firmware front-end reaches a preset number, trigger the sending of the VU trim command;
[0044] Step 208: After the vu trim command is executed, reply to each CQ Entry one by one according to the command slot id cached in cmd slot id buff.
[0045] In this embodiment, an optimized processing method for Write Zero commands under abnormal power loss is provided. This method caches the command slot IDs of multiple Write Zero commands in the firmware frontend. After the VU trim command is completed, the corresponding Write Zero command's SubmissionQueue Entry is read from the command slot according to the cached command slot ID, and the Complete Queue Entry is replied to one by one. This solves the problem of inconsistency between Host and SSD data caused by abnormal power loss during the caching of multiple write zero commands.
[0046] First, the SSD obtains the Write Zero command issued by the host.
[0047] In one embodiment, the step of the SSD obtaining the Write Zero command issued by the host further includes: extracting the LBA Range carried by the Write Zero command and saving it into the lba range buff.
[0048] Specifically, when the SSD receives a Write Zero command, it retrieves the LBA Range carried by the command and saves it to the LBA Range buff. The command slot IDs of multiple Write Zero commands are cached in the cmdslot ID buff at the firmware frontend, and the cmd slot ID of the Write Zero command is also saved to the cmd slot ID buff. At this point, no CQ Entry is responded to.
[0049] Once the front-end caches a specified number of Write Zero commands, it triggers the sending of a VU trim command to FTL / NFC. After the VU trim command completes, the front-end replies to the CQ Entry one by one based on the cmd slot id stored in the cmd slot id buff.
[0050] In the above embodiment, the command slot IDs of multiple Write Zero commands are cached in the cmd slot ID buff of the firmware frontend. Once the number of Write Zero commands cached in the firmware frontend reaches a preset number, a VU trim command is triggered. After the VU trim command is executed, the CQ Entry is replied to one by one according to the command slot IDs cached in the cmd slot ID buff. This solution solves the problem of inconsistency between Host and SSD data caused by abnormal power loss during the caching of multiple Write Zero commands, thus improving the reliability of Write Zero command processing.
[0051] In one embodiment, such as Figure 3 As shown, an optimized method for handling the Write Zero command under abnormal power failure is provided. This method also includes:
[0052] Step 302: Save the cmd slot id of the Write Zero command to the cmd slot id buff, and do not reply to CQ Entry at this time;
[0053] Step 304: The host will only determine that the command was executed successfully if it receives a Write Zero command from the CQ Entry.
[0054] Specifically, refer to Figure 4 The diagram shown illustrates the optimized processing of the Write Zero command under abnormal power failure, including the following steps:
[0055] Step 4.1: When the SSD receives a Write Zero command, it retrieves the LBA Range it carries and saves it to the LBA range buff.
[0056] Step 4.2: Simultaneously, save the cmd slot id of the Write Zero command to the cmd slot id buff. Do not reply to the CQ Entry at this time. The host will only consider the cmd command executed successfully if it receives the CQ Entry for the Write Zero command. That is, the LBA Range carried in the Write Zero command is written to 0.
[0057] Step 4.3: After the number of Write Zero commands in the front-end cache reaches the specified number (e.g., 256), the vu trim command is sent to FTL / NFC.
[0058] Step 4.4: After the vu trim command is executed, the front end replies to the CQ Entry one by one according to the cmdslot id stored in the cmd slot id buff.
[0059] In this embodiment, the command slot IDs of multiple Write Zero commands are cached in the firmware frontend. After the VU trim command completes, the corresponding WriteZero command's Submission Queue Entry is read from the command slot based on the cached command slot ID, and the Complete Queue Entry is replied to one by one. This solves the problem of inconsistency between host and SSD data caused by abnormal power loss during the caching of multiple Write Zero commands.
[0060] It should be understood that, although Figures 1-4 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figures 1-4 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.
[0061] In one embodiment, such as Figure 5 As shown, an optimized processing apparatus 500 for Write Zero commands under abnormal power failure is provided. The apparatus includes:
[0062] Acquisition module 501, the acquisition module is used for SSD to acquire the Write Zero command issued by the host;
[0063] Cache module 502, the cache module is used to cache the command slot IDs of multiple Write Zero commands in the cmd slot ID buff of the firmware front end;
[0064] Command triggering module 503, the command triggering module is used to trigger the sending of vu trim command after the number of Write Zero commands cached in the firmware front end reaches a preset number;
[0065] The response module 504 is used to reply to each CQ Entry one by one according to the command slot id cached in cmdslot id buff after the vu trim command is executed.
[0066] In one embodiment, the cache module 502 is further configured to:
[0067] The cmd slot id of the Write Zero command is saved to the cmd slot id buff, but CQ Entry is not responded to at this time.
[0068] In one embodiment, the cache module 502 is further configured to:
[0069] The host will only determine that the command was executed successfully if it receives a Write Zero command from the CQ Entry.
[0070] In one embodiment, such as Figure 6 As shown, an optimized processing apparatus 500 for Write Zero commands under abnormal power failure is provided, the apparatus further includes:
[0071] The storage module 505 is used to retrieve the LBA Range carried by the Write Zero command and save it into the lba range buff.
[0072] For specific limitations on the optimization processing device for Write Zero commands under abnormal power failure, please refer to the limitations on the optimization processing method for Write Zero commands under abnormal power failure mentioned above, which will not be repeated here.
[0073] In one embodiment, a computer device is provided, the internal structure of which can be shown as follows: Figure 7 As shown, the computer device includes a processor, memory, and a network interface connected via a device bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores operating devices, computer programs, and databases. The internal memory provides an environment for the operation of the operating devices and computer programs stored in the non-volatile storage media. The network interface is used for communication with external terminals via a network connection. When executed by the processor, the computer program implements an optimized processing method for Write Zero commands under abnormal power failure.
[0074] Those skilled in the art will understand that Figure 7 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.
[0075] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps in the various method embodiments described above.
[0076] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps in the various method embodiments described above.
[0077] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and RAMbus dynamic RAM (RDRAM), etc.
[0078] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0079] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. An optimized processing method for the Write Zero command under abnormal power failure, the method comprising: SSD obtains the Write Zero command issued by the host; The command slot IDs of multiple Write Zero commands are cached in the cmd slot ID buff at the firmware front end; Once the number of Write Zero commands cached in the firmware front-end reaches a preset number, the vu trim command is triggered. After the vu trim command is executed, reply to each CQ Entry one by one according to the command slot id cached in cmd slot id buff; The step of caching the command slot IDs of multiple Write Zero commands in the cmd slot ID buff of the firmware frontend further includes: Save the cmd slot id of the Write Zero command to the cmd slot id buff, and do not reply to CQEntry at this time; The step of saving the cmd slot id of the Write Zero command to the cmd slot id buff, without replying to CQ Entry, also includes: The host will only determine that the Write Zero command was executed successfully if it receives a CQ Entry that has received the Write Zero command.
2. The method of claim 1, wherein the method further comprises: The steps for the SSD to obtain the Write Zero command issued by the host also include: Extract the LBA Range carried by the Write Zero command and save it into the LBA Range buff.
3. An optimized processing device for Write Zero commands under abnormal power failure, characterized in that, The device includes: The acquisition module is used by the SSD to acquire the Write Zero command issued by the host; A caching module is used to cache the command slot IDs of multiple Write Zero commands in the cmd slot ID buff of the firmware frontend; The command triggering module is used to trigger the sending of the vu trim command after the number of Write Zero commands cached in the firmware front end reaches a preset number. The response module is used to reply to each CQ Entry one by one according to the command slot ID cached in cmd slotid buff after the vu trim command is executed; The caching module is also used for: Save the cmd slot id of the Write Zero command to the cmd slot id buff, and do not reply to CQEntry at this time; The caching module is also used for: The host will only determine that the Write Zero command was executed successfully if it receives a CQ Entry that has received the Write Zero command.
4. The optimized processing apparatus for Write Zero commands under abnormal power failure according to claim 3, characterized in that, The device further includes: A save module is used to retrieve the LBA Range carried by the Write Zero command and save it into the LBA Range buff.
5. A computer device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 2.
6. A computer-readable storage medium having stored thereon a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 2.