Hardware data management system, related apparatus and write command processing method

Abstract

The embodiment of the application relates to the application field of storage devices, and discloses a hardware data management system, related devices and a write command processing method. The hardware data management system comprises: a host processing module, which is used for acquiring a write command sent by a host and sending a data acquisition command to the host; and a data processing module, which is used for performing a storage operation and editing an effective bitmap instruction on data according to whether the same logical block address is stored in the hardware data management system, so as to send the effective bitmap instruction to firmware. The application can interact with the host by the hardware data management system in the process of the write command of the host, and the firmware is only used for receiving the effective bitmap instruction sent by the hardware data management system, so that the steps of receiving the write command sent by the host controller, reissuing the write command to the host controller and receiving the data reception completion information sent by the host are reduced, the write delay is reduced, and the write performance of the flash memory device is improved.

Description

Technical Field

[0001] This application relates to the field of storage device applications, and in particular to a hardware data management system, related apparatus, and write command processing method. Background Technology

[0002] Flash memory devices, such as solid state drives (SSDs), are hard drives made using solid-state electronic storage chip arrays. SSDs include a solid state drive controller and flash memory. The solid state drive controller mainly includes a main controller and firmware.

[0003] Currently, firmware manages data on the host side and schedules commands for the flash memory, completing the writing of data from the host to the flash memory. The data writing process mainly consists of two parts: the host write command process and the flash write command process.

[0004] During the host write command process, the first step is as follows: The main controller receives the write command sent by the host and forwards it to the firmware. The second step is that, upon confirming that the write command meets the reception conditions, the firmware resends the write command to the main controller. After receiving the data, the main controller sends a data reception completion message to the firmware. The third step is that, after confirming that the main controller has completed data reception, the firmware constructs a flash write command and sends it to the main controller. During the flash write command process, the main controller, based on the flash write command, writes data from the specified Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) to the corresponding location in the flash memory.

[0005] In the process of developing this application, the inventors discovered at least the following problems in the prior art:

[0006] During the host write command process, the firmware and the main controller need to perform three interactive operations, including: the firmware receiving the write command sent by the main controller, the firmware resending the write command to the main controller, and the main controller sending a data reception completion message to the firmware. The frequent interactive operations between the main controller and the firmware will cause write latency, which will lead to a decrease in the write performance of the flash memory device and a deterioration in performance stability. Summary of the Invention

[0007] This application provides a hardware data management system, related devices, and a write command processing method to reduce the interaction between the main controller and the firmware, reduce write latency, and thereby improve the write performance of flash memory devices.

[0008] The embodiments of this application provide the following technical solutions:

[0009] In a first aspect, embodiments of this application provide a hardware data management system applied to a flash memory device. The flash memory device is communicatively connected to a host. The flash memory device includes firmware and flash memory media. The hardware data management system includes:

[0010] The host processing module is used to obtain write commands sent by the host and send data acquisition commands to the host, so as to receive the first logical block address and data corresponding to the data acquisition commands sent by the host;

[0011] The data processing module is used to perform storage operations on the data and edit valid bitmap instructions based on whether the same logical block address is stored inside the hardware data management system, thereby sending valid bitmap instructions to the firmware.

[0012] Among them, the valid bitmap instruction is used to indicate whether the firmware sends a flash write command to the hardware data management system. The flash write command is used to instruct the hardware data management system to store data to the flash media.

[0013] Secondly, embodiments of this application provide a storage control chip, comprising:

[0014] Such as the hardware data management system in the first aspect;

[0015] Firmware connects to the hardware data management system and is used to obtain valid bitmap instructions and send flash write commands to the hardware data management system.

[0016] Thirdly, embodiments of this application provide a flash memory device, including:

[0017] Such as the storage control chip in the second aspect;

[0018] At least one flash memory medium is communicatively connected to the storage controller chip.

[0019] Fourthly, embodiments of this application provide a data transmission system, including:

[0020] The host is used to issue write commands to the flash memory device;

[0021] For example, a flash memory device in the third aspect communicates with the host and is used to store data according to write commands.

[0022] Fifthly, embodiments of this application provide a write command processing method, which is applied to a flash memory device according to a third aspect. The flash memory device is communicatively connected to a host. The write command processing method includes:

[0023] Retrieve the write command sent by the host, and send a data retrieval command to the host;

[0024] Receive the first logical block address and data sent by the host;

[0025] The data is stored based on the address of the first logical block.

[0026] In a sixth aspect, embodiments of this application also provide a non-volatile computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, cause the processor to execute the write command processing method as described in the fifth aspect.

[0027] The beneficial effects of this application embodiment are as follows: Unlike the prior art, this application embodiment provides a hardware data management system applied to a flash memory device. The flash memory device is communicatively connected to a host. The flash memory device includes firmware and a flash memory medium. The hardware data management system includes: a host processing module, used to acquire write commands sent by the host and send data acquisition commands to the host, to receive the first logical block address and data corresponding to the data acquisition commands sent by the host; and a data processing module, used to perform storage operations on the data and edit valid bitmap instructions based on whether the same logical block address is stored internally in the hardware data management system, thereby sending valid bitmap instructions to the firmware; wherein, the valid bitmap instructions are used to indicate whether the firmware sends a flash write command to the hardware data management system, and the flash write command is used to instruct the hardware data management system to store data in the flash memory medium.

[0028] On the one hand, by acquiring the write command sent by the host through the hardware data management system, sending a data acquisition command to the host to receive the first logical block address and data sent by the host, and sending a valid bitmap instruction to the firmware, this application enables the hardware data management system to interact with the host during the host write command process. The firmware is only used to receive the valid bitmap instruction sent by the hardware data management system, thereby reducing the steps of the firmware receiving the write command sent by the host controller, re-issuing the write command to the host controller, and receiving the data reception completion information sent by the host. That is, it reduces the interaction between the host controller and the firmware, reduces write latency, and thus improves the write performance of the flash memory device.

[0029] On the other hand, by using the hardware data management system to perform storage operations and edit valid bitmap instructions based on whether the same logical block address is stored internally, and sending valid bitmap instructions to the firmware to instruct the firmware to send a flash write command to the hardware data management system, this application can reduce the latency of writing multiple data corresponding to the same logical block address to the flash memory when the same logical block address exists in multiple write commands sent by the host, thereby improving the write performance of the flash memory device. Attached Figure Description

[0030] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0031] Figure 1 This is a schematic diagram of the structure of a flash memory device provided in an embodiment of this application;

[0032] Figure 2 This is a schematic diagram of the structure of a hardware data management system provided in an embodiment of this application;

[0033] Figure 3 This is a detailed structural diagram of a hardware data management system provided in an embodiment of this application;

[0034] Figure 4 This is a schematic diagram of a write command sent by a host according to an embodiment of this application;

[0035] Figure 5 This is a schematic diagram illustrating the storage of data in a hardware data management system according to an embodiment of this application;

[0036] Figure 6 This is a schematic diagram of a flash memory write command sent by firmware according to an embodiment of this application;

[0037] Figure 7 This is a schematic diagram illustrating another way data is stored in a hardware data management system, as provided in an embodiment of this application.

[0038] Figure 8 This is a schematic diagram of another flash write command sent by firmware according to an embodiment of this application;

[0039] Figure 9 This is a schematic diagram illustrating another type of data storage in a hardware data management system provided in this application embodiment;

[0040] Figure 10 This is a schematic diagram of another firmware-sent flash write command provided in an embodiment of this application;

[0041] Figure 11 This is a schematic diagram of the write command processing flow provided by an embodiment of this application when the data granularity of the first logical block address is the same as the granularity of the smallest unit of the flash memory device;

[0042] Figure 12 This is a schematic diagram of the write command processing flow provided by an embodiment of this application when the data granularity of the first logical block address is different from the granularity of the smallest unit of the flash memory device;

[0043] Figure 13This is a schematic diagram of the structure of a storage control chip provided in an embodiment of this application;

[0044] Figure 14 This is a schematic diagram of another flash memory device provided in an embodiment of this application;

[0045] Figure 15 This is a schematic diagram of the structure of a data transmission system provided in an embodiment of this application;

[0046] Figure 16 This is a flowchart illustrating a write command processing method provided in an embodiment of this application;

[0047] Figure 17 This is an interactive diagram of a host, a hardware data management system, and firmware provided in an embodiment of this application;

[0048] Figure 18 This is a detailed flowchart illustrating a write command processing method provided in an embodiment of this application.

[0049] Explanation of reference numerals in the attached figures:

[0050]

[0051] Detailed Implementation

[0052] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0053] It should be noted that, unless there is a conflict, the various features in the embodiments of this application can be combined with each other, all of which are within the protection scope of this application. Furthermore, although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order than the module division in the device or the order in the flowchart. Moreover, the terms "first," "second," and "third" used in this application do not limit the data or execution order, but only distinguish identical or similar items with essentially the same function and effect.

[0054] The technical solution of this application will be described in detail below with reference to the accompanying drawings:

[0055] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of a flash memory device provided in an embodiment of this application;

[0056] like Figure 1 As shown, the flash memory device 100 includes a connector 101, a storage control chip 102, other peripheral units 103, a cache unit 104, and a flash memory medium 105.

[0057] The connector 101 connects the storage control chip 102 to the host for communication, such as a computer or server. The storage control chip 102 connects the connector 101, other peripheral units 103, cache unit 104, and flash memory medium 105, and serves as a control and processing unit to manage the internal system of the flash memory device. The storage control chip 102 includes, but is not limited to, a solid-state drive controller. The peripheral units 103 connect to the storage control chip 102 and include components such as serial ports, sensors, registers, and power chips. The cache unit 104 connects to the storage control chip 102 and serves as a cache and algorithm table storage unit. The cache unit 104 is generally a dynamic random access memory (DRAM).

[0058] The flash memory medium 105, serving as the storage medium of the flash memory device 100, is also known as flash memory, Flash, Flash storage, or Flash chip. It acts as a storage unit for storing user data, system data, etc. Multiple channels connect the storage control chip 102 and the flash memory medium 105, with each channel independently connected to one flash memory medium. For example, channel 0 connects to one flash memory medium, channel 1 connects to one flash memory medium, and so on, with channel x connecting to one flash memory medium.

[0059] In this application embodiment, the flash memory device includes, but is not limited to, a solid-state drive (SSD). The SSD includes an SSD controller and flash memory. The SSD controller mainly includes a main controller and firmware. Read / write performance and performance stability have always been important indicators for SSDs.

[0060] Currently, firmware manages data on the host side and schedules commands for the flash memory, completing the writing of data from the host to the flash memory. The data writing process mainly consists of two parts: the host write command process and the flash write command process.

[0061] During the host write command process, the first step is as follows: The main controller receives the write command sent by the host and forwards it to the firmware. The second step is that, upon confirming that the write command meets the reception conditions, the firmware resends the write command to the main controller. After receiving the data, the main controller sends a data reception completion message to the firmware. The third step is that, after confirming that the main controller has completed data reception, the firmware constructs a flash write command and sends it to the main controller. During the flash write command process, the main controller, based on the flash write command, writes data from the specified Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) to the corresponding location in the flash memory.

[0062] During the host write command process, the firmware and the main controller need to perform three interactive operations, including: the firmware receiving the write command sent by the main controller, the firmware resending the write command to the main controller, and the main controller sending a data reception completion message to the firmware. The frequent interactive operations between the main controller and the firmware will cause write latency, which will lead to a decrease in the write performance of the flash memory device and a deterioration in performance stability.

[0063] Based on this, embodiments of this application provide a hardware data management system. On the one hand, by having the hardware data management system interact with the host during the host write command process, the interaction between the main controller and the firmware is reduced, write latency is lowered, and the write performance of the flash memory device is improved. On the other hand, by having the hardware data management system perform storage operations and edit valid bitmap instructions based on whether the same logical block address is stored internally, and send valid bitmap instructions to the firmware to indicate whether the firmware should send a flash write command, this application can reduce the latency of writing multiple data corresponding to the same logical block address into the flash memory and improve the write performance of the flash memory device.

[0064] Please see Figure 2 , Figure 2 This is a schematic diagram of the structure of a hardware data management system provided in an embodiment of this application;

[0065] In this embodiment, the hardware data management system is applied to a flash memory device, which is connected to a host communication device. The flash memory device includes firmware and flash memory media.

[0066] like Figure 2 As shown, the hardware data management system 200 includes a host processing module 201 and a data processing module 202. The host processing module 201 and the data processing module 202 are communicatively connected.

[0067] The host processing module 201 is used to obtain the write command sent by the host and send the data acquisition command to the host, so as to receive the first logical block address and data corresponding to the data acquisition command sent by the host.

[0068] The data processing module 202 is used to perform storage operations on the data and edit valid bitmap instructions based on whether the same logical block address is stored internally in the hardware data management system, thereby sending valid bitmap instructions to the firmware. The valid bitmap instructions instruct the firmware whether to send a flash write command to the hardware data management system, which instructs the hardware data management system to store the data in the flash memory medium.

[0069] Please see Figure 3 , Figure 3 This is a detailed structural diagram of a hardware data management system provided in an embodiment of this application;

[0070] like Figure 3 As shown, the hardware data management system 200 includes a host processing module 201, a data processing module 202, and a firmware processing module 203. The data processing module 202 is communicatively connected to both the host processing module 201 and the firmware processing module 203.

[0071] The hardware data management system 200 also includes a cache space (not shown in the figure), which is used to store logical block addresses and corresponding data, such as storing the first logical block address and the data to be written corresponding to the first logical block address.

[0072] The host processing module 201 is used to obtain the write command sent by the host and send the data acquisition command to the host, so as to receive the first logical block address and data corresponding to the data acquisition command sent by the host.

[0073] The write command includes the Start Logical Block Address (SLBA) and the address length (LBA_Length). The Start Logical Block Address is the starting position of the logical block to be written to, and the address length is the address range of the logical blocks to be written to starting from the Start Logical Block Address. The first logical block address is any logical block address (LBA) within the address length starting from the Start Logical Block Address.

[0074] The data acquisition command is used to instruct the host to send the data corresponding to the logical block address to the hardware data management system. The data acquisition command includes a first command or a second command. The first command is used to instruct the host to send the data corresponding to several first logical block addresses as a whole to the hardware data management system. The second command is used to instruct the host to send the data corresponding to several first logical block addresses in segments to the hardware data management system.

[0075] In this embodiment of the application, the host processing module 201 is specifically used for: receiving a write command sent by the host; determining the size of the free space in the cache space; if the size of the free space is greater than or equal to the address length, sending a first command to the host; if the size of the free space is less than the address length, sending a second command to the host according to the size of the free space.

[0076] Specifically, the host processing module 201 receives the write command sent by the host and determines the size of the free space in the cache space. The free space refers to the storage space in the cache space that is currently idle. This free space can be used to store the data to be written corresponding to the address of the first logical block. It is understandable that the hardware data management system manages the cache space in a fragmented manner. When a storage space in the cache space is released, the size of the free space may not immediately increase. Therefore, the hardware data management system supports retrieving data in segments based on the write command sent by the host.

[0077] Specifically, if the size of the free space is greater than or equal to the address length, the host processing module 201 requests a storage space of the address length from the cache space to store the data sent by the host later, and sends a first command to the host so that the host sends the data corresponding to several first logical block addresses to the hardware data management system 200 as a whole.

[0078] If the size of the free space is less than the address length, the host processing module 201 determines the amount of data that the free space can store based on the size of the free space, and sends a second command to the host, so that the host sends the data corresponding to several first logical block addresses in segments to the hardware data management system 200. The second command includes the amount of data that the free space can store, and the host sends the corresponding amount of data to the hardware data management system 200 in segments based on this amount.

[0079] Furthermore, the host processing module 201 receives each first logical block address and the corresponding data (i.e., the data to be written) sent by the host, and stores the data in the cache space. It then establishes a mapping relationship between each first logical block address and the corresponding data location in the cache space using a hash algorithm, and stores this mapping relationship in a hash table. The hash table is stored in the cache space, and the hash algorithm includes, but is not limited to, the Cuckoo Hashing Algorithm. The Cuckoo Hashing Algorithm is an algorithm used to implement hash tables. Its basic idea is to use two hash tables to store data, each hash table consisting of a set of hash functions and a fixed-size array.

[0080] Understandably, as host storage space increases, the range of LBAs also expands, requiring a significant amount of space for direct LBA search and matching. Therefore, this application, based on the idea of ​​trading less computation for greater space, employs a hash algorithm to process LBAs, including three processing methods: LBA insertion, LBA lookup, and LBA deletion.

[0081] The data processing module 202 is used to perform storage operations on the data and edit valid bitmap instructions based on whether the same logical block address is stored inside the hardware data management system, thereby sending valid bitmap instructions to the firmware.

[0082] The valid bitmap instruction includes a starting logical block address, an address length, and valid bitmap parameters. Each valid bit of the valid bitmap parameters corresponds to a first logical block address. Each valid bit of the valid bitmap parameters indicates whether the corresponding first logical block address needs to undergo a flash write operation. Each valid bit of the valid bitmap parameters can be set to a first value or a second value. The first value indicates that the corresponding first logical block address needs to undergo a flash write operation, and the second value indicates that the corresponding first logical block address does not need to undergo a flash write operation. For example, the first value is 1, and the second value is 0.

[0083] Specifically, after the host processing module 201 receives any first logical block address and corresponding data, the first logical block address and corresponding data can exist in three states within the hardware data management system 200, as follows:

[0084] The first scenario: There are no identical logical block addresses within the hardware data management system 200.

[0085] The second scenario is that the hardware data management system 200 contains a second logical block address that is the same as the first logical block address, and the second logical block address does not have a flash memory write status flag.

[0086] The third scenario: The hardware data management system 200 contains a second logical block address that is identical to the first logical block address, and the second logical block address has a flash write status flag. The flash write status flag indicates that a flash write operation is in progress at the logical block address, and the second logical block address is the logical block address stored in the cache space before the host processing module 201 receives the first logical block address.

[0087] Based on this, the data processing module 202 performs corresponding storage operations on the data corresponding to the first logical block address and edits the valid bitmap instruction according to whether the same logical block address is stored inside the hardware data management system, thereby sending the valid bitmap instruction to the firmware to indicate whether the firmware sends a flash write command to the hardware data management system.

[0088] In this embodiment of the application, when the data granularity of the first logical block address is the same as the granularity of the smallest unit of the flash memory device, the data processing module 202 is specifically used to: based on the hash algorithm, search for the second logical block address stored in the cache space using each first logical block address as a key to determine whether there is a common logical block address in the cache space; when a certain first logical block address is different from all the second logical block addresses stored in the cache space, store the first logical block address and the corresponding data in the cache space, and set the corresponding bit of the first logical block address in the valid bitmap parameter to a first value.

[0089] Specifically, when the data granularity of the first logical block address and the granularity of the smallest unit of the flash memory device are both 4K, the data processing module 202, based on the Cuckoo Hash algorithm, searches the hash table in the cache space for the addresses of the second logical blocks stored in the hash table, using each first logical block address as a key. If the data processing module 202 finds a second logical block address in the hash table that is identical to a first logical block address, then the data processing module 202 determines that the same logical block address exists in the cache space; if the data processing module 202 does not find a second logical block address in the hash table that is identical to a first logical block address, then the data processing module 202 determines that the same logical block address does not exist in the cache space.

[0090] Furthermore, if the data processing module 202 determines that there are no identical logical block addresses in the cache space, that is, a certain first logical block address is different from the second logical block address stored in the cache space, the data processing module 202 stores the first logical block address and the corresponding data in the cache space, and sets the corresponding bit of the first logical block address in the valid bitmap parameter to a first value. For example, the corresponding bit of the first logical block address in the valid bitmap parameter is set to 1 to indicate that the first logical block address needs to be flash written.

[0091] If the data processing module 202 determines that there are identical logical block addresses in the cache space, that is, a certain first logical block address is the same as a certain second logical block address stored in the cache space, the data processing module 202 performs corresponding storage operations on the data corresponding to the first logical block address and edits the valid bitmap instructions according to whether the second logical block address has a flash write status flag.

[0092] In this embodiment of the application, the data processing module 202 is further configured to: when a first logical block address is the same as a second logical block address stored in the cache space, and the second logical block address does not have a flash write status flag, replace the data corresponding to the first logical block address with the data corresponding to the second logical block address stored in the cache space; and set the corresponding bit of the first logical block address in the valid bitmap parameter to a second value.

[0093] Specifically, when a first logical block address is identical to a second logical block address stored in the cache space, and the second logical block address does not have a flash write status flag, the data processing module 202 replaces the data corresponding to the second logical block address stored in the cache space with the data corresponding to the first logical block address, and sets the corresponding bit in the valid bitmap parameter of the first logical block address to a second value. For example, setting the corresponding bit in the valid bitmap parameter of the first logical block address to 0 indicates that the first logical block address does not need to undergo a flash write operation. It can be understood that when the hardware data management system is performing a flash write operation on the data corresponding to a certain logical block address, the hardware data management system will set a flash write status flag for that logical block address.

[0094] In this embodiment of the application, the data processing module 202 is further configured to: when a first logical block address is the same as a second logical block address stored in the cache space, and the second logical block address has a flash write status flag, store the data corresponding to the first logical block address in the backup location in the cache space; and set the corresponding bit of the first logical block address in the valid bitmap parameter to a first value.

[0095] Specifically, when a first logical block address is identical to a second logical block address stored in the cache space, and the second logical block address has a flash write status flag, the data processing module 202 stores the data corresponding to the first logical block address in a backup location within the cache space, and sets the corresponding bit of the first logical block address in the valid bitmap parameters to a first value. For example, setting the corresponding bit of the first logical block address in the valid bitmap parameters to 1 indicates that the first logical block address needs to undergo a flash write operation. It is understood that since the cache space is based on fragmented management, the backup location within the cache space can be located at any storage location in the free space. For example, the backup location can be adjacent to the storage location of the data corresponding to the second logical block address; this embodiment does not impose any restrictions on this.

[0096] Furthermore, for each first logical block address included in a write command issued by the host, the data processing module 202 determines whether the same logical block address is stored in the internal hardware data management system, thereby performing corresponding storage operations on the data corresponding to the first logical block address, and setting the corresponding bit of each first logical block address in the valid bitmap parameter, until each valid bit of the valid bitmap parameter corresponding to the write command is set, and then sends a valid bitmap instruction to the firmware.

[0097] Please see Figure 4 , Figure 4 This is a schematic diagram of a write command sent by a host according to an embodiment of this application;

[0098] like Figure 4 As shown, the host sequentially sends write command 1, write command 2, and write command 3 to the hardware data management system. Specifically, in write command 1, each first logical block address is logical block address 0 (LBA0), logical block address 1 (LBA1), logical block address 2 (LBA2), and logical block address 3 (LBA3); in write command 2, each first logical block address is logical block address 2 (LBA2), logical block address 3 (LBA3), logical block address 4 (LBA4), and logical block address 5 (LBA5); and in write command 3, each first logical block address is logical block address 4 (LBA4), logical block address 5 (LBA5), logical block address 6 (LBA6), and logical block address 7 (LBA7).

[0099] Wherein, when the data granularity of the first logical block address is the same as the granularity of the smallest unit of the flash memory device, that is, the data granularity of the first logical block address and the granularity of the smallest unit of the flash memory device are both 4K.

[0100] exist Figure 4 The data granularity of each first logical block address in write commands 1-3 is 4K, which is the same as the granularity of the smallest unit of the flash memory device, 4K.

[0101] After write command 1 is issued, data processing module 202 sequentially determines that there is no second logical block address in the cache space that is the same as LBA0, LBA1, LBA2, and LBA3. It then stores the data corresponding to LBA0, LBA1, LBA2, and LBA3 in the cache space and sets the corresponding bits of the valid bitmap parameters of LBA0, LBA1, LBA2, and LBA3 to 1, indicating that LBA0, LBA1, LBA2, and LBA3 all need to undergo flash write operations. Then, data processing module 202 sends a valid bitmap instruction to the firmware to inform the firmware that data reception of write command 1 is complete and to instruct that LBA0, LBA1, LBA2, and LBA3 in write command 1 all need to undergo flash write operations. The starting logical block address in this valid bitmap instruction is LBA0, the address length is 4, and the valid bitmap parameter is 4'b1111.

[0102] Understandably, the valid bitmap parameter `valid_bit_map = n'bABCD`, where `n` represents the address length, i.e., the number of first logical block addresses in a write command, and `A`, `B`, `C`, and `D` represent valid bits. `D`, `C`, `B`, and `A` sequentially correspond to each first logical block address starting from the initial logical block address in the write command. For example, for write command 1, `D`, `C`, `B`, and `A` correspond to `LBA0`, `LBA1`, `LBA2`, and `LBA3`, respectively.

[0103] Furthermore, after receiving the valid bitmap instruction of write command 1, the firmware determines that LBA0, LBA1, LBA2, and LBA3 in write command 1 all need to be written to the flash memory, and then sends the flash memory write commands corresponding to LBA0, LBA1, LBA2, and LBA3 to the hardware data management system in sequence.

[0104] After write command 2 is issued, since the hardware data management system has already processed write command 1, the data processing module 202 determines, based on the hash algorithm, that there is a second logical block address in the cache space that is the same as LBA2 and LBA3 in write command 2. When neither of these two second logical block addresses has a flash write status flag, the data processing module 202 replaces the data corresponding to these two second logical block addresses with the data corresponding to LBA2 and LBA3 in write command 2, and sets the corresponding bits of LBA2 and LBA3 in the valid bitmap parameters to 0.

[0105] Simultaneously, the data processing module 202 determines, based on a hash algorithm, that there are no logical block addresses in the cache space that are identical to LBA4 and LBA5 in write command 2. It then stores the data corresponding to LBA4 and LBA5 in the cache space and sets the corresponding bits of the valid bitmap parameters for LBA4 and LBA5 to 1. Next, the data processing module 202 sends a valid bitmap instruction to the firmware to inform it that data reception for write command 2 has ended and to instruct that LBA2 and LBA3 in write command 2 do not require flash write operations, while LBA4 and LBA5 do. The starting logical block address in this valid bitmap instruction is LBA2, the address length is 4, and the valid bitmap parameter is 4'b1100. For write command 2, D, C, B, and A in the valid bitmap parameter (n'bABCD) correspond to LBA2, LBA3, LBA4, and LBA5, respectively.

[0106] Furthermore, after receiving the valid bitmap instruction of write command 2, the firmware determines that LBA2 and LBA3 in write command 2 do not require flash write operations, while LBA4 and LBA5 do require flash write operations. Therefore, it sequentially sends the corresponding flash write commands for LBA4 and LBA5 to the hardware data management system. It is understandable that for the first logical block address that does not require flash write operations, the firmware does not send the corresponding flash write command to the hardware data management system.

[0107] After write command 3 is issued, since the hardware data management system has already processed write command 2, the data processing module 202 determines, based on the hash algorithm, that there is a second logical block address in the cache space that is the same as LBA4 and LBA5 in write command 3. When neither of these two second logical block addresses has a flash write status flag, the data processing module 202 replaces the data corresponding to these two second logical block addresses with the data corresponding to LBA4 and LBA5 in write command 3, and sets the corresponding bits of LBA4 and LBA5 in the valid bitmap parameters to 0.

[0108] Simultaneously, the data processing module 202 determines, based on a hash algorithm, that there are no logical block addresses in the cache space that are identical to LBA6 and LBA7 in write command 3, and sets the corresponding bits of the valid bitmap parameters for LBA6 and LBA7 to 1. Then, the data processing module 202 sends a valid bitmap instruction to the firmware to inform it that data reception for write command 3 has ended, and instructs that LBA4 and LBA5 in write command 3 do not require flash write operations, while LBA6 and LBA7 do. The starting logical block address in this valid bitmap instruction is LBA4, the address length is 4, and the valid bitmap parameter is 4'b1100. For write command 3, D, C, B, and A in the valid bitmap parameter (n'bABCD) correspond to LBA4, LBA5, LBA6, and LBA7 respectively.

[0109] Furthermore, after receiving the valid bitmap instruction of write command 3, the firmware determines that LBA4 and LBA5 in write command 3 do not need to be written to the flash memory, while LBA6 and LBA7 need to be written to the flash memory. Therefore, it sends the flash memory write commands corresponding to LBA6 and LBA7 to the hardware data management system in sequence.

[0110] Please see Figure 5 , Figure 5 This is a schematic diagram illustrating the storage of data in a hardware data management system according to an embodiment of this application;

[0111] Figure 5 This indicates that the hardware data management system received... Figure 4 The diagram shows the storage of the data corresponding to the first logical block address in the write commands 1-3 in the cache space of the hardware data management system, obtained by processing according to the above method.

[0112] like Figure 5 As shown, the hardware data management system stores only one corresponding data for each logical block address. Specifically, D_LBA0 represents the data corresponding to LBA0, D_LBA1 represents the data corresponding to LBA1, D_LBA2 represents the data corresponding to LBA2, D_LBA3 represents the data corresponding to LBA3, D_LBA4 represents the data corresponding to LBA4, D_LBA5 represents the data corresponding to LBA5, D_LBA6 represents the data corresponding to LBA6, and D_LBA7 represents the data corresponding to LBA7.

[0113] Please see Figure 6 , Figure 6 This is a schematic diagram of a flash memory write command sent by firmware according to an embodiment of this application;

[0114] Figure 6 This indicates that the hardware data management system processes data in the manner described above. Figure 4 The diagram illustrates the several flash memory write commands sent by the firmware to the hardware data management system during write commands 1-3.

[0115] like Figure 6 As shown, the firmware sends flash write commands corresponding to LBA0, LBA1, LBA2, LBA3, LBA4, LBA5, LBA6, and LBA7 to the hardware data management system in sequence.

[0116] Therefore, the hardware data management system will only receive flash write commands corresponding to LBA0, LBA1, LBA2, LBA3, LBA4, LBA5, LBA6, and LBA7, for a total of 8 flash write commands. Compared to the existing solution where the main controller needs to receive flash write commands corresponding to LBA0, LBA1, LBA2, and LBA3 in write command 1, LBA2, LBA3, LBA4, and LBA5 in write command 2, and LBA4, LBA5, LBA6, and LBA7 in write command 3, for a total of 12 flash write commands, this application can reduce the number of flash write commands when the same logical block address exists in multiple write commands sent by the host. Furthermore, the hardware data management system can subsequently write the latest data corresponding to the logical block address to the corresponding location in the flash memory, thereby reducing write latency.

[0117] Please see Figure 7 , Figure 7 This is a schematic diagram illustrating another way data is stored in a hardware data management system, as provided in an embodiment of this application.

[0118] Specifically, when the hardware data management system receives... Figure 4 After write command 1, the data processing module 202 sequentially determines that there is no second logical block address in the cache space that is the same as LBA0, LBA1, LBA2, and LBA3. It then stores the data corresponding to LBA0, LBA1, LBA2, and LBA3 in the cache space and sets the valid bitmap parameter to 4'b1111. This sends a valid bitmap instruction to the firmware to indicate that LBA0, LBA1, LBA2, and LBA3 in firmware write command 1 all need to be written to the flash memory.

[0119] Received in the hardware data management system Figure 4After write command 2, since the hardware data management system has already processed write command 1, the data processing module 202 determines, based on the hash algorithm, that there is a second logical block address in the cache space that is the same as LBA2 and LBA3 in write command 2. When both of these second logical block addresses have flash write status flags, the data processing module 202 stores the data corresponding to LBA2 and LBA3 in write command 2 to the backup location in the cache space, and sets the corresponding bits of LBA2 and LBA3 in the valid bitmap parameters to 1.

[0120] Meanwhile, the data processing module 202 determines, based on a hash algorithm, that there is no logical block address in the cache space that is the same as LBA4 and LBA5 in write command 2. It sets the corresponding bits of LBA4 and LBA5 in the valid bitmap parameters to 1. At this time, the valid bitmap parameter is 4'b1111. Thus, the data processing module 202 sends a valid bitmap instruction to the firmware to indicate that LBA2, LBA3, LBA4 and LBA5 in firmware write command 2 all need to be written to the flash memory.

[0121] Received in the hardware data management system Figure 4 After write command 3, since the hardware data management system has already processed write command 2, the data processing module 202 determines, based on the hash algorithm, that there is a second logical block address in the cache space that is the same as LBA4 and LBA5 in write command 3. When both of these second logical block addresses have flash write status flags, the data processing module 202 stores the data corresponding to LBA4 and LBA5 in write command 3 to the backup location in the cache space, and sets the corresponding bits of LBA4 and LBA5 in the valid bitmap parameters to 1.

[0122] Meanwhile, the data processing module 202 determines, based on a hash algorithm, that there is no logical block address in the cache space that is the same as LBA6 and LBA7 in write command 3. It then stores the data corresponding to LBA6 and LBA7 in the cache space and sets the corresponding bits of LBA6 and LBA7 in the valid bitmap parameters to 1. At this time, the valid bitmap parameter is 4'b1111. Thus, the data processing module 202 sends a valid bitmap instruction to the firmware to indicate that LBA4, LBA5, LBA6, and LBA7 in firmware write command 3 all need to be written to the flash memory.

[0123] like Figure 7 As shown, in this case, the hardware data management system will store the data corresponding to each logical block address in write command 1 to write command 3 into the cache space.

[0124] Wherein, D_LBA0 represents the data corresponding to LBA0 in command 1, D_LBA1 represents the data corresponding to LBA1 in command 1, D_LBA2 represents the data corresponding to LBA2 in command 1, D_LBA2' represents the data corresponding to LBA2 in command 2, D_LBA3 represents the data corresponding to LBA3 in command 1, D_LBA3' represents the data corresponding to LBA3 in command 2, D_LBA4 represents the data corresponding to LBA4 in command 2, D_LBA4' represents the data corresponding to LBA4 in command 3, D_LBA5 represents the data corresponding to LBA5 in command 2, D_LBA5' represents the data corresponding to LBA5 in command 3, D_LBA6 represents the data corresponding to LBA6 in command 3, and D_LBA7 represents the data corresponding to LBA7 in command 3.

[0125] Please see Figure 8 , Figure 8 This is a schematic diagram of another flash write command sent by firmware according to an embodiment of this application;

[0126] Figure 8 This indicates that in the hardware data management system according to Figure 7 This diagram illustrates several flash write commands sent by the firmware to the hardware data management system when storing data in this manner.

[0127] like Figure 8 As shown, the firmware sequentially sends the flash write command corresponding to LBA0 in command 1, the flash write command corresponding to LBA1 in command 1, the flash write command corresponding to LBA2 in command 1, the flash write command corresponding to LBA3 in command 1, and the flash write command corresponding to LBA2 in command 2 to the hardware data management system. Figure 8 LBA2' in command 2 and the flash write command corresponding to LBA3 in command 2 ( Figure 8 LBA3' in command 2), the flash write command corresponding to LBA4 in command 2, the flash write command corresponding to LBA5 in command 2, and the flash write command corresponding to LBA4 in command 3 ( Figure 8 LBA4' in command 3 and the flash write command corresponding to LBA5 in command 3 ( Figure 8 LBA5' in command 3), LBA6 in command 3 corresponds to the flash write command, and LBA7 in command 3 corresponds to the flash write command.

[0128] In some embodiments, when the data granularity of the first logical block address is different from the granularity of the smallest unit of the flash memory device, the data processing module 202 is used to: obtain valid sector parameters; determine the data granularity of the current write command based on the valid sector parameters; when a first logical block address is different from all logical block addresses stored in the cache space, and at least one bit in the valid sector parameters is a second value, store the first logical block address and the corresponding data in the cache space, and set each valid bit of the valid bitmap parameter to the second value; and send the valid bitmap parameters and the data granularity of the current write command to the firmware.

[0129] Specifically, when the data granularity of the first logical block address is 512B and the granularity of the smallest cell in the flash memory device is 4K, the data granularity of the first logical block address is different from the granularity of the smallest cell in the flash memory device. Figure 4 LBA0, LBA1, LBA2, LBA3, LBA4, LBA5, LBA6, and LBA7 belong to the eight sub-units of LBA0, which has a data granularity of 4K.

[0130] When the hardware data management system receives the first logical block address (512B) and corresponding data sent by the host, the data processing module 202 obtains the valid sector parameters sent by the non-volatile memory fast storage module (NVMe module) and determines the data granularity of the current write command based on the valid sector parameters. The valid sector parameters indicate whether several logical block addresses in the current write command constitute a complete 4KB block, and each valid bit of the valid sector parameters indicates whether the corresponding logical block address has been obtained.

[0131] Understandably, during the process of the host sending data to the hardware data management system, it passes through the NVMe module. The NVMe module sends the valid sector parameters corresponding to the current write command to the hardware data management system. The valid sector parameter `sector_valid` = `N'bABCD_EFGH`, where `N` represents the quotient of the granularity of the smallest cell of the flash memory device and the data granularity of the first logical block address. For example, if the data granularity of the first logical block address is 512B and the granularity of the smallest cell of the flash memory device is 4K, then `N = 8`. `ABCD_EFGH` corresponds to the 8 partial cells of LBA0 with a data granularity of 4K, i.e., the valid bits. `H`, `G`, `F`, `E`, `D`, `C`, `B`, and `A` correspond to LBA0, LBA1, LBA2, LBA3, LBA4, LBA5, LBA6, and LBA7 of 512B, respectively. The data granularity of the write command is the product of the data granularity of the first logical block address and the number of first logical block addresses.

[0132] For example: when the hardware data management system receives... Figure 4When writing data corresponding to write command 1, the data processing module 202 simultaneously obtains the valid sector parameters sent by the NVMe module. Since write command 1 only includes LBA0, LBA1, LBA2, and LBA3 of 512B, the valid sector parameter is 8'b0000_1111, indicating that only LBA0, LBA1, LBA2, and LBA3 of 512B are obtained, and the data granularity of the write command is 512B*4.

[0133] Furthermore, the data processing module 202 uses the Cuckoo Hash algorithm to query whether the hardware data management system stores a second logical block address that is the same as a certain first logical block address.

[0134] If a first logical block address is different from the second logical block address stored in the cache space, and at least one bit in the valid sector parameters is the second value, then the data processing module 202 stores the first logical block address and the corresponding data in the cache space, and sets each valid bit of the valid bitmap parameter to the second value. After setting each valid bit in the valid bitmap parameter corresponding to a write command, the data processing module 202 sends the valid bitmap parameter and the data granularity of the current write command to the firmware to inform the firmware that the data reception of the current write command has ended and instruct the firmware to perform subsequent operations.

[0135] For example: in Figure 4 After write command 1 is issued, data processing module 202 sequentially determines that there is no second logical block address in the cache space that is the same as LBA0, LBA1, LBA2, and LBA3 in write command 1, stores the data corresponding to LBA0, LBA1, LBA2, and LBA3 in the cache space, and sets the valid bitmap parameter corresponding to write command 1 to 4'b0000.

[0136] Understandably, when not all eight partial units of the 4K LBA have been received and the 4K LBA0 cannot be formed, the data processing module 202 will set the valid bitmap parameters of the current write command to 4'b0000 to indicate that each first logical block address in the current write command of the firmware does not need to be written to the flash memory.

[0137] Furthermore, the firmware receives the valid bitmap parameters and the data granularity of the current write command sent by the data processing module 202. If each valid bit in the valid bitmap parameters is a second value, for example, each valid bit is 0, then the firmware determines not to send a flash write command to the hardware data management system.

[0138] Simultaneously, the firmware sends a fill read command to the hardware data management system based on the valid bitmap parameters and the data granularity of the current write command. This fill read command instructs the hardware data management system to read data from the flash memory medium.

[0139] For example: Figure 4 The valid bitmap parameter corresponding to write command 1 is 4'b0000, which only contains four 512B LBA0, LBA1, LBA2, and LBA3, lacking LBA4-LBA7. Therefore, it cannot form a 4K data granularity LBA0. In this case, the data corresponding to the 4K data granularity LBA0 needs to be read from the flash memory and merged with the data corresponding to the 512B LBA0-LBA3 to obtain a complete 4K data set, which is then written to the flash memory. Therefore, after determining that the four 512B LBA0-LBA3 in write command 1 cannot form a 4K data granularity LBA0, the firmware sends a fill read command to the hardware data management system, causing the hardware data management system to read the data corresponding to the 4K data granularity LBA0 from the flash memory.

[0140] In some embodiments, when the data granularity of the first logical block address is different from the granularity of the smallest unit of the flash memory device, the data processing module 202 is further configured to: replace the data corresponding to the second logical block address stored in the cache space with the data corresponding to the first logical block address when a certain first logical block address is the same as the second logical block address stored in the cache space, and at least one bit in the valid sector parameter is a second value; and set each valid bit of the valid bitmap parameter to the second value.

[0141] Specifically, when a first logical block address is the same as a second logical block address stored in the cache space, and at least one bit in the valid sector parameter is a second value, the data processing module 202 replaces the data corresponding to the second logical block address stored in the cache space with the data corresponding to the first logical block address, and sets each valid bit of the valid bitmap parameter to the second value.

[0142] For example: in Figure 4 After write command 2 is issued, the data processing module 202 receives the valid sector parameter 8'b0011_1111, indicating that LBA0-LBA5 of 512B have been acquired. Since the hardware data management system has already processed write command 1, the data processing module 202 determines, based on a hash algorithm, that there is a second logical block address in the cache space that is the same as LBA2 and LBA3 in write command 2, and that at least one bit in the valid sector parameter is 0. The data processing module 202 then replaces the data corresponding to these two second logical block addresses with the data corresponding to LBA2 and LBA3 in write command 2.

[0143] Simultaneously, the data processing module 202 determines, based on a hash algorithm, that there are no logical block addresses in the cache space that are identical to LBA4 and LBA5 in write command 2. It then stores the data corresponding to LBA4 and LBA5 in the cache space and sets the valid bitmap parameter corresponding to write command 2 to 4'b0000. Therefore, after receiving the valid bitmap parameter corresponding to write command 2 from the data processing module 202, the firmware does not send a flash memory write command to the hardware data management system.

[0144] In some embodiments, when the data granularity of the first logical block address is different from the granularity of the smallest unit of the flash memory device, the data processing module 202 is further configured to: set the last bit of the valid bitmap parameter to the first value when every bit in the valid sector parameter is a first value; send the valid bitmap parameter and the data granularity of the current write command to the firmware so that the firmware sends a flash write command to the hardware data management system.

[0145] Specifically, when the host sends out all eight partial units LBA0-LBA7 of LBA0 with a data granularity of 4K through multiple write commands, the NVMe module determines that the valid sector parameter at this time is 8'b1111_1111, and sends the valid sector parameter to the hardware data management system.

[0146] After receiving the first logical block address and data sent by the host and the valid sector parameters sent by the NVMe module, the data processing module 202 queries whether the hardware data management system stores a second logical block address that is the same as a certain first logical block address. If a certain first logical block address is different from the second logical block address stored in the cache space, and each valid bit in the valid sector parameter is a first value, then the data processing module 202 stores the first logical block address and its corresponding data in the cache space; if a certain first logical block address is the same as the second logical block address stored in the cache space, and each valid bit in the valid sector parameter is a first value, then the data processing module 202 replaces the data corresponding to the second logical block address stored in the cache space with the data corresponding to the first logical block address.

[0147] Then, the data processing module 202 sets the last bit of the valid bitmap parameter to the first value and sends the valid bitmap parameter and the data granularity of the current write command to the firmware, so that the firmware sends the flash write command to the hardware data management system.

[0148] For example: in Figure 4After write command 3 is issued, the data processing module 202 receives the valid sector parameter 8'b1111_1111, indicating that LBA0-LBA7 of 512B have been acquired. Since the hardware data management system has already processed write command 2, the data processing module 202 determines, based on a hash algorithm, that there are second logical block addresses in the cache space that are the same as LBA4 and LBA5 in write command 3. The data processing module 202 then replaces the data corresponding to these two second logical block addresses with the data corresponding to LBA4 and LBA5 in write command 3.

[0149] Simultaneously, the data processing module 202 determines, based on a hash algorithm, that there are no logical block addresses in the cache space that are identical to LBA6 and LBA7 in write command 3, and stores the data corresponding to LBA6 and LBA7 in the cache space. Then, the data processing module 202 sets the last bit of the valid bitmap parameter corresponding to write command 3 to the first value. At this time, the valid bitmap parameter is 4'b0001, and sends this valid bitmap parameter and the data granularity of the current write command to the firmware, so that the firmware sends the flash write command to the hardware data management system. It can be understood that the valid bitmap parameter of 4'b0001 indicates that LBA0 with a data granularity of 4K can be used for flash write operations. Only when the host sends out all 512B of LBA0-LBA7, combining them into a complete 4K, can the flash device perform flash write operations.

[0150] Please see Figure 9 , Figure 9 This is a schematic diagram illustrating another type of data storage in a hardware data management system provided in this application embodiment;

[0151] Figure 9 To address situations where the data granularity of the first logical block address differs from the granularity of the smallest unit in the flash memory device, the above method should be used. Figure 4 The diagram shows how the data obtained from writing commands 1-3 is stored in the hardware data management system.

[0152] like Figure 9 As shown, the data corresponding to LBA0-LBA7 of the 512B are all stored in the same data granularity, D_LBA0. D_LBA0 represents the data corresponding to LBA0 with a data granularity of 4K, which consists of LBA0-LBA7 of the 512B.

[0153] Please see Figure 10 , Figure 10 This is a schematic diagram of another firmware-sent flash write command provided in an embodiment of this application;

[0154] Figure 10 This indicates that in the hardware data management system according to Figure 9This diagram illustrates the flash write commands sent by the firmware to the hardware data management system when storing data in this manner.

[0155] like Figure 10 As shown, the firmware sends only one flash write command to the hardware data management system. This flash write command is the flash write command corresponding to LBA0 with a data granularity of 4K.

[0156] Furthermore, if the firmware has already issued a fill read command corresponding to LBA0 of 4K to the hardware data management system, the firmware needs to wait for the hardware data management system to complete the read operation before issuing the flash write command.

[0157] Firmware processing module 203 is used to: obtain flash write commands sent by the firmware, and write data into the flash medium according to the flash write commands.

[0158] In this embodiment, the firmware processing module 203 is specifically used for: obtaining a flash write command sent by the firmware; determining the storage location of data in the hardware data management system based on a hash algorithm and using the first logical block address as a key; writing the data from the storage location to the flash medium based on the target physical address; and sending a write flag to the firmware to update the mapping table between logical addresses and physical addresses.

[0159] The flash write command includes a first logical block address and a target physical address. The target physical address is the physical address in the flash medium where the data corresponding to the first logical block address needs to be written. The write flag is used to indicate that the current flash write command operation has been completed.

[0160] Specifically, the firmware processing module 203 receives the flash write command sent by the firmware and, based on a hash algorithm, uses the first logical block address in the flash write command as the key to query the mapping relationship between each first logical block address stored in the hash table and the corresponding data location in the cache space, thus determining the storage location of the data corresponding to the first logical block address in the cache space. Then, the firmware processing module 203 reads the data from the storage location in the cache space and writes it to the target physical address in the flash memory medium. After completing the write operation, the firmware processing module 203 sends a write marker to the firmware.

[0161] Accordingly, upon receiving the write flag, the firmware identifies the write flag, determines that the hardware data management system has completed the flash memory write operation, and updates the physical address corresponding to the first logical block address in the Logical address to Physical address (L2P) mapping table to the target physical address. Furthermore, the firmware sends a delete command to the hardware data management system, instructing the system to delete the mapping relationship between the first logical block address and the corresponding data location in the cache space stored in the hash table.

[0162] Furthermore, after receiving the deletion instruction, the hardware data management system deletes the mapping relationship between the address of the first logical block and the corresponding data location in the cache space stored in the hash table based on the hash algorithm.

[0163] In some embodiments, when the hardware data management system stores both first data and second data corresponding to the first logical block address, the firmware processing module 203 is configured to: write the first data corresponding to the first logical block address into the flash memory medium after writing the first data corresponding to the first logical block address into the flash memory medium.

[0164] Specifically, the first data and the second data correspond to different write commands, for example: Figure 7 The hardware data management system stores both D_LBA3 and D_LBA3'. D_LBA3 is the first data corresponding to the first logical block address LBA3 in write command 1, and D_LBA3' is the second data corresponding to the first logical block address LBA3 in write command 2.

[0165] When the firmware processing module 203 is preparing to write the second data D_LBA3' corresponding to LBA3 to the flash memory medium, it finds that the first data D_LBA3 corresponding to LBA3 is being written to the flash memory medium. Then, the firmware processing module 203 pauses the writing operation of D_LBA3', writes D_LBA3 to the flash memory medium, and then writes D_LBA3' to the flash memory medium.

[0166] In some embodiments, when the data granularity of the first logical block address is different from the granularity of the smallest unit of the flash memory device, the firmware processing module 203 is configured to: obtain a fill read command sent by the firmware; read data corresponding to the third logical block address from the flash memory medium according to the fill read command; obtain a flash write command sent by the firmware, and merge N data corresponding to the first logical block address and the data corresponding to the third logical block address according to the flash write command to obtain combined data; and write the combined data into the flash memory medium.

[0167] The fill read command includes the third logical block address and the physical address corresponding to the third logical block address. The data granularity of the third logical block address is the same as the granularity of the smallest unit of the flash memory device. The N first logical block addresses are part of the third logical block address.

[0168] Specifically, when the data granularity of the first logical block address differs from the granularity of the smallest unit of the flash memory device—for example, when the data granularity of the first logical block address is 512B and the granularity of the smallest unit of the flash memory device is 4K—the firmware processing module 203 obtains the fill read command sent by the firmware and reads the data corresponding to the third logical block address from the flash memory medium according to the physical address corresponding to the third logical block address in the fill read command. After obtaining the flash write command sent by the firmware, the firmware processing module 203 determines the storage location in the cache space of the N 512B data corresponding to the first logical block address contained in the third logical block address based on the third logical block address in the flash write command and a hash algorithm. It then merges the N 512B data corresponding to the first logical block address with the data corresponding to the third logical address to obtain combined data, and then writes the combined data to the target physical address in the flash memory medium.

[0169] For example: For Figure 4 In write command 1, after determining that the four 512B LBA0-LBA3 bytes in write command 1 cannot form an LBA0 with a data granularity of 4K, the firmware sends a fill read command to the hardware data management system. The fill read command includes the physical address corresponding to the LBA0 with a data granularity of 4K. The firmware processing module 203 reads the data corresponding to the LBA0 with a data granularity of 4K from the flash memory medium according to the physical address of the LBA0 with a data granularity of 4K.

[0170] After receiving the flash write command sent by the firmware, the firmware processing module 203 obtains the data corresponding to the four 512B LBA0-LBA3 contained in the 4K LBA0 according to the data granularity of the LBA0 in the flash write command. Then, it merges the data corresponding to the four 512B LBA0-LBA3 with the data corresponding to the 4K LBA0 to obtain combined data, and then writes the combined data to the target physical address in the flash memory medium.

[0171] In this embodiment, a hardware data management system is provided. This hardware data management system is applied to a flash memory device, which is communicatively connected to a host. The flash memory device includes firmware and a flash memory medium. The hardware data management system includes: a host processing module, used to acquire write commands sent by the host and send data acquisition commands to the host, to receive the first logical block address and data corresponding to the data acquisition commands sent by the host; and a data processing module, used to perform storage operations on the data and edit valid bitmap instructions according to whether the same logical block address is stored internally in the hardware data management system, thereby sending valid bitmap instructions to the firmware; wherein, the valid bitmap instructions are used to indicate whether the firmware sends a flash write command to the hardware data management system, and the flash write command is used to instruct the hardware data management system to store the data in the flash memory medium.

[0172] On the one hand, by acquiring the write command sent by the host through the hardware data management system, sending a data acquisition command to the host to receive the first logical block address and data sent by the host, and sending a valid bitmap instruction to the firmware, this application enables the hardware data management system to interact with the host during the host write command process. The firmware is only used to receive the valid bitmap instruction sent by the hardware data management system, thereby reducing the steps of the firmware receiving the write command sent by the host controller, re-issuing the write command to the host controller, and receiving the data reception completion information sent by the host. That is, it reduces the interaction between the host controller and the firmware, reduces write latency, and thus improves the write performance of the flash memory device.

[0173] On the other hand, compared to existing solutions, during the flash write command process, the firmware checks the write command field to determine if a duplicate write command is already in progress before constructing the write command. If a duplicate write command exists, the firmware pauses the current write command and waits for the previous write command to finish before continuing. When the host frequently issues the same write command, this can lead to increased write latency.

[0174] The hardware data management system performs storage operations and edits valid bitmap instructions based on whether the same logical block address is stored internally. It then sends valid bitmap instructions to the firmware to instruct the firmware whether to send a flash write command to the hardware data management system. This application eliminates the need for the firmware to check the write command field to determine if the same write command is in progress, thus reducing the firmware's command processing steps. Furthermore, when multiple write commands sent by the host contain the same logical block address, it reduces the latency of writing multiple data corresponding to the same logical block address to the flash memory, thereby improving the write performance of the flash memory device.

[0175] Please see Figure 11 , Figure 11This is a schematic diagram of the write command processing flow provided by an embodiment of this application when the data granularity of the first logical block address is the same as the granularity of the smallest unit of the flash memory device;

[0176] In this embodiment of the application, the data granularity of the first logical block address is 4K, and the granularity of the smallest unit of the flash memory device is 4K, so the data granularity of the two is the same.

[0177] like Figure 11 As shown, when the data granularity of the first logical block address is the same as the granularity of the smallest unit of the flash memory device, the write command processing flow includes:

[0178] Step S1101: The host sends a write command;

[0179] Specifically, host 151 sends a write command to hardware data management system 200. Correspondingly, hardware data management system 200 receives the write command and determines the size of the free space in the cache. If the size of the free space is greater than or equal to the address length in the write command, it requests storage space of the address length from the cache to store data subsequently sent by the host. If the size of the free space is less than the address length, it determines the amount of data that the free space can store based on the size of the free space.

[0180] Step S1102: The hardware data management system sends a data acquisition command;

[0181] Specifically, when the size of the free space is greater than or equal to the address length, the hardware data management system 200 sends a first command to the host 151, so that the host 151 sends the data corresponding to several first logical block addresses as a whole to the hardware data management system 200; when the size of the free space is less than the address length, the hardware data management system 200 sends a second command to the host 151, so that the host 151 sends the data corresponding to several first logical block addresses in segments to the hardware data management system 200.

[0182] Step S1103: The host sends data;

[0183] Specifically, in response to the data acquisition command sent by the hardware data management system 200, the host 151 sends the first logical block address and the corresponding data to the hardware data management system 200.

[0184] Accordingly, the hardware data management system 200 stores the data in the cache space, and performs storage operations and edits valid bitmap instructions on the data based on whether the same logical block address is stored inside the hardware data management system 200.

[0185] Step S1104: The hardware data management system sends a valid bitmap instruction;

[0186] Specifically, the hardware data management system 200 sends a valid bitmap instruction to the firmware 1021 to inform the firmware 1021 that the data reception of the current write command has ended, and to instruct the firmware 1021 whether to send a flash write command to the hardware data management system 200.

[0187] Step S1105: Firmware sends flash write command;

[0188] Specifically, firmware 1021 sends a flash write command to hardware data management system 200, wherein the flash write command includes the first logical block address and the target physical location.

[0189] Step S1106: The hardware data management system writes data to the flash memory medium;

[0190] Specifically, according to the flash write command, the hardware data management system 200 writes the data corresponding to the first logical block address from inside the hardware data management system 200 to the target physical location in the flash memory medium 105.

[0191] Step S1107: Flash write command completed.

[0192] Specifically, after the write operation is completed, the hardware data management system 200 sends a write flag to the firmware 1021 to indicate that the flash write command has been executed. Accordingly, the firmware recognizes the write flag and updates the mapping table between logical addresses and physical addresses.

[0193] Please see Figure 12 , Figure 12 This is a schematic diagram of the write command processing flow provided by an embodiment of this application when the data granularity of the first logical block address is different from the granularity of the smallest unit of the flash memory device;

[0194] In this embodiment of the application, the data granularity of the first logical block address is 512B, and the granularity of the smallest unit of the flash memory device is 4K, which are different data granularities.

[0195] like Figure 12 As shown, when the data granularity of the first logical block address differs from the granularity of the smallest unit of the flash memory device, the write command processing flow includes:

[0196] Step S1201: The host sends a write command;

[0197] Specifically, host 151 sends a write command to hardware data management system 200. Correspondingly, hardware data management system 200 receives the write command and determines the size of the free space in the cache. If the size of the free space is greater than or equal to the address length in the write command, it requests storage space of the address length from the cache to store data subsequently sent by host 151. If the size of the free space is less than the address length, it determines the amount of data that the free space can store based on the size of the free space.

[0198] Step S1202: The hardware data management system sends a data acquisition command;

[0199] Specifically, when the size of the free space is greater than or equal to the address length, the hardware data management system 200 sends a first command to the host 151, so that the host 151 sends the data corresponding to several first logical block addresses as a whole to the hardware data management system 200; when the size of the free space is less than the address length, the hardware data management system 200 sends a second command to the host 151, so that the host 151 sends the data corresponding to several first logical block addresses in segments to the hardware data management system 200.

[0200] Step S1203: The host sends data;

[0201] Specifically, in response to the data acquisition command sent by the hardware data management system 200, the host 151 sends the first logical block address and the corresponding data to the hardware data management system 200.

[0202] Accordingly, the hardware data management system 200 stores the data in the cache space, and performs storage operations and edits valid bitmap instructions on the data based on whether the same logical block address is stored inside the hardware data management system 200.

[0203] Step S1204: The hardware data management system sends instructions;

[0204] Specifically, the hardware data management system 200 sends an instruction to the firmware 1021, which includes valid bitmap parameters and the data granularity of the current write command, to inform the firmware 1021 that the data reception of the current write command has ended, and to instruct the firmware 1021 whether to send a fill read command or a flash write command to the hardware data management system 200.

[0205] Step S1205: Firmware sends a fill read command;

[0206] Specifically, firmware 1021 sends a fill read command to hardware data management system 200. The fill read command includes the third logical block address and the physical address corresponding to the third logical block address.

[0207] Step S1206: The hardware data management system reads the data;

[0208] Specifically, the hardware data management system 200 reads the data corresponding to the third logical block address from the flash memory medium 105 into the hardware data management system 200 according to the physical address corresponding to the third logical block address.

[0209] Step S1207: Data reading completed;

[0210] Specifically, after reading the data corresponding to the address of the third logical block, the hardware data management system 200 sends a read completion message to the firmware 1021. The read completion message indicates that the hardware data management system 200 has completed the data reading operation.

[0211] Step S1208: Firmware sends flash write command;

[0212] Specifically, firmware 1021 sends a flash write command to hardware data management system 200, wherein the flash write command includes the third logical block address and the target physical location.

[0213] Step S1209: The hardware data management system writes data to the flash memory medium;

[0214] Specifically, the hardware data management system 200 writes the data corresponding to the third logical block address from inside the hardware data management system 200 to the target physical location in the flash memory medium 105 according to the flash memory write command.

[0215] It is understandable that after each execution of step S1204, steps S1205-S1207 are not necessarily required. When the N first logical block addresses contained in the current write command cannot form a third logical block address with a data granularity of 4K, steps S1205-S1207 are required to read the data corresponding to the third logical block address from the flash memory medium, and then merge the data corresponding to the third logical block address with the data corresponding to the N first logical block addresses to obtain combined data. This combined data is then written to the target physical location in the flash memory medium.

[0216] Step S1210: Flash write command completed;

[0217] Specifically, after the write operation is completed, the hardware data management system 200 sends a write flag to the firmware 1021 to indicate that the flash write command has been executed. Accordingly, the firmware 1021 recognizes the write flag and updates the mapping table between logical addresses and physical addresses.

[0218] Please see Figure 13 , Figure 13 This is a schematic diagram of the structure of a storage control chip provided in an embodiment of this application;

[0219] like Figure 13 As shown, the storage control chip 102 includes a hardware data management system 200 and firmware 1021. The hardware data management system 200 and firmware 1021 are communicatively connected.

[0220] The hardware data management system 200 includes a host processing module 201 and a data processing module 202.

[0221] The host processing module 201 is used to obtain the write command sent by the host and send the data acquisition command to the host, so as to receive the first logical block address and data corresponding to the data acquisition command sent by the host.

[0222] The data processing module 202 is used to perform storage operations on the data and edit valid bitmap instructions based on whether the same logical block address is stored inside the hardware data management system, thereby sending valid bitmap instructions to the firmware.

[0223] In some embodiments, the hardware data management system 200 further includes a firmware processing module. The firmware processing module is configured to: acquire a flash write command sent by the firmware, and write data to the flash memory medium according to the flash write command.

[0224] Firmware 1021 connects to the hardware data management system 200 and is used to obtain valid bitmap instructions and send flash write commands to the hardware data management system 200.

[0225] In this application embodiment, a storage control chip is provided, which includes a hardware data management system and firmware. On the one hand, this application can reduce the interaction between the main controller and the firmware, thereby reducing write latency; on the other hand, this application can reduce the latency of writing multiple data corresponding to the same logical block address into the flash memory, thereby improving the write performance of the flash memory device.

[0226] For details, please refer to Figure 14 , Figure 14 This is a schematic diagram of another flash memory device provided in an embodiment of this application;

[0227] like Figure 14 As shown, the flash memory device 100 includes a storage controller chip 102 and at least one flash memory medium 105. Figure 14 Take a flash memory medium 105 as an example. The flash memory medium 105 is communicatively connected to the storage controller chip 102.

[0228] The storage control chip 102 is used to acquire write commands sent by the host, process the write commands, acquire data sent by the host, and store the data in the flash memory medium 105.

[0229] Flash memory medium 105 is used for storing data.

[0230] In this application embodiment, a flash memory device is provided, which includes a storage controller chip and at least one flash memory medium. This application can reduce write latency and improve the write performance of the flash memory device.

[0231] Please see Figure 15 , Figure 15 This is a schematic diagram of the structure of a data transmission system provided in an embodiment of this application;

[0232] like Figure 15 As shown, the data transmission system 150 includes a host 151 and a flash memory device 100. The host 151 and the flash memory device 100 are communicatively connected.

[0233] The host 151 is used to send write commands and data to the flash memory device 100.

[0234] Flash memory device 100 is used to store data according to write commands issued by host 151.

[0235] In this embodiment, a data transmission system is provided, comprising a host and a flash memory device. This application can reduce the latency of writing data sent by the host into the flash memory device and improve the write performance of the flash memory device.

[0236] Please see Figure 16 , Figure 16 This is a flowchart illustrating a write command processing method provided in an embodiment of this application;

[0237] The write command processing method is applied to a flash memory device that is communicatively connected to a host. The flash memory device includes a hardware data management system and firmware. The hardware data management system includes a host processing module, a data processing module, a firmware processing module, and a cache space.

[0238] like Figure 16 As shown, the write command processing method includes:

[0239] Step S1601: Obtain the write command sent by the host, and send a data acquisition command to the host;

[0240] Specifically, the host processing module obtains the write command sent by the host and determines the size of the free space in the cache. When the size of the free space is greater than or equal to the address length in the write command, the host processing module requests storage space of size equal to the address length from the cache to store the data subsequently sent by the host, and sends a first command to the host so that the host sends the data corresponding to several first logical block addresses as a whole to the hardware data management system.

[0241] When the size of the free space is less than the address length, the host processing module determines the amount of data that the free space can store based on the size of the free space, and sends a second command to the host so that the host sends the data corresponding to several first logical block addresses in segments to the hardware data management system.

[0242] Step S1602: Receive the first logical block address and data sent by the host;

[0243] Specifically, the data processing module receives the first logical block address and data sent by the host.

[0244] Step S1603: Perform a storage operation on the data according to the address of the first logical block.

[0245] Specifically, the data processing module performs storage operations on the data and edits the valid bitmap instruction based on whether the same logical block address is stored in the cache space, thereby sending the valid bitmap instruction to the firmware to instruct the firmware whether to send a flash write command to the hardware data management system.

[0246] When the data granularity of the first logical block address is the same as the granularity of the smallest unit of the flash memory device:

[0247] When a first logical block address is different from the second logical block address stored in the cache space, the data processing module stores the first logical block address and the corresponding data in the cache space, and sets the corresponding bit of the first logical block address in the valid bitmap parameter to the first value.

[0248] When a first logical block address is the same as a second logical block address stored in the cache space, and the second logical block address does not have a flash write status flag, the data processing module replaces the data corresponding to the second logical block address stored in the cache space with the data corresponding to the first logical block address, and sets the corresponding bit of the first logical block address in the valid bitmap parameter to the second value.

[0249] When a first logical block address is the same as a second logical block address stored in the cache space, and the second logical block address has a flash write status flag, the data processing module stores the data corresponding to the first logical block address in the backup location in the cache space, and sets the corresponding bit of the first logical block address in the valid bitmap parameter to the first value.

[0250] When the data granularity of the first logical block address differs from the granularity of the smallest unit of the flash memory device:

[0251] The data processing module obtains the valid sector parameters and determines the data granularity of the current write command based on these parameters. If a first logical block address differs from all logical block addresses stored in the cache space, and at least one bit in the valid sector parameters is a second value, the data processing module stores the first logical block address and its corresponding data in the cache space. It then sets each valid bit of the valid bitmap parameter to the second value and sends the valid bitmap parameters and the data granularity of the current write command to the firmware, enabling the firmware to send a fill read command to the hardware data management system.

[0252] When a first logical block address is the same as a second logical block address stored in the cache space, and at least one bit in the valid sector parameter is the second value, the data processing module replaces the data corresponding to the second logical block address stored in the cache space with the data corresponding to the first logical block address, and sets each valid bit of the valid bitmap parameter to the second value.

[0253] When every bit in the valid sector parameter is the first value, the hardware data management system sets the last bit of the valid bitmap parameter to the first value and sends the data granularity of the valid bitmap parameter and the current write command to the firmware, so that the firmware sends the flash write command to the hardware data management system.

[0254] Furthermore, the firmware processing module obtains the flash write command sent by the firmware and writes data into the flash memory medium according to the flash write command.

[0255] Please see Figure 17 , Figure 17 This is an interactive diagram of a host, a hardware data management system, and firmware provided in an embodiment of this application;

[0256] like Figure 17 As shown, the interaction flow between the host, the hardware data management system, and the firmware includes:

[0257] Step S1701: The host sends a write command;

[0258] Specifically, host 151 sends a write command to hardware data management system 200. The write command is {Start_LBA, LBA_Length}, where Start_LBA represents the starting logical block address and LBA_Length represents the address length.

[0259] Step S1702: The hardware data management system sends a data acquisition command;

[0260] Specifically, the hardware data management system 200 sends a data acquisition command, which is {Start_LBA, LBA_Length}, where Start_LBA represents the starting logical block address and LBA_Length represents the address length.

[0261] Step S1703: The host sends data;

[0262] Specifically, host 151 sends the first logical block address and corresponding data to hardware data management system 200.

[0263] Step S1704: The hardware data management system sends a valid bitmap instruction;

[0264] Specifically, the hardware data management system 200 sends a valid bitmap instruction to the firmware 1021. The valid bitmap instruction is {Start_LBA, LBA_Length, Valid_bit_map}, where Start_LBA represents the starting logical block address, LBA_Length represents the address length, and valid_bit_map represents the valid bitmap parameters.

[0265] Step S1705: Firmware sends flash write command;

[0266] Specifically, firmware 1021 sends a flash write command to hardware data management system 200. The flash write command is, for example, {write_tag, LBA, PBA}, where write_tag represents the write tag, LBA represents the first logical block address, and PBA represents the target physical location.

[0267] Step S1706: The hardware data management system sends a write tag.

[0268] Specifically, the hardware data management system 200 writes the data corresponding to the first logical block address from inside the hardware data management system 200 to the target physical location in the flash memory medium according to the flash memory write command, and sends a write mark to the firmware 1021 after completing the write operation.

[0269] Please see Figure 18 , Figure 18 This is a detailed flowchart illustrating a write command processing method provided in an embodiment of this application;

[0270] In this embodiment of the application, the hardware data management system further includes a hash module 204, which is used to complete LBA insertion, LBA lookup and LBA deletion operations based on a hash algorithm.

[0271] like Figure 18 As shown, the detailed flow of this write command processing method includes:

[0272] Step S1: The host sends a write command to the hardware data management system;

[0273] Step S2: The host processing module obtains the size of the free space;

[0274] Specifically, the host processing module receives the write command and determines the size of the free space in the cache.

[0275] Step S3: The host processing module sends a data acquisition command to the host;

[0276] Step S4: The host sends data;

[0277] Step S5: The data processing module writes the data into the cache space;

[0278] Step S6: The data processing module sends an LBA insert request to the hash module;

[0279] Specifically, the LBA insertion request is used to instruct the hash module 204 to establish a mapping relationship between each first logical block address and the corresponding data location in the cache space through a hash algorithm, and to store the mapping relationship in a hash table.

[0280] Step S7: Data reception complete;

[0281] Specifically, the data processing module 202 sends a data reception completion message to the host 151, which indicates that the hardware data management system has finished receiving the data sent by the host 151.

[0282] Step S8: The data for the current write command has been received;

[0283] Specifically, the hardware data management system sends a valid bitmap instruction to the firmware to inform the firmware that the current write command has finished receiving data, and to instruct the firmware whether to send a flash write command to the hardware data management system.

[0284] Step S9: The firmware sends a fill read command to the hardware data management system;

[0285] Step S10: The firmware processing module reads data from the flash memory medium;

[0286] Step S11: Data reading complete;

[0287] The firmware processing module 203 sends a data reading completion message to the firmware, which indicates that the hardware data management system has completed the data reading operation.

[0288] Step S12: The firmware sends a flash write command to the hardware data management system;

[0289] Step S13: The firmware processing module sends an LBA lookup request to the hash module;

[0290] Specifically, the LBA lookup request is used to instruct the hash module 204 to determine the storage location of the data corresponding to the first logical block address in the flash write command in the cache space based on the hash algorithm.

[0291] Step S14: The hash module reports the storage location of the data in the cache space to the firmware processing module;

[0292] Step S15: The firmware processing module writes data to the flash memory medium;

[0293] Step S16: Flash write command completed;

[0294] Specifically, after completing the flash memory write operation, the hardware data management system sends a write flag to the firmware to indicate that the flash memory write command has been executed. Accordingly, the firmware recognizes the write flag and updates the mapping table between logical addresses and physical addresses.

[0295] Step S17: The firmware sends an LBA deletion request to the hardware data management system;

[0296] Specifically, the LBA deletion request instructs the hardware data management system to delete the address of the first logical block that has completed a flash memory write operation within the system. Correspondingly, the hash module, based on the LBA deletion request and using a hash algorithm, deletes the address of the first logical block stored in the hash table.

[0297] Specifically, when the data granularity of the first logical block address is different from the granularity of the smallest unit of the flash memory device, and the N 512B first logical block addresses contained in the current write command cannot form an LBA0 with a data granularity of 4K, the write command processing flow of steps S1-S17 is executed; otherwise, the write command processing flow of steps S1-S8 and steps S12-S17 is executed sequentially.

[0298] In this embodiment, a write command processing method is provided, applied to a flash memory device communicatively connected to a host. The flash memory device includes a hardware data management system. The write command processing method includes: acquiring a write command sent by the host and sending a data acquisition command to the host; receiving a first logical block address and data sent by the host; and performing a storage operation on the data according to the first logical block address. This application can reduce the latency of writing multiple data corresponding to the same logical block address to the flash memory when multiple write commands sent by the host contain the same logical block address, thereby improving the write performance of the flash memory device.

[0299] This application also provides a non-volatile computer storage medium storing computer-executable instructions that are executed by one or more processors. For example, the one or more processors can execute the write command processing method in any of the above method embodiments, such as executing the write command processing method in any of the above method embodiments, or executing the steps described above.

[0300] The apparatus or device embodiments described above are merely illustrative. The unit modules described as separate components may or may not be physically separate, and the components shown as module units may or may not be physical units; that is, they may be located in one place or distributed across multiple network module units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0301] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented using software plus a general-purpose hardware platform, or of course, using hardware. Based on this understanding, the above technical solutions, in essence or the parts that contribute to the related technology, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., including several instructions for a computer device (which may be a personal computer, server, or network device, etc.) to execute the various embodiments or some parts of the embodiments.

[0302] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of this application as described above. For the sake of brevity, they are not provided in detail; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A hardware data management system, characterized in that, Applied to a flash memory device, the flash memory device being communicatively connected to a host, the flash memory device including firmware and flash memory media, the hardware data management system including: The host processing module is used to acquire write commands sent by the host and send data acquisition commands to the host, so as to receive the first logical block address and data corresponding to the data acquisition commands sent by the host; The data processing module is used to perform storage operations and edit valid bitmap instructions on the data according to whether the hardware data management system stores a logical block address that is the same as the first logical block address, thereby sending the valid bitmap instructions to the firmware. The valid bitmap instruction is used to indicate whether the firmware sends a flash write command to the hardware data management system, and the flash write command is used to instruct the hardware data management system to store the data in the flash memory medium. The hardware data management system includes a cache space, which is used to store logical block addresses and corresponding data. The valid bitmap instruction includes the starting logical block address, the address length, and the valid bitmap parameters. Each valid bit of the valid bitmap parameters is used to indicate whether the corresponding first logical block address needs to be written to flash memory. The data processing module is specifically used for: Based on the hash algorithm, each first logical block address is used as a key to search for the second logical block addresses stored in the cache space to determine whether there are identical logical block addresses in the cache space. When a first logical block address is different from the second logical block address stored in the cache space, the first logical block address and the corresponding data are stored in the cache space, and the corresponding bit of the first logical block address in the valid bitmap parameter is set to a first value, wherein the first value indicates that the corresponding first logical block address needs to be flash written.

2. The system according to claim 1, characterized in that, The data acquisition command includes a first command or a second command. The first command is used to instruct the host to send the data corresponding to several first logical block addresses as a whole to the hardware data management system. The second command is used to instruct the host to send the data corresponding to several first logical block addresses in segments to the hardware data management system. The host processing module is specifically used for: Receive a write command sent by the host, wherein the write command includes an address length; Determine the size of the free space in the cache space; If the size of the free space is greater than or equal to the address length, then send the first command to the host; If the size of the free space is less than the address length, then the second command is sent to the host according to the size of the free space.

3. The system according to claim 1, characterized in that, The data processing module is also used for: When a first logical block address is the same as a second logical block address stored in the cache space, and the second logical block address does not have a flash write status flag, the data corresponding to the first logical block address replaces the data corresponding to the second logical block address stored in the cache space. The corresponding bit of the first logical block address in the effective bitmap parameter is set to a second value, wherein the second value indicates that the corresponding first logical block address does not need to be written to the flash memory.

4. The system according to claim 1, characterized in that, The data processing module is also used for: When a first logical block address is the same as a second logical block address stored in the cache space, and the second logical block address has a flash write status flag, the data corresponding to the first logical block address is stored in the backup location in the cache space. Set the address of the first logical block to the corresponding bit of the valid bitmap parameter and set it to the first value.

5. The system according to claim 3, characterized in that, The data processing module is also used for: When the data granularity of the first logical block address is different from the granularity of the smallest unit of the flash memory device, a valid sector parameter is obtained, wherein each valid bit of the valid sector parameter is used to indicate whether the corresponding logical block address has been obtained; Based on the valid sector parameters, determine the data granularity of the current write command; When a first logical block address is different from the second logical block address stored in the cache space, and at least one bit in the valid sector parameter is a second value, the first logical block address and the corresponding data are stored in the cache space, and each valid bit of the valid bitmap parameter is set to the second value. Send the valid bitmap parameters and the data granularity of the current write command to the firmware.

6. The system according to claim 5, characterized in that, When the data granularity of the first logical block address differs from the granularity of the smallest unit of the flash memory device, the data processing module is further configured to: When a first logical block address is the same as a second logical block address stored in the cache space, and at least one bit of the valid sector parameter is a second value, the data corresponding to the first logical block address replaces the data corresponding to the second logical block address stored in the cache space. Set each valid bit of the valid bitmap parameter to a second value.

7. The system according to claim 5, characterized in that, When the data granularity of the first logical block address differs from the granularity of the smallest unit of the flash memory device, the data processing module is further configured to: When every valid bit in the valid sector parameters is the first value, the last bit of the valid bitmap parameters is set to the first value; The firmware sends the valid bitmap parameters and the data granularity of the current write command to the firmware so that the firmware sends a flash write command to the hardware data management system.

8. The system according to claim 1, characterized in that, The hardware data management system also includes a firmware processing module; The firmware processing module is used for: Obtain the flash write command sent by the firmware, wherein the flash write command includes a first logical block address and a target physical address; Based on a hash algorithm, the storage location of the data in the hardware data management system is determined using the address of the first logical block as the key. Based on the target physical address, the data is written from the storage location to the flash memory medium; A write flag is sent to the firmware to update the mapping table between logical addresses and physical addresses, wherein the write flag indicates that the current flash write command operation has been completed.

9. The system according to claim 8, characterized in that, When the hardware data management system simultaneously stores first data and second data corresponding to the first logical block address, the firmware processing module is used to: After writing the first data corresponding to the first logical block address into the flash memory medium, the second data corresponding to the first logical block address into the flash memory medium is written, wherein the first data and the second data correspond to different write commands.

10. The system according to claim 8, characterized in that, When the data granularity of the first logical block address differs from the granularity of the smallest unit of the flash memory device, the firmware processing module is used to: Obtain the fill read command sent by the firmware, wherein the fill read command includes a third logical block address, and the data granularity of the third logical block address is the same as the granularity of the smallest unit of the flash memory device; According to the fill read command, read the data corresponding to the third logical block address from the flash memory medium; Obtain the flash write command sent by the firmware, and according to the flash write command, merge the data corresponding to the N first logical block addresses with the data corresponding to the third logical block address to obtain combined data, wherein the N first logical block addresses are partial units of the third logical block address; The combined data is written to the flash memory medium.

11. A storage control chip, characterized in that, include: The hardware data management system as described in any one of claims 1 to 10; The firmware, connected to the hardware data management system, is used to obtain valid bitmap instructions and send flash write commands to the hardware data management system.

12. A flash memory device, characterized in that, include: The storage control chip as described in claim 11; At least one flash memory medium is communicatively connected to the storage control chip.

13. A data transmission system, characterized in that, include: The host is used to issue write commands to the flash memory device; The flash memory device of claim 12 is communicatively connected to the host and is used to store data according to the write command.

14. A write command processing method, characterized in that, Applied to the flash memory device of claim 12, wherein the flash memory device is communicatively connected to a host, the method includes: Retrieve the write command sent by the host, and send a data retrieval command to the host; Receive the first logical block address and data sent by the host; The data is stored according to the address of the first logical block.

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