A matrix multiplication operation execution method and device, electronic equipment and storage medium

Abstract

This invention discloses a matrix multiplication operation execution method, apparatus, electronic device, and storage medium. The method includes: in response to a matrix multiplication operation instruction, acquiring a first matrix to be operated on, a second matrix to be operated on, and an initial matrix to be updated; determining a block size for matrix partitioning based on cache space capacity; by partitioning the matrix into blocks, obtaining a first submatrix of the first matrix to be operated on, a second submatrix of the second matrix to be operated on, and a third submatrix of the initial matrix to be updated; selecting a storage vector register and a pre-stored vector register from various vector registers based on the block size; sequentially acquiring the corresponding submatrix from the storage vector register and the pre-stored vector register for matrix multiplication operations until the operation termination condition is met, thereby obtaining the matrix multiplication operation result. The technical solution provided by this invention improves the operational efficiency of matrix multiplication by optimizing function performance.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of numerical analysis technology, and in particular to a matrix multiplication operation execution method, apparatus, electronic device and storage medium. Background Technology

[0002] Numerical computation is a crucial tool in scientific research, and high-performance computing based on numerical computation has become a key technological element representing a nation's comprehensive strength, holding significant importance in fields such as atomic physics, computational chemistry, bioinformatics, atmospheric science, and artificial intelligence. Numerical linear algebra is the core computational method in the field of numerical computation. It uses matrices as the primary data representation and matrix operations as the ultimate goal for problem-solving.

[0003] Because numerical linear algebra has wide applications in scientific and engineering computing, researchers have continuously developed powerful numerical linear algebra libraries, among which BLAS (Basic Linear Algebra Subprograms) is relatively well-known. The linear algebra operations in BLAS are mainly divided into three aspects: vector-vector is called Level-1 BLAS, vector-matrix is ​​called Level-2 BLAS, and matrix-matrix is ​​called Level-3 BLAS.

[0004] In existing technologies, matrix multiplication is performed by multiplying a row of matrix A by a column of matrix B and then updating the corresponding elements of matrix C. However, regardless of whether the matrices are stored in memory using row-major or column-major storage, when the cache retrieves a row of matrix A or a column of matrix B from main memory, due to the non-contiguous address space, significant cache misses and translation lookaside buffer (TLB) misses occur on either side. This reduces the computation-to-memory access ratio and significantly impacts computation speed. Furthermore, the reduced computation speed in existing technologies makes numerical linear algebra computation inefficient, resulting in slow execution. Summary of the Invention

[0005] This invention provides a matrix multiplication operation execution method, apparatus, electronic device, and storage medium to improve the operation efficiency of matrix multiplication.

[0006] In a first aspect, embodiments of the present invention provide a method for performing matrix multiplication operations, the method comprising:

[0007] In response to a matrix multiplication operation instruction, obtain the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated;

[0008] Determine the block size for matrix partitioning based on the cache space capacity;

[0009] Based on the block size, the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated are divided into blocks to obtain the first sub-matrix of the first matrix to be operated on, the second sub-matrix of the second matrix to be operated on, and the third sub-matrix of the initial matrix to be updated, respectively.

[0010] Based on the block size, a storage vector register and a pre-stored vector register are selected from each vector register; the storage vector register is used to store the first sub-matrix, the second sub-matrix, and the third sub-matrix in the current operation cycle; the pre-stored vector register is used to store the first sub-matrix and the second sub-matrix in the next operation cycle.

[0011] The corresponding submatrices are sequentially retrieved from the storage vector register and the pre-stored vector register for matrix multiplication until the operation termination condition is met, and the result of the matrix multiplication operation is obtained.

[0012] Secondly, embodiments of the present invention also provide a matrix multiplication operation execution device, the device comprising:

[0013] The matrix acquisition module is used to acquire the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated in response to the matrix multiplication operation command;

[0014] The block step size determination module is used to determine the block step size for matrix block division based on the cache space capacity.

[0015] The submatrix acquisition module is used to divide the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated into blocks according to the block size, so as to obtain the first submatrix of the first matrix to be operated on, the second submatrix of the second matrix to be operated on, and the third submatrix of the initial matrix to be updated, respectively.

[0016] The register selection module is used to select the storage vector register and the pre-stored vector register from each vector register according to the block step size; the storage vector register is used to store the first sub-matrix, the second sub-matrix and the third sub-matrix in the current operation cycle; the pre-stored vector register is used to store the first sub-matrix and the second sub-matrix in the next operation cycle.

[0017] The result acquisition module is used to sequentially retrieve the corresponding submatrices from the storage vector register and the pre-stored vector register to perform matrix multiplication operations until the operation termination condition is met, and then obtain the matrix multiplication result.

[0018] Thirdly, embodiments of the present invention also provide an electronic device, comprising:

[0019] At least one processor; and

[0020] A memory that is communicatively connected to at least one processor; wherein,

[0021] The memory stores a computer program that can be executed by at least one processor, such that the at least one processor is able to execute a matrix multiplication operation execution method according to any embodiment of the present invention.

[0022] Fourthly, embodiments of the present invention also provide a storage medium containing computer-executable instructions, which, when executed by a computer processor, enable the computer processor to execute any matrix multiplication operation execution method provided in the embodiments of the present invention.

[0023] This invention, in response to a matrix multiplication operation instruction, obtains a first matrix to be operated on, a second matrix to be operated on, and an initial matrix to be updated. Based on the cache space capacity, it determines the block size for matrix partitioning. According to the block size, it performs matrix partitioning on the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated, obtaining a first sub-matrix of the first matrix to be operated on, a second sub-matrix of the second matrix to be operated on, and a third sub-matrix of the initial matrix to be updated. According to the block size, it selects a storage vector register and a pre-stored vector register from each vector register. The storage vector register stores the first, second, and third sub-matrices in the current operation cycle; the pre-stored vector register stores the first and second sub-matrices in the next operation cycle. It sequentially obtains the corresponding sub-matrices from the storage vector register and the pre-stored vector register for matrix multiplication operations until the operation termination condition is met, obtaining the matrix multiplication result. The technical solution provided by this invention optimizes function performance to improve the operational efficiency of matrix multiplication.

[0024] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a flowchart of a matrix multiplication operation execution method provided in Embodiment 1 of the present invention;

[0027] Figure 2 This is a flowchart of another matrix multiplication operation execution method provided in Embodiment 2 of the present invention;

[0028] Figure 3 This is a schematic diagram of a matrix multiplication operation execution device according to Embodiment 3 of the present invention;

[0029] Figure 4 This is a schematic diagram of an electronic device for performing a matrix multiplication operation according to Embodiment 4 of the present invention. Detailed Implementation

[0030] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0031] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0032] Furthermore, it should be noted that the collection, storage, use, processing, transmission, provision, and disclosure of relevant data involved in the technical solution of this invention all comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0033] Example 1

[0034] Figure 1This is a flowchart of a matrix multiplication operation execution method provided in Embodiment 1 of the present invention. This embodiment is applicable to situations where function performance is optimized to improve the efficiency of matrix multiplication. The method can be executed by a matrix multiplication operation execution device, which can be implemented in hardware and / or software. The matrix multiplication operation execution device can be configured in an electronic device, such as a terminal device or a server, etc. The present invention does not impose any limitations on this.

[0035] like Figure 1 As shown in the figure, the matrix multiplication operation execution method provided by the embodiment of the present invention specifically includes the following steps:

[0036] S110, in response to the matrix multiplication operation instruction, obtain the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated.

[0037] Specifically, in response to the numerical computation requirement of matrix multiplication, upon receiving a matrix multiplication operation instruction, a first matrix to be operated on, a second matrix to be operated on, and an initial matrix to be updated can be obtained. In particular, this embodiment of the invention does not limit the response method to the matrix multiplication operation instruction. Furthermore, this embodiment of the invention does not limit the method of obtaining the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated.

[0038] Here, the first and second matrices to be operated on can be understood as the matrices to be operated on after responding to the matrix multiplication operation command. For example, matrix multiplication can be performed using the Single Precision General Matrix-matrix Multiplication (SGEMM) function in the Level-3 BLAS numerical computing library. SGEMM is a general matrix multiplication function that can achieve the multiplication of arbitrary matrices by modifying its function parameters. When performing matrix multiplication operations using SGEMM, the following formula can be used:

[0039] C=alpha×op(A)×op(B)+beta×C;

[0040] Here, alpha and beta are scalar factors, and A, B, and C are operation matrices. It should be noted that A and B are the first and second matrices to be operated on, obtained in response to the matrix multiplication operation instruction. The initial matrix to be updated can be obtained based on the already obtained A and B, according to the above formula. In this case, the calculated output matrix C can be used as the initial matrix to be updated.

[0041] In response to a matrix multiplication operation command, a first matrix to be operated on, a second matrix to be operated on, and an initial matrix to be updated can be obtained, so as to carry out subsequent numerical calculations of the matrix based on the obtained operation matrix and the initial matrix to be updated.

[0042] S120. Determine the block size for matrix partitioning based on the cache space capacity.

[0043] Specifically, the block size for matrix partitioning can be determined based on the limitations of the cache space capacity in the computer memory. It should be noted that the computer storage hierarchy, from bottom to top, includes three levels: main memory, cache, and registers. The storage space size and access clock cycle of each level are different. This embodiment of the invention does not restrict the method for determining the block size for matrix partitioning based on the cache space capacity.

[0044] The size of the block size for dividing the matrix is ​​determined by the cache space capacity, which facilitates subsequent matrix calculations.

[0045] S130. Based on the block size, perform matrix block division on the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated, to obtain the first sub-matrix of the first matrix to be operated on, the second sub-matrix of the second matrix to be operated on, and the third sub-matrix of the initial matrix to be updated, respectively.

[0046] Specifically, based on the determined block size, the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated can be divided into blocks, thereby obtaining the first sub-matrix of the first matrix to be operated on, the second sub-matrix of the second matrix to be operated on, and the third sub-matrix of the initial matrix to be updated. In particular, in this embodiment of the invention, the matrix block selection method is not limited when performing matrix block division on the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated.

[0047] It's important to note that in a computer's storage hierarchy, the Central Processing Unit (CPU), the core of the computer system's computation and control, typically has different access speeds for registers, cache, main memory, and hard disks. Generally, registers are used to store temporary data and instructions. Because the CPU can directly read and write data in registers, the access speed is very fast, usually on the nanosecond level, making it the fastest storage medium within the CPU. The cache is the storage medium located between the CPU and main memory, used to accelerate access to main memory. Caches can be divided into multiple levels, such as L1, L2, and L3. L1 cache is closest to the CPU and therefore very fast, while L3 cache is farther from the CPU and therefore slower. Typically, cache access speeds are between a few nanoseconds and tens of nanoseconds. Main memory, the primary storage medium for storing programs and data in a computer system, usually refers to Random Access Memory (RAM). It is internal memory that directly exchanges data with the CPU, can be read and written at any time, and is very fast. It is often used as temporary data storage for the operating system or other running programs. When RAM is working, information can be written to (i.e., stored) or read out (i.e., retrieved) from any specified address at any time. The difference between RAM and Read-Only Memory (ROM) lies in the volatility of the data; that is, stored data is lost once power is off. RAM is used in computers and digital systems to temporarily store programs, data, and intermediate results. However, compared to registers and caches, main memory access speed is slower, typically between tens and hundreds of nanoseconds. Hard disks, as devices used for permanent data storage in computer systems, are the slowest storage medium. Hard disk access speeds are significantly slower than main memory, generally taking milliseconds or even longer.

[0048] Optionally, after dividing the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated into matrix blocks according to the block size, to obtain the first sub-matrix of the first matrix to be operated on, the second sub-matrix of the second matrix to be operated on, and the third sub-matrix of the initial matrix to be updated, the method further includes: storing the first sub-matrix of the first matrix to be operated on based on a preset row storage method; and storing the second sub-matrix of the second matrix to be operated on based on a preset column storage method.

[0049] Specifically, based on the block size, when dividing the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated into blocks, a first sub-matrix of the first matrix to be operated on, a second sub-matrix of the second matrix to be operated on, and a third sub-matrix of the initial matrix to be updated can be obtained respectively. Afterwards, the first sub-matrix of the first matrix to be operated on can be stored based on a preset row storage method, and the second sub-matrix of the second matrix to be operated on can be stored based on a preset column storage method. In particular, this embodiment of the invention does not limit the specific storage method of the preset row storage method and the preset column storage method.

[0050] Based on the block size, the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated can be divided into blocks to obtain the first sub-matrix of the first matrix to be operated on, the second sub-matrix of the second matrix to be operated on, and the third sub-matrix of the initial matrix to be updated. Afterward, the first sub-matrix of the first matrix to be operated on can be stored using a preset row-based storage method, and the second sub-matrix of the second matrix to be operated on can be stored using a preset column-based storage method. For example, in summary, the matrix in memory can be divided using matrix block division, so that the smaller sub-matrixes obtained from the division can be stored in the cache. This allows the CPU to directly retrieve elements from the cache for computation, thereby achieving fast access to elements in the matrix.

[0051] S140. Based on the block step size, select the storage vector register and the pre-stored vector register from each vector register; the storage vector register is used to store the first sub-matrix, the second sub-matrix and the third sub-matrix in the current operation cycle; the pre-stored vector register is used to store the first sub-matrix and the second sub-matrix in the next operation cycle.

[0052] Specifically, based on the block size, a storage vector register and a pre-stored vector register can be selected from the vector registers. The storage vector register can be used to store the first, second, and third sub-matrices in the current operation cycle; the pre-stored vector register can be used to store the first and second sub-matrices in the next operation cycle.

[0053] By selecting a storage vector register and a pre-stored vector register from various vector registers, the selected storage vector register can be used to store the first, second, and third sub-matrices of the current operation cycle; the selected pre-stored vector register can be used to store the first and second sub-matrices of the next operation cycle, so as to carry out subsequent work based on the sub-matrices in the storage vector register and the pre-stored vector register. By reading the sub-matrices, the computational efficiency of the matrix can be improved.

[0054] S150. Sequentially retrieve the corresponding submatrices from the storage vector register and the pre-stored vector register and perform matrix multiplication operations until the operation termination condition is met, and obtain the matrix multiplication result.

[0055] Specifically, by sequentially retrieving the corresponding submatrices from the storage vector register and the pre-stored vector register, and performing matrix multiplication operations based on the retrieved submatrices, the matrix multiplication result can be obtained when the operation termination condition is met. In particular, this embodiment of the invention does not impose restrictions on the operation termination condition.

[0056] By using the stored vector register and the pre-stored vector register, and selecting the corresponding submatrices to perform matrix multiplication operations, the final matrix multiplication result can be obtained when the termination condition is met. This method of performing matrix multiplication operations on submatrices and obtaining the result upon meeting the termination condition effectively improves the computational efficiency of matrices.

[0057] This invention, in response to a matrix multiplication operation instruction, obtains a first matrix to be operated on, a second matrix to be operated on, and an initial matrix to be updated. Based on the cache space capacity, it determines the block size for matrix partitioning. According to the block size, it performs matrix partitioning on the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated, obtaining a first sub-matrix of the first matrix to be operated on, a second sub-matrix of the second matrix to be operated on, and a third sub-matrix of the initial matrix to be updated. According to the block size, it selects a storage vector register and a pre-stored vector register from each vector register. The storage vector register stores the first, second, and third sub-matrices in the current operation cycle; the pre-stored vector register stores the first and second sub-matrices in the next operation cycle. It sequentially obtains the corresponding sub-matrices from the storage vector register and the pre-stored vector register for matrix multiplication operations until the operation termination condition is met, obtaining the matrix multiplication result. The technical solution provided by this invention optimizes function performance to improve the operational efficiency of matrix multiplication.

[0058] Example 2

[0059] Figure 2 This is a flowchart of another matrix multiplication operation execution method provided in Embodiment 2 of the present invention. The technical solution of the present invention is further optimized based on the above optional technical solutions.

[0060] Furthermore, the phrase "determining the block size for matrix partitioning based on cache space capacity" is further refined to "determining the number of matrix partitioning operations based on the matrix dimensions of the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated; and determining the block size of the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated in different dimensions under each number of matrix partitioning operations based on cache space capacity," in order to improve the operational efficiency of matrix multiplication. It should be noted that parts not described in this embodiment can be referred to in other embodiments, and will not be repeated here.

[0061] like Figure 2 As shown, another matrix multiplication operation execution method provided by this embodiment of the invention specifically includes the following steps:

[0062] S210. In response to the matrix multiplication operation instruction, obtain the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated.

[0063] S220. Determine the number of matrix partitioning operations based on the matrix dimensions of the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated.

[0064] Specifically, in response to a matrix multiplication operation instruction, a first matrix to be operated on, a second matrix to be operated on, and an initial matrix to be updated can be obtained. Then, based on the size of the obtained matrices, the number of matrix partitioning operations can be determined. In particular, this embodiment of the invention does not limit the number of matrix partitioning operations.

[0065] Upon receiving a matrix multiplication operation command, the number of matrix partitioning operations can be determined based on the sizes of the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated. This allows for the acquisition of submatrices for each matrix based on the number of matrix partitioning operations, and subsequent operations can then be performed based on the acquired submatrices.

[0066] S230. Based on the cache space capacity, determine the block step size of the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated in different dimensions under each matrix block number.

[0067] S240. Based on the block size, the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated are divided into blocks to obtain the first sub-matrix of the first matrix to be operated on, the second sub-matrix of the second matrix to be operated on, and the third sub-matrix of the initial matrix to be updated, respectively.

[0068] Specifically, based on the cache space capacity, the block size of the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated under different dimensions can be determined for each number of matrix block operations. Based on the determined block size, the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated can be divided into blocks, thereby obtaining the corresponding first sub-matrix of the first matrix to be operated on, the second sub-matrix of the second matrix to be operated on, and the third sub-matrix of the initial matrix to be updated.

[0069] It should be noted that, depending on the block size, when performing matrix block division on the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated, the matrices can be divided by row or by column to obtain the corresponding submatrices. This embodiment of the invention does not restrict the matrix block division method selected.

[0070] Optionally, based on the block size, the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated are divided into blocks to obtain the first sub-matrix of the first matrix to be operated on, the second sub-matrix of the second matrix to be operated on, and the third sub-matrix of the initial matrix to be updated, respectively. This includes: dividing the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated into blocks according to the block size of the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated in different dimensions under each number of matrix block divisions, to obtain the first block matrix of the first matrix to be operated on, the second block matrix of the second matrix to be operated on, and the third block matrix of the initial matrix to be updated under each number of matrix block divisions; determining the first block matrix of the first matrix to be operated on under the last number of matrix block divisions as the first sub-matrix, determining the second block matrix of the second matrix to be operated on as the second sub-matrix, and determining the third block matrix of the initial matrix to be updated as the third sub-matrix.

[0071] Specifically, based on the block size, when dividing the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated into blocks, the first sub-matrix of the first matrix to be operated on, the second sub-matrix of the second matrix to be operated on, and the third sub-matrix of the initial matrix to be updated can be obtained respectively. The specific method of obtaining these sub-matrixes is as follows: based on the block size of the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated in different dimensions under each number of matrix block divisions, the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated are divided into blocks according to the block size of the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated in different dimensions. Then, the first block matrix of the first matrix to be operated on, the second block matrix of the second matrix to be operated on, and the third block matrix of the initial matrix to be updated can be obtained under each number of matrix block divisions.

[0072] Based on the different number of times each matrix is ​​divided and the step size of the matrix in different dimensions, each matrix can be divided into blocks, thereby obtaining the block matrix of each matrix under each number of matrix divisions. In addition, the first block matrix of the first matrix to be operated on under the last number of matrix divisions can be determined as the first submatrix, the second block matrix of the second matrix to be operated on can be determined as the second submatrix, and the third block matrix of the initial matrix to be updated can be determined as the third submatrix, so as to carry out subsequent work such as matrix calculation based on the submatrixes obtained at this time.

[0073] S250. Based on the block step size, select the storage vector register and the pre-stored vector register from each vector register; the storage vector register is used to store the first sub-matrix, the second sub-matrix and the third sub-matrix in the current operation cycle; the pre-stored vector register is used to store the first sub-matrix and the second sub-matrix in the next operation cycle.

[0074] Specifically, based on the obtained block step size, a storage vector register and a pre-stored vector register can be selected from each vector register. The storage vector register can be used to store the first sub-matrix, the second sub-matrix, and the third sub-matrix in the current operation cycle; the pre-stored vector register can be used to store the first sub-matrix and the second sub-matrix in the next operation cycle.

[0075] Optionally, based on the block size, storage vector registers and pre-stored vector registers are selected from each vector register, including: determining storage vector registers for storing the first sub-matrix, second sub-matrix, and third sub-matrix in the current operation cycle based on the block size of the first matrix to be operated, the second matrix to be operated, and the initial matrix to be updated in the last matrix block count; and selecting pre-stored vector registers for storing the first and second sub-matrix in the next operation cycle based on the number of registers in the storage vector registers.

[0076] Specifically, based on the block size of the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated under the last matrix block number, the storage vector registers for storing the first submatrix, the second submatrix, and the third submatrix under the current operation cycle are determined; based on the number of storage vector registers, the pre-stored vector registers for storing the first and second submatrixes under the next operation cycle are selected from each vector register. In particular, this embodiment of the invention does not restrict the method of selecting the storage vector registers and pre-stored vector registers from each vector register based on the block size.

[0077] Optionally, based on the block size of the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated under the last matrix block number, a storage vector register for storing the first submatrix, the second submatrix, and the third submatrix under the current operation cycle is determined, including: determining a first storage vector register for storing the first submatrix under the current operation cycle based on the block size of the first matrix to be operated on under the last matrix block number; determining a second storage vector register for storing the second submatrix under the current operation cycle based on the block size of the second matrix to be operated on under the last matrix block number; determining a third storage vector register for storing the third submatrix under the current operation cycle based on the block size of the initial matrix to be updated under the last matrix block number; and determining the first storage vector register, the second storage vector register, and the third storage vector register as storage registers.

[0078] Specifically, when determining the storage vector registers for storing the first, second, and third submatrices in the current computation cycle based on the block size of the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated under the last matrix block number, the first storage vector register for storing the first submatrice in the current computation cycle can be determined based on the block size of the first matrix to be operated on under the last matrix block number. Similarly, the second storage vector register for storing the second submatrice in the current computation cycle can be determined based on the block size of the second matrix to be operated on under the last matrix block number; and the third storage vector register for storing the third submatrice in the current computation cycle can be determined based on the block size of the initial matrix to be updated under the last matrix block number. Alternatively, the first, second, and third storage vector registers can be designated as storage registers. In particular, this embodiment of the invention does not limit the method for determining the storage vector registers corresponding to each submatrix in the current computation cycle. The submatrixes described include a first submatrix, a second submatrix, and a third submatrix, and the corresponding storage vector registers include a first storage vector register, a second storage vector register, and a third storage vector register.

[0079] Specifically, based on the number of registers in the storage vector registers, a pre-stored vector register for storing the first submatrix and the second submatrix for the next operation cycle is selected from each vector register, including: selecting a first pre-stored vector register for storing the first submatrix for the next operation cycle from each vector register based on the number of first registers in the first storage vector registers; and selecting a second pre-stored vector register for storing the second submatrix for the next operation cycle from each vector register based on the number of second registers in the second storage vector registers.

[0080] Specifically, when selecting the pre-stored vector registers for storing the first and second sub-matrices in the next operation cycle from among the vector registers based on the number of registers in the storage vector registers, the first pre-stored vector register for storing the first sub-matrices in the next operation cycle can be selected from among the vector registers based on the number of first registers in the first storage vector register; similarly, the second pre-stored vector register for storing the second sub-matrices in the next operation cycle can be selected from among the vector registers based on the number of second registers in the second storage vector registers. In particular, this embodiment of the invention does not restrict the method of selecting the pre-stored vector registers corresponding to each sub-matrix in the next operation cycle based on the number of registers in each storage vector register. It should be noted that the storage vector registers described here include both the first and second storage vector registers; the pre-stored vector registers include both the first and second pre-stored vector registers.

[0081] Based on the block size of the first matrix to be operated on under the last matrix block count, a first storage vector register for storing the first submatrix under the current operation cycle can be determined; based on the block size of the second matrix to be operated on under the last matrix block count, a second storage vector register for storing the second submatrix under the current operation cycle can be determined; based on the block size of the initial matrix to be updated under the last matrix block count, a third storage vector register for storing the third submatrix under the current operation cycle can be determined; the first, second, and third storage vector registers are designated as storage registers. These storage vector registers can be used to store the first, second, and third submatrixes under the current operation cycle. Based on the number of first registers in the first storage vector register, a first pre-stored vector register for storing the first submatrix under the next operation cycle is selected from each vector register; based on the number of second registers in the second storage vector register, a second pre-stored vector register for storing the second submatrix under the next operation cycle is selected from each vector register. This facilitates reading each submatrix from each vector memory and then performing numerical calculations on each submatrix.

[0082] S260. Sequentially retrieve the corresponding submatrices from the storage vector register and the pre-stored vector register and perform matrix multiplication operations until the operation termination condition is met, and obtain the matrix multiplication result.

[0083] Specifically, by sequentially retrieving the corresponding submatrices from the storage vector register and the pre-stored vector register and performing matrix multiplication operations, the corresponding matrix multiplication result can be obtained until the end condition of the operation is met. In summary, the above-described technical solution can obtain the final matrix multiplication result.

[0084] In one optional implementation, an example is given of a matrix A of size m×k, a matrix B of size k×n, and a matrix C of size m×n, wherein matrices A and B are input matrices, and C is the output matrix to be updated.

[0085] Based on the three matrices A, B, and C obtained above, matrix partitioning is performed. Specifically, matrix B is partitioned column-wise in the n-dimensional direction with a step size of nc, resulting in a submatrix b of size k×nc; matrix C is partitioned column-wise in the n-dimensional direction with a step size of nc, resulting in a submatrix c of size m×nc; matrix A is partitioned column-wise in the k-dimensional direction with a step size of kc, resulting in a submatrix a of size m×kc; submatrix b is partitioned row-wise in the k-dimensional direction with a step size of kc, resulting in a submatrix bb of size kc×nc; and submatrix a is partitioned row-wise in the m-dimensional direction with a step size of mc, resulting in a submatrix bb of size mc×nc. The submatrix aa is a submatrix of size kc. In the m-dimensional direction, with a step size mc, the submatrix c is divided into rows, resulting in a submatrix cc of size mc × nc. In the nc-dimensional direction, with a step size nr, the submatrix bb is divided into columns, resulting in a submatrix bbb of size kc × nr. In the nc-dimensional direction, with a step size nr, the submatrix cc is divided into columns, resulting in a submatrix ccc of size mc × nr. In the mc-dimensional direction, with a step size mr, the submatrix aa is divided into rows, resulting in a submatrix aaa of size mr × kc. In the mc-dimensional direction, with a step size mr, the submatrix ccc is divided into rows, resulting in a submatrix cccc of size mr × nr.

[0086] Specifically, after completing the above matrix partitioning operation, the sizes of the submatrix A, submatrix B, and submatrix C obtained at this time are mr×kc, kc×nr, and mr×nr, respectively. After this, submatrix C can be calculated using a vector register in conjunction with the Level-1 (i.e., L1) cache. The partitioning parameters mc, kc, nc, mr, and nr described above all depend on the specific processor's cache space size for reasonable partitioning. In this invention, considering that the partitioning parameters are limited by the Level-1 cache, such as the small L1 space, the following formulas (1) and (2) should be satisfied when making reasonable partitions. The specific formulas are as follows:

[0087]

[0088]

[0089] Among them, mc, kc, nc, mr and nr cannot exceed the size of L1. Therefore, mc, kc, nc, mr and nr can be 96kb, 96kb, 64kb, 16kb and 4kb respectively.

[0090] Secondly, when rearranging the data in the obtained submatrices, after block partitioning, the floating-point numbers stored in matrices A and B are not contiguous in memory addresses. This severely affects the cache hit rate, causing the cache to fail to retrieve contiguous data each time it accesses main memory, resulting in numerous cache misses and impacting computational efficiency. To avoid this, the obtained submatrix B (bb) of size kc×nc and submatrix A (aa) of size mc×kc can be rearranged along the kc direction to ensure that the data within them are contiguous in memory addresses, thereby improving the cache hit rate. First, the kc×nc submatrix B is divided into several kc×4 smaller matrices by columns, these smaller matrices are stored row-wise, and then the smaller matrices are concatenated sequentially. Second, the mc×kc submatrix A is divided into several 16×kc smaller matrices by rows, these smaller matrices are stored column-wise, and then the smaller matrices are concatenated sequentially.

[0091] Then, when allocating vector registers for the rearranged submatrices, the vector registers are mainly used for vectorization to accelerate computation. Generally, the more vector registers used, the greater the performance improvement. Therefore, under the limited number of vector registers, a reasonable allocation strategy is needed to maximize their utilization. In this invention, since the hardware vector registers used have a width of 128 bits and can store four single-precision floating-point numbers, mr (16 in the example above) / 4 vector registers are used to store the elements of matrix A, nr (4 in the example above) / 4 vector registers are used to store the elements of matrix B, and mr×nr / 4 vector registers are used to store the elements of matrix C. In addition, four vector registers are used to store the 16 prefetched elements of matrix A, and one vector register is used to store the 4 prefetched elements of matrix B. Therefore, a total of 26 vector registers are used.

[0092] Subsequently, when rearranging the acquired data, the required data can be pre-loaded into the cache. During computation, the data can be directly retrieved from the cache, reducing the time spent waiting for data to be loaded from memory. Furthermore, data prefetching can also prevent cache misses, thus significantly improving computational efficiency. When writing assembly computation code, it is necessary to avoid processor pipeline stalls caused by conflicts such as data dependencies. Therefore, this invention, considering the characteristics of the hardware pipeline, avoids RAW-type pipeline conflicts that could lead to pipeline stalls. The assembly instructions are rearranged to efficiently utilize the processor's computing power, fully utilize the pipeline, and improve the computational efficiency of GEMM.

[0093] The technical solution adopted in this invention significantly improves computational efficiency by vectorizing matrix multiplication. It can be performed on processors supporting the RISC-V Vector Extensions instruction set (version 0.7.1) without requiring additional hardware. Furthermore, this invention redesigns the computational kernel for the matrix dimension and implements it using hand-assembled code. By combining the characteristics of the hardware processor, the optimal matrix partitioning strategy, matrix partitioning parameters, and register allocation strategy can be calculated and determined. Therefore, the optimization method implemented in this invention significantly improves computational speed compared to the most primitive triple cyclic matrix multiplication method.

[0094] In this embodiment of the invention, in response to a matrix multiplication operation instruction, a first matrix to be operated on, a second matrix to be operated on, and an initial matrix to be updated are obtained. The number of matrix partitioning operations is determined based on the matrix dimensions of these matrices. Based on the cache space capacity, the partitioning stride of each matrix at each number of matrix partitioning operations is determined at different dimensions. The first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated are then partitioned into matrix blocks to obtain the first block matrix of the first matrix to be operated on, the second block matrix of the second matrix to be operated on, and the third block matrix of the initial matrix to be updated at each number of matrix partitioning operations. The first block matrix of the first matrix to be operated on at the last number of matrix partitioning operations is determined as the first submatrix, the second block matrix of the second matrix to be operated on is determined as the second submatrix, and the third block matrix of the initial matrix to be updated is determined as the third submatrix. Based on the partitioning stride of the first matrix to be operated on at the last number of matrix partitioning operations, a first storage vector register is determined to store the first submatrix in the current operation cycle. Based on the partitioning stride of the second matrix to be operated on at the last number of matrix partitioning operations, a first storage vector register is determined to store the first submatrix in the current operation cycle. A second storage vector register is designated to store the second submatrix in the current operation cycle; a third storage vector register is determined to store the third submatrix in the current operation cycle based on the block size of the initial matrix to be updated under the last matrix block count; the first, second, and third storage vector registers are designated as storage registers; a first pre-stored vector register for storing the first submatrix in the next operation cycle is selected from each vector register based on the number of first registers in the first storage vector register; a second pre-stored vector register for storing the second submatrix in the next operation cycle is selected from each vector register based on the number of second registers in the second storage vector register; the storage vector registers are used to store the first, second, and third submatrixes in the current operation cycle; the pre-stored vector registers are used to store the first and second submatrixes in the next operation cycle; the corresponding submatrixes are sequentially retrieved from the storage vector registers and pre-stored vector registers for matrix multiplication operations until the operation termination condition is met, and the matrix multiplication result is obtained. The technical solution provided by this embodiment of the invention improves the operation efficiency of matrix multiplication by optimizing function performance.

[0095] Example 3

[0096] Figure 3 This is a schematic diagram of a matrix multiplication operation execution device provided in Embodiment 3 of the present invention. Figure 3 As shown, this matrix multiplication operation execution device includes: a matrix acquisition module 310, a block step size determination module 320, a submatrix acquisition module 330, a register selection module 340, and a result acquisition module 350. Wherein:

[0097] The matrix acquisition module 310 is used to acquire the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated in response to the matrix multiplication operation instruction;

[0098] The block step size determination module 320 is used to determine the block step size for matrix block division based on the cache space capacity.

[0099] The submatrix acquisition module 330 is used to perform matrix partitioning on the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated according to the block step size, so as to obtain the first submatrix of the first matrix to be operated on, the second submatrix of the second matrix to be operated on, and the third submatrix of the initial matrix to be updated, respectively.

[0100] The register selection module 340 is used to select the storage vector register and the pre-stored vector register from each vector register according to the block step size; the storage vector register is used to store the first sub-matrix, the second sub-matrix and the third sub-matrix in the current operation cycle; the pre-stored vector register is used to store the first sub-matrix and the second sub-matrix in the next operation cycle.

[0101] The resulting module 350 is used to sequentially retrieve the corresponding submatrices from the storage vector register and the pre-stored vector register to perform matrix multiplication operations until the operation termination condition is met, and then obtain the matrix multiplication result.

[0102] This invention, in response to a matrix multiplication operation instruction, obtains a first matrix to be operated on, a second matrix to be operated on, and an initial matrix to be updated. Based on the cache space capacity, it determines the block size for matrix partitioning. According to the block size, it performs matrix partitioning on the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated, obtaining a first sub-matrix of the first matrix to be operated on, a second sub-matrix of the second matrix to be operated on, and a third sub-matrix of the initial matrix to be updated. According to the block size, it selects a storage vector register and a pre-stored vector register from each vector register. The storage vector register stores the first, second, and third sub-matrices in the current operation cycle; the pre-stored vector register stores the first and second sub-matrices in the next operation cycle. It sequentially obtains the corresponding sub-matrices from the storage vector register and the pre-stored vector register for matrix multiplication operations until the operation termination condition is met, obtaining the matrix multiplication result. The technical solution provided by this invention optimizes function performance to improve the operational efficiency of matrix multiplication.

[0103] Optionally, the block step size determination module 320 includes:

[0104] The block number determination unit is used to determine the number of matrix blocks based on the matrix dimension of the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated.

[0105] The block step size determination unit is used to determine the block step size of the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated in different dimensions under each number of matrix block operations, based on the cache space capacity.

[0106] Optionally, the block step size determination module 320 includes matrix block units, specifically used for:

[0107] Based on the block size, the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated are divided into blocks to obtain the first sub-matrix of the first matrix to be operated on, the second sub-matrix of the second matrix to be operated on, and the third sub-matrix of the initial matrix to be updated, including:

[0108] The sub-units obtained from the block matrix are used to perform matrix block division on the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated under different dimensions according to the block step size of the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated under each matrix block division number, so as to obtain the first block matrix of the first matrix to be operated on, the second block matrix of the second matrix to be operated on, and the third block matrix of the initial matrix to be updated under each matrix block division number.

[0109] The submatrix determines the sub-unit, which is used to determine the first block matrix of the first matrix to be operated on under the last matrix block number as the first submatrix, the second block matrix of the second matrix to be operated on as the second submatrix, and the third block matrix of the initial matrix to be updated as the third submatrix.

[0110] Optionally, the block step size determination module 320 includes a register selection unit, specifically used for:

[0111] Based on the block size, select the storage vector register and the pre-stored vector register from each vector register, including:

[0112] The storage register determination sub-unit is used to determine the storage vector register for storing the first sub-matrix, the second sub-matrix, and the initial sub-matrix in the current operation cycle based on the block size of the first sub-matrix, the second sub-matrix, and the initial sub-matrix under the last matrix block count.

[0113] The pre-stored register determination sub-unit is used to select the pre-stored vector register for storing the first and second sub-matrices in the next operation cycle from each vector register, based on the number of registers in the storage vector register.

[0114] Optionally, the storage register determines the sub-unit, specifically for:

[0115] Based on the block size of the first matrix to be operated on under the last matrix block count, determine the first storage vector register used to store the first sub-matrix under the current operation cycle;

[0116] Based on the block size of the second matrix to be operated on under the last matrix block count, determine the second storage vector register used to store the second sub-matrix under the current operation cycle;

[0117] Based on the block size of the initial matrix to be updated under the last matrix block count, determine the third storage vector register used to store the third submatrix under the current operation cycle;

[0118] The first storage vector register, the second storage vector register, and the third storage vector register are designated as storage registers.

[0119] Optionally, the pre-stored register determines the sub-unit, specifically used for:

[0120] Based on the number of first registers in the first storage vector register, select the first pre-stored vector register from each vector register to store the first sub-matrix in the next operation cycle;

[0121] Based on the number of second registers in the second storage vector register, a second pre-stored vector register for storing the second sub-matrix in the next operation cycle is selected from each vector register.

[0122] Optionally, the submatrix obtaining module 330 also includes a matrix storage unit, including:

[0123] A row storage subunit is used to store the first submatrix of the first matrix to be operated on based on a preset row storage method; and,

[0124] The column storage subunit is used to store the second submatrix of the second matrix to be operated on based on a preset column storage method.

[0125] The matrix multiplication operation execution device provided in this embodiment of the invention can execute a matrix multiplication operation execution method provided in any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0126] Example 4

[0127] Figure 4A schematic diagram of an electronic device 400 that can be used to implement embodiments of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0128] like Figure 4 As shown, the electronic device 400 includes at least one processor 410 and a memory, such as a read-only memory (ROM) 420 or a random access memory (RAM) 430, communicatively connected to the at least one processor 410. The memory stores computer programs executable by the at least one processor. The processor 410 can perform various appropriate actions and processes based on the computer program stored in the ROM 420 or loaded from storage unit 480 into the RAM 430. The RAM 430 may also store various programs and data required for the operation of the electronic device 400. The processor 410, RAM 420, and RAM 430 are interconnected via a bus 440. An input / output (I / O) interface 450 is also connected to the bus 440.

[0129] Multiple components in electronic device 400 are connected to I / O interface 450, including: input unit 460, such as keyboard, mouse, etc.; output unit 470, such as various types of monitors, speakers, etc.; storage unit 480, such as disk, optical disk, etc.; and communication unit 490, such as network card, modem, wireless transceiver, etc. Communication unit 490 allows electronic device 400 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0130] Processor 410 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 410 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 410 performs the various methods and processes described above, such as a matrix multiplication operation execution method.

[0131] In some embodiments, a matrix multiplication operation execution method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 480. In some embodiments, part or all of the computer program may be loaded and / or installed on electronic device 400 via (RAM) 420 and / or communication unit 490. When the computer program is loaded into (RAM) 430 and executed by processor 410, one or more steps of the matrix multiplication operation execution method described above may be performed. Alternatively, in other embodiments, processor 410 may be configured to execute a matrix multiplication operation execution method by any other suitable means (e.g., by means of firmware).

[0132] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0133] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0134] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0135] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0136] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or computing systems that include middleware components (e.g., application servers), or computing systems that include frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0137] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0138] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0139] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for performing matrix multiplication, characterized in that, include: In response to a matrix multiplication operation instruction, obtain the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated; Based on the cache space capacity, the block size for matrix partitioning is determined, including: determining the number of matrix partitioning operations based on the matrix dimension size of the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated; and determining the block size of the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated in different dimensions under each number of matrix partitioning operations based on the cache space capacity. Based on the block size, the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated are divided into blocks to obtain the first sub-matrix of the first matrix to be operated on, the second sub-matrix of the second matrix to be operated on, and the third sub-matrix of the initial matrix to be updated, respectively. Based on the block size, a storage vector register and a pre-stored vector register are selected from each vector register, including: determining the storage vector registers for storing the first sub-matrix, second sub-matrix, and third sub-matrix in the current operation cycle based on the block size of the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated under the last matrix block count; selecting the pre-stored vector registers for storing the first sub-matrix and second sub-matrix in the next operation cycle based on the number of registers in the storage vector registers; the storage vector registers are used to store the first sub-matrix, second sub-matrix, and third sub-matrix in the current operation cycle; the pre-stored vector registers are used to store the first sub-matrix and second sub-matrix in the next operation cycle; The corresponding submatrices are sequentially retrieved from the storage vector register and the pre-stored vector register for matrix multiplication until the operation termination condition is met, and the result of the matrix multiplication operation is obtained.

2. The method according to claim 1, characterized in that, The step of dividing the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated into matrix blocks according to the block size, to obtain a first sub-matrix of the first matrix to be operated on, a second sub-matrix of the second matrix to be operated on, and a third sub-matrix of the initial matrix to be updated, includes: Based on the block size of the first matrix to be operated, the second matrix to be operated, and the initial matrix to be updated under different dimensions according to the number of times the matrix is ​​divided into blocks, the first matrix to be operated, the second matrix to be operated, and the initial matrix to be updated are divided into blocks to obtain the first block matrix of the first matrix to be operated, the second block matrix of the second matrix to be operated, and the third block matrix of the initial matrix to be updated under the number of times the matrix is ​​divided into blocks. The first block matrix of the first matrix to be operated on under the last matrix block number is determined as the first submatrix, the second block matrix of the second matrix to be operated on is determined as the second submatrix, and the third block matrix of the initial matrix to be updated is determined as the third submatrix.

3. The method according to claim 1, characterized in that, The step of determining the storage vector registers for storing the first sub-matrix, second sub-matrix, and third sub-matrix in the current operation cycle based on the block size of the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated under the last matrix block number includes: Based on the block size of the first matrix to be operated on under the last matrix block count, determine the first storage vector register used to store the first sub-matrix under the current operation cycle; Based on the block size of the second matrix to be operated on under the last matrix block count, determine the second storage vector register used to store the second sub-matrix under the current operation cycle; Based on the block size of the initial matrix to be updated under the last matrix block count, determine the third storage vector register used to store the third submatrix under the current operation cycle; The first storage vector register, the second storage vector register, and the third storage vector register are defined as storage registers.

4. The method according to claim 3, characterized in that, The step of selecting a pre-stored vector register from the vector registers to store the first and second sub-matrices for the next operation cycle, based on the number of registers in the storage vector registers, includes: Based on the number of first registers in the first storage vector register, select the first pre-stored vector register from each vector register to store the first sub-matrix in the next operation cycle; Based on the number of second registers in the second storage vector register, a second pre-stored vector register for storing the second sub-matrix in the next operation cycle is selected from each vector register.

5. The method according to claim 1, characterized in that, After dividing the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated into matrix blocks according to the block size, to obtain the first sub-matrix of the first matrix to be operated on, the second sub-matrix of the second matrix to be operated on, and the third sub-matrix of the initial matrix to be updated, the method further includes: The first submatrix of the first matrix to be operated on is stored according to a preset row storage method; and, The second submatrix of the second matrix to be operated on is stored based on a preset column storage method.

6. A matrix multiplication operation execution device, characterized in that, include: The matrix acquisition module is used to acquire the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated in response to the matrix multiplication operation command; The block step size determination module is used to determine the block step size for matrix block division based on the cache space capacity. The block step size determination module includes: a block number determination unit, used to determine the number of matrix blocks based on the matrix dimension size of the first matrix to be operated, the second matrix to be operated, and the initial matrix to be updated; and a block step size determination unit, used to determine the block step size of the first matrix to be operated, the second matrix to be operated, and the initial matrix to be updated in different dimensions under each matrix block number, based on the cache space capacity. The submatrix acquisition module is used to perform matrix partitioning on the first matrix to be operated on, the second matrix to be operated on, and the initial matrix to be updated according to the block step size, so as to obtain the first submatrix of the first matrix to be operated on, the second submatrix of the second matrix to be operated on, and the third submatrix of the initial matrix to be updated, respectively. A register selection module is used to select a storage vector register and a pre-stored vector register from each vector register according to the block size; the storage vector register is used to store the first sub-matrix, the second sub-matrix, and the third sub-matrix in the current operation cycle; the pre-stored vector register is used to store the first sub-matrix and the second sub-matrix in the next operation cycle; the register selection module includes: a storage register determination subunit, used to determine the storage vector registers for storing the first sub-matrix, the second sub-matrix, and the initial sub-matrix to be updated in the current operation cycle according to the block size of the first sub-matrix, the second sub-matrix, and the initial sub-matrix to be updated in the last matrix block count; and a pre-stored vector register determination subunit, used to select the pre-stored vector registers for storing the first sub-matrix and the second sub-matrix in the next operation cycle from each vector register according to the number of registers in the storage vector registers; The result acquisition module is used to sequentially retrieve the corresponding submatrices from the storage vector register and the pre-stored vector register to perform matrix multiplication operations until the operation termination condition is met, and then obtain the matrix multiplication result.

7. An electronic device, characterized in that, include: One or more processors; Memory, used to store one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement a matrix multiplication operation execution method as described in any one of claims 1-5.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements a matrix multiplication operation execution method as described in any one of claims 1-5.

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