Context switching systems, methods, electronic devices, and computer storage media

Abstract

The application discloses a context switching system, method, electronic device and computer storage medium, the system comprises: a processor configured to send a task request to a target coprocessor, transfer first context information of a first processing task from a general register group included in the processor to a backup register, and control the backup register to transfer the first context information to a memory; the coprocessor is configured to execute a first subtask included in the first processing task after receiving the task request, and send a context switching request to the processor after the execution ends; the processor is further configured to control the backup register to obtain the first context information from the memory after receiving the context switching request, and obtain the first context information from the backup register when in an idle state, and restore the first processing task according to the first context information. The application improves the efficiency of context information transfer by setting the backup register with a bit width greater than that of the memory.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and in particular to a context switching system, method, electronic device, and computer storage medium. Background Technology

[0002] A master-slave architecture multi-tasking, multi-core processing system provides a general-purpose register set within the processor, consisting of multiple general-purpose registers, to simultaneously store and process multiple data sets. During data processing, this system accelerates task processing by offloading specific tasks from the processor to a co-processor engine (CoPE). Because the processor must wait for the coprocessor to return during processing, it cannot handle that task. To improve multi-tasking efficiency, the processor can be switched to handle other tasks, thus increasing data processing efficiency.

[0003] Currently, task switching in the processor is mainly achieved through context switching. The context of a task that is offloaded to the coprocessor engine is stored in memory, and after the coprocessor engine finishes processing, the context of that task is swapped from memory to the processor.

[0004] However, when the processor needs to switch the context in the general-purpose registers and the context in memory, the clock cycle for context switching is longer because the bit width of the general-purpose register set and the memory are different. Summary of the Invention

[0005] In view of this, this application provides a context switching system, method, electronic device, and computer storage medium to solve the technical problem that the inconsistent bit width between the general-purpose register group and the memory in conventional solutions leads to a long clock cycle for context switching.

[0006] This application provides a context switching system, comprising: a processor, a backup register, a plurality of coprocessors, and a memory; the processor is configured to determine a target coprocessor for processing the first subtask from the plurality of coprocessors based on a first subtask included in a first processing task, send a task request to the target coprocessor, transfer first context information of the first processing task from a general-purpose register group included in the processor to the backup register, and control the backup register to transfer the first context information to the memory, wherein the first context information is generated by the processor after processing a second subtask included in the first processing task, the second subtask being a preceding task of the first subtask, and the bit width of the backup register being greater than the bit width of the memory; the coprocessors are configured to execute the first subtask included in the first processing task after receiving the task request, and send a context switching request to the processor after execution; the processor is further configured to control the backup register to retrieve the first context information from the memory after receiving the context switching request, and when in an idle state, retrieve the first context information from the backup register according to the context switching request, and restore the first processing task according to the first context information.

[0007] Optionally, the bit width of the backup register is equal to the bit width of the general-purpose register group.

[0008] Optionally, the processor is configured to write the address information of the first context information stored in the memory into the cut-out queue after controlling the backup register to transfer the first context information to the memory; the coprocessor is configured to obtain the address information from the cut-out queue after receiving the task request, and execute the first subtask included in the first processing task when it is in an idle state.

[0009] Optionally, the coprocessor is configured to write the address information into the switching queue after executing the first subtask included in the first processing task; the processor is configured to obtain the address information from the switching queue after receiving the context switching request, and control the backup register to obtain the first context information from the memory according to the address information.

[0010] Optionally, the processor is configured to transfer the first context information from the backup register to the storage area in the memory corresponding to the task number information of the first processing task according to the task number information of the first processing task, and write the task number information of the first processing task into the cut-out queue; the coprocessor is configured to obtain the task number information from the cut-out queue after receiving the task request, and execute the first sub-task included in the first processing task when it is in an idle state.

[0011] Optionally, the coprocessor is configured to write the task number information into the switching queue after executing the first subtask included in the first processing task; the processor is configured to obtain the task number information from the switching queue after receiving the context switching request, and control the backup register to obtain the first context information from the memory according to the task number information.

[0012] Optionally, the processor is configured to receive and process a second processing task after transferring the first context information from the general-purpose register group to the backup register, and to obtain the first context information from the backup register and restore the first processing task according to the first context information when the second processing task is switched out or completed.

[0013] A second aspect of this application provides a context switching method applied to a processor including a general-purpose register set, comprising: determining a target coprocessor for processing the first subtask from a plurality of coprocessors based on a first subtask included in a first processing task; sending a task request to the target coprocessor and transferring first context information of the first processing task from the general-purpose register set included in the processor to a backup register, wherein the first context information is generated by the processor after processing a second subtask included in the first processing task, the second subtask being a preceding task of the first subtask, and the bit width of the backup register being greater than the bit width of the memory; upon receiving the context switching request, controlling the backup register to retrieve the first context information from the memory; when in an idle state, retrieving the first context information from the backup register according to the context switching request; and resuming the first processing task based on the first context information.

[0014] According to a third aspect of the present application, an electronic device is provided, including: a processor, a communication interface, a memory, and a communication bus, wherein the processor, the memory, and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, which causes the processor to perform the operation corresponding to the method described in the second aspect of the present application.

[0015] According to a fourth aspect of the present application, a computer storage medium is provided that stores a computer program thereon, which, when executed by a processor, implements the method described in the second aspect of the present application.

[0016] This application utilizes a backup register with a bit width greater than that of the memory. Therefore, the efficiency of context information transfer between the processor and the backup register is higher than that of direct context information transfer between the processor and memory, resulting in more efficient context switching. Furthermore, since the processor controls the backup register to retrieve the first context information from memory upon receiving a context switch request, pre-recovery of the first processing task is achieved. Once the processor is idle, it can directly retrieve the first context information from the backup register, further improving the efficiency of context switching. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0018] Figure 1 This is a schematic diagram of the structure of a context switching system according to an embodiment of this application;

[0019] Figure 2 This is a schematic diagram of a context switching system performing multitasking according to an embodiment of this application;

[0020] Figure 3 This is a flowchart of the steps of a context switching method according to an embodiment of this application;

[0021] Figure 4 This is a schematic diagram of the structure of an electronic device according to an embodiment of this application. Detailed Implementation

[0022] To enable those skilled in the art to better understand the technical solutions in the embodiments of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art should fall within the protection scope of the embodiments of this application.

[0023] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0024] It should be understood that although the terms first, second, third, etc., may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to determination."

[0025] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In the absence of conflict, the following embodiments and their technical features can be combined with each other.

[0026] Register-based computer architecture is a common computer architecture that uses multiple general-purpose registers to store and process data. Due to its high efficiency, flexibility, and scalability, this architecture is widely used in various application scenarios. In register-based computer architecture, general-purpose registers are one of the core components, and the data within them can be accessed through register numbers or register names. Typically, register-based computer architectures provide multiple general-purpose registers forming a general-purpose register set to store and process multiple data simultaneously. These general-purpose registers can store different types of data such as integers, floating-point numbers, and pointers, as well as data such as communication addresses.

[0027] In a master-slave architecture multi-tasking, multi-core processing system, offloading specific tasks from the processor to a co-processor engine (CoPE) is a crucial method for accelerating task processing. Context plays a vital role in this acceleration process. Context encompasses the environment and state information of the program execution during task processing. This information can include variable values, function call details, execution location, etc., providing necessary support for correct code execution. After offloading a specific task to the co-processor engine, a context switch is required between the processor and external memory to ensure the co-processor can handle related tasks correctly and to ensure the processor can resume tasks. When the processor decides to run another task, it saves the context of the currently running task and performs a context switch to store this information in external memory. After the context switch is complete, the processor reloads the context of the next task to be run from memory into general-purpose registers and begins execution of the next task. However, when the processor switches the context in general-purpose registers from the context in memory, the inconsistent bit widths of the general-purpose register set and memory result in a long clock cycle for the context switch. Therefore, this application proposes a context switching system, method, electronic device, and computer storage medium to solve the above-mentioned problems.

[0028] Figure 1 This is a schematic diagram of the structure of a context switching system according to an embodiment of this application, as shown below. Figure 1 As shown. The context switching system 100 includes: a processor 101, a backup register 102, multiple coprocessors 103, and a memory 104.

[0029] The processor 101 is configured to determine a target coprocessor for processing the first subtask from a plurality of coprocessors 103 based on the first subtask included in the first processing task, send a task request to the target coprocessor, transfer the first context information of the first processing task from the general-purpose register group included in the processor 101 to the backup register 102, and control the backup register 102 to transfer the first context information to the memory 104, wherein the first context information is generated by the processor 101 after processing the second subtask included in the first processing task, the second subtask being the preceding task of the first subtask, and the bit width of the backup register 102 is greater than the bit width of the memory 104.

[0030] The coprocessor 103 is configured to execute a first subtask included in the first processing task after receiving a task request, and send a context switching request to the processor 101 after the execution is completed.

[0031] The processor 101 is also configured to control the backup register 102 to obtain first context information from the memory 104 after receiving a context switching request, and to obtain the first context information from the backup register 102 when in an idle state, and to restore the first processing task according to the first context information.

[0032] During task processing, the first processing task may include multiple subtasks that require different operations, such as second subtask A, first subtask B, and second subtask C. For processor 101, the efficiency of executing different subtasks is not the same. To improve the processing efficiency of processor 101, multiple coprocessors 103 are provided in the context switching system 100. Each coprocessor 103 is configured to process a specific subtask; that is, each coprocessor 103 can process a specific subtask with high efficiency. Therefore, when processor 101 processes the first subtask B included in the first processing task, it can select from the multiple coprocessors 103. The target coprocessor is used to process the first subtask B. After that, the processor 101 is unable to continue executing the first processing task, so it needs to switch the first context information generated after processing the second subtask A in the first processing task to the memory 104. After that, the target coprocessor can process the first subtask B. After the target coprocessor processes the first subtask B, the processor 101 needs to restore the first processing task. Therefore, it needs to perform another context switch with the memory 104 so that the processor 101 can regain the first context information and restore the first processing task according to the first context information. After that, the processor 101 can process the second subtask C.

[0033] To improve the efficiency of context switching, a backup register 102 is provided in the context switching system 100, and the bit width of the backup register 102 is larger than the bit width of the memory 104. Therefore, when a context switch is required, the processor 101 needs to transfer the first context information to the backup register 102, and then transfer the first context information from the backup register 102 to the memory 104. After the coprocessor 103 processes the first subtask B, it sends a context switch request to the processor 101. When the processor 101 receives the context switch request, it controls the backup register 102 to retrieve the first context information from the memory 104. When the processor 101 is in an idle state, it retrieves the first context information from the backup register 102.

[0034] In this embodiment, because a backup register 102 with a bit width greater than that of memory 104 is provided, the context information transfer efficiency between processor 101 and backup register 102 is higher than that between processor 101 and memory 104, thus making the context switching of processor 101 more efficient. For example, if the general-purpose register group of processor 101 includes 32 general-purpose registers with a bit width of 16 bits and memory 104 has a bit width of 64 bits, then the context information transfer consumes at least 16 clock cycles. If a backup register 102 with a bit width of 128 bits is provided, the context information transfer is shortened to consume at least 8 clock cycles. In addition, since processor 101 controls backup register 102 to obtain the first context information from memory 104 after receiving a context switching request, the pre-recovery of the first processing task can be realized. When processor 101 is in an idle state, it can directly obtain the first context information from backup register 102, thereby further improving the efficiency of context switching.

[0035] In one possible implementation, the bit width of backup register 102 is equal to the bit width of the general-purpose register set.

[0036] In this embodiment, by setting the bit width of the backup register 102 to be equal to the bit width of the general-purpose register group, data exchange between the backup register 102 and the general-purpose register group can be completed within one clock cycle, thereby improving the efficiency of context switching.

[0037] In one possible implementation, the processor 101 can also be used to write the address information of the first context information stored in the memory 104 into the cut-out queue after the control backup register 102 transfers the first context information to the memory 104.

[0038] The coprocessor 103 can also be used to obtain address information from the cut-out queue after receiving a task request, and to execute the first subtask included in the first processing task when it is in an idle state.

[0039] After the processor 101 controls the backup register 102 to transfer the first context information to the memory 104, the address information of the general-purpose register group stored in the processor 101 can be written into the cut-out queue. After the target coprocessor receives the task request sent by the processor 101, it obtains the address information from the cut-out queue, and then executes the first subtask included in the first processing task when it is in an idle state, that is, when it has sufficient processing resources.

[0040] It should be noted that the address information does not play a role in the task processing of the target coprocessor, but the target coprocessor needs to obtain the address information to provide it to the processor 101 when the processor 101 resumes the task, so as to improve the efficiency of the processor 101 in controlling the backup register 102 to obtain the first context information from the memory 104.

[0041] In this embodiment of the application, by writing the address information of the first context information in the processor 101 into the switchout queue, the storage location of the first context information in the processor 101 can be retained in the switchout queue, providing a specific location for obtaining the first context information for subsequent task recovery, which can improve the efficiency of context switching.

[0042] In one possible implementation, the coprocessor 103 can also be used to write address information into the cut-in queue after executing the first subtask included in the first processing task.

[0043] The processor 101 can also be used to obtain address information from the switching queue after receiving a context switching request, and control the backup register to obtain the first context information from the memory according to the address information.

[0044] After executing the first subtask included in the first processing task, the target coprocessor writes the address information into the switching queue. After the processor 101 receives the context switching request, it retrieves the address information from the switching queue. Then, it can control the backup register 102 to retrieve the first context information from the memory 104 according to the address information, thereby realizing the pre-recovery of the first processing task.

[0045] In this embodiment of the application, by writing the address information into the switching queue, the processor 101 can control the backup register 102 to obtain the first context information from the memory 104 according to the address information to perform the pre-recovery of the first processing task. When the processor 101 is in an idle state, it can directly obtain the first context information from the backup register 102, thereby improving the efficiency of context switching.

[0046] In one possible implementation, the processor 101 can also be used to transfer the first context information from the backup register 102 to the storage area in the memory 104 corresponding to the task number information of the first processing task, and write the task number information of the first processing task into the cut-out queue, based on the task number information of the first processing task.

[0047] The coprocessor 103 can also be used to obtain task number information from the cut-out queue after receiving a task request, and execute the first subtask included in the first processing task when it is in an idle state.

[0048] In memory 104, different storage areas can be divided according to the task number of the processing task. When processor 101 controls backup register 102 to transfer the first context information to memory 104, the first context information can be stored in the storage area of ​​memory 104 corresponding to the task number information of the first processing task, and the task number information is written into the cut-out queue. After the target coprocessor receives the task request sent by processor 101, it first receives the task number information sent by the cut-out queue, and then, when it is in an idle state, that is, when it has sufficient processing resources, it executes the first sub-task included in the first processing task.

[0049] It should be noted that the task number information does not play a role in the task processing of the target coprocessor, but the target coprocessor needs to obtain the task number information in order to provide it to the processor 101 when the processor 101 resumes the task, so as to improve the efficiency of the processor 101 in obtaining the first context information.

[0050] In this embodiment of the application, by dividing the memory 104 into a storage area corresponding to the task number information, the processor 101 can directly obtain the first context information from the corresponding storage area according to the task number information when controlling the backup register 102 to obtain the first context information from the memory 104, thereby improving the efficiency of context switching.

[0051] In one possible implementation, the coprocessor 103 can also be used to write task number information into the cut-in queue after executing the first subtask included in the first processing task.

[0052] The processor 101 can also be used to obtain task number information from the switching queue after receiving a context switching request, and control the backup register 102 to obtain the first context information from the memory 104 according to the task number information.

[0053] After the target coprocessor executes the first subtask included in the first processing task, the target coprocessor writes the task number information into the switching queue. After the processor 101 receives the context switching request sent by the target coprocessor, it retrieves the task number information from the switching queue and controls the backup register 102 to quickly retrieve the first context information from the storage area of ​​the corresponding task number information in the memory 104 according to the task number information. Afterwards, when the processor 101 is in an idle state, that is, when it has sufficient processing resources, it retrieves the first context information from the backup register 102.

[0054] In this embodiment, since the coprocessor 103 writes the task number information into the switching queue, after the processor 101 receives the context switching request, it obtains the task number information from the switching queue. This allows the processor 101 to directly obtain the first context information from the corresponding storage area based on the task number information when controlling the backup register 102 to obtain the first context information from the memory 104, thereby improving the efficiency of context switching.

[0055] In one possible implementation, the processor 101 can also be used to receive and process the second processing task after transferring the first context information from the general-purpose register set to the backup register 102, and to obtain the first context information from the backup register 102 when the second processing task is switched out or completed, and to restore the first processing task according to the first context information.

[0056] For example, such as Figure 2 As shown, processor 101 can first process subtask A in task 1. After processing, if the target coprocessor needs to process subtask B, it generates first context information and transfers it from the general-purpose register set to the backup register 102. At this time, the processor is in an idle state. While waiting for the target coprocessor to process subtask B, it can switch to task 2 for processing. After the target coprocessor finishes processing subtask B, it sends a context switch request to processor 101. Then, processor 101 receives the context switch request, controls the backup register 102 to obtain the first context information from memory 104, and after processor 101 finishes processing task 2, it obtains the first context information from the backup register 102, and then restores task 1 according to the first context information to continue processing subtask C.

[0057] In this embodiment of the application, after the processor 101 transfers the first context information from the general-purpose register set to the backup register 102, it can receive and process the second processing task, thereby improving the utilization of the processor 101.

[0058] Figure 3 This is a flowchart of the steps of a context switching method according to an embodiment of this application, as follows: Figure 3 As shown, the context switching method includes the following steps:

[0059] Step 301: Based on the first subtask included in the first processing task, determine the target coprocessor for processing the first subtask from among multiple coprocessors.

[0060] Step 302: Send a task request to the target coprocessor and transfer the first context information of the first processing task from the general-purpose register group included in the processor to the backup register.

[0061] Step 303: After receiving the context switch request, control the backup register to obtain the first context information from the memory.

[0062] Step 304: When in an idle state, obtain the first context information from the backup register according to the context switch request.

[0063] Step 305: Restore the first processing task based on the first context information.

[0064] During task processing, the first processing task may include multiple subtasks that require different operations, such as second subtask A, first subtask B, and second subtask C. For the processor, the efficiency of executing different subtasks is not the same. In order to improve the processor's processing efficiency, multiple coprocessors are set up in the context switching system. Each coprocessor is set to process a certain subtask, that is, the coprocessor can process a certain subtask with high processing efficiency. Therefore, when the processor processes the first subtask B included in the first processing task, it can determine the target coprocessor for processing the first subtask B from among the multiple coprocessors. Afterwards, since the processor cannot continue to execute the first processing task, it needs to switch the first context information generated after processing the second subtask A in the first processing task to memory. Then the target coprocessor can process the first subtask B. After the target coprocessor processes the first subtask B, the processor needs to restore the first processing task. Therefore, it needs to perform another context switch with memory to allow the processor to regain the first context information and restore the first processing task according to the first context information. Afterwards, the processor can process the second subtask C.

[0065] To improve the efficiency of context switching, a backup register can be set up, with a bit width larger than that of memory. Therefore, when a context switch is required, the processor needs to transfer the first context information to the backup register, and then transfer the first context information from the backup register to memory. After the coprocessor processes the first subtask B, it sends a context switch request to the processor. When the processor receives the context switch request, it controls the backup register to retrieve the first context information from memory. When the processor is idle, it retrieves the first context information from the backup register.

[0066] In this embodiment, since the processor controls the backup register to obtain the first context information from the memory after receiving the context switching request, the pre-recovery of the first processing task can be achieved. After the processor is in an idle state, it can directly obtain the first context information from the backup register, thereby further improving the efficiency of context switching.

[0067] In this embodiment, an electronic device 400 is provided, such as... Figure 4As shown, the electronic device 400 may include: a processor 401, a communications interface 402, a memory 403, and a communication bus 404. Wherein:

[0068] The processor 401, communication interface 402, and memory 403 communicate with each other through the communication bus 404.

[0069] Communication interface 402 is used for communication with other electronic devices or servers.

[0070] The processor 401 is used to execute program 405, specifically to perform the relevant steps in the aforementioned context switching method embodiment.

[0071] Specifically, program 405 may include program code that includes computer operation instructions.

[0072] Processor 401 may be a CPU, an Application Specific Integrated Circuit (ASIC), or configured as one or more integrated circuits. A smart device may include one or more processors, which can be of the same type, such as one or more CPUs; or they may be of different types, such as one or more CPUs and one or more ASICs.

[0073] Memory 403 is used to store program 405. Memory 403 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.

[0074] Specifically, program 404 can be used to cause processor 401 to execute the context switching method in the foregoing embodiments.

[0075] The specific implementation of each step in program 404 can be found in the corresponding steps and units described in the foregoing context switching method embodiments, and will not be repeated here. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the devices and modules described above can be referred to the corresponding process descriptions in the foregoing method embodiments, and will not be repeated here.

[0076] The electronic device 400 of this application embodiment, by providing a backup register with a bit width greater than that of the memory, achieves higher efficiency in context information transfer between the processor and the backup register compared to direct context information transfer between the processor and memory, thereby enhancing the efficiency of processor context switching. Furthermore, since the processor controls the backup register to retrieve the first context information from memory upon receiving a context switching request, pre-recovery of the first processing task is achieved. This allows the processor to directly retrieve the first context information from the backup register when it is in an idle state, further improving the efficiency of context switching.

[0077] In this embodiment, a computer-readable storage medium is provided, storing instructions for causing a machine to perform a context switching method as described herein. Specifically, a system or apparatus equipped with a storage medium storing software program code that implements the functions of any of the embodiments described above, and enabling the computer (or CPU or MPU) of the system or apparatus to read and execute the program code stored in the storage medium.

[0078] In this case, the program code read from the storage medium can itself implement the functions described in the above method embodiments, so the program code and the storage medium storing the program code constitute a part of this application.

[0079] Examples of storage media used to provide program code include floppy disks, hard disks, magneto-optical disks, optical disks (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), magnetic tapes, non-volatile memory cards, and ROMs. Alternatively, program code can be downloaded from a server computer via a communication network.

[0080] In this embodiment, a computer program product is provided, including computer instructions that instruct a computing device to perform the operations corresponding to the above-described method embodiments.

[0081] It should be noted that, depending on the implementation needs, the various components / steps described in the embodiments of this application can be broken down into more components / steps, or two or more components / steps or parts of the operation of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of this application.

[0082] The methods described above according to embodiments of this application can be implemented in hardware, firmware, or implemented as software or computer code that can be stored in a recording medium (such as CD ROM, RAM, floppy disk, hard disk, or magneto-optical disk), or implemented as computer code originally stored in a remote recording medium or a non-transitory machine-readable medium and to be stored in a local recording medium after being downloaded via a network. Thus, the methods described herein can be processed by software stored on a recording medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware (such as an ASIC or FPGA). It is understood that the computer, processor, microprocessor controller, or programmable hardware includes storage components (e.g., RAM, ROM, flash memory, etc.) capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods described herein. Furthermore, when a general-purpose computer accesses code used to implement the methods shown herein, the execution of the code transforms the general-purpose computer into a dedicated computer for performing the methods shown herein. Although this application has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art based on a reading and understanding of this specification and the accompanying drawings. This application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the aforementioned components, the terminology used to describe such components is intended to correspond to any component (unless otherwise indicated) that performs the specified function of said component (e.g., is functionally equivalent to it), even if it is not structurally equivalent to the disclosed structure that performs the functions in the exemplary implementations of this specification shown herein.

[0083] That is, the above description is only an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, such as the combination of technical features between different embodiments, or direct or indirect application in other related technical fields, are similarly included within the patent protection scope of this application.

[0084] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0085] The above description is provided to enable any person skilled in the art to implement and use this application. Various details are set forth in the above description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be implemented without using these specific details. In other embodiments, well-known processes will not be described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed herein.

[0086] It should be noted that, without conflict, the various embodiments and / or technical features described in this application can be arbitrarily combined with each other, and the resulting technical solutions should also fall within the protection scope of this application.

[0087] It should be understood that the specific examples in the embodiments of this application are only for the purpose of helping those skilled in the art to better understand the embodiments of this application, and are not intended to limit the scope of the embodiments of this application. Those skilled in the art can make various improvements and modifications based on the above embodiments, and all such improvements or modifications fall within the protection scope of this application.

[0088] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A context switching system, characterized in that, include: Processor, backup registers, multiple coprocessors, and memory; The processor is configured to determine a target coprocessor for processing the first subtask from among the plurality of coprocessors based on the first subtask included in the first processing task, send a task request to the target coprocessor, transfer the first context information of the first processing task from the general-purpose register group included in the processor to the backup register, and control the backup register to transfer the first context information to the memory, wherein the first context information is generated by the processor after processing the second subtask included in the first processing task, the second subtask being the preceding task of the first subtask, and the bit width of the backup register being greater than the bit width of the memory; The coprocessor is configured to execute the first subtask included in the first processing task after receiving the task request, and send a context switching request to the processor after the execution is completed. The processor is further configured to, upon receiving the context switching request, control the backup register to obtain the first context information from the memory, and, when in an idle state, obtain the first context information from the backup register and restore the first processing task based on the first context information.

2. The system according to claim 1, characterized in that, The bit width of the backup register is equal to the bit width of the general-purpose register group.

3. The system according to claim 1, characterized in that, The processor is configured to write the address information of the first context information stored in the memory into the cut-out queue after controlling the backup register to transfer the first context information to the memory; The coprocessor is configured to obtain the address information from the cut-out queue after receiving the task request, and execute the first sub-task included in the first processing task when it is in an idle state.

4. The system according to claim 3, characterized in that, The coprocessor is configured to write the address information into the inbound queue after executing the first subtask included in the first processing task. The processor is configured to, upon receiving the context switching request, obtain the address information from the switching queue and control the backup register to obtain the first context information from the memory based on the address information.

5. The system according to claim 1, characterized in that, The processor is configured to transfer the first context information from the backup register to the storage area in the memory corresponding to the task number information of the first processing task according to the task number information of the first processing task, and write the task number information of the first processing task into the cut-out queue. The coprocessor is configured to obtain the task number information from the cut-out queue after receiving the task request, and execute the first sub-task included in the first processing task when it is in an idle state.

6. The system according to claim 5, characterized in that, The coprocessor is configured to write the task number information into the inbound queue after executing the first subtask included in the first processing task. The processor is configured to, upon receiving the context switching request, obtain the task number information from the switching queue and control the backup register to obtain the first context information from the memory based on the task number information.

7. The system according to claim 1, characterized in that, The processor is configured to receive and process a second processing task after transferring the first context information from the general-purpose register group to the backup register, and to obtain the first context information from the backup register and restore the first processing task according to the first context information when the second processing task is switched out or completed.

8. A context switching method applied to a processor including a general-purpose register set, characterized in that, include: Based on the first subtask included in the first processing task, a target coprocessor for processing the first subtask is determined from a plurality of coprocessors; A task request is sent to the target coprocessor, and the first context information of the first processing task is transferred from the general-purpose register group included in the processor to a backup register. The first context information is generated by the processor after processing the second subtask included in the first processing task. The second subtask is the preceding task of the first subtask. The bit width of the backup register is greater than the bit width of the memory. Upon receiving a context switching request, the backup register is controlled to retrieve the first context information from the memory; When in an idle state, the first context information is obtained from the backup register according to the context switching request; The first processing task is restored based on the first context information.

9. An electronic device, characterized in that, include: The processor, communication interface, memory, and communication bus communicate with each other through the communication bus. The memory is used to store at least one executable instruction that causes the processor to perform the operation corresponding to the method described in claim 8.

10. A computer storage medium having a computer program stored thereon, which, when executed by a processor, implements the method of claim 8.

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