Method, device and equipment for determining abnormal loading of memory data in intelligent network card and medium
By detecting the address read/write consistency and handshake signal timing of the smart network card memory chips, the problem of inaccurate DRAM damage in existing technologies has been solved, enabling precise location of damaged DRAM memory chips and improving system stability and data transmission efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INSPUR SUZHOU INTELLIGENT TECH CO LTD
- Filing Date
- 2023-12-22
- Publication Date
- 2026-07-14
AI Technical Summary
Existing intelligent network interface card (NIC) memory data loading anomaly detection solutions cannot accurately locate the specific memory chip that is damaged in the DRAM, which affects system stability and data transmission efficiency.
By detecting the memory chips connected to each programmable input/output unit block in the field-programmable gate array chip of the smart network card, it is determined whether they meet the fault conditions of address read/write inconsistency and/or handshake signal timing inconsistency with the preset timing, thereby determining that there is a fault in the memory chip.
It can accurately locate the specific memory chip that is damaged in DRAM, improving system stability and data transmission efficiency, reducing CPU load, and meeting the needs of large-scale data centers and cloud computing.
Smart Images
Figure CN117785529B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of smart network interface card (NIC) technology, and in particular to a method, apparatus, device, and medium for determining abnormal memory data loading in a smart NIC. Background Technology
[0002] As data center network performance demands increase and data center scale expands, the need for improved network performance also grows. Traditional network interface cards (NICs) have limited processing capabilities and cannot meet the needs of large-scale data centers. Furthermore, with the development of cloud computing and edge computing, these technologies place higher demands on the utilization of computing resources. Traditional NIC processing methods consume significant CPU resources, impacting computing efficiency. Smart NICs, through hardware acceleration and offloading technologies, significantly improve network performance. Moreover, smart NICs can offload some network processing tasks, reducing CPU load and improving the utilization of computing resources.
[0003] The relationship between smart network interface cards (NICs) and dynamic random access memory (DRAM) is very close; they work together to support network data transmission and processing. Currently, detection methods for abnormal memory data loading in smart NICs generally include hardware and software detection methods. However, neither of these methods can pinpoint the specific damaged DRAM memory chip. Summary of the Invention
[0004] The purpose of this application is to provide a method, apparatus, device, and medium for determining abnormal memory data loading in a smart network card, used to locate the specific memory chip that is damaged in the DRAM.
[0005] This application provides a method for determining abnormal data loading in the memory of a smart network interface card (NIC), including:
[0006] For each memory chip connected to each programmable input / output unit block in the field-programmable gate array chip of the smart network card, detect whether the memory chip meets the fault conditions; the fault conditions include address read / write inconsistency of the memory chip and / or handshake signal timing of the memory chip being inconsistent with the preset timing.
[0007] If the memory chip meets the fault conditions, it is determined that the memory chip is faulty, thereby determining that the smart network card memory data loading is abnormal.
[0008] Optionally, detecting whether the memory chip meets the fault conditions includes:
[0009] Simultaneously, it detects whether the address read / write of each memory chip connected to the multiple programmable input / output unit blocks is inconsistent, and whether the handshake signal timing of the memory chip is inconsistent with the preset timing.
[0010] Optionally, detecting whether the memory chip meets the fault conditions includes:
[0011] Detect whether the handshake signal timing of the memory chip is inconsistent with the preset timing;
[0012] If the handshake signal timing of the memory chip is consistent with the preset timing, detect whether the address of the memory chip is inconsistent between read and write operations.
[0013] Optionally, detecting whether the memory chip meets the fault conditions, and determining that the memory chip is faulty if the memory chip meets the fault conditions, includes:
[0014] Write and read operations are performed sequentially on multiple addresses of the memory chip via the data bus connected to the memory chip.
[0015] The consistency of the first write operation result and the first read operation result corresponding to each address of the memory particle is compared to obtain the first comparison result;
[0016] If the first comparison result is inconsistent, troubleshooting should be performed on the data bus.
[0017] If the data bus is found to be fault-free, troubleshooting is performed on the address corresponding to the first comparison result.
[0018] If there is no fault at the address corresponding to the first comparison result, write and read operations are sequentially performed on multiple addresses of the memory chip through the address bus connected to the memory chip;
[0019] The consistency of the second write operation result and the second read operation result corresponding to each address of the memory particle is compared to obtain the second comparison result;
[0020] If the second comparison result is inconsistent, troubleshooting should be performed on the address bus.
[0021] If there is no fault in the address bus, troubleshooting is performed on the address corresponding to the second comparison result;
[0022] If the address corresponding to the second comparison result is found to be fault-free, it is determined that the memory chip is faulty.
[0023] Optionally, detecting whether the memory chip meets the fault conditions, and determining that the memory chip is faulty if the memory chip meets the fault conditions, includes:
[0024] The frame-to-be-framed data signal sent by the field-programmable gate array chip is buffered in a first-in-first-out queue;
[0025] Obtain each of the frame data signals to be assembled that is cached in the first-in-first-out queue;
[0026] For each of the data signals to be framed that is cached in the first-in-first-out queue, when the field-programmable gate array chip interacts with the memory chip, the data signals to be framed are processed to obtain the framed data signals.
[0027] The framed data signal is cached in a cache unit of the memory particle for reading and writing;
[0028] The completion of reading and writing of the framed data signal is used as a trigger signal. In response to the trigger signal, the next framed data signal is cached in the next cache unit in the memory particle for reading and writing.
[0029] Detect whether the handshake signal timing of the memory chip is inconsistent with the preset timing within a preset time interval;
[0030] If the handshake signal timing of the memory chip is inconsistent with the preset timing within the preset time interval, it is determined that the memory chip is faulty.
[0031] This application also provides a device for determining abnormal memory data loading in a smart network interface card, comprising:
[0032] The detection module is used to detect whether each memory chip connected to each programmable input / output unit block in the field-programmable gate array chip of the smart network card meets the fault conditions; the fault conditions include address read / write inconsistency of the memory chip and / or handshake signal timing of the memory chip being inconsistent with the preset timing.
[0033] The determination module is used to determine that the memory chip is faulty when the memory chip meets the fault conditions, thereby determining that the smart network card memory data loading is abnormal.
[0034] This application also provides a field-programmable gate array chip, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it implements the steps of the method for determining memory data loading anomalies of a smart network card as described above.
[0035] This application also provides a system-on-a-chip (SoC) including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it implements the steps of the method for determining memory data loading anomalies of a smart network interface card as described above. The SoC accesses a field-programmable gate array (FPGA) chip through an intermediate layer interface.
[0036] This application also provides a smart network interface card (NIC), including a field-programmable gate array (FPGA) chip as described above, a system-on-a-chip (SoC) as described above, and multiple memory chips; wherein the SoC accesses the FPGA chip through an intermediate layer interface, and each programmable input / output unit block in the FPGA chip is connected to two or three of the memory chips.
[0037] This application also provides a computer program product, including a computer program / instructions that, when executed by a processor, implement the steps of the method for determining abnormal memory data loading of a smart network interface card as described above.
[0038] This application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method for determining abnormal memory data loading of a smart network card as described above.
[0039] The method, apparatus, device, and medium for determining memory data loading anomalies in smart network interface cards (NICs) provided in this application first detect whether each memory chip connected to each programmable input / output unit block in the field-programmable gate array (FPGA) chip of the smart NIC meets fault conditions. Fault conditions include address read / write inconsistencies and / or handshake signal timing inconsistencies with preset timings. Then, if the memory chip meets the fault conditions, it is determined that the memory chip is faulty, thereby confirming a memory data loading anomaly in the smart NIC. Therefore, this application can locate the specific memory chip that is damaged in the DRAM. Attached Figure Description
[0040] To more clearly illustrate the technical solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0041] Figure 1 This is a schematic diagram of an FPGA chip accessing DRAM memory chips according to an embodiment of this application;
[0042] Figure 2This is a schematic diagram of the SOC chip provided in this application accessing the FPGA DRAM memory chip through the MEZZ interface;
[0043] Figure 3 This is a schematic diagram of the communication bus between the SOC chip and the DRAM memory chip provided in the embodiments of this application;
[0044] Figure 4 This is one of the flowcharts illustrating the method for determining abnormal memory data loading of a smart network interface card provided in this application embodiment;
[0045] Figure 5 This is the second flowchart illustrating the method for determining abnormal memory data loading of a smart network interface card provided in this application embodiment;
[0046] Figure 6 This is the third flowchart illustrating the method for determining abnormal memory data loading of a smart network interface card provided in this application embodiment;
[0047] Figure 7 This is the fourth flowchart of the method for determining abnormal memory data loading of a smart network card provided in the embodiments of this application;
[0048] Figure 8 This is a schematic diagram of the structure of the smart network card memory data loading anomaly determination device provided in the embodiments of this application;
[0049] Figure 9 This is a schematic diagram of the structure of the field-programmable gate array chip provided in the embodiments of this application;
[0050] Figure 10 This is a schematic diagram of the structure of the system-on-a-chip provided in the embodiments of this application;
[0051] Figure 11 This is a schematic diagram of the structure of the smart network card provided in the embodiment of this application. Detailed Implementation
[0052] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0053] The terms "first," "second," etc., used in this application's specification are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class, without limiting the number of objects; for example, a first object can be one or more. Furthermore, in the specification, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects have an "or" relationship.
[0054] As data center network performance demands increase and data center scales continue to expand, the need for network performance also grows. Traditional network interface cards (NICs) have limited processing capabilities and cannot meet the needs of large-scale data centers. Smart NICs, through hardware acceleration and offloading technologies, significantly improve network performance.
[0055] Furthermore, with the development of cloud computing and edge computing, these technologies place higher demands on the utilization of computing resources. Traditional network interface card (NIC) processing methods consume a significant amount of CPU resources, impacting computing efficiency. Smart NICs, on the other hand, can offload some network processing tasks, reducing CPU load and improving the utilization of computing resources.
[0056] With the application of emerging network technologies such as Software Defined Networking (SDN), there is a growing demand for more powerful network interface cards (NICs). Smart NICs offer greater programmability and flexibility to meet the needs of these new technologies. Alibaba's MocoKA is one such example. This smart NIC utilizes self-developed chips and system software, enabling hardware acceleration for various functions including networking, storage, and security, significantly improving network performance while reducing CPU load. Furthermore, MocoKA supports flexible network programming models to meet the needs of various complex network environments.
[0057] The relationship between Smart Network Interface Card (Smart NIC) and Dynamic Random Access Memory (DRAM) mainly lies in data processing and storage. This relationship can be understood from the following aspects:
[0058] 1) Data caching: In network data transmission, smart network cards need to use DRAM as a cache to temporarily store received data packets, waiting for the CPU to process them. This can improve data transmission efficiency and reduce the CPU load.
[0059] 2) Network function acceleration: Smart network cards typically have their own processor and memory, allowing them to perform network functions such as virtual switching, encryption / decryption, and data compression / decompression on-board, without having to delegate these tasks to the host CPU. This memory is usually DRAM.
[0060] 3) Storage Virtualization: In modern data centers, smart network interface cards (NICs) can also be used for storage virtualization. By deploying storage services on the NIC, DRAM or SSDs can be accessed directly, enabling more efficient data storage and access.
[0061] 4) Memory Expansion: In some advanced applications, smart network interface cards (NICs) can also be used for memory expansion. For example, remote direct memory access (RDMA) technology can be used to map DRAM on other servers as local memory, thereby expanding the available memory space.
[0062] It is evident that smart network interface cards (NICs) and DRAM are closely related, working together to support network data transmission and processing. In the future, with advancements in network and memory technologies, the collaboration between smart NICs and DRAM will unlock even greater possibilities.
[0063] DRAM memory chips are commonly used machine memory components, such as those in Baseboard Management Controllers (BMCs) and Field Programmable Gate Arrays (FPGAs), where they are typically used to store running programs and data. However, due to various reasons, data loading in DRAM memory can fail, potentially leading to system instability and data loss. In more severe cases, it can cause the system to fail to load properly and thus be unable to perform its functions. For smart network interface cards (NICs), DRAM data loading anomalies can cause one or more memory cells in the controller to fail to read or write data, paralyzing the entire system. Furthermore, if the CPU's operating system (OS) and the FPGA's ARM (Advanced RISC Machines) processing system (HPS) fail, they cannot share the data processing load from the host, reducing transmission efficiency.
[0064] Currently, detection methods for abnormal data loading in smart network interface cards (NICs) generally include hardware detection methods and software detection methods.
[0065] 1) Hardware detection solution
[0066] This is typically achieved through fault detection mechanisms built into the memory controller and memory chip. These mechanisms can detect errors in memory and notify the system to handle them. Hardware detection can promptly identify data loading anomalies and has high accuracy and efficiency.
[0067] Specifically, hardware detection solutions generally employ a "five-step chessboard method":
[0068] 1. Write all zeros: Writes all cells as 0;
[0069] 2. Chessboard pattern write: Write all cells according to a chessboard pattern (e.g., alternating 0s and 1s);
[0070] 3. Read and verify the chessboard pattern: Read all cells and verify whether the data matches the chessboard pattern;
[0071] 4. Reverse checkerboard pattern write: Write all cells in a reverse checkerboard pattern (e.g., alternating 1s and 0s);
[0072] 5. Read and verify the reverse checkerboard pattern: Read all cells and verify whether the data matches the reverse checkerboard pattern.
[0073] These five steps effectively detect faults in DRAM. For example, if a cell fails to store data correctly in checkerboard mode, it will be detected in step 3. Similarly, if a cell fails to store data correctly in reverse checkerboard mode, it will be detected in step 5. However, this approach may not be able to detect some more complex faults.
[0074] 2) Software detection solution
[0075] Detecting data loading anomalies in memory can be achieved by running specially designed memory testing programs. For example, you can try using memory testing tools such as Memtest86 or Windows Memory Diagnostic, which can check for errors in DRAM. These tests perform read and write operations on memory and check the correctness of the data; they can be run while the system is running and do not require special hardware support.
[0076] Specifically, hardware detection schemes generally employ the March algorithm testing method. The March algorithm is a common method for testing memory chips such as Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM), with the primary goal of detecting faults in memory cells. However, while March testing is very effective in many cases, it also has some limitations: 1) Fault coverage: Although March testing can detect many common memory faults, it cannot guarantee 100% fault coverage. Some complex or hidden faults may not be detected by March testing. 2) Time efficiency: March testing typically requires multiple read and write operations on each cell in the memory, which consumes a significant amount of time. Especially for large-capacity memories, the time efficiency of March testing can become a problem. 3) Dependence on fault models: March tests are usually designed based on some predefined fault models. If the actual fault does not conform to these models, March testing may not be able to effectively detect these faults. 4) Difficulty in detecting dynamic faults: March testing mainly targets static faults and has limited ability to detect dynamic faults (such as speed faults, crosstalk, etc.). 5) Difficulty in coping with new memory technologies: As memory technology continues to develop, new types and modes of failure may emerge.
[0077] March tests may require continuous modification and updates to adapt to these new technologies. Therefore, while March tests play an important role in memory testing, they also need to be used in conjunction with other testing methods to improve the comprehensiveness and accuracy of the tests.
[0078] The two solutions mentioned above are general DRAM fault location solutions. However, for FPGA smart network cards with onboard processors, these two solutions cannot locate the specific memory chip that is damaged when DRAM data loading is abnormal.
[0079] Based on this, this application provides a method, apparatus, device, and medium for determining abnormal memory data loading in a smart network interface card (NIC), which will be described in detail below.
[0080] First, the application scenarios of the method for determining abnormal data loading in the memory of a smart network card are explained.
[0081] Please refer to Figure 1 , Figure 1 This is a schematic diagram illustrating how an FPGA chip accesses DRAM memory chips, as provided in an embodiment of this application. Figure 1As shown, the SOC chip and the FPGA chip are connected for communication. The FPGA chip includes a DRAM controller and a DRAM PHY chip. The DRAM controller accesses the DRAM chips through the buses connected to the DRAM PHY chip. PHY stands for Physical Layer.
[0082] Specifically, in the case of connecting two DRAM chips, the DRAM controller accesses the first DRAM chip through the buses connected to the DRAM PHY chip (e.g., RAS_NA16, CK, DQ[0:15], CA[13:0], CAS_NA16 and WE_NA14), and the DRAM controller accesses the second DRAM chip through the buses connected to the DRAM PHY chip (e.g., RAS_NA16, CK, DQ[16:31], CA[13:0], CAS_NA16 and WE_NA14).
[0083] In the case of connecting three DRAM chips, the DRAM controller accesses the first DRAM chip through the buses connected to the DRAM PHY chip (e.g., RAS_NA16, CK, DQ[0:15], CA[13:0], CAS_NA16 and WE_NA14), the second DRAM chip through the buses connected to the DRAM PHY chip (e.g., RAS_NA16, CK, DQ[16:31], CA[13:0], CAS_NA16 and WE_NA14), and the third DRAM chip through the buses connected to the DRAM PHY chip (e.g., RAS_NA16, CK, DQ[32:39], CA[13:0], CAS_NA16 and WE_NA14).
[0084] Please refer to Figure 2 , Figure 2 This is a schematic diagram illustrating how the SOC chip provided in this application accesses the FPGA DRAM memory chip via the MEZZ interface. Figure 2As shown, the SOC chip communicates with the FPGA chip via a middleware (MEZZ) interface. The FPGA chip includes eight programmable input / output blocks (Banks): Bank 2A, Bank 2B, Bank 2C, Bank 2D, Bank 3A, Bank 3B, Bank 3C, and Bank 3D. For Banks 2A, 2B, 2C, and 2D, each Bank connects two DRAM chips. Bank 3D connects three DRAM chips with a 40-bit bit width. The chips with 8ecc error correction can be shared with the HPS system, so the HPS system can also perform write and read operations on them.
[0085] Please refer to Figure 3 , Figure 3 This is a schematic diagram of the communication bus between the SOC chip and the DRAM memory chip provided in an embodiment of this application. Figure 3 As shown, the SOC chip includes an SOC processor, an ARM core processor, a communication interface, output devices, input devices, and a communication bus. The SOC processor, ARM core processor, communication interface, output devices, and input devices communicate with each other through the communication bus and run the DRAM chip control program.
[0086] The method for determining abnormal memory data loading of a smart network card provided in this application will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.
[0087] Please refer to Figure 4 , Figure 4 This is one of the flowcharts illustrating the method for determining memory data loading anomalies in a smart network interface card (NIC) according to embodiments of this application. This method can be applied to FPGA chips and / or SOC chips, such as... Figure 4 As shown, the method may include the following steps:
[0088] Step 401: For each memory chip connected to each programmable input / output unit block in the field-programmable gate array chip of the smart network card, check whether the memory chip meets the fault conditions; the fault conditions include address read / write inconsistency of the memory chip and / or handshake signal timing of the memory chip is inconsistent with the preset timing.
[0089] Step 402: If the memory chip meets the fault conditions, determine that the memory chip is faulty, thereby determining that the smart network card memory data loading is abnormal.
[0090] For example, memory chips can be Figure 1-3 The DRAM chip shown. (As shown in the image) Figure 2As shown, Bank 2A, Bank 2B, Bank 2C, and Bank 2D in the FPGA chip of the smart network card connect two memory chips, and Bank 3D connects three DRAM chips.
[0091] For the first memory chip in Bank 2A, write and read operations are performed sequentially at multiple addresses of the first memory chip, and the results of the write and read operations are checked for consistency. If the write and read results are inconsistent, the first memory chip in Bank 2A and its specific address are located.
[0092] For the first memory chip in Bank 2A, check whether the handshake signal timing of the first memory chip is inconsistent with the preset timing. If the handshake signal timing of the first memory chip is inconsistent with the preset timing, locate the first memory chip in Bank 2A.
[0093] The handshake signal timing may include:
[0094] 1) Excitation signal: The DRAM controller sends an excitation signal to the DRAM chip to start the DRAM preparing for data transmission.
[0095] 2) Request signal: The DRAM controller sends a request signal to the DRAM chip to indicate that data transmission is required.
[0096] 3) Response signal: After receiving the request signal, the DRAM chip will send a response signal to the DRAM controller, indicating that it is ready to transmit data.
[0097] 4) Data transmission: After the handshake signal is completed, the DRAM chip and the DRAM controller begin data transmission.
[0098] 5) End signal: After the data transmission is completed, the DRAM chip sends an end signal to the DRAM controller to indicate that the data transmission has been successfully completed.
[0099] It is important to note that the handshake signal timing between DRAM chips is extremely fast, typically on the nanosecond scale. During the handshake signal, a series of complex electrical signal interactions occur between the DRAM chip and the DRAM controller to ensure the correctness and integrity of data transmission.
[0100] The method for determining memory data loading anomalies in a smart network interface card (NIC) provided in this application first checks whether each memory chip connected to each programmable input / output unit block in the NIC's field-programmable gate array (FPGA) chip meets fault conditions. Fault conditions include address read / write inconsistencies and / or handshake signal timing inconsistencies with preset timings. Then, if the memory chip meets the fault conditions, it is determined that the memory chip is faulty, thereby confirming the smart NIC's memory data loading anomaly. Therefore, this application can locate the specific memory chip that is damaged in the DRAM.
[0101] In one example embodiment, detecting whether the memory chip meets the fault conditions in step 401 includes: simultaneously detecting whether the address of each memory chip connected to multiple programmable input / output unit blocks is inconsistent between read and write operations and whether the handshake signal timing of the memory chip is inconsistent with the preset timing.
[0102] For example, such as Figure 2 As shown, it simultaneously detects whether the address read / write of each memory chip connected to Bank 2A and Bank 2B is inconsistent and whether the handshake signal timing of the memory chip is inconsistent with the preset timing.
[0103] In this embodiment, simultaneously detecting whether the address read / write of each memory chip connected to multiple programmable input / output unit blocks is inconsistent and whether the handshake signal timing of the memory chip is inconsistent with the preset timing can greatly improve the efficiency of fault detection.
[0104] In another example embodiment, step 401, detecting whether the memory chip meets the fault conditions, includes: detecting whether the handshake signal timing of the memory chip is inconsistent with the preset timing; and if the handshake signal timing of the memory chip is consistent with the preset timing, detecting whether the address of the memory chip is inconsistent between reading and writing.
[0105] For example, such as Figure 2 As shown, for the first memory chip in Bank 2A, the handshake signal timing of the first memory chip is first checked to see if it is inconsistent with the preset timing. If the handshake signal timing of the first memory chip is inconsistent with the preset timing, the first memory chip in Bank 2A is determined to be faulty. If the handshake signal timing of the first memory chip is consistent with the preset timing, write and read operations are sequentially performed on multiple addresses of the first memory chip, and the write operation results are checked to see if they are consistent with the read operation results. If the write operation results are inconsistent with the read operation results, the first memory chip in Bank 2A and its specific address are located.
[0106] In specific implementation, such as Figure 5 As shown, the method for determining abnormal data loading in the memory of a smart network interface card (NIC) may include:
[0107] 1) such as Figure 5 As shown, the main control chip (i.e., the SOC chip) is powered on;
[0108] 2) Trigger the detection program, i.e., run the method to determine abnormal data loading in the smart network card memory;
[0109] 3) Based on the connectivity of the address bus, the FPGA EMIF BANK[0:16] address handshake signals are detected sequentially;
[0110] 4) Handshake signal timing judgment: If an abnormal fault is detected by handshake signal timing, locate the abnormal fault record log (SOC OS log or HPS OS log) and continue to trigger the detection program.
[0111] 5) Perform read and write tests on the address bits based on the MR address bus. Perform read and write tests on each of the thirteen addresses. If an abnormal fault is detected through the read and write test, locate the abnormal fault record log (SOC OS log or HPS OS log) and continue to trigger the detection program; Write[] represents a write operation and read[] represents a read operation.
[0112] 6) If no abnormal faults are found, the test is normal and the power-on initialization will begin.
[0113] In this embodiment, the timing of the handshake signal of the memory chip is detected to be inconsistent with the preset timing. If the timing of the handshake signal of the memory chip is consistent with the preset timing, the timing of the address read and write of the memory chip is detected to accurately detect whether the memory chip is faulty.
[0114] In one example embodiment, such as Figure 6 As shown, the method for determining abnormal data loading in the memory of a smart network interface card (NIC) may include:
[0115] Step 601: Perform write and read operations on multiple addresses of the memory chip sequentially through the data bus connected to the memory chip;
[0116] Step 602: Perform a consistency comparison between the first write operation result and the first read operation result corresponding to each address of the memory chip to obtain the first comparison result;
[0117] Step 603: If the first comparison result is inconsistent, troubleshoot the data bus.
[0118] Step 604: If no fault is found in the data bus, troubleshoot the address corresponding to the first comparison result.
[0119] Step 605: If there is no fault at the address corresponding to the first comparison result, write and read operations are performed sequentially on multiple addresses of the memory chip through the address bus connected to the memory chip.
[0120] Step 606: Perform a consistency comparison between the second write operation result and the second read operation result corresponding to each address of the memory chip to obtain the second comparison result;
[0121] Step 607: If the second comparison result is inconsistent, troubleshoot the address bus.
[0122] Step 608: If there is no fault in the address bus, troubleshoot the address corresponding to the second comparison result;
[0123] Step 609: If the address corresponding to the second comparison result is found to be fault-free, then the memory chip is determined to be faulty.
[0124] For example, such as Figure 2 As shown, for the first memory chip in Bank 2A, write and read operations are performed on address 0 of the first memory chip through the data bus connected to the first memory chip; the first write operation result and the first read operation result corresponding to address 0 of the first memory chip are compared for consistency to obtain the first comparison result; if the first comparison result is inconsistent, the data bus connected to the first memory chip is checked for faults. If there is no fault, the address 0 of the first memory chip is checked for faults until all addresses [0:13] of the first memory chip have been polled; if there is no fault, write and read operations are performed on address 0 of the first memory chip through the address bus connected to the first memory chip; the second write operation result and the second read operation result corresponding to address 0 of the first memory chip are compared for consistency to obtain the second comparison result; if the second comparison result is inconsistent, the address bus connected to the first memory chip is checked for faults. If there is no fault, the address 0 of the first memory chip is checked for faults until all addresses [0:13] of the first memory chip have been polled; if there is no fault, it is determined that the memory chip is faulty.
[0125] For example, when an address bus failure occurs, the following read / write error alarm will appear in the SOC OS log or HPS OS log:
[0126] First Fail Addr:0x0000000000000000
[0127] First Failue-Read Data:0x00000000fefefe00000000fffefefe01ffffffff000000ffffffff0000000000
[0128] First Failure-Expected Data:0x00000000fefefe0000000001ffffff ffffffffff00000001fefefe0000000000
[0129] Targeted Read Rata:0x00000000000000000000000000000000000000000000000000000000000000
[0130] Pass not Fail Signal:0xffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff
[0131] In this embodiment, the location of the fault can be checked one by one until the exact location of the fault is detected.
[0132] In another example embodiment, such as Figure 7 As shown, the method for determining abnormal data loading in the memory of a smart network interface card (NIC) may include:
[0133] Step 701: Buffer the frame-to-be-framed data signal sent by the field-programmable gate array chip in a first-in-first-out queue;
[0134] Step 702: Obtain the data signal of each frame to be assembled that is cached in the first-in-first-out queue;
[0135] Step 703: For each data signal to be framed that is cached in the first-in-first-out queue, when the field-programmable gate array chip interacts with the memory chip, the data signal to be framed is processed to obtain the framed data signal.
[0136] Step 704: Buffer the framed data signal into a buffer unit in the memory chip for reading and writing;
[0137] Step 705: Using the completion of reading and writing of the framed data signal as a trigger signal, respond to the trigger signal and cache the next framed data signal in the next cache unit in the memory chip for reading and writing;
[0138] Step 706: Detect whether the handshake signal timing of the memory chip within the preset time interval is inconsistent with the preset timing;
[0139] Step 707: If the handshake signal timing of the memory chip is inconsistent with the preset timing within a preset time interval, it is determined that the memory chip is faulty.
[0140] For example, such as Figure 2 As shown, for the first memory chip in Bank 2A, the data signal to be framed sent by the FPGA chip is buffered in a first-in-first-out queue. Each data signal to be framed is acquired. When the FPGA chip interacts with the first memory chip, the data signal to be framed is processed to obtain the framed data signal. The framed data signal is buffered in a buffer unit of the first memory chip for reading and writing. The completion of reading and writing of the framed data signal is used as a trigger signal to trigger the next framed data signal to be buffered in the next buffer unit of the first memory chip for reading and writing. It is detected whether the handshake signal timing of the first memory chip is inconsistent with the preset timing within a preset time interval. If they are inconsistent, it is determined that the first memory chip is faulty.
[0141] In this embodiment, the start of the next framed data signal is initiated by the completion of the reading and writing of the previous framed data signal, triggering the handshake mechanism, which can realize the fault flow monitoring of memory chips.
[0142] It should be noted that the execution entity of the smart network interface card (NIC) memory data loading anomaly determination method provided in this application embodiment can be a smart NIC memory data loading anomaly determination device, or a control module in the smart NIC memory data loading anomaly determination device for executing the smart NIC memory data loading anomaly determination method. This application embodiment uses the execution of the smart NIC memory data loading anomaly determination method by the smart NIC memory data loading anomaly determination device as an example to illustrate the smart NIC memory data loading anomaly determination device provided in this application embodiment.
[0143] It should be noted that, in the embodiments of this application, the methods for determining abnormal smart network card memory data loading shown in the accompanying drawings are all illustrated by way of example with reference to one of the accompanying drawings in the embodiments of this application. In specific implementation, the methods for determining abnormal smart network card memory data loading shown in the accompanying drawings can also be implemented in conjunction with any other accompanying drawings shown in the above embodiments, which will not be elaborated here.
[0144] The following describes the device for determining abnormal memory data loading of a smart network card provided in this application. The method for determining abnormal memory data loading of a smart network card described below can be referred to in correspondence with the method described above.
[0145] Please refer to Figure 8 , Figure 8 This is a schematic diagram of the structure of the smart network card memory data loading anomaly determination device provided in an embodiment of this application. Figure 8 As shown, the device may include:
[0146] The detection module 10 is used to detect whether each memory chip connected to each programmable input / output unit block in the field-programmable gate array chip of the smart network card meets the fault conditions; the fault conditions include address read / write inconsistency of the memory chip and / or handshake signal timing of the memory chip is inconsistent with the preset timing.
[0147] The determination module 20 is used to determine that the memory chip is faulty when the memory chip meets the fault conditions, thereby determining that the smart network card memory data loading is abnormal.
[0148] Optionally, the detection module 10 is specifically used to: simultaneously detect whether the address of each memory chip connected to multiple programmable input / output unit blocks is inconsistent between read and write operations and whether the handshake signal timing of the memory chip is inconsistent with the preset timing.
[0149] Optionally, the detection module 10 is specifically used to: detect whether the handshake signal timing of the memory chip is inconsistent with the preset timing; and if the handshake signal timing of the memory chip is consistent with the preset timing, detect whether the address of the memory chip is inconsistent between reading and writing.
[0150] Optionally, the detection module 10 and the determination module 20 are specifically used for:
[0151] Write and read operations are performed sequentially on multiple addresses of the memory chip via the data bus connected to the memory chip.
[0152] The consistency of the first write operation result and the first read operation result corresponding to each address of the memory chip is compared to obtain the first comparison result;
[0153] If the first comparison result is inconsistent, troubleshoot the data bus.
[0154] If no fault is found in the data bus, troubleshoot the address corresponding to the first comparison result.
[0155] If there is no fault at the address corresponding to the first comparison result, write and read operations are performed sequentially on multiple addresses of the memory chip through the address bus connected to the memory chip.
[0156] The consistency of the second write operation result and the second read operation result corresponding to each address of the memory chip is compared to obtain the second comparison result;
[0157] If the second comparison result is inconsistent, troubleshoot the address bus.
[0158] If there is no fault in the address bus, troubleshoot the address corresponding to the second comparison result;
[0159] If the address corresponding to the second comparison result is found to be fault-free, it is determined that the memory chip is faulty.
[0160] Optionally, the detection module 10 and the determination module 20 are specifically used for:
[0161] The frame-to-be-framed data signal sent by the field-programmable gate array chip is buffered in a first-in-first-out queue;
[0162] Retrieve the data signal for each frame to be assembled that is cached in the first-in-first-out queue;
[0163] For each data signal to be framed that is cached in the first-in-first-out queue, the data signal to be framed is processed during the interaction between the field-programmable gate array chip and the memory chip to obtain the framed data signal.
[0164] The framed data signal is cached in a cache unit of the memory chip for reading and writing;
[0165] The completion of reading and writing of the framed data signal is used as the trigger signal. In response to the trigger signal, the next framed data signal is cached in the next cache unit in the memory particle for reading and writing.
[0166] Detect whether the handshake signal timing of the memory chip is inconsistent with the preset timing within a preset time interval;
[0167] If the handshake signal timing of the memory chip is inconsistent with the preset timing within a preset time interval, it is determined that the memory chip is faulty.
[0168] Figure 9 An example is a schematic diagram of the physical structure of a field-programmable gate array (FPGA) chip, such as... Figure 9As shown, the field-programmable gate array (FPGA) chip may include: a processor 910, a communication interface 920, a memory 930, and a communication bus 940. The processor 910, communication interface 920, and memory 930 communicate with each other via the communication bus 940. The processor 910 can call logic instructions in the memory 930 to execute a method for determining an anomaly in the smart network card's memory data loading. This method includes: for each memory chip connected to each programmable input / output unit block in the FPGA chip of the smart network card, detecting whether the memory chip meets fault conditions; fault conditions include address read / write inconsistency of the memory chip and / or handshake signal timing inconsistency with preset timing of the memory chip; if the memory chip meets the fault conditions, determining that the memory chip is faulty, thereby determining that the smart network card's memory data loading is abnormal.
[0169] Figure 10 An example is a schematic diagram of the physical structure of a system-on-a-chip, such as... Figure 10 As shown, the system-on-a-chip (SoC) may include: a processor 1010, a communication interface 1020, a memory 1030, and a communication bus 1040. The processor 1010, communication interface 1020, and memory 1030 communicate with each other via the communication bus 1040. The processor 1010 can call logic instructions in the memory 1030 to execute a method for determining an anomaly in the smart network interface card's (NIC) memory data loading. This method includes: for each memory chip connected to each programmable input / output unit block in the NIC's field-programmable gate array (FPGA) chip, detecting whether the memory chip meets fault conditions; fault conditions include address read / write inconsistency of the memory chip and / or handshake signal timing inconsistency with a preset timing sequence; if the memory chip meets the fault conditions, determining that the memory chip is faulty, thereby determining that the smart NIC's memory data loading is abnormal. The SoC accesses the FPGA chip through an intermediate layer interface.
[0170] Furthermore, when the logical instructions in any of the aforementioned memories can be implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0171] Figure 11 An example is a schematic diagram of the physical structure of a smart network interface card, such as... Figure 11 As shown, the smart network card may include: a field-programmable gate array (FPGA) chip 1101, a system-on-a-chip (SoC) 1102, and multiple memory chips 1103; wherein, the SoC 1102 accesses the FPGA chip 1101 through an intermediate layer interface, and each programmable input / output unit block in the FPGA chip 1101 is connected to two or three memory chips 1103.
[0172] On the other hand, this application also provides a computer program product, which includes a computer program stored on a computer-readable storage medium. The computer program includes program instructions, and when the program instructions are executed by a computer, the computer can execute the smart network card memory data loading anomaly determination method provided by the above methods. The method includes: for each memory chip connected to each programmable input / output unit block in the field-programmable gate array chip of the smart network card, detecting whether the memory chip meets the fault conditions; the fault conditions include address read / write inconsistency of the memory chip and / or handshake signal timing of the memory chip being inconsistent with the preset timing; if the memory chip meets the fault conditions, determining that the memory chip is faulty, thereby determining that the smart network card memory data loading is abnormal.
[0173] In another aspect, this application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, is implemented to perform the aforementioned methods for determining memory data loading anomalies in smart network interface cards (NICs). The method includes: for each memory chip connected to each programmable input / output unit block in the field-programmable gate array (FPGA) chip of the smart NIC, detecting whether the memory chip meets fault conditions; the fault conditions include address read / write inconsistency of the memory chip and / or handshake signal timing inconsistency with a preset timing; if the memory chip meets the fault conditions, determining that the memory chip is faulty, thereby determining that the smart NIC memory data loading is abnormal.
[0174] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.
[0175] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.
[0176] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.
Claims
1. A method for determining abnormal data loading in the memory of a smart network interface card, characterized in that, include: For each memory chip connected to each programmable input / output unit block in the field-programmable gate array chip of a smart network card, detect whether the memory chip meets the fault conditions; The fault conditions include address read / write inconsistency of the memory chip and / or handshake signal timing of the memory chip being inconsistent with the preset timing. If the memory chip meets the fault conditions, it is determined that the memory chip is faulty, thereby determining that the smart network card memory data loading is abnormal; The detection of whether the memory chip meets the fault conditions includes: Fault detection is performed independently for each memory chip under each unit block to detect whether the handshake signal timing of the memory chip is inconsistent with the preset timing. If the handshake signal timing of the memory chip is consistent with the preset timing, detect whether the address of the memory chip is inconsistent between read and write. The step of detecting whether the memory chip meets the fault conditions, and determining that the memory chip is faulty if the memory chip meets the fault conditions, includes: Write and read operations are performed sequentially on multiple addresses of the memory chip via the data bus connected to the memory chip. The consistency of the first write operation result and the first read operation result corresponding to each address of the memory particle is compared to obtain the first comparison result; If the first comparison result is inconsistent, troubleshooting should be performed on the data bus. If the data bus is found to be fault-free, troubleshooting is performed on the address corresponding to the first comparison result. If there is no fault at the address corresponding to the first comparison result, write and read operations are sequentially performed on multiple addresses of the memory chip through the address bus connected to the memory chip. The consistency of the second write operation result and the second read operation result corresponding to each address of the memory particle is compared to obtain the second comparison result; If the second comparison result is inconsistent, troubleshooting should be performed on the address bus. If there is no fault in the address bus, troubleshooting is performed on the address corresponding to the second comparison result; If the address corresponding to the second comparison result is found to be fault-free, it is determined that the memory chip is faulty.
2. The method for determining abnormal data loading in a smart network interface card (NIC) memory according to claim 1, characterized in that, The detection of whether the memory chip meets the fault conditions includes: Simultaneously, it detects whether the address read / write of each memory chip connected to the multiple programmable input / output unit blocks is inconsistent, and whether the handshake signal timing of the memory chip is inconsistent with the preset timing.
3. The method for determining abnormal data loading in the memory of a smart network card according to claim 1, characterized in that, The step of detecting whether the memory chip meets the fault conditions, and determining that the memory chip is faulty if the memory chip meets the fault conditions, includes: The frame-to-be-framed data signal sent by the field-programmable gate array chip is buffered in a first-in-first-out queue; Obtain each of the frame data signals to be assembled that is cached in the first-in-first-out queue; For each of the data signals to be framed that is cached in the first-in-first-out queue, when the field-programmable gate array chip interacts with the memory chip, the data signals to be framed are processed to obtain the framed data signals. The framed data signal is cached in a cache unit of the memory particle for reading and writing; The completion of reading and writing of the framed data signal is used as a trigger signal. In response to the trigger signal, the next framed data signal is cached in the next cache unit in the memory particle for reading and writing. Detect whether the handshake signal timing of the memory chip is inconsistent with the preset timing within a preset time interval; If the handshake signal timing of the memory chip is inconsistent with the preset timing within the preset time interval, it is determined that the memory chip is faulty.
4. A device for determining abnormal data loading in the memory of a smart network interface card, characterized in that, include: The detection module is used to detect whether each memory chip connected to each programmable input / output unit block in the field-programmable gate array chip of the smart network card meets the fault conditions; the fault conditions include address read / write inconsistency of the memory chip and / or handshake signal timing of the memory chip being inconsistent with the preset timing. The determination module is used to determine that the memory chip is faulty when the memory chip meets the fault conditions, thereby determining that the smart network card memory data loading is abnormal. The detection of whether the memory chip meets the fault conditions includes: Fault detection is performed independently for each memory chip under each unit block to detect whether the handshake signal timing of the memory chip is inconsistent with the preset timing. If the handshake signal timing of the memory chip is consistent with the preset timing, detect whether the address of the memory chip is inconsistent between read and write. The step of detecting whether the memory chip meets the fault conditions, and determining that the memory chip is faulty if the memory chip meets the fault conditions, includes: Write and read operations are performed sequentially on multiple addresses of the memory chip via the data bus connected to the memory chip. The consistency of the first write operation result and the first read operation result corresponding to each address of the memory particle is compared to obtain the first comparison result; If the first comparison result is inconsistent, troubleshooting should be performed on the data bus. If the data bus is found to be fault-free, troubleshooting is performed on the address corresponding to the first comparison result. If there is no fault at the address corresponding to the first comparison result, write and read operations are sequentially performed on multiple addresses of the memory chip through the address bus connected to the memory chip. The consistency of the second write operation result and the second read operation result corresponding to each address of the memory particle is compared to obtain the second comparison result; If the second comparison result is inconsistent, troubleshooting should be performed on the address bus. If there is no fault in the address bus, troubleshooting is performed on the address corresponding to the second comparison result; If the address corresponding to the second comparison result is found to be fault-free, it is determined that the memory chip is faulty.
5. A field-programmable gate array chip, characterized in that, The method includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of the method for determining an anomaly in the memory data loading of a smart network interface card as described in any one of claims 1 to 3.
6. A system-on-a-chip, characterized in that, The system includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of the method for determining an anomaly in the memory data loading of a smart network interface card as described in any one of claims 1 to 3; The system-on-a-chip accesses the field-programmable gate array (FPGA) chip through an intermediate layer interface.
7. A smart network interface card, characterized in that, It includes the field-programmable gate array (FPGA) chip as described in claim 5, the system-on-a-chip (SoC) as described in claim 6, and multiple memory chips; wherein the SoC accesses the FPGA chip through an intermediate layer interface, and each programmable input / output unit block in the FPGA chip is connected to two or three memory chips.
8. A computer-readable storage medium, characterized in that, It stores a computer program, which, when executed by a processor, implements the steps of the method for determining abnormal memory data loading of a smart network card as described in any one of claims 1 to 3.